JP3938697B2 - Function function reconfigurable integrated circuit - Google Patents

Description

ただし、ｔｈ₁＝０＋０．５において、０．５の部分をαとすれば、０＜α＜１であればよい。本実施例では、動作マージンを考慮して、α＝０．５であるとした。
【００３５】
他の１段目のしきい素子回路ＦＴＥ［ｉ］についても、上記と同様である。他の１段目のしきい素子回路ＦＴＥ［ｉ］のしきい値については、以下のようにする。
【００３６】
まず、１段目のしきい素子回路ＦＴＥ［ｉ］を、２つのグループに分ける。つまり、１段目のしきい素子回路ＦＴＥ［２ｊ］のグループと、１段目のしきい素子回路ＦＴＥ［２ｊ＋１］のグループとに分ける。ｊは、１≦ｊ≦ｎの整数であると定義する。１段目のしきい素子回路ＦＴＥ［２ｊ］とＦＴＥ［２ｊ＋１］とのしきい値として、次の式（３）、式（４）で表される４つの候補から１つを選択する。
【００３７】
【数２】

たとえば、１段目のしきい素子回路ＦＴＥ［２］、ＦＴＥ［３］のしきい値ｔｈ₂、ｔｈ₃として、次の式（５）、（６）に記載されているそれぞれ４つの候補から１つを選択する。
【００３８】
【数３】

上記１段目のしきい素子回路ＦＴＥ［ｉ］に対するしきい値の設定によって、１段目のしきい素子回路ＦＴＥ［１］は、入力状態数Ｚ＝１についてのみ、出力値Ｘ_f[1]＝０，１の２つの論理値のいずれかを、しきい値に依存して選択することができる。入力状態数Ｚ＝０である場合は、出力値Ｘ_f[1]＝１であり、入力状態数Ｚ＞１である場合は、出力値Ｘ_f[1]＝０である。
【００３９】
また、１段目のしきい素子回路ＦＴＥ［２ｊ］とＦＴＥ［２ｊ＋１］との出力値Ｘ_f[2j]、Ｘ_f[2j+1]は、Ｚ≦（３ｊ−２）である場合、Ｘ_f[2j]＝１、Ｘ_f[2j+1]＝１であり、Ｚ＞（３ｊ＋１）である場合、Ｘ_f[2j]＝０、Ｘ_f[2j+1]＝０であり、（３ｊ−１）≦Ｚ≦（３ｊ＋１）である場合、Ｘ_f[2j]＝０，１のように、２つの論理値のいずれか一方を選択することができる。
【００４０】
次に、２段目のしきい素子回路ＳＴＥに着目する。
【００４１】
今、入力状態数を連続量であると仮定し、２段目のしきい素子回路ＳＴＥに入力される変数の値と重みとの積和演算の結果を、Ｓｕｍ_sとする。
【００４２】
図２は、上記実施例において、２段目のしきい素子回路ＳＴＥにおける入力状態数Ｚと、積和演算結果Ｓｕｍ_sとの関係を表す図である。
【００４３】
図２中、各入力状態数において取り得る積和演算結果Ｓｕｍ_sの値を，丸印で示し、黒丸は、積和演算結果Ｓｕｍ_sがしきい値ｔｈ_sよりも大きい場合を示す印であり、白丸は、逆に、積和演算結果Ｓｕｍ_sがしきい値ｔｈ_sよりも小さい場合を示す印である。
【００４４】
図２から判るように、入力状態数Ｚ＝０以外の入力状態では、選択されるしきい値に応じて、ｔｈ_sと比較して大小いずれか一方の値を取ることが可能であることが判る。
【００４５】
２段目のしきい素子回路ＳＴＥの出力値としては、図２に示す黒丸の状態が、論理的０として出力され、逆に、白丸の状態が、論理的１として出力される。このために、Ｚ≧１である場合、任意の論理値を出力することができる。入力状態数Ｚ＝０である場合にのみ、論理値が０に固定されているので、ｋ入力変数対称関数における２^k個の関数のみを実現することができる。この実現される２^k個の関数は、ｋ入力変数に対して実現可能な２^(k+1)個の対称関数の半分に当たる。
【００４６】
上記第１の実施例における１段目のしきい素子回路ＦＴＥ［１］の機能を、任意のＦＴＥ［ｉ］に与えることができる例として、ＦＴＥ［ｍ］のしきい値が、次の式（７）で表される値のいずれか１つであり、ｗ_f[m]＝２である場合について、説明する。
【００４７】
【数４】

また、１段目のしきい素子回路ＦＴＥ［ｍ］以外のＦＴＥ［ｉ］のしきい値を、次の式（８）、式（９）のように設定する。ただし、ｈは、１≦ｈ≦ｎを満たす整数であるとする。
【００４８】
【数５】

たとえば、１段目のしきい素子回路ＦＴＥ［ｍ−２］、ＦＴＥ［ｍ−１］のしきい値として、次に示す式（１０）、式（１１）に記載の４つの候補から、１つを選択する。
【００４９】
ただし、上記の通り、ｍとｋとの関係は、ｍ＝（２／３）ｋ＋（１／３）であり、また、ｋ＝３ｎ＋１であるので、ｍ−２＝２ｎ−１、ｍ−１＝２ｎであり、ともに、ｈ＝ｎの場合を示している。
【００５０】
【数６】

上記第１の例と同様に、２段目のしきい素子回路ＳＴＥにおける積和演算結果としきい値との関係に着目する。
【００５１】
図３は、上記実施例において、２段目のしきい素子回路ＳＴＥにおける入力状態数Ｚと、積和演算結果Ｓｕｍ_sとの関係を表す図である。
【００５２】
ｋ入力変数対称関数において、入力状態数Ｚがｋである場合のみ、積和演算結果Ｓｕｍ_sは、固定された値を取る。一方、入力状態数Ｚが、１≦Ｚ≦（ｋ−１）である場合、１段目のしきい素子回路ＦＴＥ［ｉ］のしきい値の値と、２段目のしきい素子回路ＳＴＥのしきい値ｔｈ_sとを比較し、大小いずれか一方の値を取る。
【００５３】
これによって、２段目のしきい素子回路ＳＴＥの出力値Ｙは、入力状態数Ｚがｋである場合に、論理的１に固定される以外は、ある入力状態数Ｚにおいて、論理的１、論理的０の一方が選択される。
【００５４】
したがって、ｋ入力変数対称関数中の半分である２^k個の対称関数を実現することができる。
【００５５】
上記内容をまとめると、次のようになる。
【００５６】
つまり、入力状態数の中の連続する２つの状態における２段目のしきい素子回路ＳＴＥの出力値を、１つの１段目のしきい素子回路ＦＴＥの出力値によって制御する。このときに、１段目のしきい素子回路ＦＴＥの出力値に対する２段目のしきい素子回路ＳＴＥにおける重みを、２とする。これによって、２つの状態の中のいずれか一方の状態において、１段目のしきい素子回路ＦＴＥの出力値が、固定された値になり、他の１つの状態においては、論理的１または論理的０のいずれか一方が、１段目のしきい素子回路ＦＴＥのしきい値によって決定される。
【００５７】
また、上記特性を有する１段目のしきい素子回路ＦＴＥが制御する以外の入力状態数の３つの状態を１グループにし、２つの１段目のしきい素子回路ＦＴＥの出力値によって、その３つの状態における２段目のしきい素子回路ＳＴＥの出力値を制御する。このときに、２つの１段目のしきい素子回路ＦＴＥの中の１つのＦＴＥの出力値に対する重みを１とし、残りの１つの１段目のしきい素子回路ＦＴＥの出力値に対する重みを、２とする。２つの１段目のしきい素子回路ＦＴＥのしきい値は、ともに、４つのしきい値の中から１つが選択される。
【００５８】
これによって、３つの入力状態数のそれぞれにおいて、２段目のしきい素子回路ＳＴＥの出力値を、論理的１または論理的０のいずれか一方に決定することができる。この回路構成によって、ｋ入力変数対称関数の中の２^k個の対称関数を実現することができる。また、上記１つの１段目のしきい素子回路ＦＴＥの出力値によって、２段目のしきい素子回路ＳＴＥの出力値が制御される連続する２つの入力状態数は、０≦Ｚ≦ｋのどの入力状態数であってもよい。
【００５９】
本実施例の再構成可能集積回路は、ある入力状態数における値が固定されていてもよい場合において、少ないしきい素子回路によって対称関数を実現することができる。
【００６０】
［複数のしきい値候補の実現方法および回路構成］
１段目のしきい素子回路ＦＴＥは、２つまたは４つのしきい値候補の中から、１つのしきい値を選択できることを仮定している。
【００６１】
次に、４つのしきい値候補から、１つのしきい値を選択する方法について、説明する。
【００６２】
図１に記載されている１段目のしきい素子回路ＦＴＥ［１］〜ＦＴＥ［ｍ］の入力端子１０５〜１０８に、しきい値選択変数Ｃ_th[i]〜Ｃ_th[m]を入力する。４つから１つを選ぶことを可能にするために、少なくともしきい値選択変数は、４つの状態を持ち、上記各状態としきい値候補とを１対１に対応させる。これによって、４つの中から１つを選択することができる。
【００６３】
具体的には、しきい値選択変数として多値表現された変数を用いる。多値表現として、物理的に電圧、電流、電荷量等による多値信号を用いる場合と、複数の２値信号の組合せによる多値表現とがある。後者の場合は、２ビットで、４つの状態を表現し、それぞれに、１つのしきい値候補を対応させることになる。
【００６４】
また、任意の連続する入力状態数の間に、４つのしきい値候補を設定できる場合、ある連続する３つの入力状態数における２段目のしきい素子回路ＳＴＥの出力値は、２つの１段目のしきい素子回路ＦＴＥのしきい値によって、任意の値に決めることができる。一方、上記のように１段目のしきい素子回路ＦＴＥのしきい値候補が連続する場合、２つのしきい値候補を有する１段目のしきい素子回路ＦＴＥのしきい値は、連続する３つの入力状態数の前後であれば、いずれの入力状態数の前後にも設定できる。たとえば、図２の場合は、その入力状態数は１であり、図３の場合は（ｋ−１）である。
【００６５】
再構成可能集積回路１００においては、必ずしも全ての対称関数が必要とされるとは限らないので、１つの入力状態数において、出力値が論理的１または論理的０に固定されてもよい場合には、関数機能再構成可能集積回路１００は、単位機能当たりの素子数の低減に対して非常に有効になる。
【００６６】
［全ての論理関数における（１／２）の関数の実現］
関数機能再構成可能集積回路１００における取り得る入力状態数の数Ｎは、Ｎ＝３ｎ＋２で表され、その中のＮ＝８，３２，１２８…は、指数部分が整数である２のべき乗で表すことができる。入力変数の数ｋに対応する全ての論理関数の数は、２の２^kである。ここで、２^kは、取り得る入力状態数の数を示す。また、しきい素子回路においては、入力変数に対する重みｗ_iを、２ⁱ，ｉ＝０，１，２，３，…ｋ−１に設定することによって、取り得る入力状態数の数を２^kにすることができる。
【００６７】
上記のように、関数機能再構成可能集積回路１００の入力変数に対する重みを変更すると、対称関数に対して適用した方法と同様の方法によって、全ての論理関数の（１／２）の論理関数を実現することができる。
【００６８】
（第２の実施例）
図４は、本発明の第２の実施例である関数機能再構成可能集積回路２００を示す回路図である。
【００６９】
関数機能再構成可能集積回路２００は、関数機能再構成可能集積回路１００の出力端子に、インバータ回路２１２と、セレクタ回路（マルチプレクサ回路とも呼ぶ）２１３とを設けた回路であり、これによって、任意の対称関数を実現することができる。
【００７０】
また、第１の実施例で説明したと同様に、関数機能再構成可能集積回路２００を応用することによって、任意の論理関数をも実現することができる。
【００７１】
関数機能再構成可能集積回路１００において対称関数を実現する場合、ある１つの入力状態数においてのみ、出力値の論理値が固定されている。
【００７２】
ここでは、ｋ入力変数対称関数において、出力論理値が１に固定されているとする。
【００７３】
関数機能再構成可能集積回路２００は、関数機能再構成可能集積回路１００の出力端子に相当する端子２１０に、インバータ回路２１２が接続され、端子２１０とインバータ回路２１２の出力端子２１１とを入力端子とするセレクタ回路２１３が接続されている。
【００７４】
端子２０９から入力されたセレクタ信号Ｓの論理値に基づいて、端子２１０の値、端子２１１の値のいずれか一方が選択される。これによって、入力状態数がｋである場合に、論理的１または論理的０のいずれか一方を、関数機能再構成可能集積回路２００の出力値Ｙとして、出力端子２１８が出力することができる。固定されている論理値の論理反転を出力することによって、任意の対称関数を実現することができる。
【００７５】
上記実施例によれば、しきい素子回路に入力される入力変数とその重みとの積和演算結果である入力状態数の数Ｎが、Ｎ＝３ｎ＋２で表される場合に、２段論理しきい素子回路網における１段目のしきい素子回路の数を、［（２／３）Ｎ−（１／３）］とする回路構成によって、１つの入力状態数の場合を除いて、全ての入力状態数における出力値として、論理的１または論理的０を選択することができる。
【００７６】
これは、ｋ入力変数対称関数を実現しようとした場合に、２^(k+1)個存在する対称関数中の半分である２^k個を実現することを意味し、ｋ入力変数論理関数を実現しようとする場合に、２の２^k乗個存在する論理関数中の半分である２の２^(k-1)乗個を実現することができることを意味している。
【００７７】
さらに、回路の出力端子に、インバータ回路を接続し、２段目のしきい素子回路の出力端子とインバータ回路の出力端子とを入力端子とするセレクタ回路を追加することによって、任意の対称関数または任意の論理関数を実現することができる。
【００７８】
この回路構成によって、任意の対称関数または論理関数をしきい素子回路網によって実現する際に、回路を構成する素子数を低減することができる。
【００７９】
【発明の効果】
本願発明によれば、論理関数機能を再構成することが可能な集積回路において、少ないしきい素子回路数によって、単位面積当たりの機能を向上させることができるという効果を奏する。
【図面の簡単な説明】
【図１】 本発明の第１の実施例である関数機能再構成可能集積回路１００を示す図である。
【図２】 ２段目のしきい素子回路ＳＴＥにおける入力状態数Ｚと、積和演算結果Ｓｕｍ_ｓとの関係を表す図である。
【図３】 上記実施例において、２段目のしきい素子回路ＳＴＥにおける入力状態数Ｚと、積和演算結果Ｓｕｍ_ｓとの関係を表す図である。
【図４】 本発明の第２の実施例である関数機能再構成可能集積回路２００を示す回路図である。
【図５】 特開２００１−２６６１０６公報に記載されている回路図であり、２段論理フィードフォワードしきい素子回路網に構成データとして多値を用い、任意のｋ入力変数論理関数を実現する回路の構成図である。
【図６】 図６は、図５に示す回路において、ｖＭＯＳインバータをしきい素子回路で置換した回路であり、連続する４つの入力状態数における回路の出力値Ｙを、３つの１段目のしきい素子回路の出力値（たとえば、Ｘ_ｆ［１］、Ｘ_ｆ［２］、Ｘ_ｆ［３］）によって決定する回路である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit having a threshold element circuit as a constituent element, and is capable of reconfiguring a function function even after manufacturing an integrated circuit, and more particularly to a function function using multi-value configuration data. The present invention relates to a reconfigurable integrated circuit and a function function reconfiguration method.
[0002]
[Prior art]
Japanese Patent Laid-Open No. 2001-266106 describes a variable logic unit (an integrated circuit in which a logical function can be reconfigured) using a threshold element circuit and a design method thereof. A logic function reconfigurable integrated circuit is an integrated circuit that can reconfigure the logic function functions of the integrated circuit even after the integrated circuit is manufactured.
[0003]
FIG. 5 is a circuit diagram described in the above publication, and is a configuration diagram of a circuit that realizes an arbitrary k-input variable logic function using multi-values as configuration data in a two-stage logic feedforward threshold element network. is there.
[0004]
As the threshold element circuit, an inverter circuit (vMOS inverter) composed of neuron MOS transistors is used.
[0005]
According to the conventional example described above, when an arbitrary k-input variable logic function is realized by a two-stage logic feedforward circuit when the data (configuration data) constituting the logic function is not multi-valued, the first stage As the threshold element circuit, 2 ^k and one second-stage threshold element circuit are required. In this case, by multi-level configuration data, the number of the threshold element circuit of the first stage is reduced to (3/4) · 2 ^k pieces.
[0006]
Here, the number of input states is defined as a product-sum operation result that is a result of adding the product of the logical value of the input variable and the weight for each input variable for all input variables. In this case, 2 ^k which is the number of elements in the first-stage threshold element circuit is the number of the input states.
[0007]
FIG. 6 is a circuit in which the vMOS inverter is replaced with a threshold element circuit in the circuit shown in FIG. 5, and the output value Y of the circuit in four consecutive input state numbers is expressed as three first-stage threshold element circuits. Is determined based on the output value (for example, X _{f [1]} , X _{f [2]} , X _{f [3]} ). With the circuit shown in FIG. 6, the number of threshold element circuits in the circuit is (3/4) · 2 ^k +1.
[0008]
As described above, in a two-stage logic feedforward type threshold element network, a circuit using multiple values as configuration data for realizing an arbitrary k-input variable logic function is known, and in this case, at least (3 / 4) · 2 ^k +1 threshold elements are required.
[0009]
[Problems to be solved by the invention]
As described above, in order to realize an arbitrary k-input variable logic function in a two-stage logic feedforward function function reconfigurable integrated circuit using a threshold element circuit, (3/4) · 2 ^k +1 One threshold element is required.
[0010]
Incidentally, in order to increase the functionality of a reconfigurable integrated circuit, it is desired to further improve the function per unit area.
[0011]
The present invention relates to a function function reconfigurable integrated circuit and a function capable of configuring a function function reconfigurable integrated circuit with a smaller number of threshold element circuits in an integrated circuit capable of reconfiguring a logic function function. The object is to provide a function reconfiguration method.
[0012]
[Means for Solving the Problems]
The present invention is a functionally reconfigurable integrated circuit comprising a first stage threshold element and a second stage threshold element coupled to the first stage threshold element. The threshold element of the stage has a first threshold element and a second threshold element, and the threshold element of the second stage has a third threshold element, and the first threshold element The threshold element has at least four threshold candidates set before and after three consecutive input state numbers, and a threshold selection variable for selecting one threshold candidate from the at least four threshold candidates. The threshold element to be input, and the second threshold element has two threshold candidates set before and after one input state number, and one threshold candidate is selected from the two threshold candidates. A threshold selection variable for inputting a threshold selection variable, the first threshold The weight for the output terminal is set to one of a predetermined value and twice the predetermined value, and the weight for the output terminal of the second threshold element is set to twice the predetermined value. And the output terminal of the first threshold element and the output terminal of the second threshold element are connected via the weight, and the third threshold element has a fixed threshold value. A function function reconfigurable integrated circuit, wherein the output value of the third threshold element is fixed when the threshold element is at least one input state number.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
(First embodiment)
FIG. 1 is a diagram showing a function-function reconfigurable integrated circuit 100 according to a first embodiment of the present invention.
[0014]
The function function reconfigurable integrated circuit 100 is a reconfigurable integrated circuit capable of realizing a function of (1/2) among all symmetric functions of k input variables, and includes a threshold element circuit as a component. A reconfigurable integrated circuit.
[0015]
The number of input states is defined as a product-sum value obtained by summing the product of the logical value of the input variable and the weight for the input variable for all input variables. In this case, the functional function reconfigurable integrated circuit 100 can realize half the number of symmetric functions among all the symmetric functions with a threshold element circuit smaller than that of the conventional circuit in a certain number of input states. .
[0016]
In the following description, the circuit configuration will be described, and then a method of selecting one threshold from the four threshold candidates used in the threshold element circuit will be described. It will be described that (1/2) of all logical functions can be realized with a certain number of input variables by simply changing the weights of the input variables in the circuit to be realized.
[0017]
[Circuit configuration for realizing (1/2) of all symmetric functions]
The function-function reconfigurable integrated circuit 100 realizes 2 ^k halves out of 2 ^{(k + 1)} k-input variable symmetric functions.
[0018]
When the maximum value Z _{max of the} number of input states Z (where Z _max = k) is Z _max = 3n + 1 (when the number N of all possible input states is 3n + 2), the function function is reconfigured. in a possible integrated circuit 100, (2/3) by N-(1/3) pieces of first-stage inverted output type threshold element circuit FTE [1] ~FTE [m] , realized 2 ^k pieces of symmetric function can do.
[0019]
However, n = (0, 1, 2, 3,...), And specific N is N = 2, 5, 8, 11, 14,.
[0020]
The negative output type threshold element circuit compares the threshold value of the threshold element circuit with the product-sum value that is the sum of the product of the input variable and the weight for all input variables. This is a threshold element circuit that outputs logical 0 when it is large and outputs logical 1 when the product-sum value is small.
[0021]
Hereinafter, the negative output type threshold element circuit is simply referred to as “threshold element circuit”.
[0022]
This function function reconfigurable integrated circuit 100 has a configuration described in Japanese Patent Laid-Open No. 2001-266106 ( Title of Invention: Logic Function Function Reconfigurable Integrated Circuit and its Design Method) (3/4) N pieces As compared with the case of using the FTE [i], at least half of the k-input variable symmetric function can be realized with a smaller number of elements.
[0023]
Next, the function function reconfigurable integrated circuit 100 will be described in detail.
[0024]
In the function-function reconfigurable integrated circuit 100, k input terminals 101 to 104 are terminals for inputting input variables X _{1 to} X _k , and threshold element circuits FTE [1] to FTE [m of the first stage are input. And the second stage threshold element circuit STE.
[0025]
In order to realize a symmetric function whose function value is unchanged even if the logical value of an arbitrary input variable is replaced, weights w _{1 to} w _k multiplied by input variables input to all threshold element circuits are set. Make equal. In this embodiment, the weight w ₁ to w _k is assumed to be 1 equally.
[0026]
Further, since the threshold element circuit FTE [i] in the first stage has a plurality of threshold candidates in advance, a variable for selecting a threshold other than the input variable, threshold selection variable C _{th [i ]}
[0027]
Threshold selection variables C _{th [i] to} C _{th [m]} are input to the first-stage threshold element circuits FTE [1] to FTE [m], respectively. The threshold values selected by the threshold selection variables C _{th [i] to} C _{th [m]} are th _{1 to} th _m , respectively.
[0028]
The output terminals 110 to 113 of the first stage threshold element circuits FTE [1] to FTE [m] are connected to the second stage threshold element circuit STE. In this case, the weights multiplied by the output terminals of the first-stage threshold element circuits FTE [1] to FTE [m] are w _{f [1] to} w _{f [m]} .
[0029]
Further, the threshold value of the second-stage threshold element circuit STE is fixed to th _s . The threshold element circuit STE at the second stage compares the product sum value with the threshold value th _s and outputs the output value Y from the output terminal 109 according to the comparison result. M in the function function reconfigurable integrated circuit 100 is in the relationship of the following expression (1) between N and k.
[0030]
m = (N−2) / 3 × 2 + 1 = (2/3) N−1 / 3 = (2/3) k + 1/3
......... Formula (1)
Next, the threshold value of FTE [i] of the functional function reconfigurable integrated circuit 100 for realizing 2 ^k symmetric functions and the weight multiplied by the threshold value will be described.
[0031]
As a first example, a case where w _{f [1]} = 2 is described.
[0032]
At this time, the weight for half of the output terminals of the threshold element circuits FTE [2] to FTE [m] is set to 1, and the weight for the remaining half of the terminals is set to 2. Here, since m−1 = 2n holds, the weight distribution is always possible for any number k of input variables.
[0033]
Here, the weight for the output terminal of the threshold element circuit FTE [2] at the first stage is 1, and the weight for the output terminal of the threshold element circuit FTE [3] at the first stage is 2. i], the weights for the output terminals are alternately repeated as 1, 2, 1, 2,... in ascending order. Further, as the threshold value th ₁ of the first stage of the threshold element circuit FTE [1], and you can select one shown in the following equation (2).
[0034]
[Expression 1]

However, when th ₁ = 0 + 0.5, if 0.5 is α, 0 <α <1. In this embodiment, α = 0.5 is set in consideration of the operation margin.
[0035]
The same applies to the other first-stage threshold element circuit FTE [i]. The threshold values of the other first-stage threshold element circuit FTE [i] are as follows.
[0036]
First, the first-stage threshold element circuit FTE [i] is divided into two groups. In other words, the first stage threshold element circuit FTE [2j] is divided into the group of the first stage threshold element circuit FTE [2j + 1]. j is defined as an integer of 1 ≦ j ≦ n. As threshold values for the first-stage threshold element circuits FTE [2j] and FTE [2j + 1], one is selected from the four candidates represented by the following expressions (3) and (4).
[0037]
[Expression 2]

For example, as thresholds th ₂ and th ₃ of threshold element circuits FTE [2] and FTE [3] in the first stage, four candidates described in the following equations (5) and (6) are used. Select one.
[0038]
[Equation 3]

By setting the threshold value for the first-stage threshold element circuit FTE [i], the first-stage threshold element circuit FTE [1] outputs the output value X _{f [1} only for the input state number Z = _{1. ]} Either of two logical values of 0 and 1 can be selected depending on the threshold value. When the number of input states Z = 0, the output value X _{f [1]} = 1, and when the number of input states Z> 1, the output value X _{f [1]} = 0.
[0039]
Further, the output values X _{f [2j]} and X _{f [2j + 1]} of the threshold element circuits FTE [2j] and FTE [2j + 1] in the first stage are X ≦ (3j−2), _{If f [2j]} = 1, _{Xf [2j + 1]} = 1, and Z> (3j + 1), then _{Xf [2j]} = 0, _{Xf [2j + 1]} = 0, and (3j −1) When Z ≦ (3j + 1), either one of the two logical values can be selected as X _{f [2j]} = 0,1.
[0040]
Next, attention is focused on the second-stage threshold element circuit STE.
[0041]
Now, assuming that the number of input states is a continuous amount, the sum of products of the values of variables and weights input to the second-stage threshold element circuit STE is Sum _s .
[0042]
FIG. 2 is a diagram illustrating the relationship between the number of input states Z in the second-stage threshold element circuit STE and the product-sum operation result Sum _s in the above embodiment.
[0043]
In Figure 2, the value of possible product-sum operation result Sum _s in the number of each input state, indicated by circles, black circles, be a mark indicating when the product-sum operation result Sum _s is greater than the threshold th _s On the contrary, the white circle is a mark indicating a case where the product-sum operation result Sum _s is smaller than the threshold value th _s .
[0044]
As can be seen from FIG. 2, in an input state other than the number of input states Z = 0, it is possible to take one of the values larger or smaller than th _s according to the selected threshold value. I understand.
[0045]
As the output value of the threshold element circuit STE at the second stage, the black circle state shown in FIG. 2 is output as logical 0, and conversely, the white circle state is output as logical 1. For this reason, when Z ≧ 1, an arbitrary logical value can be output. Since the logical value is fixed to 0 only when the number of input states Z = 0, only 2 ^k functions in the k-input variable symmetric function can be realized. The realized 2 ^k functions are half of 2 ^{(k + 1)} symmetric functions that can be realized for k input variables.
[0046]
As an example in which the function of the first-stage threshold element circuit FTE [1] in the first embodiment can be given to any FTE [i], the threshold value of FTE [m] is given by The case where any one of the values represented by (7) and w _{f [m]} = 2 is described.
[0047]
[Expression 4]

Further, threshold values of FTE [i] other than the first-stage threshold element circuit FTE [m] are set as in the following Expressions (8) and (9). However, h is an integer satisfying 1 ≦ h ≦ n.
[0048]
[Equation 5]

For example, as threshold values of the threshold element circuits FTE [m−2] and FTE [m−1] in the first stage, 1 is selected from the four candidates described in the following expressions (10) and (11). Select one.
[0049]
However, as described above, the relationship between m and k is m = (2/3) k + (1/3) and k = 3n + 1, so that m−2 = 2n−1 and m−1. = 2n, and both show the case of h = n.
[0050]
[Formula 6]

As in the first example, attention is paid to the relationship between the product-sum operation result and the threshold value in the second-stage threshold element circuit STE.
[0051]
FIG. 3 is a diagram illustrating the relationship between the number of input states Z in the second-stage threshold element circuit STE and the product-sum operation result Sum _s in the above embodiment.
[0052]
In the k-input variable symmetric function, the product-sum operation result Sum _s takes a fixed value only when the number of input states Z is k. On the other hand, when the number of input states Z is 1 ≦ Z ≦ (k−1), the threshold value of the first-stage threshold element circuit FTE [i] and the second-stage threshold element circuit STE Is compared with the threshold value th _s, and takes one of the larger or smaller values.
[0053]
As a result, the output value Y of the threshold element circuit STE at the second stage is logical 1 at a certain input state number Z except that the output value Y is fixed to logical 1 when the input state number Z is k. One of logical 0 is selected.
[0054]
Therefore, 2 ^k symmetric functions which are half of k input variable symmetric functions can be realized.
[0055]
The above contents are summarized as follows.
[0056]
That is, the output value of the second-stage threshold element circuit STE in two consecutive states in the number of input states is controlled by the output value of one first-stage threshold element circuit FTE. At this time, the weight in the second stage threshold element circuit STE with respect to the output value of the first stage threshold element circuit FTE is set to 2. As a result, in one of the two states, the output value of the threshold element circuit FTE at the first stage becomes a fixed value, and in the other one state, logical 1 or logical One of the target zeros is determined by the threshold value of the threshold element circuit FTE in the first stage.
[0057]
Further, three states of the number of input states other than those controlled by the first-stage threshold element circuit FTE having the above characteristics are grouped into one group, and the three states are determined by the output values of the two first-stage threshold element circuits FTE. The output value of the second stage threshold element circuit STE in one state is controlled. At this time, the weight for the output value of one FTE of the two first-stage threshold element circuits FTE is set to 1, and the weight for the output value of the remaining one-stage threshold element circuit FTE is 2. As the threshold values of the two first-stage threshold element circuits FTE, one of the four threshold values is selected.
[0058]
Thereby, in each of the three input state numbers, the output value of the threshold element circuit STE in the second stage can be determined as either logical 1 or logical 0. With this circuit configuration, 2 ^k symmetric functions among k input variable symmetric functions can be realized. The number of two consecutive input states in which the output value of the second threshold element circuit STE is controlled by the output value of the one first threshold element circuit FTE is 0 ≦ Z ≦ k. Any number of input states may be used.
[0059]
The reconfigurable integrated circuit of this embodiment can realize a symmetric function with a small threshold element circuit when the value at a certain number of input states may be fixed.
[0060]
[Method and circuit configuration for realizing multiple threshold candidates]
It is assumed that the threshold element circuit FTE in the first stage can select one threshold value from two or four threshold value candidates.
[0061]
Next, a method for selecting one threshold from four threshold candidates will be described.
[0062]
Threshold selection variables C _{th [i] to} C _{th [m]} are input to the input terminals 105 to 108 of the first-stage threshold element circuits FTE [1] to FTE [m] shown in FIG. To do. In order to make it possible to select one from four, at least the threshold selection variable has four states, and each of the states and the threshold candidates correspond to each other on a one-to-one basis. As a result, one of the four can be selected.
[0063]
Specifically, a variable expressed in multiple values is used as the threshold selection variable. As the multi-value expression, there are a case where a multi-value signal physically using voltage, current, charge amount, etc. is used, and a multi-value expression using a combination of a plurality of binary signals. In the latter case, 4 bits are represented by 2 bits, and one threshold value candidate is associated with each.
[0064]
Further, when four threshold candidates can be set between any number of consecutive input states, the output value of the second-stage threshold element circuit STE at a certain number of consecutive three input states is two 1's. An arbitrary value can be determined by the threshold value of the threshold element circuit FTE at the stage. On the other hand, when the threshold candidates of the first threshold element circuit FTE are continuous as described above, the thresholds of the first threshold element circuit FTE having two threshold candidates are continuous. As long as the number of input states is around three, it can be set before or after any number of input states. For example, in the case of FIG. 2, the number of input states is 1, and in the case of FIG. 3, it is (k-1).
[0065]
In the reconfigurable integrated circuit 100, not all symmetric functions are necessarily required, so that the output value may be fixed to logical 1 or logical 0 in one input state number. The function function reconfigurable integrated circuit 100 is very effective for reducing the number of elements per unit function.
[0066]
[Realization of (1/2) function in all logical functions]
The number N of possible input states in the function-function reconfigurable integrated circuit 100 is represented by N = 3n + 2, where N = 8, 32, 128... Is represented by a power of 2 whose exponent part is an integer. be able to. The number of all logical functions corresponding to the number k of input variables are 2 of 2 ^k. Here, 2 ^k indicates the number of possible input states. In the threshold element circuit, the number of possible input states is set to 2 ^k by setting the weights w _i for the input variables to 2 ⁱ , i = 0, 1, 2, 3,... K−1. Can be.
[0067]
As described above, when the weight for the input variable of the function function reconfigurable integrated circuit 100 is changed, (1/2) logical functions of all the logical functions are obtained by a method similar to the method applied to the symmetric function. Can be realized.
[0068]
(Second embodiment)
FIG. 4 is a circuit diagram showing a function-function reconfigurable integrated circuit 200 according to the second embodiment of the present invention.
[0069]
The function-function reconfigurable integrated circuit 200 is a circuit in which an inverter circuit 212 and a selector circuit (also referred to as a multiplexer circuit) 213 are provided at the output terminal of the function-function reconfigurable integrated circuit 100. Symmetric functions can be realized.
[0070]
As described in the first embodiment, an arbitrary logical function can be realized by applying the function function reconfigurable integrated circuit 200.
[0071]
When a symmetric function is realized in the function function reconfigurable integrated circuit 100, the logical value of the output value is fixed only in a certain number of input states.
[0072]
Here, it is assumed that the output logical value is fixed to 1 in the k-input variable symmetric function.
[0073]
In the function-function reconfigurable integrated circuit 200, an inverter circuit 212 is connected to a terminal 210 corresponding to the output terminal of the function-function reconfigurable integrated circuit 100, and the terminal 210 and the output terminal 211 of the inverter circuit 212 are input terminals. A selector circuit 213 is connected.
[0074]
Based on the logical value of the selector signal S input from the terminal 209, either the value of the terminal 210 or the value of the terminal 211 is selected. As a result, when the number of input states is k, the output terminal 218 can output either logical 1 or logical 0 as the output value Y of the functional function reconfigurable integrated circuit 200. An arbitrary symmetric function can be realized by outputting a logical inversion of a fixed logical value.
[0075]
According to the above embodiment, when the number N of input states, which is the product-sum operation result of the input variable input to the threshold element circuit and its weight, is expressed as N = 3n + 2, two-stage logic is performed. With the circuit configuration in which the number of threshold element circuits in the first stage in the threshold element circuit network is [(2/3) N− (1/3)], all except the case of one input state number As an output value in the number of input states, logical 1 or logical 0 can be selected.
[0076]
This is because when an attempt is made to realize a k input variables symmetric functions, 2 ^{(k + 1)} means to realize a 2 ^k pieces is half in symmetric function number is present, realized k input variable logic function This means that it is possible to realize 2 2 ^{(k−1) power,} which is half of the 2 2 ^k logic functions.
[0077]
Further, by connecting an inverter circuit to the output terminal of the circuit and adding a selector circuit having the output terminal of the second-stage threshold element circuit and the output terminal of the inverter circuit as input terminals, any symmetric function or Arbitrary logic functions can be realized.
[0078]
With this circuit configuration, when an arbitrary symmetric function or logical function is realized by a threshold element circuit network, the number of elements constituting the circuit can be reduced.
[0079]
【The invention's effect】
According to the present invention, in an integrated circuit in which a logic function function can be reconfigured, the function per unit area can be improved with a small number of threshold element circuits.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a function-function reconfigurable integrated circuit 100 according to a first embodiment of the present invention.
[Figure 2] and the number of input state Z in the second-stage threshold element circuit STE, a graph showing the relation between the product-sum operation result Sum _s.
[3] In the above embodiments, it is a diagram showing the number of input state Z in the threshold element circuit STE of the second stage, the relationship between the product-sum operation result Sum _s.
FIG. 4 is a circuit diagram showing a function-function reconfigurable integrated circuit 200 according to a second embodiment of the present invention.
[Figure 5] is a circuit diagram disclosed in 2001-266106 JP, using the multi-value as configuration data in the two-stage logic feed-forward threshold element network, to realize any k input variable logic function circuit FIG.
FIG. 6 is a circuit in which the vMOS inverter is replaced with a threshold element circuit in the circuit shown in FIG. 5, and the output value Y of the circuit in four consecutive input state numbers is expressed by three first stages. This is a circuit that is determined by the output values (for example, X _{f [1]} , X _{f [2]} , X _{f [3]} ) of the threshold element circuit.

Claims (4)

A function function reconfigurable integrated circuit comprising a first stage threshold element and a second stage threshold element coupled to the first stage threshold element,
The first stage threshold element has a first threshold element and a second threshold element, and the second stage threshold element has a third threshold element,
The first threshold element has at least four threshold candidates set before and after three consecutive input state numbers, and a threshold for selecting one threshold candidate from the at least four threshold candidates. Threshold element to which a value selection variable is input,
The second threshold element has two threshold candidates set before and after one input state number, and a threshold selection variable for selecting one threshold candidate from the two threshold candidates. The threshold element to be input,
The weight for the output terminal of the first threshold element is set to one of a predetermined value and twice the predetermined value, and the weight for the output terminal of the second threshold element is Set to twice a predetermined value, the output terminal of the first threshold element and the output terminal of the second threshold element are connected via the weight, and the third threshold element is: A function function reconfigurable integrated circuit, characterized in that it is a threshold element having a fixed threshold value, and the output value of the third threshold element is fixed when the number of input states is at least one. . In claim 1 ,
The number of input possible states N is, N = 3n + 2, n = 1,2,3, when ... is the number of the first threshold element is [(2/3) N- (1/3) The function function reconfigurable integrated circuit is characterized in that the number of the second threshold elements is one. In claim 1 or claim 2 ,
An inverter circuit connected to the output terminal of the third threshold element ;
A selector circuit for selecting one of the output signal of the third threshold element and the output signal of the inverter circuit;
A functional function reconfigurable integrated circuit comprising: In claim 2 or claim 3 ,
Of the number N of possible input states, three consecutive input state numbers are defined as one first group, n first groups are set, and the remaining two consecutive input state numbers are When the second group is different from the first group,
When the number of input states is one first group, the output value of the third threshold element is two depending on the value of the threshold selection variable input to the first threshold element. Selected as one of the logical values,
The output value of the third threshold element when the number of input states is any one of the two input state numbers belonging to the second group is input to the second threshold element. A function function reconfigurable integrated circuit , wherein one of two logical values is selected according to a value of a threshold selection variable .

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