JP3931384B2 - FIFO memory controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a FIFO memory control device.
The FIFO memory is generally used for high-speed data transfer between input / output devices. However, since serial transfer is performed, unnecessary data is transferred when data having different data widths is transferred continuously. An effective data transfer rate is lowered and a solution is desired.
[0002]
[Prior art]
FIG. 4 shows the configuration of a system that performs data transfer using a FIFO memory control device. In the figure, 11 is a processor that controls the entire transfer source system, 12 is a transfer source RAM that stores data to be transferred, 13 is a FIFO memory control device, 14 is a transfer destination RAM in the transfer destination system, and 15 is A DMAC that controls data transfer from the transfer source RAM 12 to the transfer destination RAM 14 on behalf of the processor 1, sends data stored in the transfer source RAM 12 to the FIFO memory control device 13, and further transfers data from the FIFO memory control device 13 to the transfer destination. The data is transferred to the RAM 14. In addition to the RAM, a storage device such as a hard disk is used as a transfer source and transfer destination storage device.
[0003]
FIG. 5 is a block diagram showing the configuration of the FIFO memory control device 13. Input data is stored in a FIFO memory unit 16 composed of a buffer memory such as a RAM. The write address and read address of the input data in the FIFO memory unit 16 are designated by the write pointer W and the read pointer R, respectively. The write pointer W is incremented by 1 every time 1 byte of data is written and designates the next write address, and the read pointer R is incremented by 1 every time 1 byte of data is read and designates the next read address.
[0004]
FIG. 6 schematically shows the flow of data when data transfer is performed from the transfer source RAM to the transfer destination RAM through the 32-bit data bus line using the FIFO memory control device. One bit of the transfer source RAM shown in the figure stores 8-bit data, and each column stores 4 bytes (1 word) of data. Therefore, one word of data having a 32-bit width is stored in four squares of the same column, divided into 8 bits from D0 indicating the least significant bit to D32 indicating the most significant bit. .
[0005]
In the above configuration, when all the data to be transferred is 32 bits wide, effective data is stored in all squares of the transfer source RAM. However, when 16-bit or 8-bit width data is mixed, invalid data that does not need to be transferred may be included in the transfer source RAM. For example, as shown in FIG. Each square of the RAM may contain invalid data indicated by “x” in addition to valid data numbered from 1 to 8.
[0006]
In the example shown in (1) in the figure, data for 3 words is stored in the transfer source RAM consisting of the first row of 4 rows and 3 columns, and the data is surrounded by the dotted line stored in the first column. The data of the first word has a data width of 16 bits, the upper 2 bytes numbered 1 and 2 are valid data, and the lower 2 bytes indicated by “x” are invalid data. The data of the second word stored in the second column has a data width of 32 bits, and all 4 bytes numbered 3, 4, 5, and 6 are valid. The data of the third word has a data width of 16 bits, the upper 2 bytes with “x” are invalid data, and the lower 2 bytes with numbers 7 and 8 are valid data.
[0007]
The FIFO memory section is composed of four buffer memories # 1 to # 4 having a capacity of 8 bits × n words (n = 1, 2,...) Arranged in parallel, and 32 bits wide input data. Can be transferred in parallel. The number of buffer memories arranged in parallel is set according to the data bus line width.
[0008]
When writing the data stored in the transfer source RAM to the FIFO memory unit, as shown in FIG. 2A, first, the write pointer W and the read pointer R are cleared, and the write to the buffer memories # 1 to # 4 is performed. The read address and the read address are designated as “0”. In the figure, numbers 1, 2,... N attached to the upper part of the buffer memory # 1 indicate write / read addresses, and are common to the other buffer memories # 2, # 3, and # 4. Used for.
[0009]
Next, 4 bytes of the first word surrounded by a dotted line in the figure are written to the write addresses “0” of the buffer memories # 1 to # 4, respectively. Next, as shown in FIG. 2B, the write pointer W is incremented by 1 to designate the next write address “1”, and the 4 bytes of the second word surrounded by the dotted line are written. Next, as shown in FIG. 3C, the write pointer W is incremented by 1 to designate the next write address “2”, and the data of the third word surrounded by the dotted line is written. Through the above process, data for three words stored in the transfer source RAM is written into the buffer memories # 1 to # 4.
[0010]
When data is read, as shown in FIG. 4 (4), the data written in the buffer memories # 1 to # 4 are sequentially transferred from the read address “0” designated by the read pointer R to the transfer destination RAM. Sent to.
[0011]
[Problems to be solved by the invention]
As described above, when transferring data through a data bus line having a predetermined data width, a FIFO memory unit is configured by arranging a plurality of buffer memories corresponding to the data width in parallel. Process data in parallel. Conventionally, a write address to these buffer memories has been designated by one write pointer. Therefore, as described with reference to FIG. 6, even when 16-bit width data is input through the 32-bit width data bus line, one write pointer is allocated to all of the four buffer memories # 1 to # 4. Thus, the same write address is designated for all of the four buffer memories # 1 to # 4.
[0012]
Accordingly, 16-bit data is written in two buffer memories # 1 and # 2 of the four buffer memories, but transferred to the remaining two buffer memories # 3 and # 4. Invalid data that does not need to be written is written, or a vacancy occurs without data being written. That is, all the data including the invalid data described above are written and read out in the same order. As a result, there is a problem that the capacity of the FIFO memory unit is wasted for storing invalid data, and the effective transfer rate is lowered for writing / reading these invalid data.
[0013]
Accordingly, an object of the present invention is to improve the effective data transfer rate by enabling continuous transfer of data having different data widths.
[0014]
[Means for Solving the Problems]
In order to solve the above problem, in a FIFO memory control apparatus for writing / reading data input through a bus line having a predetermined data width, a FIFO memory unit in which a plurality of buffer memories corresponding to the predetermined data width are arranged in parallel , A plurality of write pointers for designating write addresses to the buffer memories, and the write pointers assigned to the buffer memories based on data width information of input data, and designated write addresses of the buffer memories A FIFO memory control device comprising a selector for selecting whether or not to write data to the buffer memory, and writing input data having an arbitrary data width into the respective buffer memories by using a write pointer allocated by the selector,
Alternatively, a data rearrangement unit that rearranges data between the buffer memories based on the data width information of the input data is provided, and the data written in each buffer memory is rearranged in the input order and read. This is achieved by the FIFO memory control device.
[0015]
In the present invention, a different write pointer can be allocated to each buffer memory, and whether to write data to a specified write address in each buffer memory can be selected based on the data width information of the input data. Therefore, for example, in the example described with reference to FIG. 6, when 16-bit width data is input through a 32-bit width data bus line, one write pointer is allocated to two buffer memories # 1 and # 2 and written. A 16-bit width data is written to this write address. If data is not written to the remaining two buffer memories # 3 and # 4, and the next input data is written, valid data without writing invalid data to each buffer memory. It becomes possible to write only by packing.
[0016]
In addition, when data having different data widths are written together, the relationship between the upper and lower bits of the input data may not be correctly reflected and stored in the buffer memory. Therefore, by rearranging the data stored in each buffer memory based on the data width information of the input data, the relationship between the upper bits and the lower bits can be corrected and read out to the outside.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of a FIFO memory control device according to an embodiment of the present invention. 1 is a block of 4 bits each having a capacity of 8 bits × n words (n = 1, 2,...). A FIFO memory unit in which buffer memories # 1 to # 4 are arranged in parallel, 2 is a write pointer control unit for controlling two write pointers W1 and W2 for designating write addresses to the buffer memories # 1 to # 4, 3 Allocates write pointers W1 and W2 to the buffer memories # 1 to # 4 based on the data width information of the input data, and selects whether to write data to the designated write addresses of the buffer memories # 1 to # 4. The selector 4 is a rearrangement code section for generating a rearrangement code for instructing rearrangement of data between the buffer memories # 1 to # 4 based on the data width information of the input data, and 5 is based on the rearrangement code. A data rearrangement unit for rearranging data between the buffer memories # 1 to # 4, 6 a data latch unit for latching data output from the data rearrangement unit 5, and 7 a read pointer for controlling the read pointer R It is a control unit.
[0018]
FIGS. 2 and 3 illustrate the flow of data when transferring three words of data from a transfer source RAM to a transfer destination RAM through a 32-bit data bus line using the FIFO memory control device. FIG. 2 is a diagram for explaining data writing and fixing, and FIG. 3 is a diagram for explaining a data reading process. Components having the same functions as those in FIG. Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0019]
First, as shown in FIG. 2 (1), 4 bytes of the first word surrounded by a dotted line stored in the transfer source RAM are inputted through the 32-bit bus line, and byte enable (BE) is synchronized with this. A signal and a write enable (WE) signal are input. The BE signal indicates data width information of input data.
[0020]
The BE signal input together with the input data of the first word is represented by “1100”, in which bits indicating whether the data from the least significant byte to the most significant byte are valid or invalid are arranged in order from the right. Here, bit “1” indicates valid data, and “0” indicates invalid data. Therefore, in the above BE signal, the data width of the input data of the first word is 16 bits, the upper 2 bytes with numbers 1 and 2 are valid, and the lower 2 with “x” attached. Indicates that the byte is invalid.
[0021]
The write pointer control unit 2 clears the write addresses designated by the write pointers W1 and W2 at the start of data transfer, sets them to “0”, and sends them to the selector 3. The selector 3 allocates the write pointers W1 and W2 sent from the write pointer control unit 2 to the buffer memories # 1 to # 4 based on the BE signal. That is, the selector 3 recognizes from the transmitted BE signal that the upper 2 bytes of the first word are valid and the lower 2 bytes are invalid, and writes to the buffer memories # 1 and # 2 storing the upper 2 bytes. The pointer W1 is allocated, and the write pointer W2 is allocated to the buffer memories # 3 and # 4 that store the lower 2 bytes. Then, an enable signal is sent to the buffer memories # 1 and # 2 in which the upper 2 bytes, which are valid data, are stored, and writing of data by the write pointer W1 is permitted. As a result, the upper 2 bytes are written in the buffer memories # 1 and # 2.
[0022]
Next, the write pointer control unit 2 is notified that data has been written by the write pointer W1, and the write pointer control unit 2 increments the write address of the write pointer W1 by one. On the other hand, the enable signal is not sent to the buffer memories # 3 and # 4 allocated to the lower 2 bytes which are invalid data, and the write address “0” is not changed. As described above, the upper 2 bytes that are valid data are written to the FIFO memory unit 1 and the lower 2 bytes that are invalid data are not written.
[0023]
Subsequently, as shown in FIG. 2 (2), the input data of the second word surrounded by the dotted line is sent. All 4 bytes of the input data of the second word are valid, and the BE signal is “1111”. The meaning of the BE signal is the same as described above. The selector 3 allocates the write pointer W1 to the buffer memories # 1 and # 2 that store the upper 2 bytes, and allocates the write pointer W2 to the buffer memories # 3 and # 4 that store the lower 2 bytes. Then, an enable signal is sent to all the buffer memories # 1 to # 4 to allow data writing. As a result, the upper 2 bytes are written to the write addresses “1” of the buffer memories # 1 and # 2, and the lower 2 bytes are written to the write addresses “0” of the buffer memories # 3 and # 4.
[0024]
Next, the write pointer controller 2 increments the write addresses of the write pointers W1 and W2 by one. As described above, the 4 bytes of the second word are written in the buffer memories # 1 to # 4, respectively.
[0025]
As shown in FIG. 3 (3), in the input data of the third word surrounded by a dotted line, the upper 2 bytes are invalid, the lower 2 bytes are valid, and the BE signal is “0011”. The selector allocates the write pointer W1 to the buffer memories # 1 and # 2 that store the upper 2 bytes, and allocates the write pointer W2 to the buffer memories # 3 and # 4 that store the lower 2 bytes. Then, an enable signal is sent only to the buffer memories # 3 and # 4 allocated to the lower 2 bytes, which are valid data, to permit data writing. As a result, the lower 2 bytes are written in the buffer memories # 3 and # 4, and the write pointer control unit 2 increments the write address of the write pointer W2. The enable signal is not sent to the buffer memories # 1 and # 2 allocated to the upper 2 bytes which are invalid data, and the write address “1” is not changed. As described above, the lower 2 bytes that are valid data are written in the FIFO memory unit 1, and the upper 2 bytes that are invalid data are not written.
[0026]
As described above, the data written using the two write pointers W1 and W2 is written in the FIFO memory unit 1 in a state in which the relationship between the upper and lower bits of each word is not correctly reflected. Therefore, a rearrangement code for instructing data rearrangement is generated based on the BE signal, and at the time of reading, data is rearranged using the rearrangement code, and is output and sent to the transfer destination RAM. That is, as shown in FIG. 3, the data stored in the address “0” of the buffer memories # 1 and # 2 is the lower byte and is stored in the address “0” of the buffer memories # 3 and # 4. Since it can be recognized from the BE signal that the data is the upper byte, a rearrangement code for rearranging the upper 2 bytes and the lower 2 bytes is created and stored in the rearrangement code unit 4. At the time of reading, the data stored in the address “0” of the buffer memories # 1 to # 4 together with the above rearrangement code is input to the data rearrangement unit 5, and the lower 2 bytes and the upper 2 bytes are arranged. Replacement is performed. Thereafter, the data is rearranged in the same manner, so that the relationship between the upper bits and the lower bits is corrected and sent to the transfer destination RAM.
[0027]
Note that the reading process described above is performed by assigning the read pointer R to the buffer memories # 1 to # 4. In FIG. 1, the read pointer control unit 7 assigns addresses to the buffer memories # 1 to # 4 and reads data and data. However, since the operation of the read pointer R is the same as that of the conventional example, the description of the operation and the signal lines in FIG. 1 are omitted here.
[0028]
The above embodiment shows a case where data of 32 bit width and 16 bit width are mixed and transferred, and the transfer of invalid data can be prevented by using two write pointers. When width data are mixed, the same effect can be obtained by using three or more write pointers.
[0029]
【The invention's effect】
As described above, according to the present invention, when data is serially transferred using a FIFO memory, only valid data can be transferred without transferring invalid data. Data can be transferred continuously, which is useful for improving the effective data transfer rate.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a FIFO memory control device according to the present invention. FIG. 2 is a diagram for explaining a data write process to a FIFO memory unit. FIG. 3 is a diagram for explaining a data read process from a FIFO memory unit. FIG. 4 is a block diagram showing a configuration of a data transfer system. FIG. 5 is a block diagram showing a configuration of a conventional FIFO memory control device. FIG. 6 is a diagram explaining a conventional data writing / reading process.
1, 16 FIFO memory section 7 Read pointer control section 2 Write pointer control section 11 Processor 3 Selector 12 Transfer source RAM
4 Rearrangement code section 13 FIFO memory control device 5 Data rearrangement section 14 Transfer destination RAM
6 Data latch 15 DMAC

Claims (2)

In a FIFO memory control device for writing / reading data input through a bus line having a predetermined data width,
A FIFO memory unit in which two or more buffer memories corresponding to the predetermined data width are arranged in parallel;
The 2 and more write pointer for designating a write address to the buffer memory,
Based on the data width information of the input data, among the two or more buffer memories, and a buffer memory corresponding to valid data, in the buffer memory corresponding to the invalid data, with each assigned the write pointer, the effective comprising a selector which enables writing data to the write address specified in the buffer memory corresponding to such data, and
The input data of arbitrary data widths, FIFO memory controller, wherein the write pointer allocated by said selector by writing packed to the each buffer memory. A data shuffle play unit for rearranging data between the respective buffer memory on the basis of the data width information of the input data,
2. The FIFO memory control device according to claim 1, wherein the data written in each of the buffer memories is read out in the order of input.

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