JP3930582B2 - Plasma display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display panel.
[0002]
[Prior art]
FIG. 8 is an exploded perspective view of a general surface discharge type plasma display panel (PDP), and shows a basic structure corresponding to one pixel. On the inner surface of the glass substrate 901 serving as a display surface, row electrode pairs 902 and 902 are formed which are composed of a wide transparent electrode 902a made of a transparent conductive film and a bus electrode 902b made of a metal film that supplements the conductivity. A dielectric layer 904 and an MgO layer 905 are stacked thereon.
[0003]
On the other hand, column electrodes 907 are formed on the glass substrate 906 on the back side in a direction orthogonal to the row electrodes 902 and 902. Ribs 910 are provided between the column electrodes, and a phosphor layer 908 is formed so as to cover the column electrodes and the ribs. A mixed gas such as Ne or Xe is sealed in the discharge space 909 between the two substrates 901 and 906.
[0004]
Such PDP display control is performed as follows.
First, when a reset write pulse is applied to a pair of row electrodes, a discharge is generated between the paired row electrodes, and wall charges are accumulated and formed on the dielectric layer after the end of the discharge. Next, when a pixel data pulse is applied to the column electrode and a scan pulse (selective erase pulse) is applied to one row electrode of the row electrode pair, a discharge is generated between the column electrode and the row electrode, and the dielectric layer is The wall charges are selectively eliminated, and pixel data is written. Next, when sustain pulses are alternately applied to the pair of row electrodes, only the pixels in which the wall charges remain are discharged, and the discharge is maintained. Next, when an erasing pulse is applied to the row electrode, a discharge occurs, the wall charges disappear, and the sustain discharge stops.
[0005]
[Problems to be solved by the invention]
In the above PDP, generally, the line widths of the row electrode pairs 902 and 902 are equal, and wall charges having substantially the same absolute value are accumulated and formed on the pair of row electrodes 902 and 902 by the discharge by the reset write pulse. When writing pixel data, this wall charge works to enhance the electric field strength in the discharge space, so that the voltage of the pixel data pulse can be reduced.
In this way, when the voltage of the pixel data pulse is lowered, it is necessary to increase the electric field strength in the discharge space by increasing the discharge due to the reset write pulse to increase the amount of wall charges on the row electrode pair. As a result, the potential difference between the row electrodes increases, and unnecessary discharge is likely to occur between the row electrodes. On the other hand, in order to prevent unnecessary discharge between the row electrodes, it is necessary to weaken the discharge due to the reset write pulse to reduce the wall charge amount on the row electrode pair and to reduce the potential difference between the row electrodes. Then, it is necessary to increase the voltage of the pixel data pulse in order to stabilize the discharge between the column electrode and the row electrode, resulting in an increase in the cost of the column electrode driving IC.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a plasma display panel capable of stable display operation at low cost.
[0006]
[Means for Solving the Problems]
The plasma display panel according to claim 1 has a plurality of row electrode pairs and a plurality of column electrodes that are spaced apart from and orthogonal to the row electrode pairs, and a unit light emitting region at the intersection of the row electrode pairs and the column electrodes. The plasma display panel is configured to select light emission of the unit light emitting region by one row electrode and column electrode of the row electrode pair, and the plasma display panel of the row electrode pair in the unit light emitting region emits light. The area of one row electrode to be selected is made smaller than the area of the other row electrode.
[0008]
[Action]
The area of the pair of row electrodes in the unit light emitting region is made different, and write discharge is generated between the row electrode and the column electrode having a smaller area.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration of a plasma display panel driving apparatus according to the present invention. In FIG. 1, an input video signal is obtained by separating and extracting an R video signal corresponding to a red video component, a G video signal corresponding to a green video signal component, and a B video signal corresponding to a blue video component. / D conversion circuit 3 is supplied. The sync separation circuit 1 extracts horizontal and vertical sync signals from the video signal and supplies them to the timing pulse generation circuit 2. The timing pulse generation circuit 2 generates various timing pulses based on these horizontal and vertical synchronization signals. The A / D conversion circuit 3 synchronizes the R video signal, the G video signal, and the B video signal with the digital R pixel data, G pixel data, and B respectively in synchronization with the timing pulse supplied from the timing pulse generation circuit 2. These are converted into pixel data and supplied to the frame memory 4.
[0010]
The memory control circuit 5 supplies a write signal and a read signal synchronized with the timing pulse supplied from the timing pulse generating circuit 2 to the frame memory 4. The frame memory 4 sequentially captures each pixel data supplied from the A / D conversion circuit 3 in response to the write signal. Further, the frame memory 4 sequentially reads out pixel data stored in the frame memory 4 in response to the readout signal and supplies it to the output processing circuit 6 at the next stage.
[0011]
The read timing signal generation circuit 7 generates a timing signal corresponding to the pixel data pulse supply timing and supplies it to the output processing circuit 6.
The read timing signal generation circuit 7 applies to the PDP 11 a scan pulse for starting the discharge light emission, a sustain pulse for maintaining the discharge state, and an erasing pulse for stopping the discharge light emission in order to perform the discharge light emission. Supply timing signals are generated and supplied to the row electrode drive pulse generation circuit 10. The output processing circuit 6 generates pixel data corresponding to each subfield divided for each field of pixel data supplied from the frame memory 4, and synchronizes these with the timing signal from the read timing signal generation circuit 7. To the pixel data pulse generation circuit 12.
[0012]
The row electrode drive pulse generation circuit 10 generates the scan pulse, the sustain pulse, and the erase pulse in response to the various timing signals supplied from the read timing signal generation circuit 7 to generate the row electrodes Y _{1 to} Y of the PDP 11. supplied to the _n and _X 1 to X _n. The pixel data pulse generation circuit 12 generates pixel data pulses having voltage values corresponding to logic “1” or “0” of pixel data for one field supplied from the output processing circuit 6, and outputs this pixel data pulse for each row. The pixel data pulse for each divided row is applied to the column electrodes D _{1 to} D _{m in a} time division manner.
[0013]
The PDP 11 starts discharge light emission corresponding to the pixel data pulse when the scan pulse is applied from the row electrode drive pulse generation concave 10, and this light emission state is maintained over the period during which the sustain pulse is applied. maintain. Thereafter, the discharge light emission is stopped by applying the erase pulse from the row electrode drive pulse generation circuit 10. Thus, the row electrode drive pulse includes a scan pulse, a sustain pulse, an erase pulse, and the like.
[0014]
FIG. 2 is a diagram showing the timing of the drive pulse signal of FIG. In FIG. 2, first, a negative voltage reset address pulse RPx is applied to all the row electrodes X _{1 to} X _n from the driving device, and simultaneously, a positive voltage reset address pulse RPy is applied to each of the row electrodes Y _{1 to} Y _n . Apply. By applying such a reset address pulse, a discharge is generated between all the row electrode pairs of the PDP. By this discharge, charged particles and excited particles are generated in each pixel cell, and wall charges are accumulated and formed after the discharge ends.
[0015]
Next, the pixel data pulses DP _{1 to} DP _n corresponding to the pixel data for each row are sequentially applied from the driving device to the column electrodes D _{1 to} D _m . From the driving device, the selective erasing pulse SP is sequentially applied to the row electrodes Y ₁ to Y _n in synchronization with the application timing of the pixel data pulses DP _{1 to} DP _n . At this time, discharge is generated only in the pixel cells to which the pixel data pulse DP and the selective erasing pulse SP are simultaneously applied to the column electrode and the row electrode, respectively, and most of the wall charges formed by the reset address disappear. On the other hand, in the pixel cell to which the selective erasing pulse SP is applied but the pixel data pulse DP is not applied, the discharge as described above does not occur. It is selectively erased according to the contents.
[0016]
Then, from the drive unit, together with the positive polarity sustain pulse IPx continuously applied to each of the row electrodes X ₁ to X _n, and the application timing of the sustain pulses IPx, at shifted timings positive the sustain pulse IPy are continuously applied to the respective row electrodes _Y 1 to Y _n. Only the pixel cells in which the wall charges remain over the period in which the sustain pulse is continuously applied maintain the discharge light emission.
Next, the drive apparatus, by applying a sustain erase pulse EP people to the row electrodes X ₁ to X _n respectively, allowed to stop the sustain discharge.
[0017]
FIG. 3 shows the structure of the PDP 11 described above. On the inner surface of the glass substrate 901 serving as a display surface, a pair of row electrodes 302 including wide transparent electrodes 302a and 303a made of a transparent conductive film and bus electrodes 302b and 303b made of a narrow metal film to supplement the conductivity. 303 are formed, and a dielectric layer 904 and an MgO layer 905 are stacked thereon. On the other hand, column electrodes 907 are formed on the glass substrate 906 on the back side in a direction orthogonal to the row electrode pairs 902 and 902. Ribs 910 are provided between the column electrodes, and a phosphor layer 908 is formed so as to cover the column electrodes and the ribs. A mixed gas such as Ne—Xe is sealed in the discharge space 909 between the two substrates 901, 906.
Here, when writing pixel data, the row electrode 302 (for selecting (addressing) the light emission of the unit light emission region EC with the column electrode 907 (corresponding to the column electrodes D _{1 to} D _m in FIGS. 1 and 2). The width l ₁ (area) of the row electrodes Y _{1 to} Y _n in FIG. 1 and FIG. 2 is the other row electrode (rows in FIG. 1 and FIG. 2) paired as shown in FIG. It is narrower than the width l ₂ (area) of the electrodes X _{1 to} X _n .
[0018]
Next, the operation of the PDP having the row electrode pair structure will be described.
First, after the discharge by the reset write pulses RPx and RPy is completed, wall charges having the same absolute value are accumulated and formed on the dielectric layers on the row electrodes 302 and 303. The area of the row electrode 302 is the area of the row electrode 303. Since it is smaller, the wall charge density on the row electrode 302 becomes larger than the wall charge density on the row electrode 303.
Then, the effect of enhancing the electric field strength between the column electrode 907 and the row electrode 302 becomes larger than when the area of the row electrode pair is equal, and the application of the pixel data pulse and the selective erasing pulse (scanning pulse). At this time, discharge between the column electrode 907 and the row electrode 302 is likely to occur, and the address operation is stabilized. On the other hand, since the electric field strength between the row electrodes 302 and 303 is the same as when the area of the row electrode pair is equal, no unnecessary discharge occurs between the row electrodes 302 and 303.
[0019]
In the above embodiment, as an example in which the area of the row electrode pair in the unit light emitting region is made different, the widths l ₁ and l ₂ of the paired row electrodes 302 and 303 are made different. Even when the shape shown in FIG. 7 is adopted, the same effect as in the above embodiment is exhibited.
In FIG. 5, the pair of row electrodes 402 and 403 in the unit light emission region EC have protrusions facing each other, and the length l ₁ of the protrusion of the row electrode 402 for selecting light emission is set to the protrusion of the row electrode 403. It is smaller than the length l ₂ of the.
In FIG. 6, similarly to FIG. 5, the pair of row electrodes 502 and 503 in the unit light emission region EC have protrusions facing each other, and the length l ₁ and width of the protrusions of the row electrode 502 that selects light emission. W ₁ is made smaller than the length l ₁ and the width W ₂ of the protruding portion of the row electrode 503.
In FIG. 7, the row electrodes 602 and 603 that make a pair in the unit light emission region EC have T-shaped protrusions facing each other in the same manner as in FIG. 5, and the width of the protrusion of the row electrode 602 that selects light emission is wide. The length d ₁ of the tip end portion is made smaller than the length d 2 of the wide tip end portion of the protruding portion of the row electrode 603.
[0020]
Further, in the above-described embodiment, an example in which the area of the row electrode pair in the unit light emitting region is made different is shown. However, the electric capacity of the dielectric layer on the row electrode that makes a pair in the unit light emitting region EC is made different. However, the same effect as the above embodiment is exhibited.
That is, in the dielectric layer on the row electrode that makes a pair in the unit light emitting region EC, the electric capacity of the dielectric layer on the row electrode that selects light emission is more than the electric capacity of the dielectric layer on the other row electrode. By enlarging, it is possible to increase the wall charge density on the row electrode where light emission is selected, thereby enhancing the effect of increasing the electric field strength. Specifically, the dielectric constant of the dielectric layer on the row electrode for selecting light emission is set to be larger than the dielectric constant of the dielectric layer on the other row electrode forming a pair.
[0021]
According to the PDP of the present invention, by selecting the light emission among the paired row electrodes in the unit light emitting region, the area of one row electrode is made smaller than the area of the other row electrode, thereby selecting the light emission. Since the wall charge density on the electrode is increased and the electric field strength enhancement effect is increased, the column electrode driver can be manufactured at low cost and a stable display operation can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a driving device for a plasma display panel according to the present invention.
FIG. 2 is a diagram illustrating timings of drive pulse signals in FIG.
FIG. 3 is a view showing a row electrode structure of the plasma display panel of the present invention.
FIG. 4 is a view showing a row electrode structure of another embodiment of the plasma display panel of the present invention.
FIG. 5 is a view showing a row electrode structure of another embodiment of the plasma display panel of the present invention.
FIG. 6 is a view showing a row electrode structure of another embodiment of the plasma display panel of the present invention.
FIG. 7 is a view showing a row electrode structure according to another embodiment of the plasma display panel of the present invention.
FIG. 8 is a diagram showing a configuration of a panel portion of a conventional plasma display panel.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Sync separation circuit 2 ... Timing pulse generation circuit 3 ... A / D conversion circuit 4 ... Frame memory 5 ... Memory control circuit 6 ... ... Output processing circuit 7 ... Read timing signal generation circuit 10 ... Row electrode drive pulse generation circuit 11 ... PDP
12... Pixel data pulse generation circuits 302 and 303... Row electrodes 302 a and 303 a... Transparent electrodes 302 b and 303 b. 902, 903... Row electrodes 902a, 903a... Transparent electrodes 902b, 903b... Transparent electrodes 904 .. Dielectric layer 905. ... Back glass substrate 907 ... Column electrode 908 ... Phosphor layer 909 ... Discharge space 910 ... Rib

Claims (1)

  A plurality of row electrode pairs and a plurality of column electrodes spaced apart and orthogonal to the row electrode pairs, wherein a unit light emitting region is defined at an intersection of the row electrode pairs and the column electrodes, and one of the row electrode pairs A plasma display panel configured to select light emission of the unit light-emitting region by the row electrode and the column electrode, wherein one of the row electrode pairs in the unit light-emitting region selects light emission. A plasma display panel characterized in that the area of the row electrode is smaller than the area of the other row electrode.

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