JP3924389B2 - Signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing apparatus that stores variable-length code data in a fixed area or efficiently performs reverse processing.
[0002]
[Prior art]
In recent years, VTRs that record video / audio signals on a magnetic tape or the like as digital signals have attracted attention. The digital VTR has been rapidly spread as a portable device such as a video camera, and low power consumption is demanded from the position as a portable device.
Moreover, since it is digitized, data is compressed by a high-efficiency encoding technique. When a very large amount of information such as a moving image is handled, a compression technique is important, and a method using a plurality of compression techniques such as orthogonal transformation, quantization, and variable length coding is the mainstream. When moving image data converted into a variable length code by compressing the zero run value and the amplitude value is stored on a magnetic tape or the like, the data is stored in a fixed length. What is needed at this time is formatting, and vice versa for playback.
Deformat processing that is the above processing is necessary.
[0003]
Data encoded in a variable length code is formatted according to the rules described below. The four luminance signals and the two color difference signals are collectively referred to as a macro block. The luminance signal has a fixed area of 16 bits × 7 words, and the color difference signal has a fixed area of 16 bits × 5 words, and each one is called DCT. 1DCT has a maximum of 64 variable-length code data, and finally has a 4-bit end-of-block code (EOB) indicating a delimiter. The five macroblocks are collectively called a video sync, and the format processing is performed in units of one video sync.
[0004]
1 video sync = 5 macroblocks
1 macroblock = 4 DCT (luminance signal) +2 DCT (color difference signal)
1 DCT (luminance signal) = 7 words
1 DCT (color difference signal) = 5 words
1 word = 16 bits
[0005]
The formatting process
(STA0) The variable-length code data is concatenated in word units as much as possible in the fixed area corresponding to the DCT number and written in order. The data stored at this time is referred to as “LAC”.
(STA1) The variable length code data that could not be stored in the fixed area of the same macroblock is concatenated and stored in units of words from the smallest DCT number in the free area of the fixed area in the same macroblock. At this time, the stored data is referred to as “HAC0”.
[0006]
(STA2) The variable length code data that could not be stored by the processing of (STA1) is stored in the space area of the fixed area in the video sync in units of words starting from the smallest DCT number. At this time, the stored data is referred to as “HAC1”.
It is performed in the procedure. Further, the deformatting process is the reverse process.
As one method for performing the above format / deformat processing, the following signal processing apparatus has been proposed.
[0007]
Figure 6 These are block diagrams of the conventional signal processing apparatus. Figure 6 101, 102 are terminals, 103 is a first data controller, 104 is a first address controller, 105 is a second data controller, 106 is a second address controller, and FRAM 108 and VRAM 109 are Memory for use in the deformatting process, FPRAM 107 and VPRAM 110, are memories used as pointers for FRAM 108 and VRAM 109, respectively.
[0008]
The format procedure according to the prior art is shown below.
The variable length code data input from the terminal 101 is connected in word units by the first data controller 103. An EOB signal is added at the end of the DCT, and the EOB signal is also connected in units of words.
First, data is written in the fixed area on the FRAM 108 until the fixed area is filled. When the fixed area is filled, data is written into the VRAM 109. In STA 0, only 1 DCT data is written in the fixed area on the FRAM 108. In the fixed area of the FRAM 108, the luminance signal has a larger capacity than the color difference signal. Since the amount of data to be finally stored in the FRAM 108 is (5 macroblocks) × (4 × 7 words (luminance signal) + 2 × 5 words (color difference signal)) = 190 words, the VRAM 109 is most necessary. In this case, the data of the three color difference signals is very large, and the other 27 DCT data are only the DC component and EOB. Therefore, (5 macroblock total capacity)-(27 DCT DCT + EOB)-(color difference signal 3 capacity) + (VRAM free capacity) = 190 words-27 * (12 bits + 4 bits) -3 * 5 words + 3 words = 151 words are required. As for 3 words in the gap area of VRAM 109, the last data is 1 as a result of adding EOB.
This area is provided only for storing EOB data that exceeds 6 bits and cannot be stored in the last data area.
[0009]
Next, a method for storing data in the VRAM 109 will be described. Of the data amount that can be stored in one macroblock, the maximum data amount of HAC0 and HAC1 that can be stored in the VRAM 109 without entering the fixed area of the FRAM 108 is very large because the data amount of one color difference signal is very large. Since the signal and color difference signal are only DC components, (1 macroblock capacity) − (DC component + EOB) × 5− (one color difference signal) = 38 words−5 words−5 words = 28 words is there. Writing data to the VRAM 109 is shown in the figure. 7 As shown in FIG. 5, 28 words at the maximum are stored for each macroblock, and data exceeding 28 words is stored in order from the end. However, if the address stored from the head matches the address stored from the rear, the data stored from the head is prioritized and the data from the end is discarded. Even if the data stored from the end is already stored, if data is written from the beginning, it is overwritten with priority. The discarded or overwritten data is originally unnecessary because there is no space to store in the FRAM 108. As described above, the start address of the storage position of the macroblock unit of the data stored in the VRAM 109 based on the first address controller is stored in the VPRAM 110.
[0010]
Next, the second data controller 105 detects the final position of data stored in the fixed area of the FRAM 108, that is, EOB, and stores it in the FRAM 107 for each DCT block. When EOB is detected, the next head position of EOB and a flag indicating that EOB has been detected are stored in FPRAM 107. When all the fixed areas are filled, a flag indicating that the last position of the last data and EOB has not been detected is stored in the FPRAM 107. Then, based on the information stored in the FPRAM 107 and the VPRAM 110, the second data controller 105 packs the data of the VRAM 109 into the free area of the fixed area.
[0011]
Next, the procedure of the deformatting process according to the prior art is shown below. The deformatting process is the reverse process of the formatting process. The second data controller 105 reads the variable length code data from the FRAM 108, and another DCT data stored in the same macroblock from this data is stored in units of words from the top of the VRAM 109. At this time, if an EOB code is detected, the remaining area is skipped and HAC0 of the next DCT is stored. The storage information of HAC0 is stored in the VPRAM 110 in units of macro blocks. Next, HAC1 stored in another macroblock is written in the empty area at the last address stored in the same macroblock, and then stored from the end of the VRAM 109. The storage start position in the tail direction is stored in the VPRAM 110 in units of macroblocks.
The variable length code data stored in the FRAM 108 is controlled by the first address controller 104 and output to the outside. The first address controller 104 reads DCT variable length encoded data from the FRAM 108 and the VRAM 109 in units of words based on the information stored in the VPRAM 110.
[0012]
[Problems to be solved by the invention]
In the signal processing apparatus described above, the data that could not fit in the fixed area during the formatting operation is temporarily stored in the VRAM 109, but the data always includes EOB. For example, the figure 7 As shown in FIG. 6, the DCT2 and DCT5 overflow data requires an extra area for one word only for EOB. However, since EOB is a fixed bit string, it is not necessary to store the data itself in the VRAM 109 as long as the bit length is known. That is, the capacity added to the VRAM 109 for EOB processing is not necessary. In the prior art, the search process is performed again by means of detecting EOB by the second data controller 105 after data is once stored in the FRAM 109. This processing is performed when the first data controller 103 stores data in the FRAM 108.
Since the information indicating where the final data of the RAM 108 is or where all the data is filled is known, it is troublesome twice.
[0013]
Further, the high frequency data HAC0 and HAC1 that did not fit in the fixed area during the deformatting operation are temporarily stored in the VRAM 109. However, since the data itself is already stored in the FRAM 108, it is not necessary to re-store the data that has not completely entered the fixed area in the VRAM 109.
In view of the above, an object of the present invention is to provide a signal processing apparatus capable of reducing the capacity of an essentially unnecessary VRAM 109 memory and suppressing unnecessary data.
[0014]
[Means for Solving the Problems]
Book The signal processing device of the invention is a signal processing device for returning data stored in a fixed area with a fixed bit width to variable-length code data, a first table for detecting a bit length and an end-of-block code from input data, The fixed length data input to the device is stored in the first memory, the first memory data is input to the first table to obtain the bit length and the end-of-block code, and the information is stored in the third memory. A first data controller for storing, a second table for detecting a bit length and an end-off block code from the input data, and reading the data in the first memory in the order of the information stored in the third memory; A second data controller for inputting variable length code data to the second table is provided.
[0015]
As a result, only the information indicating where the last data in the fixed area is stored is stored in the third memory, so that the second memory used in the format is essentially unnecessary.
A second memory functioning as a FIFO, wherein the second table has means for detecting a zero run value and an amplitude value of the input data, and the second data controller includes a zero run value from the second table and By outputting the output data of the amplitude value through the second memory, it is possible to adjust the output timing by using the second memory that is not used in the deformatting process as an output buffer.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings.
FIG. 1 shows the present invention. The fruit It is a block diagram of a signal processing device in an embodiment. In FIG. 1, 1 is an input terminal, 2 is an output terminal, 3 is a first data controller, 4 is a second data controller, 5 is a second memory (hereinafter referred to as FRES), and 6 is a first data controller. A memory (hereinafter referred to as FBUF), 7 is a third memory (referred to as FINF), 8 is a first table, and 9 is a second table. FBUF6, FRES5, and FINF7 are each composed of two memories of the same capacity, and store VLC data, overflow data, and pointers to FBUF6 / FRES5, respectively. The data flow during the formatting operation is indicated by a solid line, and the data flow during the formatting operation is indicated by a broken line.
[0017]
In the present embodiment, the minimum bit length of the variable-length encoded data is 3 bits, the maximum bit length is 16 bits, and the end-of-block code (hereinafter referred to as EOB) representing the end of the block is 4 bits. The number of words in FBUF6 is 190 words. The number of words of FRES5 becomes the maximum when the three color difference signals do not completely enter the fixed area and the other luminance / color difference signals are composed of data of only the DC component, so (6 words × 20) + (4 words X7) = 148 words. The number of words in FINF 7 is (total number of DCTs) + (5 macroblocks × 2).
[0018]
The format operation of the signal processing apparatus of the present invention configured as described above will be described.
Light up. In the formatting operation, the VLC data input from the input terminal 1 is stored in an area as shown in FIG. FIG. 2 has a data width of 16 bits and five macroblock areas. Each macroblock has a total of 38 words, 4 luminance signal areas of 7 words and 2 color difference signal areas of 5 words, for a total of 190 words. In this embodiment, it corresponds to FBUF6.
[0019]
The format processing procedure is shown below.
(1) The variable length code data is first concatenated every 16 bits by the first data controller 3. Data concatenated to 16 bits is stored in the corresponding fixed area in the FBUF 6 as much as possible, that is, up to 7 words for the luminance signal and up to 5 words for the color difference signal. Data that could not be stored in the FBUF 6 is stored in the FRES 5. In FRES5, up to a certain number of words per macroblock is stored in order from the front, and thereafter stored from the back of FRES5.
[0020]
The number of words stored from the front (2) The maximum value stored in the same macroblock, which is performed in the above process, may be used. The maximum value is that four luminance signals and one color difference signal are only DC components, that is,
DC component (12 bits) + EOB (4 bits) = 16 bits = 1 word
Since the other of the color difference signals has very large data and is sent to another DCT,
Maximum value = maximum empty area of luminance signal × 4 + maximum empty area of color difference signal
= 6 words x 4 + 4 words = 28 words
It is. In addition, when data is already written from the rear of FRES5 and there is no free area in FRES5 when processing different macroblocks, the writing from the front is overwritten. There is no problem because the overwritten data is data that cannot be stored in the FBUF 6 from the beginning. This principle is the same as the conventional method. After one DCT process is completed, a flag indicating the location of the final data ('0': FBUF5, '2' in FRES5 (write from the front) corresponding to the DCT being processed is shown in FIG. ), '4' FRES5 (write from behind) and '6' FRES5 is full and data is discarded), and the address and bit length of the final data are stored.
Further, before starting the processing of one macroblock, the head address in FRES5 used by each macroblock is stored in an area called MB (S) in FIG.
[0021]
(2) Data in FRES5 is stored in a free area of a fixed area in the same macroblock. First, MB (S) data is read from the FINF 7 for each macroblock. This is the head address of the write data from the front of FRES5, and the data of FRES5 is read sequentially from address MB (S). Next, the FINF7 flag is searched in ascending order of DCT number. When the flag is “0”, there is an empty area for storing other DCT data. When the flag is “1” to “6”, it means that the data cannot be stored in the fixed area. Therefore, it is only necessary to sequentially connect the data having the flags “1” to “6” to the last data of the DCT having the flag “0”. This process is continued until there is no free area in the FBUF 6 assigned to the DCT with the flag “0” or there is no data in the FRES 5. When one of them disappears, the flag is updated, the next flag is searched for a macroblock with “0” or “1” to “6”, and the same processing is continued until both are not searched. When one macroblock processing is completed, the current address and bit length of FRES5, that is, the boundary between the data already stored in FBUF6 and the data not yet stored, is stored in the area MB (E) of FINF7. .
[0022]
(3) In the free area of the fixed area in the same video sink, (2) Store unused data in the process. The content of the process is (2) And the same for every video sink
The point is different. The FRES5 data starts with the address of MB (E), the data up to MB (S) +27 is data from the front, and the data thereafter is data from the rear. The data of FRES5 is read in this order.
[0023]
(4) Data in the FBUF 6 is output every 8 bits in order from the top.
This completes the formatting operation for one video sync. The two memories are provided because the second data controller accesses the other memory while the first data controller is accessing one of the memories. That is, each memory is used alternately for each video sync.
[0024]
Next, in this signal processing device Fruit Explanation of the embodiment . Real The embodiment relates to a deformatting process during reproduction. FIG. 1 is a block diagram of a signal processing apparatus according to the present invention. In The The data flow is indicated by broken lines in the figure.
The deformatting process is performed according to the following procedure.
(1) Data is written from the terminal 2 in order from the head address of the FBUF 6.
[0025]
(2) The EOB is searched for the fixed area of each DCT. That is, data is sequentially read from the fixed area corresponding to each DCT, and the bit length and EOB are detected by LCTBL9.
(a) Read the first data from the fixed area.
(b) The data of (a) is shifted to the MSB side by 12 bits. This is because the EOB detection is skipped with a DC component in which EOB cannot exist. At the same time, the next fixed area data is read.
(c) Concatenate two data and input to LCTBL9. In LCTBL9, this data
The bit length and the presence or absence of EOB are checked. Then, the data is shifted to the MSB side by the bit length detected by LCTBL9.
(d) The data is connected from the fixed area and the bit length and EOB are detected by LCTBL9.
Repeat the process. This process is repeated until EOB is detected or all the data in the fixed area is examined.
[0026]
When the EOB is found after the above processing is completed, the flag “0” indicating that the EOB has been found, the address where the EOB was found, and the remaining code length are recorded. When the EOB is found and the EOB is found at the end of the fixed area (that is, the data is completed in the fixed area), the flag “7” is recorded in the corresponding FINF 7. If it is not found, the final address and the bit length of the remaining data are recorded in the FINF 7 as the flag “1” indicating that it was not found and the position information of the uninspected data in the fixed area.
[0027]
(3) Based on the information of FINF7, EOB is detected in the same macroblock.
First, in ascending order of DCT numbers flag Detects DCT of '0' and '1', respectively. Figure 4 The operation at this time will be described with reference to FIG.
When the DCTs with the flags in the FINF 7 of “0” and “1” are searched in ascending order of the DCT numbers, DCT2 and DCT0 are respectively searched. Therefore, it can be seen that the data following DCT0 is in DCT2. Now, it can be seen that the data of the DCT 2 itself is the position of A2 in the figure from the address and bit length information in the FINF 7, and the data after that is data of other DCT. Further, it can be seen from the address of FINF7 of DCT0 and the bit length information that the data D0 after the position of A0 is uninspected data and the data is connected to another DCT. Since the continuation of D0 is D2, the flag of the FINF7 data of DCT0 is set to “7”, and the address and bit length data are replaced with those of the FINF7 of DCT2.
[0028]
Now that the connection of data is known, the data are connected and EOB is detected by LCTBL9. This procedure is the same as (2).
When EOB of DCT0 is found in the data of DCT2, the FINF6 of DCT2 is updated to the flag “0”, the address and bit length of the position of EOB, and the DCT whose next flag is “1” is searched. Then, the DCT0 EOB data after DCT0 in DCT2 is connected to the unconfirmed DCT data found, and EOB is detected by LCTBL9. Conversely, if no EOB is found, the flag “1” and the address and bit length of unsearched data at this time are stored in the FINF 6 of the DCT 2. Then, a DCT whose flag is “0” is searched, data after EOB is connected to unconfirmed data in DCT2, and EOB is detected. Thus, the process continues until both the flag “0” and “1” are not searched.
[0029]
(4) Based on the information of FINF7, EOB is detected as a whole. The processing content is the same as (3) except that the processing unit is changed from the macro block of (3) to video sync.
The processing from (1) to (4) is performed by the second data controller.
[0030]
(5) Based on the information of FINF7, the data of FBUF6 is sequentially output. This process is performed by the first data controller.
As a result of the processing up to (4), information on where the next data of each fixed area is in the FBUF 6 or information that there is no next data is stored in the FINF 7, and therefore the DCT number is small. If data is read sequentially from its own fixed area and processed to the end of the fixed area, and EOB is not detected, EOB is detected even though there is no next data from the information of FINF7 Is not detected, EOB is forcibly output and the next DCT processing is performed. Note that according to this method, the FRES 5 of FIG. 1 is not used.
[0031]
By the way, as a result of performing the deformatting process according to the second embodiment, for example, FIG. 5 As shown in the figure, in the worst case, 16-bit data is divided into 1-bit data. That is, one data may be distributed at 16 locations on the FBUF 6. That is, when an ordinary RAM that can process only one word in one cycle is used as the FBUF 6, it means that 16 cycles are necessary to reconstruct one output data at worst. Of course, if the output timing is not specified, there is no problem even if the data is output to the terminal 1 as it is, but if the output requires real-time property, the data cannot be prepared when necessary. Can happen.
When real-time property is required, the present invention is as follows. In the case of the deformatting process, FRES5 is not used at all. Therefore, instead of outputting the output of the first data controller to the terminal 1 as it is, the FRES 5 is used as a FIFO and is output there.
[0032]
Now, the bit width of FRES5 is 16 bits. The data itself is a 3-16 bit variable length code. For this reason, only data is stored as it is, and the bit length cannot be recorded. The variable length code is decoded into a zero run value and an amplitude value after the deformatting process. For example, if the zero run value is 6 bits and the amplitude value is 9 bits, only 15 bits are required. Therefore, when searching for the bit length and EOB code in RATBL8, the zero run value and the amplitude value are also searched at the same time, and if the output is the zero run value and the amplitude value, it can be kept within 16 bits of FRES5. Further, since FRES5 is a memory that was not originally used in the deformatting process, it is not necessary to add a new memory.
[0033]
In this embodiment, the description has been made assuming that the code length is 3 to 16 bits, EOB is 4 bits, and the processing unit is 16 bits. However, in other cases, the processing unit, the number of bits, and the number of words are changed. The present invention can be adopted simply by doing. In this embodiment, 1 video sync = 5 frames.
It is assumed that the black block = 5 × (4 luminance signal + 2 color difference signal) = 5 × (4 × 7 words + 2 × 4 words). For example, 1 video sync = 5 macroblock = 5 × (6 luminance signal + 2 color difference signal) ) = 5 × (6 × 5 words + 2 × 4 words), etc., the present invention can be adopted only by changing the fixed area of FBUF6, the number of words to be written from the front of FRES5 during the formatting operation, and FINF7.
[0034]
【The invention's effect】
As described above, by using the present invention, it is possible to suppress a useless increase in memory capacity for storing data that could not be stored in the fixed area caused by EOB addition. In addition, since the first data controller stores the end address and bit length of FBUF 6 in FINF 7, it is necessary to search EOB again by the second data controller later to search for the end address and bit length of FBUF 6. Absent. For this reason, the number of processes can be limited and power consumption can be suppressed.
[0035]
Next, in the deformatting process, only the reading process from the FBUF 6 is performed, and the writing process to the FRES 5 is not performed. For this reason, useless data writing becomes unnecessary, and power consumption can be suppressed. Further, when real time output is required, the timing is guaranteed by converting the output into a zero-run value and an amplitude value in RATBL8 and outputting the value to FRES5.
[Brief description of the drawings]
FIG. 1 shows the present invention. The fruit The block diagram of the signal processing apparatus in embodiment.
FIG. 2 is a configuration diagram of a first memory FBUF6.
FIG. 3 is a configuration diagram of a third memory FINF7.
[Figure 4 A schematic diagram showing an example of the deformatting process.
[Figure 5 A schematic diagram showing an example in which data is dispersed as a result of the deformatting process.
[Figure 6 A block diagram of a conventional signal processing apparatus.
[Figure 7 A schematic diagram showing a conventional EOB storage method.
[Explanation of symbols]
1: Input terminal
2: Output terminal
3: First data controller
4: Second data controller
5: Second memory
6: First memory
7: Third memory
8: First table
9: Second table

Claims (2)

  A signal processing device for returning data stored in a fixed area with a fixed bit width to variable-length code data, a first table for detecting a bit length and an end-of-block code from input data, and a fixed length input to the device Data is stored in the first memory, the data of the first memory is input to the first table, the bit length and the end-of-block code are obtained, and the information is stored in the third memory. The second table for detecting the bit length and the end-off block code from the input data, and the data in the first memory are read in the order of the information stored in the third memory, and input to the second table. And a second data controller for extracting variable-length code data. A second memory functioning as a FIFO, the second table having means for detecting zero run values and amplitude values of the input data, and the second data controller having zero run values and amplitude values from the second table; the signal processing apparatus according to claim 1, characterized in that the output via the second memory output data.

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