JP3923695B2 - Image control apparatus and data output method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image control apparatus and a data output method, for example, an image processing apparatus and an image display unit that perform transfer control of image data for displaying image data stored in a memory according to a predetermined standard, particularly a television standard. And is suitable for application to an apparatus having a function of displaying on the image display unit with input / output of image data.
[0002]
[Prior art]
For example, when displaying image data on a display device such as a television set, the image data is recorded in a frame memory, and the image data is read from the frame and displayed during a scanning period defined in the broadcast standard. . On the other hand, rewriting of image data in the frame memory is generally performed by control of a CPU (Central Processor Unit) during the blanking period of the broadcast standard. This is because if the image data is rewritten during the image display period, the disturbance of the display image due to the occurrence of noise, etc. will appear on the screen, and the time restrictions associated with the rewriting will be a problem. is doing. Considering these points, the average access speed of the CPU to the frame memory is very slow during image display.
[0003]
As a method of coping with this problem, first, a method of using a buffer memory known as FIFO (First-In First-Out) or the like and temporarily transferring data to the buffer memory at a high speed is taken. The transfer at this time is faster than the clock rate of the television signal used in the television set. On the other hand, when reading from the buffer memory, the clock used for reading is matched with the television signal. In this method, data in the frame memory is rewritten within a time difference generated between the writing and reading rates. The buffer memory generally has a capacity equal to or greater than the number of pixels in the horizontal direction of the image. Because of the FIFO memory capacity and the write / read rate difference in this way, CPU access to the frame memory in this method is not limited to the above-described blanking period, and access is ensured in other periods as well. be able to. The image data transfer from the frame memory to the buffer memory is actually performed at a clock rate several times that of the television signal.
[0004]
In addition, the system that displays image data has a so-called electronic zoom function that displays a part of the image represented by the image data as if it were being shot, for example, by zooming in / out on the display. There are many built-in systems. In such a system, the luminance data Y and the color difference data C of the image data are easily converted into a television signal and / or the memory capacity is limited. _R , C _B Are recorded in the frame memory in a dot sequential format (4: 2: 2).
[0005]
[Problems to be solved by the invention]
However, even with the above-described countermeasure against the first problem, the CPU cannot access the memory during a period in which image data for one line is transferred from the frame memory to the buffer memory. The CPU idle state during this period means that CPU time is wasted. This makes it difficult to respond to CPU access requests, making it impossible to fully exploit the capabilities of certain systems. Currently, in a situation where higher speed of image processing is demanded, it is desired to make the system capability function sufficiently effectively while taking the correspondence between the final television display standard and image processing. .
[0006]
Similar to this requirement, Japanese Patent Application Laid-Open No. 7-49937 discloses an image processing apparatus that can process various image processing requests at high speed regardless of the contents. This image processing apparatus performs processing dedicated to image processing, a sequential processing method, and a data driving method, respectively, and performs transfer control with each other under the control of a control unit. However, the image processing apparatus performs optimum processing in each processing, but it is only described in the official gazette that the results are transferred and supplied to each other thereafter, and the processing results are transferred. There is no mention of how to respond quickly.
[0007]
Further, according to the signal processing apparatus / method and the memory storage method described in Japanese Patent Application Laid-Open No. 10-84532, the control means for controlling the writing and reading of each data with respect to the memory means includes the processing order and processing unit by the processing means. For example, data that is a signal processing unit is stored in the column (ie, burst) direction continuously by controlling the data to be arranged in accordance with To enable high-speed access.
[0008]
By the way, when the electronic zoom function is performed, the color difference data C based on the above-described dot sequential format relationship in which the address relationship of the frame memory is accurately determined by the zoom magnification _R , C _B This prevents the reading relationship of the sampling pairs. As a result, the relationship between sampling pairs in this format is broken. As a result, a false color is generated in the image and the image quality is deteriorated. A second problem that is independent of the problem described above arises. The invention described in Japanese Patent Laid-Open No. 10-84532 described above for this problem describes a memory configuration that takes into account data storage such as stitching, viewfinder, or character display in a monitor, and further encoding. It describes that dot sequential format (4: 2: 2) is thinned and converted to (4: 1: 1) or (4: 2: 0) at the time of processing, and reverse interpolation processing is performed at the time of decoding. However, in the invention described in Japanese Patent Application Laid-Open No. 10-84532, no consideration or countermeasure is taken for the problem that occurs when the electronic zoom process is performed.
[0009]
In general, in order to avoid this problem, when performing electronic zoom, color difference data C _R , C _B The data is synchronized by sampling again and the zoom is performed with the dot sequential format as (4: 4: 4). However, changing the format processing in accordance with the format relationship in the zoom processing increases the configuration of the apparatus and may lead to complicated processing.
[0010]
The present invention eliminates the disadvantages of the prior art and maximizes the hardware capabilities. For example, the present invention provides an image control apparatus capable of preventing image quality deterioration even when electronically zooming in the form of recorded data, for example. An object is to provide a data output method.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention adjusts output of this image data through a bus shared for the supplied image data, controls the output of the image data, and processes the image data obtained by signal processing. In the image control apparatus for outputting, a memory means for storing the supplied image data, and a standard adjusting means for writing the image data from the memory means and adjusting the timing of the already written image data to a predetermined standard for output And the amount of image data to be handled in batches when adjusting the sampling order and outputting the image data based on the conditions supplied according to the combination of luminance data and color data in the image data read from the memory means Display adjustment means for managing the supply of a predetermined number of units of image data to be output on one line per unit, and a memory means. The access to be executed first, the output of the image data, and the arbitration means for arbitrating the access request for the control data different from the image data for the remaining accessible time, and the input / output of the image data supplied to the memory means Control, set the amount of image data and a predetermined number of units, maintain a pair of data to be read in response to a request for enlargement / reduction of the image data, and perform control to read by requesting access to the memory means And memory control means for controlling at least memory means, display adjustment means, arbitration means, and standard adjustment means.
[0012]
The image control apparatus of the present invention controls at least the memory means, the display adjustment means, the arbitration means, and the standard adjustment means by the memory control means, stores the image data supplied to the memory means, and is read by the standard adjustment means Before writing the image data and performing processing for adjusting the timing of the already written image data to a predetermined standard and outputting it, a condition based on the combination of the luminance data and the color data in the image data read by the display adjustment means is set. When adjusting the sampling order, the arbitration means prioritizes access to the memory means, and when arbitrating access requests for the remaining accessible time and supplying image data to the standard adjustment means, the memory by the memory control means In the input / output control of the image data supplied to the means, the memory control means Set the amount of image data to be handled collectively (that is, the number of data in one packet) and the number of units that supply this image data amount in one unit to one line to be displayed (that is, the number of packets of an image included in one line), By controlling the reading of image data from the memory means while maintaining a pair of data to be read in response to an enlargement / reduction display request for image data, the response of image supply is improved, and the control is not limited to simple memory control. Other control over the memory means is also possible, and the occurrence of false colors is suppressed even for display requests.
[0013]
In order to solve the above-mentioned problems, the present invention provides a data output method for controlling the output of supplied image data to output the image data in a format conforming to a predetermined standard. A step of generating a first clock having a format conforming to a predetermined standard and a second clock having a frequency higher than that of the first clock, and an enlargement / reduction mode or an equal-magnification display mode when displaying in the predetermined standard A display mode setting step for setting the data amount to be collectively processed continuously and the number of units for outputting this data amount per line as one unit, and each address interval corresponding to the set display mode. Of the address calculation process for calculating the address to be read in consideration and the address obtained by calculation for the stored image data, A data read process for reading image data with random access to the start address of the image data read for handling, and a pair that conforms to a predetermined standard by separating the read image data into data corresponding to a plurality of signal components Order adjustment process to make data adjusted in accordance with the relationship, address data to be read, image data stored corresponding to the address, stored image data, external control information or image data stored in a predetermined cycle The process is adjusted in consideration of the priority of the process according to the instruction command supplied at the time of each process with respect to the refresh for performing the update, and the order permitted by the arbitration is maintained and adjusted. Of the data, at least the set number of units have already been retained during the period of one line of the specified standard. And an output adjustment step of performing output preparation including the number of units in the adjusted data supplied by the second clock in preparation for the next reading, in synchronization with the first clock. Features.
[0014]
The data output method of the present invention generates a first clock that outputs image data in a format that conforms to a predetermined standard and a second clock having a higher frequency than the first clock, and displays an enlarged / reduced display or Set the same size display mode, set the amount of data to be handled in batches and the number of units to output one line per unit of this data amount, and consider each address interval corresponding to the set display mode To calculate the address to be read. From among the addresses obtained after this, random access is made to the head address of the image data to be read when handling them all at once, and the read image data is separated into data corresponding to a plurality of signal components to meet a predetermined standard. The data relationship is adjusted to the matched pair relationship. At the time of each processing for the refresh to update the data of the address to be read, the image data to be stored corresponding to the address, the stored image data, the external control information or the image data stored in a predetermined cycle In consideration of the priority of the process according to the instruction command supplied to the data, the arbitration of each process is performed and the permitted order is maintained, and among the adjusted data, at least during the period of one line of a predetermined standard, The data already held including the set number of units is read in synchronization with the first clock, and the output data including the number of units is prepared in the adjusted data supplied by the second clock at the next reading. By doing so, the response of image supply is improved and the occurrence of false colors is suppressed even for display requests.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of an image control apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
[0016]
The image control apparatus of the present invention controls at least the memory unit, the display adjustment unit, the arbitration unit, and the standard adjustment unit by the memory control unit, stores the image data supplied to the memory unit, and is read by the standard adjustment unit Before writing image data and adjusting the timing of the already written image data to a predetermined standard and outputting it, a condition based on the combination of luminance data and color data in the image data read by the display adjustment unit is set. The arbitration unit supplies image data to the memory unit with priority given to the refresh processing access, and supplies other control data in the access request for the remaining accessible time. If the image data is supplied to the standard adjustment unit after arbitrating according to the priority order, the memory by the memory control unit In the input / output control of the image data supplied to the image data, the memory control unit handles the image data continuously in a batch (that is, the number of data in one packet) and this image data amount is displayed in one unit for one line to be displayed. The number of units to be supplied (that is, the number of image packets included in one line) is set, and control is performed to read image data from the memory unit while maintaining a data pair to be read in response to an image data enlargement / reduction display request. This improves the response of image supply, enables not only mere memory control but also other control of the memory unit, and suppresses the generation of false colors in response to a display request.
[0017]
The image control apparatus 10 of the present invention will be described sequentially. Further, illustration and description of portions not directly related to the present invention are omitted. Here, the reference number of the signal is represented by the reference number of the connecting line that appears.
[0018]
As shown in FIG. 1, the image control apparatus 10 is generally provided with a timing adjustment unit 12, an image memory 14, a memory control unit 16, a bus arbitration unit 18, and a display sequencer 20. The image control device 10 is a device that reads image data stored in the image memory 14 accurately, for example, in conformity with a broadcast standard, and controls and transfers it to a display device. In general, the image control device 10 is used by being incorporated in, for example, an image processing device or an image display device. The above-described components are controlled as a whole by a system control unit (not shown). Among them, in particular, the memory control unit 16 controls the timing adjustment unit 12, the image memory 14, the bus arbitration unit 18, and the display sequencer 20. Further, the memory control unit 16 not only controls, but also responds with commands supplied by the bus arbitration unit 18, the display sequencer 20, and an external control device described later.
[0019]
In this embodiment, the external control device includes a central processing unit (hereinafter abbreviated as CPU) 22, a direct memory access (hereinafter abbreviated as DMA) control unit 24, and a signal input unit 26. In the image control device 10, a memory control unit 16, a bus arbitration unit 18, a display sequencer 20, a CPU 22, a DMA control unit 24, and a signal input unit 26 are connected to a shared bus 30.
[0020]
Next, each component will be described. The timing adjustment unit 12 includes a timing signal generation unit 12a and a buffer memory unit 12b. Although not shown, the timing signal generator 12a of the present embodiment includes a clock 4f that is often used in broadcasting standards. _SC Is the first clock 10a, and the second clock 10b is the clock 4f. _SC Each oscillator has a higher frequency clock. Clock 4f _SC For example, the subcarrier frequency f used in the NTSC (National Television System Committee) system _SC = 4 times of 3.579545MHz, that is, 14.31818MHz. The clock 10a is supplied to the buffer memory unit 12b and the signal processing unit 28 that performs signal processing (encoding processing) on the image data output from the buffer memory unit 12b.
[0021]
On the other hand, the second clock 10b may be a high-frequency signal that satisfies the above-described conditions. In this embodiment, a high frequency signal close to 50 MHz is generated and used. As shown in FIG. 1, the clock 10b is supplied to the buffer memory unit 12b and the display sequencer 20. Although not shown, it is also supplied to other elements via the shared bus 30.
[0022]
In the case of using a frequency relationship obtained by multiplying the subcarrier frequency, the timing adjustment unit 12 may use the second clock as a primary, and divide and use the obtained second clock. This makes it possible to use only one oscillator. However, both clocks do not necessarily have to be kept in synchronization.
[0023]
The buffer memory unit 12b is provided with a plurality of first-in first-out (FIFO) memories. When one FIFO memory is outputting, the remaining FIFO memory is writing data for one horizontal line of the supplied image memory. As can be seen from this, at least two FIFO memories are used. A more detailed configuration will be described later.
[0024]
As the image memory 14, a synchronous volatile random access memory (abbreviated as SDRAM) or a volatile random access memory (abbreviated as DRAM) is used. The difference between the two is that the memory control is different from synchronous and asynchronous. Due to demands for handling large amounts of image data, the image memory 14 is composed of a plurality of banks. When the SDRAM is used for the image memory 14 with such a configuration, the image memory 14 can be controlled independently for each bank by performing an access method using a command (request signal or the like). In this case, interleave operation for each bank can be performed as compared with normal DRAM operation. The image memory 14 is supplied with a second clock 10b.
[0025]
The memory control unit 16 controls input / output of image data to / from the image memory 14 and also issues an instruction for refresh processing of the image memory 14 (REF_REQP = 1). The memory control unit 16 has a refresh timer so that this refresh process can be performed. The memory control unit 16 includes, for example, an initial setting function unit 16a, a display control function unit 16b, a bus control function unit 16c, and a refresh function unit 16d so as to perform its own setting and control of each unit. The memory control unit 16 is connected to the shared bus 30 via the signal line 16e. The memory control unit 16 inputs / outputs image data and controls the image data via the image memory 14 and the signal line 16f. The memory control unit 16 is connected to the buffer memory unit 12b by a signal line 16g. The signal line 16g includes, for example, various control signals for controlling the buffer memory unit 12b in addition to the image data supplied via the signal line 16e and the control data. The functions of the functional units 16a to 16d shown in FIG. 2 include a processing procedure based on conditions on how to operate according to a hardware configuration and a software method.
[0026]
The initial setting function unit 16a is a function for setting each unit to conditions (parameters) set in advance when power is supplied to the image control apparatus 10 for the first time or when the image control apparatus 10 is reset.
[0027]
The display control function unit 16b is a function unit that performs display control in response to supply of a command on how to consider the reading order of image data for display. The bus control function unit 16c is an initial setting function unit 16a, a display control function unit 16b, a refresh function unit 16d, a write function unit and a read function unit of an external CPU 22 (not shown), excluding the bus control function unit 16c in this embodiment. And a function unit that outputs information indicating whether or not the DMA function unit of the DMA control unit 24 can occupy the bus according to the priority of each function unit according to the priority. The refresh function unit 16d has a function of refreshing the image memory 14 in accordance with information from a refresh timer (not shown).
[0028]
Returning to FIG. 1, when the permission selection is enabled by the function unit 16c, the bus arbitration unit 18 outputs permission permission information according to a preset priority. As shown in FIG. 1, in the bus arbitration unit 18, the display sequencer 20, the CPU 22, the DMA control unit 24, and the signal input unit 26 described above are connected by input / output lines. The bus arbitration unit 18 determines the bus occupancy request information according to the priority, and outputs the bus occupancy permission information as a target. In the image control apparatus 10, the refresh process of the memory control unit 16 is assigned as the highest priority. The permission selection for each priority will be described in detail later in the operation.
[0029]
The display sequencer 20 includes a data separator 20a, a color signal selector 20b, and a pair generator 20c (see FIG. 3). The display sequencer 20 starts to operate in response to the supplied request signal (DISP_REQ). The data separation unit 20a includes data holding units 200a, 202a, and 204a that divide and latch the 16-bit read image data supplied from the image memory 14 into 8-bit data. The data holding unit 200a captures 8 bits of the supplied 16-bit read data at the rising edge of the clock CLK during the enable period of the luminance enable YEN, and outputs the captured data according to this edge. The remaining 8-bit image data separated is supplied to the data holding units 202a and 204a, respectively. The data holding unit 202a captures at the rising edge of the clock CLK during the enable period of the supplied color R enable CREN and outputs the captured data according to this edge. The data holding unit 204a captures at the rising edge of the clock CLK during the enable period of the supplied color B enable CBEN, and outputs the captured data according to this edge. The data holding unit 200a supplies the image data separated and temporarily held according to each enable period to be supplied to the pair generation unit 20C, and the data holding units 202a and 204a respectively supply the color data selection unit 20b. .
[0030]
The color signal selection unit 20b displays the supplied color data C when there is a request for enlargement / reduction display or equal magnification. _R , C _B Is selected and supplied to the pair generation unit 20c by selecting a color that can be correlated with the luminance data Y. For this selection, color C _R And color C _B A color selection signal RLB for selecting is supplied. The color selection timing will be described in detail later.
[0031]
The pair generation unit 20c is configured by a data latch. The pair generation unit 20c includes the supplied 8-bit luminance data Y and the selected 8-bit color data color C. _R / Color C _B 16-bit image data combined with any of the above is supplied. The pair generation unit 20c captures the supplied image data at the rising edge of the clock CLK supplied during the enable period of the data enable DEN. Then, the image data temporarily held at the rising edge of the clock CLK supplied during this period is output.
[0032]
With this configuration, the luminance data and color data pairs are in a predetermined relationship (4: 2: 2 relationship in this embodiment) regardless of the display instruction request, and the image data is maintained in the display sequence. Is done.
[0033]
The obtained image data is displayed by the display sequencer 20 under the control of the memory control unit 16, and in this embodiment, eight image data are included as one packet and 80 image packets are included in one line. Control data related to / write, control data related to CPU read / write, and the like are packetized and output to the buffer memory unit 12b.
[0034]
As shown in FIG. 4, the buffer memory unit 12b includes a bank switching circuit 120b, a W / R clock generation circuit 122b, a read counter 124b, a write counter 126b, a selector 128b, FIFO memories 130b and 132b, and a read selector 134b. ing.
[0035]
The bank switching circuit 120b uses the first clock 10a, the reset signal (RSTL) 10c, and the blank signal (FIFO_BLANK) 10d to select one of the FIFO memories 130b and 132b synchronized with the horizontal synchronization signal HD. 10e is generated. The bank selection signal 10e is supplied to the selector 128b and the read selector 134b. The bank switching circuit 120b also generates a signal (FIFO_BLKST) related to blanking of the FIFO memories 130b and 132b, which is not shown, and supplies it to the write counter 126b.
[0036]
The W / R clock generation circuit 122b has a function of generating a write / read clock among the clocks used in the buffer memory unit 12b. In addition to the first clock 10a, the second clock 10b, and the reset signal (RSTL) 10c, the clock (M2CLK) 10l and the clock (M4CLK) are supplied to the W / R clock generation circuit 122b. Using these signals, the W / R clock generation circuit 122b outputs a write clock (F_WCK) 10f and a read clock (F_RCK) 10g to the FIFO memories 130b and 132b, respectively.
[0037]
The read counter 124b has a counting function for counting and outputting the read address. A first clock 10a, a reset signal (RSTL) 10c, and a blank signal (FIFO_BLANK) 10d are supplied to the reading counter 124b. In this embodiment, the read counter 124b supplies 10-bit address data 10i in synchronization with the packet as a signal 10h (not shown) for masking data using these signals and a read address for the FIFO memories 130b and 132b. To do. For example, when image data is masked among data, other control data is packetized and stored at the masked position.
[0038]
The write counter 126b has a counting function for counting and outputting the write address. Write counter 126b has reset signal (RSTL) 10c, FIFO write enable signal (FIFO_WEL) 10i, clock (M2CLK) 10l , And a signal (FIFO_BLKST) are supplied. In this embodiment, the write counter 126b supplies 10-bit address data 10j as an address to be written in the FIFO memories 130b and 132b in synchronization with the packet.
[0039]
The selector 128b has a function of controlling one of the FIFO memories 130b and 132b to write and the other memory to read. A bank selection signal 10e and a FIFO write enable signal (FIFO_WEL) 10k are supplied to the selector 128b. While this enable signal 10k is supplied, a write inhibit signal (F1_WEI) 10m and a write inhibit signal (F2_WEI) 10n are supplied to either of the FIFO memories 130b and 132b in accordance with the supplied bank selection signal 10e. . Image data is not written into the FIFO memory that is write-protected by this signal. The selector 128b also performs control for writing to the FIFO memories 130b and 132b independently bit by bit (F1_V1, F2_V1). In addition, various prohibition signals are generated corresponding to the FIFO memories 130b and 132b and supplied to the FIFO memories 130b and 132b, respectively.
[0040]
The FIFO memories 130b and 132b are supplied with a write clock 10f and a read clock 10g so that when one is reading, the other is writing. Both FIFO memories 130b and 132b are supplied with 16-bit image data 10p. Of the FIFO memories 130b and 132b, the FIFO memory enters the read mode when the write inhibit signal is supplied. The FIFO memories 130b and 132b output the read mode memory to the read selector 134b with the read clock 10g. The FIFO memories 130b and 132b have their outputs 10q and 10r connected to the read selector 134b so that either of them can be in this mode. In addition, the FIFO memory 130b, 132b is also supplied with both a selection signal (SCANSEL) for scanning and a clock (SCANCLK) for scanning (not shown).
[0041]
The read selector 134b has a function of selecting one of the supplied image data 10q and 10r and inserting the control data supplied from the other into the selected image data in a packet. In order to realize these functions, in addition to the supplied image data 10q and 10r, a first clock 10a for adjusting output timing, a signal (DMASK) 10h, a bank selection signal 10e, and a reset signal 10c are supplied. . Using these signals, the read selector 134b outputs a series of 16-bit read data 10s in which a packet including data other than image data is inserted into one line to the signal processing unit 28.
[0042]
Returning to FIG. 1, the CPU 22 is not a control unit of the image control apparatus 10 but a central processing unit provided outside. The CPU 22 includes a CPU write function unit and a CPU read function unit which are not shown in the figure. Control information related to writing and control information related to reading from the CPU 22 which is one of the external control devices of the present embodiment are supplied via the shared bus 30, respectively.
[0043]
The DMA control unit 24 directly controls the data transfer with the main memory by passing the control right to the interface device of the peripheral device, for example, without passing the data through the CPU. The DMA control unit 24 is supplied with and outputs control information related to writing and control information related to reading from the DMA control unit 24 which is one of the external control devices. The supplied control information is subjected to data transfer or the like according to the priority order for the shared bus 30.
[0044]
The signal input unit 26 corresponds to the peripheral device interface device described above. For example, a device such as a keyboard is connected to the shared bus 30. Information other than image data is also controlled by the memory control unit 16 via the shared bus 30 and supplied from the buffer memory unit 12b to the signal processing unit 28 as described above.
[0045]
The signal processing unit 28 has a function of performing encoder processing conforming to a predetermined broadcast standard. In order to exhibit this function, the signal processing unit 28 extracts and encodes only the image data used for display from the supplied packets. The encoded image data 10t is output to a display device (not shown).
[0046]
With this configuration, it is possible to perform display corresponding to high-speed processing, and in particular, it is possible to avoid occupying the shared bus and easily access memory from other control units and external devices. As a result, the image control apparatus 10 can provide a process with high response. In addition, since so-called electronic zoom such as enlargement / reduction display including the same magnification of display can be performed so as not to break the sampling pair relationship, generation of false colors can be suppressed.
[0047]
Next, the reason why the above-described operation of each unit of the image control apparatus 10 is processed will be described. Consider the case of performing so-called electronic zoom such as the display described above. For example, when displaying one line in the horizontal direction with 640 pixels, each component data of Y / C separated image data is sampled in the (4: 4: 4) format shown in Fig. 5 (a). Color data C for one luminance data Y _R , C _B Are sampled correspondingly one by one, that is, color data C for four luminance data Y _R , C _B Corresponds to four each.
[0048]
On the other hand, when the sampling of the well-known (4: 2: 2) method shown in FIG. 5 (b) is performed, this method uses the color data C for the four luminance data Y. _R , C _B Are sampled in duplicate, and color data C _B Generate image data as a pair of color data of adjacent luminance data Y. (4: 2: 2) When the so-called double-magnification electronic zoom is performed without changing the method (see FIG. 5 (c)), sampling is performed with the same image data arranged at two pixel intervals. Become.
[0049]
By the way, when 1/2 reduction electronic zoom is performed in the (4: 2: 2) method (see FIG. 5 (d)), pixel data is sampled, for example, only odd-numbered luminance data Y. At this time, color sampling is performed using color data C _R Only sampling. In this case, color data C _B Will disappear. Conversely, if only even luminance data is sampled, color data C _R Disappears. Thus, one color data may be lost according to the electronic zoom display. As a result, a false color is generated in the displayed image.
[0050]
In order to deal with such a problem, the display sequencer 20 samples and adjusts the luminance data Y and the color data C in units of 3 clocks of the second clock 10b to be supplied, using the configuration of FIG. One case will be described. To explain general sampling, the luminance data contains Y _n , Y _{n + 1} , Y _{n + K} For color data, CR _n , CB _n And are used. Here, the subscript n represents a natural number, and K represents a zoom factor. First, when continuous reading is performed at the same magnification, that is, K = 1, color data is selected as follows according to the timing relationship shown in FIG. Luminance data from K = 1 to Y _n , Y _{n + 1} Are sampled 8 bits (see FIG. 6 (a)). Considering the sampling of color data in the (4: 2: 2) method in Fig. 5, the color data is represented by the symbol CR. _n , CB _n (See FIG. 6 (b)). In the brightness enable YEN shown in FIG. 6 (c), for example, the brightness data Y is captured at the rising edge of the second clock. _n Is output to the pair generation unit 20c (see FIG. 6 (d)).
[0051]
On the other hand, when the color R enable CREN is enabled in FIG. 6 (e), the color data CR is detected at the rising edge of the clock 10b. _n As shown in FIG. 6 (f), this color data CR is risen at the rising edge of the second clock. _n Will continue to be output. Similarly, when the color B enable CBEN in FIG. 6 (g) is enabled, the color data CB at the rising edge of the clock 10b. _n As shown in Fig. 6 (h), this color data CB _n Will continue to be output.
[0052]
When the color selection signal RLB supplied to the color signal selection unit 20b is supplied at the signal level of FIG. 6 (i), the color data CR is selected when the level of this signal is “L”, and the signal level is “ Since the color data CB is selected when H ″, the color data selection by the color signal selection unit 20b is supplied to the pair generation unit 20c in the order of the color data in FIG. 6 (j).
[0053]
As shown in FIG. 6 (k), the pair generation unit 20c generates a pair when the luminance data output in FIG. 6 (d) and the color data in FIG. 6 (j) are supplied at the second clock. The rising edge of the data enable DEN is supplied to the unit 20c so that the 16-bit luminance data Y _n , Color data CR _n Is captured. This clearly shows that the selection is completed in two clocks in this case.
[0054]
Then, at the rise of the third clock, it is output in the relationship of FIG. 6 (l) and FIG. 6 (m). In this case, two pixels of data, that is, a pair of luminance data and color data (Y _n , CR _n ) And (Y _{n + 1} , CB _n ) Is output continuously. In FIG. 6 (n), the FWEL signal is supplied as an enable signal for the range width. This signal is output as an inverted latch output of the data enable DEN.
[0055]
Sampling adjustment for enlargement / reduction display in the display sequencer 20 will be described. The subscript n is an even number. Of the supplied image data, the first luminance data Y of the luminance data Y _n That is, when the number is even, the luminance data Y reads three data. That is, even luminance data Y _n , Adjacent odd luminance data Y _{n + 1} And luminance data Y taking into account the enlargement / reduction factor _{n + K} (See FIG. 7 (a)). The color data is the luminance data Y that is continuously supplied. _n , Y _{n + 1} CR corresponding to each _n , CB _n Is supplied (see FIG. 7 (b)).
[0056]
The luminance data Y in this case is captured at the rising edge of the clock CLK during the enable (high level period) of the luminance enable YEN shown in FIG. 7 (c), which is supplied to the data holding unit 200a of the data separation unit 20a. The output of the data holding unit 200a is as shown in FIG. 7 (d) from the relationship between the luminance data Y taken into the data holding unit 200a and the rising edge of the clock 10b.
[0057]
On the other hand, the color data CR is the color data CR at the rising edge of the clock 10b when the color R enable CREN is enabled in FIG. _n As shown in FIG. 7 (f), this color data CR is risen at the rising edge of the second clock. _n Will continue to be output. Similarly, when the color B enable CBEN is enabled in FIG. _n As shown in Fig. 7 (h), this color data CB at the rising edge of the third clock _n Will continue to be output.
[0058]
When the color selection signal RLB supplied to the color signal selection unit 20b is supplied at the signal level in FIG. 7 (i), the color selection by the color signal selection unit 20b is performed in the order of the color data in FIG. The color data of CR and CB is supplied to the pair generation unit 20c.
[0059]
As shown in FIG. 7 (k), the pair generation unit 20c generates a pair when the luminance data output in FIG. 7 (d) and the color data in FIG. 7 (j) are supplied at the second clock. When the rising edge of the data enable DEN is supplied to the unit 20c at the third clock, the 16-bit luminance data Y _n , Color data CR _n Is captured. This clearly shows that the selection is completed in three clocks in this case.
[0060]
And the rise of the fourth clock, that is, the luminance data Y in the relationship of FIG. 7 (l) and FIG. 7 (m) _n , Color data CR _n Is output. As a result, data for two pixels, ie, a pair of luminance data and color data (Y _n , CR _n ) And (Y _{n + 1} , CB _n ) Is output continuously. In FIG. 7 (n), the FWEL signal is supplied as an enable signal for the range width. This signal is output as an inverted latch output of the data enable DEN. At this time, the relationship between luminance data and color data in the (4: 2: 2) method is maintained.
[0061]
Finally, among the supplied image data, the first luminance data Y of the luminance data Y _{n + 1} That is, when the number is odd, the luminance data Y reads three data. That is, even luminance data Y _{n + 1} , Adjacent even brightness data Y _n And luminance data Y taking into account the enlargement / reduction factor _{n + K} (See FIG. 8 (a)). This means that the color data must correspond to the color CR for the first luminance data, as shown in the previous sampling relationship, that is, the relationship between the luminance data and color data in the (4: 2: 2) method. . However, the color data corresponding to the odd luminance data is the color CB as will be described later. If sampling is performed as it is, a pair of luminance data and color data is shifted, and there is a possibility that image quality degradation such as false color may occur when so-called electronic zooming is performed. Therefore, when the odd number comes to the top, adjustment is made so that the image data address is read by returning the address of the image data to be read second, and the subsequent sampling timing is also taken into consideration for this point. .
[0062]
The color data is the luminance data Y that is continuously supplied. _{n + 1} , Y _n CB corresponding to each _n , CR _n Is supplied (see FIG. 8 (b)). This is different from FIG.
[0063]
The luminance data Y in this case is taken in at the rising edge of the clock CLK during the enable (high level period) of the luminance enable YEN shown in FIG. 8 (c), which is supplied to the data holding unit 200a of the data separator 20a. The output of the data holding unit 200a is as shown in FIG. 8 (d) from the relationship between the luminance data Y captured by the data holding unit 200a and the rising edge of the clock 10b.
[0064]
On the other hand, when the odd number is the head of the color data CR, the color R enable CREN in FIG. 8E is enabled at the second clock rising edge of the clock 10b. _n As shown in Fig. 8 (f), this color data CR is _n Will continue to be output. In addition, when the color B enable CBEN is enabled in FIG. 8 (g), the color data CB is detected at the rising edge of the first clock of the clock 10b. _n As shown in Fig. 8 (h), this color data CB at the rise of the second clock _n Will continue to be output.
[0065]
The color selection signal RLB supplied to the color signal selection unit 20b is supplied at the signal level shown in FIG. 8 (i). Supply at this timing is the luminance data Y to be paired _{n + K} The color selection signal RLB is set to the level “L” at the same time as the rise of the brightness enable YEN for selecting the “L”. By supplying the color selection signal RLB, the color selection by the color signal selection unit 20b is performed in the order of the color data in FIG. 8 (j), that is, in the order of the color data of the colors CB, CR, and CB.
[0066]
In the pair generation unit 20c, as shown in FIG. 8 (k), when the luminance data output in FIG. 8 (d) and the color data in FIG. 8 (j) are supplied at the second clock, the pair generation unit 20c When the rising edge of data enable DEN is supplied at the third clock in 20c, 16-bit luminance data Y _{n + 1} , Color data CR _n Is captured. Since the data enable DEN is continuously in the enabled state, it can be seen that two consecutive pixels are selected and that the selection is completed in three clocks.
[0067]
Then, at the rise of the fourth clock, it is output in the relationship of FIG. 8 (l) and FIG. 8 (m). For continuous readout, the data for 2 pixels in 3 clocks is a pair of luminance data and color data (Y _{n + 1} , CR _n ) And (Y _{n + K} , CB _n ) Is output continuously. In FIG. 8 (n), the FWEL signal is supplied as an enable signal for the range width. This signal is output as an inverted latch output of the data enable DEN. By adjusting the sampling in this way, the relationship between the luminance data and the color data can be maintained even if so-called electronic zoom processing is performed by the (4: 2: 2) method.
[0068]
Next, transmission of a packet output from the bus arbitration unit 18 to the buffer memory unit 12b will be briefly described. In this embodiment, one packet is defined as a collection of data obtained by collecting eight 8-bit data. The period for supplying the packet is supplied during the effective scanning period indicated by the horizontal synchronizing signal in FIG. 9A (see FIG. 9B). Packet data is written into one of the FIFO memories 130b and 132b of the buffer memory unit 12b. One line has 80 image data packets written therein. The numbers in FIG. 9 (c) represent packet numbers. The characters “FREE” after the packet number 80 in FIG. 9 (c) indicate that there is no information. The character “REF” indicates a packet for instructing the image memory 14 to perform a refresh process.
[0069]
Further, as shown in FIGS. 9 (d) and 9 (e), in addition to image data, characters “CPU” and “DMA” are inserted between image data packets, for example, control related to the external CPU 22 And information on DMA control from the DMA controller 24 from the outside. As shown in FIGS. 9 (c) and 9 (e), 80 packets / line of image data packets are completed during the effective scanning period. However, as shown by the packet relationship in FIGS. 9 (f) and 9 (g), when 80 packets / line is not completed during the effective scanning period, there is no data at the edge of the image. The number of image data packets to be displayed on one line must satisfy 80 defined while undergoing the arbitration process. Packets are sent to satisfy this relationship.
[0070]
Next, the overall operation of the image control apparatus 10 will be described. Turn on the power and start operation. With this start, the timing signal generator 12a immediately generates various timing signals including the clocks 10a and 10b. Then, the process proceeds to the memory control process of subroutine SUB1. In the memory control process, various settings such as initial settings are performed, and arbitration is performed according to the priority of the shared bus 30 and display processing is performed on the image data read from the image memory 14. The image data packetized by the display sequence control for the image data in the subroutine SUB1 is output to the buffer memory unit 12b line by line.
[0071]
The buffer memory unit 12b controls the high-rate writing / normal-rate reading of the supplied packet (step S10). The read packetized image data is extracted by the signal processing unit 28, and the obtained image data is encoded and output to a display device (not shown) (step S12).
[0072]
Thereafter, it is determined whether the image display is completed (step S14). If the image is still being displayed (NO), the process returns to the subroutine SUB1 to repeat the series of image data control described above. If the image display is completed (YES), the control related to the image display is ended.
[0073]
The subroutine SUB1 including the features of the present embodiment will be described. In the subroutine SUB1, it is first determined whether or not the initial setting in the image control apparatus 10 has been completed (substep SS100). When the initial setting has not been completed yet (YES), the process proceeds to the initial setting process (substep SS102). When the initial setting has already been performed (NO), the process proceeds to the bus arbitration process (substep SS104). In the bus arbitration process, determination is performed in descending order of priority. The process with the highest priority is the refresh process of the image memory 14. In this process, since the DRAM or SDRAM is used for the image memory 14, it is necessary to refresh the memory in a predetermined cycle. Whether or not there is a request is determined based on whether or not a flag for performing refresh processing is set in the bus arbitration unit 18 (substep SS104). This flag can be set according to the count value of a refresh counter (not shown), for example. When the refresh flag is set or the count value reaches a predetermined value (YES), it is determined whether or not the current shared bus 30 can be used (substep SS106). If it is not usable (NO), it is not displayed explicitly in FIG. 11, but immediately a process for saving the process in use of the current shared bus 30 is performed, and the process waits. When the shared bus 30 is usable (YES), refresh processing is performed (substep SS108). In the refresh process, control information to be refreshed is packetized and output to the buffer memory unit 12b. If the refresh flag or the refresh count value has not been reached (NO), the process proceeds to display reading (sub-step SS110).
[0074]
It is determined whether a display reading flag or a request signal (REQ) is supplied (substep SS110). If there is a request for reading the display (YES), it is determined whether or not the shared bus 30 can be used and whether or not the processing is temporarily saved in consideration of the priority of the processing used previously (substep SS112). When the previous process is lower than the display reading process, the previous process is saved (NO). When the shared bus 30 is usable (YES), the process proceeds to display reading processing (subroutine SUB2).
[0075]
In the subroutine SUB2, processing corresponding to packetization of image data, processing corresponding to a pair in the (4: 2: 2) system, and the like are performed, and the image data is output to the buffer memory unit 12b. Subroutine SUB2 will be described in detail later, including other processing. If there is no request for reading the display (NO), the processing shifts to processing related to control by the external CPU 22.
[0076]
With this shift, the bus arbitration unit 18 determines whether a CPU control flag or a request signal (REQ) is supplied (sub-step SS114). If there is a request for CPU control (YES), it is next determined whether or not the CPU control is write processing (substep SS116). In the case of write processing (YES), the process proceeds to determination of whether the shared bus 30 can be used (substep SS118). In the case of non-write processing (NO), the process proceeds to determination of whether another shared bus 30 can be used (substep SS120). ). In sub-steps SS118 and SS120, the priority of the preceding process is compared with the priority of the process to be performed, and the process with the higher priority is performed. At this time, if the priority of the CPU control process is higher (NO), the preceding process is temporarily saved. When the shared bus 30 is usable (YES), the process proceeds to sub-step SS118, SS120 and subsequent write control processing (sub-step SS122) and read-out processing (sub-step SS124), respectively. Not only after each writing / reading process, but also after sub-step SS108 and subroutine SUB2, the process proceeds to the end of packet control via connector A (sub-step SS126).
[0077]
It is determined whether or not output control of packetized data including other control data packets has been completed (sub-step SS126). If completed (YES), return to the main routine of FIG. 10 via return. If it has not been completed yet (NO), the process returns to the sub-step SS104 via the connector B.
[0078]
In the above-described substep SS114, if the request is not CPU control (NO), the bus arbitration unit 18 proceeds to determine whether the DMA control unit 24 has issued a DMA control request via the connector C. (See sub-step SS128 in Figure 12). This determination is made when DMA control is performed (YES), and the process proceeds to processing for determining whether or not DMA control is writing (sub-step SS130). If it is determined that the write process is to be performed (YES), it is determined whether or not the shared bus 30 is usable as described above (sub-step SS132). When it is not in the usable state (NO), it stands by and temporarily saves when a low priority is processed in advance according to the priority. When the use permission of the shared bus 30 is granted (YES), the DMA write control is performed (substep SS134).
[0079]
When DMA control is performed and when it is determined that writing is not performed (NO), the process proceeds to sub-step SS136 to determine whether or not the shared bus 30 is permitted to be used. The processing based on this determination is the same as the processing in sub-step SS132 when there is no use permission (sub-step SS136). When permission to use the shared bus 30 is received, read control processing in DMA control is performed (substep SS138). Both the write control and read control processes in the DMA control put control information in one packet and output it. Thereafter, the process proceeds to sub-step SS126 to determine whether or not the packet control is finished.
[0080]
By the way, when DMA control is not performed (NO), it is determined whether or not data is input from an external device and whether or not there is control (substep SS140). If there is this request (YES), control from the outside is performed (substep SS142). Examples of such control include devices such as a keyboard. On the other hand, if the result of the above determination does not correspond to any of the above (NO), the process proceeds to sub-step SS126 without performing any processing. The determination at sub-step SS126 is as described above. If a series of judgments have been completed (YES), the process returns to the main routine via return. In this way, it is determined whether the shared bus 30 is free for the required processing, and at this time, each processing is performed according to the priority. Therefore, not only image data packetization but also other control is efficient. Can be done. Various data supply including the packetized image data is performed during the effective image display period of one line as shown in FIG. Time can be used effectively for processing.
[0081]
Next, a procedure for packetizing the image data in the subroutine SUB2 and reading it in accordance with the display sequence (order) will be described. Although not shown explicitly in the configuration of the image control apparatus 10, for example, the signal input unit 26 sets a so-called electronic zoom size for an image to be processed from now on via a mouse or a keyboard provided. (Substep SS200). The set value here is a zoom coefficient when performing image display. If the same magnification (1.0) is set to 256, the double enlargement is 512, and the half reduction is 128. The data amount per packet of image data and the number of packets per line of image data are also set. The amount of packet data and the number of packets may be fixedly set if there are hardware restrictions. In this embodiment, eight consecutive image data are fixedly handled as one packet. Then, it is set so that 80 packets are included in one line for the image data. It should be noted that the electronic zoom can be set by interrupt processing.
[0082]
After this setting, an address of image data to be read from the image memory 14 is calculated (substep SS202). Here, the address calculation may be performed by randomly setting the head address of the packet described above. The following seven consecutive image data are calculated in consideration of the zoom coefficient of the electronic zoom with respect to the head address of the designated packet. The calculated address data is supplied to the memory control unit 16. More specific address calculation in this embodiment is obtained by rounding off the value after the decimal point after adding the zoom distance. By this calculation, it is possible to prevent the head position from being shifted.
[0083]
The memory control unit 16 reads out image data and performs read control for adjustment while maintaining a pair relationship between luminance data and color data corresponding to, for example, the (4: 2: 2) method (subroutine SUB3: data read out) Order adjustment). The actual sequence adjustment is performed by the display sequencer 20. By this reading, it is possible to suppress a phenomenon of deteriorating image quality such as false colors even when electronic zoom is performed by the (4: 2: 2) method. In particular, the control for maintaining the above-described pair relationship will be described in detail later.
[0084]
After this processing, the process proceeds to sub-step SS204, where the vertical blanking signal (Vertical BLanKing: hereinafter referred to as VBLK) is used as a synchronization signal when starting display. Yes. When the VBLK signal is not detected (NO), the process returns to sub-step SS204 and waits. When the VBLK signal arrives (YES), the process proceeds to display sequence processing (subroutine SUB4).
[0085]
In the subroutine SUB4, processing for arranging the order of supplying the packet of the image data read so far to the buffer memory unit 12b is performed. This series of processing is performed by the display sequencer 20 described above. Along with the horizontal reading, this processing also performs processing related to vertical reading control corresponding to the electronic zoom. These processes will also be described in detail later. After this processing, the process proceeds to return and returns to the subroutine SUB1.
[0086]
For the purpose of high-speed processing, it may be determined whether transmission of image data for one screen is completed after this display sequence. When data transmission is incomplete (NO), the process returns to the address calculation process and is repeated. However, in this embodiment, as an example of the process, the determination process in sub-step SS204 is bypassed until the number of lines for image display reaches a predetermined value based on the rise of the VBLK signal so that this series of repetition processes is performed. Let When the data transmission is completed (YES), the process proceeds to return, and this subroutine SUB2 is terminated.
[0087]
Next, a procedure (subroutine SUB3) regarding the order of data reading and maintaining the pair relationship will be described. First, it is determined whether there is continuity with the processing in which image data has been read so far. Information on continuity is determined using a flag or a combination condition flag. If there is continuity (YES), go to sub-step SS302 to load the address. The address loaded at this time is the address read at the end of the previous packet. After this processing, the process proceeds to substep SS304. Similarly, when there is no continuity (NO), the process proceeds to sub-step SS304 since the image data is read for the first time this time.
[0088]
In sub-step SS304, various parameters used for memory control are initialized. This parameter is set, and then the address is set (substep SS306). Then, the operation start is set (substep SS308). The operation here means operation control for the image memory 14. For example, the operation of chip select (CS) or row address select (RAS) is started.
[0089]
Next, it is determined whether or not the first head address set is an even number (substep SS310). This is the start of color selection processing. In this case, the flag is used effectively. For example, the determination is made based on whether an odd flag is set. When the odd number flag is not raised, that is, when the head address is an even number (YES), the count number N = 0 is set (substep SS312). When the odd flag is set (NO), the head address is determined to be odd and the process proceeds to the odd color selection process shown in FIG.
[0090]
After setting the count number N = 1 in the even color selection process, the head address which is the first reading in the (4: 2: 2) method is accessed and read from the image memory 14 (substep SS314: READ_YCR). The read image data is 16 bits. The image data is separated into luminance data Y and color data CR, and data is temporarily stored. This stage temporarily stores the image data in FIGS. 6 (a) and (b) by selecting the area of the luminance data Y and the color data CR by the enable signals in FIGS. 6 (c) and (e) and temporarily holding them. It is determined whether or not to perform zoom processing (substep SS316). When the same magnification process is performed (NO), the color selection signal RLB = 0 is supplied so that the color signal selection unit 20b selects the color CR from the temporarily stored color CR. Then, the image data selected and output during this period is taken into the pair generation unit 20c as a pair (see FIG. 6 (k)). Proceed to FIG. 15 via connector E (substep SS320). On the other hand, when the zoom process is performed (YES), a process (READ_CB) described later is performed via the connector F.
[0091]
Returning to the same magnification processing, the count number N is incremented by 1 according to the selection of the color CR (substep SS320), and the luminance data and the color data CB are temporarily held and the held data is output. (Substep SS322). As a result, the area that is the basis of the second image data in the (4: 2: 2) method is selected (READ_YCB).
[0092]
By the way, after this process, it is determined whether or not the count number exceeds 8 (substep SS324: priority 1). This is because the number of packet data is set to eight. When the delimiter of the image data for one packet is reached (YES), the processing is shifted via the connector G. If the image data for one packet is not packed (NO), the process proceeds to substep SS326.
[0093]
Here, it is determined whether or not this address space has reached the right end of the address space in which the memory area of the image memory 14 is represented in two dimensions (substep SS326: priority 2). This determination is also made according to whether the flag is set. When the right end has been reached (YES), the color CB is selected in consideration of the order (substep SS328). The color selection signal RLB is supplied with “1” in order to perform color selection in consideration of the order. At this time, the count is incremented by 1 (substep SS330). Then, line feed processing in the address space to be read next and address update processing associated therewith are performed (substep SS332: READNOP2). In the address update process, for example, a process for setting the address value to zero in advance is performed. After this processing, the process returns to the sub-step SS306 in FIG.
[0094]
When the access in the address space has not yet reached the right end in the determination in substep SS326 performed previously (NO), the process proceeds to the next determination process (substep SS334: priority 3). In this determination, it is determined whether or not the next head address is an odd number. When the head address is an odd number (YES), the color CB is identified, and “1” is supplied as the color selection signal RLB to perform color selection in consideration of the order. As a result, the color CB is selected (substep SS336). At this time, the count is incremented by 1 (sub-step SS338), and then the process corresponding to the case where the head address becomes an odd number is transferred via the connector I (READ_YCB1). This process will be described later.
[0095]
Further, when the next head address is not an odd number (NO), by identifying the color CB in consideration of the order among the areas obtained by the sub-step SS322 of the equal magnification process (sub-step SS340), the color CR is obtained. A pair of luminance data Y and color data CB is continuously obtained in combination. At this time, the count number N is incremented by 1 (substep SS342), and the process returns to the substep SS314 of FIG. This loop forms an equal magnification processing loop. When this same magnification processing is performed, that is, when the address value incremented by 1 to the first address value matches the address value to be read next, the color data CB corresponding to this scheduled address value is selected and paired Thereafter, the luminance data Y of the planned address is selected.
[0096]
Next, when the top address is an even number and zoom processing is performed, the process proceeds to the sub-step SS344: READ_CB) of FIG. 16 via the connector F as described above. Here, although not appearing in the flow, the region of the color data CR performed in sub-step SS318 is temporarily selected to perform region extraction (see FIGS. 7 (e) and (f)). On the other hand, no area is selected for the color data CB because the enable signal CBEN is at level “L”. Then, in sub-step SS344 via connector F, color data CB is identified and area selection is performed, but at this stage there is no data as shown in FIG. Data will be sampled. In this selection, the color selection signal RLB is supplied with “1” (see FIGS. 7 (g) to (j)). At this time, the count number N is incremented by 1 (substep SS346).
[0097]
Next, a process of temporarily latching the color CB area is performed (see sub-step SS348: color enable CBEN = “1”). After this processing, as described above, it is determined whether or not access to the address space to be read has reached the right end (substep SS350). The detection of the right end can also be determined by a preset flag value. If the right end has been reached (YES), line feed processing is performed for the address space to be accessed (substep SS352). The line feed process is a series of address update processes. Thereafter, the process proceeds to selection of the next new luminance data Y (substep SS354).
[0098]
When the address has not yet reached the right end (NO), the color data CR is identified and selected as shown in FIGS. 7 (i) and (j), and the region is also selected (substep SS354: RLB = 0, DEN = 1). The counting for this result is omitted because it is performed in the previous sub-step SS346.
[0099]
Next, the second luminance data Y to be read continuously is selected (substep SS356: READ_Y2). In this selection, when the first address is an even number and zoom processing is performed from sub-step SS314, the first obtained luminance data Y and color data CR pair is validated, and then the second separated luminance data Y is read out. It corresponds to processing. At this time, it is determined whether the count number N exceeds 8 (substep SS358: priority 1). When the count number N exceeds 8 (YES), the color data CB corresponding to the selected luminance data Y is selected (substep SS360: RLB = 1). When the count number N is still smaller than 8 (NO), the process proceeds to a determination process for determining whether or not to reach the right end of the address space and to perform a line feed (substep SS362: priority 2). When reaching the right end of the address space to start a new line (YES), color CB is selected in substep SS364.
[0100]
This is because an address different from the case where the address value is incremented by +1 as in the case where the color CB is the same size, that is, an address added with the zoom distance indicating the zoom size is accessed. Select the color data of color CB that is paired with CR. At this time, the count number N is incremented by 1 (substep SS366). Then, the process proceeds to sub-step SS332 (READNOP) via the connector K.
[0101]
When the condition in sub-step SS362 is not satisfied (NO), the process proceeds to sub-step SS368 (priority 3) in FIG. Here, it is determined whether or not the next head address is an odd number. When this address value is an even number (NO), the color CB is selected for the same reason as the processing in sub-step SS364 (sub-step SS370). At this time, the count number N is incremented by 1 (substep SS372). After this processing, the process returns to the sub-step SS314 (READ_YCR) in FIG. 14 via the connector L.
[0102]
If the first address value is an odd number (YES) in sub-step SS368 (YES), color CB is selected in sub-step SS374 and the count number N is incremented by 1 (sub-step SS376). After this process, the process shifts to an odd first address process (substep SS378: READ_YCB1).
[0103]
As a result of such a series of operations, when the head address is an even number, the address value incremented by one to the address value read first instead of the data separated from the luminance data Y and the so-called electronic zoom address distance (or zoom distance). By selecting the color data CB and reading the next luminance data Y, the pair relationship between the luminance data and the color data is maintained.
[0104]
Next, the processing procedure in the case of an odd number is performed after substep SS378. First, the luminance data Y is extracted with the enable signal, and the color data CB is also extracted (substep SS378: CBEN = 1). The color data CB obtained by performing this process selects the level “H” period of the color selection signal RLB (substep SS380). At this time, the count number N is incremented by 1 (substep SS382). In the case of this odd number processing, color data CR obtained when one address is returned is selected (substep SS384: READ_CR).
[0105]
At this stage, it is determined whether or not the right end of the address space has been reached (substep SS386). When not reached (NO), the color data CR corresponding to the address of the luminance data Y when it is returned is read and selected (sub-step SS388: RLB = 0). Then, a pair with luminance data Y is output. Thereafter, the process proceeds to sub-step SS356 (READ_Y2) of FIG. By operating in this way, even when so-called electronic zoom is performed on (4: 2: 2) image data, the image data can be read out without shifting the color data pair relationship with the luminance data. .
[0106]
If the right end of the address space has been reached (YES), the process proceeds to substep SS352 (READNOP3) via the connector N. Here, the arrival at the right end is detected by monitoring information such as a set flag.
[0107]
By the way, when the read image data (luminance data Y, color data CR / CB) is read for one packet (priority 1) as described above even in the case of an even number, the process proceeds to sub-step SS390 shown in FIG. Here, image data is read into the image memory 14. After this process, the process proceeds to the timing adjustment process of FIG. 18 via the connector P (substep SS392). In this timing adjustment process, the operation of sampling with the clock 10b is asynchronous with the television signal such as the horizontal synchronizing signal and the vertical synchronizing signal. Adjustment is made so that the timing of delivery of image data with these signals can be taken well. This timing is monitored in substep SS394. When adjustment is complete (YES), the process returns to return. If the adjustment is not completed (NO), the process returns to sub-step SS392 and the adjustment is continued.
[0108]
By processing in this way, the display sequencer 20 can suppress the occurrence of false colors and the like due to color misregistration when sampling the image data for the same magnification and zoom with the (4: 2: 2) method. .
[0109]
The display sequencer 20 outputs the image data read in this way according to the subroutine SUB4. Perform initial settings when starting the display sequence (substep SS400). Various parameters used when adjusting the display order are set. It is determined whether or not to start preprocessing of display output sequence processing. For example, when the display stop flag is set (NO: STOP_DISP = 1), the operation preparation stage is awaited.
[0110]
Next, when preparation is started (YES), the process proceeds to sub-step SS404 according to the supplied parameters (for example, DVD, DFLD). At this stage, when the parameters DVD = 0 and DFLD = 0, the display output is an even number and the display is determined to be the second field. If it is determined that it is not an even number (NO), when the parameter DVD = 0 and DFLD = 1, the display output is an odd number and the display is determined to be the first field.
[0111]
Next, when the conditions for starting operation (STFLG = 1, DVD = 1, DHD = 1, DISP_REQ = 1) are satisfied in sub-step SS408 (YES), the start address is set (sub-step SS410). At the same time, the initial value of the packet to be counted is set (substep SS412). After this processing, the process proceeds to substep SS414 in FIG. When the operation start condition is not satisfied (NO), the process returns to sub-step SS408 and enters a standby state.
[0112]
Next, it is determined whether or not the shared bus 30 that is used when the image data is transferred to the buffer memory unit 12b can be used although it is in the operation start state (substep SS416). The use permission of the shared bus 30 is supplied to the bus arbitration unit 18, and the bus arbitration unit 18 outputs the use permission to the processing unit that requested the use permission according to the priority. When this use permission cannot be obtained (NO), a standby state is set. When the use permission is obtained (YES), the process proceeds to substep SS418.
[0113]
Here, it is determined whether or not the number of packets so far inserted into one line has been reached. If the predetermined number of packets has not been reached yet (NO), the process proceeds to sub-step SS420. In response to this determination, a packet transmission request is output (DISP_REQ = 1). In response to this request, the packet is actually transmitted (substep SS422). After this processing, the process returns to substep SS416. If the predetermined number of packets is exceeded (YES), packet transmission is prohibited (substep SS424). As a result, image data for one line is supplied as a packet. In this embodiment, the number of packets is set to 80.
[0114]
When so-called electronic zoom is performed after this processing, if zoom control is performed not only in the horizontal direction described so far but also in the vertical direction, a good zoom image in consideration of the aspect ratio is displayed. Will be able to. Therefore, in sub-step SS426, a start address to be read next in the vertical direction corresponding to the zoom distance (or address distance) is calculated. Based on the calculated address value, image data is sent to the next line.
[0115]
After this calculation, the display sequencer 20 determines whether the horizontal synchronization signal HD has arrived, that is, whether the end of one line has come (substep SS428). If it is determined that the end of the horizontal synchronization signal HD has not yet arrived (NO), the process waits in sub-step SS430. This state corresponds to the period of the character “FREE” as shown in FIG. If it is determined that the end of the horizontal synchronizing signal HD has arrived (YES), it is determined whether a display end command is supplied (sub-step SS432). Until a command is supplied, the process returns to the sub-step SS408 in FIG. 19 through the connector R to repeat a series of processes. If the display end command is supplied (YES), the process proceeds to return and the subroutine SUB4 is ended.
[0116]
When operated in this manner, the image data can be supplied and written to the buffer memory unit 12b within a predetermined time, and not described explicitly, but not only the image data as shown in FIG. Also, data such as CPU and DMA can be supplied to enable effective memory control within a limited time.
[0117]
In addition, as for the address change in the row direction, the electronic zoom is efficiently processed by updating the address so that the change in the address in the column direction is detected only when valid luminance data is read.
[0118]
By configuring as described above, it is possible to effectively access other devices while avoiding the occupation of the shared bus even during the image display period and to improve access response. Processing such as rewriting can be performed at a higher speed than before. By changing the effective pixel number (packet size) of one packet, the occupation time of the shared bus can be varied to give priority to access of data to be read relatively.
[0119]
In addition, when (4: 2: 2) sampling is performed and electronic zooming is performed, a pairing relationship between luminance data and color data sampling is maintained. It is also possible to prevent the image quality from being deteriorated due to the occurrence of the above.
[0120]
【The invention's effect】
As described above, according to the image control apparatus of the present invention, the memory control unit controls at least the memory unit, the display adjustment unit, the arbitration unit, and the standard adjustment unit, stores the image data supplied to the memory unit, and stores the standard adjustment unit. In addition to writing the image data read out in step 1, and adjusting the timing of the already written image data to a predetermined standard and outputting it, the luminance data and the color data in the image data read out by the display adjustment means When adjusting the sampling order using conditions based on the combination, the arbitration unit gives top priority to access to the memory unit, and arbitrates access requests for the remaining accessible time and supplies image data to the standard adjustment unit. Memory control in the input / output control of image data supplied to the memory means by the memory control means The amount of image data (ie, the number of data of one packet) handled in a row by the stage and the number of units for supplying this amount of image data to one line to be displayed (ie, the number of packets of an image included in one line) ) And the control of reading out the image data from the memory means while maintaining the pair of data to be read in response to the image data enlargement / reduction display request, thereby improving the response of the image supply. Not only the memory control but also other control for the memory means is possible, and the generation of false colors is suppressed even for the display request. In particular, relative priority processing such as priority of reading out image display by increasing the number of units and priority of external control by decreasing the number of units becomes possible.
[0121]
The data output method of the present invention generates a first clock for outputting image data in a format that conforms to a predetermined standard and a second clock having a higher frequency than the first clock, and enlarges / reduces the display. Set the display mode or the same size display mode, set the data amount to be handled in batches and the number of units to output this data amount for one line, and each address interval corresponding to the set display mode The address to be read is calculated in consideration of From among the addresses obtained after this, random access is made to the head address of the image data to be read when handling them all at once, and the read image data is separated into data corresponding to a plurality of signal components to meet a predetermined standard. The data relationship is adjusted to the matched pair relationship. At the time of each processing for the refresh to update the data of the address to be read, the image data to be stored corresponding to the address, the stored image data, the external control information or the image data stored in a predetermined cycle In consideration of the priority of the process according to the instruction command supplied to the data, the arbitration of each process is performed and the permitted order is maintained, and among the adjusted data, at least during the period of one line of a predetermined standard, The data already held including the set number of units is read in synchronization with the first clock, and the output data including the number of units is prepared in the adjusted data supplied by the second clock at the next reading. By doing so, the response of the image supply can be improved, and other controls on the memory means can be made besides simple memory control. , To suppress the generation of false colors to the display request. In particular, it is possible to perform relative priority processing in which priority is given to reading out image display by increasing the number of units and control priority from outside by decreasing the number of units.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an image control apparatus of the present invention.
FIG. 2 is a schematic diagram showing each functional unit provided in the memory control unit of FIG. 1;
3 is a circuit diagram for selecting generation of a pair of luminance data and color data in the display sequencer of FIG. 1; FIG.
4 is a block diagram showing a schematic configuration of a buffer memory unit in FIG. 1; FIG.
FIG. 5 is a diagram schematically showing a relationship of sampling of each method of luminance data in image data and two color data.
FIG. 6 is a timing chart of a process for maintaining a pair relationship between luminance data and color data by a (4: 2: 2) system equal magnification process.
FIG. 7 is a timing chart of a process of maintaining a pair relationship in which the head is an even number in the zoom data of the (4: 2: 2) method for luminance data and color data.
FIG. 8 is a timing chart of a process of maintaining a pair relationship in which the head is an odd number in the zoom data of the (4: 2: 2) method for luminance data and color data.
FIG. 9 is a timing chart schematically showing a relationship between packets transmitted in one line in the image control apparatus.
FIG. 10 is a main flowchart for explaining the operation of the image control apparatus.
FIG. 11 is a flowchart illustrating an operation procedure of a subroutine SUB1 of the image control apparatus.
12 is a flowchart for explaining the operation procedure subsequent to subroutine SUB1 of the image control device shown in FIG.
FIG. 13 is a flowchart illustrating an operation procedure of a subroutine SUB2 of the image control apparatus.
FIG. 14 is a flowchart illustrating an operation procedure of a subroutine SUB3 of the image control apparatus.
FIG. 15 is a flowchart illustrating an operation procedure subsequent to subroutine SUB3 of the image control apparatus shown in FIG.
16 is a flowchart for explaining the operation procedure following the subroutine SUB3 of the image control device shown in FIG.
FIG. 17 is a flowchart illustrating an operation procedure subsequent to subroutine SUB3 of the image control apparatus shown in FIG.
18 is a flowchart illustrating an operation procedure subsequent to subroutine SUB3 of the image control apparatus shown in FIG.
FIG. 19 is a flowchart illustrating an operation procedure of a subroutine SUB4 of the image control apparatus.
FIG. 20 is a flowchart illustrating an operation procedure subsequent to subroutine SUB4 of the image control device shown in FIG.
[Explanation of symbols]
10 Image controller
12 Timing adjustment section
14 Image memory
16 Memory controller
18 Bus arbitration department
20 Display sequencer
28 Signal processor
12a Timing signal generator
12b Buffer memory section

Claims (30)

In an image control apparatus that outputs image data obtained by performing output control of the image data in accordance with a predetermined standard via a shared bus for the supplied image data and performing signal processing, the apparatus includes:
Memory means for storing the supplied image data;
A standard adjusting means for writing the image data from the memory means and adjusting the timing of the already written image data to the predetermined standard;
The amount of image data to be handled in batches when adjusting the sampling order and outputting the image data based on the conditions supplied according to the combination of the luminance data and the color data in the image data read from the memory means Display adjustment means for managing the supply of a predetermined number of units of image data to be output to one line per unit;
Arbitration means for giving priority to access for refreshing the memory means, for arbitrating access requests for control data different from the image data for the remaining accessible time, together with output of the image data;
Control input / output of image data to be supplied to the memory means, set the image data amount and the predetermined unit number, and maintain a data pair to be read in response to an enlargement / reduction display request of the image data An image control including: a memory control unit that controls the memory unit to request access and reads, and controls at least the memory unit, the display adjustment unit, the arbitration unit, and the standard adjustment unit; apparatus. 2. The apparatus according to claim 1, wherein the standard adjusting unit generates a first clock used for displaying the supplied image data in accordance with a predetermined standard and a second clock having a higher frequency than the first clock. Means to
A plurality of lines of buffer means corresponding to the output of the data in accordance with the predetermined standard, and output adjusting means for selecting a line when outputting from the plurality of lines of buffer means. An image control device. 2. The image control apparatus according to claim 1, wherein operations of the standard adjustment unit, the display adjustment unit, and the memory control unit are controlled in accordance with a supplied request signal. 2. The image control apparatus according to claim 1, wherein the memory means uses a synchronous volatile random access memory or a random access memory. 2. The apparatus according to claim 1, wherein the memory control means includes a setting function block for performing initial setting of the apparatus;
A refresh function block for controlling refresh processing for the memory means;
An order control function block for controlling the display order of the data corresponding to a combination of image data read out by random access to the memory means, and for performing control in response to an instruction of enlargement display / reduction display in the display;
An image control apparatus comprising: an arbitration function block that arbitrates in accordance with an occupation priority of a bus for sharing and transmitting the image data to the setting function block, the refresh function block, and the order control function block. 2. The apparatus according to claim 1, wherein the memory control unit performs read control for continuously displaying the image data stored in the memory unit for each set number of units and displaying them in a horizontal direction. An image control apparatus characterized by randomly reading and controlling the address of the head image data of each unit. 7. The apparatus according to claim 6, wherein the memory control means designates an address for reading out the read image data in the vertical direction of the image data read from the memory means independently of the read control for displaying in the horizontal direction. An image control apparatus for controlling. 2. The apparatus according to claim 1, wherein the display adjustment unit separates the read image data from the luminance data and the color data, and further separates the color data into two types.
Color selection means for selecting one of the two types of color data separated by the separation means;
An image control apparatus comprising: combining means for forming a pair with one of the luminance data and the color data respectively output from the separating means and the color selecting means. 9. The apparatus according to claim 8, wherein the display adjustment means outputs two of the three pieces of image data supplied within three clock periods of the supplied clock when enlargement / reduction display of the image data is requested. Select and output image data,
An image control apparatus that outputs image data supplied during a two-clock period of a supplied clock when the same-size display of the image data is requested. 10. The apparatus according to claim 9, wherein the color selection means selects a predetermined correspondence relationship between the two types of color data corresponding to luminance data sequentially obtained by component separation of image data at the head address in the unit. And
The synthesizing unit outputs the selected color data and the luminance data in a pair relationship based on the predetermined correspondence relationship. 11. The image control apparatus according to claim 10, wherein the color selection unit sets the predetermined correspondence relationship to a 4: 2: 2 dot sequential format relationship. 11. The apparatus according to claim 10, wherein the separation unit maintains the predetermined correspondence with each of the luminance data and the two types of color data and responds to an output timing of each supplied image data. And an image control apparatus including a function of outputting image data. 6. The apparatus according to claim 5, wherein when the memory control unit calculates an address to be read from the memory unit, an interval between addresses to be read according to an enlarged / reduced display including an equal magnification display of image data is used as a zoom distance. Add,
An image control apparatus using an address obtained by rounding off the decimal point of the added address value. 5. The apparatus according to claim 4, wherein said memory control means detects whether or not the address of said memory means has reached an end and detects the address of the next column in said memory means only at the time of reading effective luminance data. The image control apparatus is characterized in that the image data is continuously updated by the updated address. 6. The image control apparatus according to claim 5, wherein the memory control unit includes a timer for supplying a refresh timing to the refresh function block every predetermined cycle. In a data output method for controlling the output of supplied image data and outputting the image data in a format conforming to a predetermined standard, the method includes:
Generating a first clock having a format that matches the supplied image data with a predetermined standard and a second clock having a higher frequency than the first clock;
Set the enlargement / reduction mode or the same size display mode when displaying in the predetermined standard, and set the amount of data to be handled continuously and the number of units for outputting the data amount as one unit. A display mode setting process;
An address calculation step for calculating an address to be read in consideration of each address interval corresponding to the set display mode;
A data reading step for reading out the image data by randomly accessing the head address of the image data to be read out when handling the batched image data among the addresses obtained by calculation of the stored image data,
A sequence adjustment step of separating the read image data into data corresponding to a plurality of signal components, and adjusting the data to a pair relationship that conforms to the predetermined standard;
Supplied for each processing for the address data to be read, the image data stored corresponding to the address, the stored image data, the control information from the outside, or the refresh that updates the image data stored in a predetermined cycle A step of arbitrating the processing in consideration of the priority of the processing according to the instruction command to be performed;
While maintaining the order permitted by the arbitration, among the adjusted data, the data already held at least including the set number of units during the period of one line of the predetermined standard is the first clock. A data output method comprising: an output adjustment step of performing output preparation including the number of units in the adjusted data supplied by the second clock in preparation for the next read. 17. The data output method according to claim 16, wherein in the output adjustment step, the first clock is a signal synchronized with a broadcast standard. 17. The data output method according to claim 16, wherein the number of units is set to a number at which reading of the image data is completed in one horizontal line. 17. The method according to claim 16, wherein the address calculating step calculates and designates independently according to a display magnification of an image for displaying an address for reading the image data in a vertical direction orthogonal to the one horizontal line. A data output method characterized by the above. 17. The data output method according to claim 16, wherein the order adjustment step selects two pixels from three pixels of the image data within the three clock periods of the second clock in the reading of the image data. . 21. The method according to claim 20, wherein the order adjustment step selects the image data within two clock periods of the second clock when the reading of the image data starts at an even address and the display magnification is equal. A data output method characterized by the above. 21. The method according to claim 20, wherein the order adjustment step divides the image data in the three clock periods into luminance data and two color data, and sequentially corresponds to luminance data at the head address in the period. When the color data is selected, the color data with respect to the luminance data is selected to maintain a predetermined correspondence relationship, and the selected color data and the luminance data are output in a paired relationship. Data output method. 23. The data output method according to claim 22, wherein the predetermined correspondence is a dot-sequential format of 4: 2: 2. 23. The data output method according to claim 22, wherein when the predetermined correspondence is satisfied, the second address is reversed and the corresponding color data is selected. 25. The data output method according to claim 24, wherein the color data selection process is performed when a leading address in the period is an odd number. 23. The method according to claim 22, wherein when the leading address in the period is an even number, the relationship between the luminance data and the color data indicated by the leading address is maintained and the address interval separated from the leading address is When the second address is equal to a value obtained by incrementing the leading address by one, the color data obtained corresponding to the luminance data of the second address is enabled,
When the second address is different from the value advanced by 1 to the head address, the color data of the address indicated by the value obtained by the advance is read, and the luminance data of the second address is read and the pair is read. A data output method characterized by: 23. The method according to claim 22, wherein when the leading address in the period is an odd number, the relationship between the luminance data indicated by the leading address and one of the color data is maintained, and one address is returned from the leading address. A data output method characterized in that the other color data of the address is read and the luminance data of the second address is read to make a pair. 17. The data output method according to claim 16, wherein the address calculation step calculates an address to be read next by rounding a value obtained by adding the address interval to the read address. 17. The method according to claim 16, wherein when the obtained address is represented as a two-dimensional space, the data reading step reaches the right end of the space by reading the address in the row direction. A data output method comprising: detecting whether or not and updating a row-direction address to be read according to the detection result. 17. The data output method according to claim 16, wherein the method outputs the image data and / or audio data according to a predetermined standard.

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