JP3920166B2 - IC card and information processing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC card used for, for example, electronic money and an ID card and an information processing method thereof, and more particularly to a technology for processing information stored in a non-volatile memory mounted on the IC card.
[0002]
[Prior art]
2. Description of the Related Art An IC card system that reads and writes data between an IC card that owns a memory for storing information and a reader / writer is used as an electronic wallet in a leisure facility use ticket or a financial institution. There are two types of IC cards: a contact type IC card having a contact point for contacting a reader / writer and exchanging signals, and a non-contact type IC card that performs communication using radio waves.
[0003]
The contact IC card has contacts for interface with signals such as power, ground, clock, data, and reset, and is supplied with stable power from the reader / writer. On the other hand, the non-contact type IC card incorporates an antenna coil and a capacitor for receiving a carrier from a reader / writer, and a power source rectifies the carrier from the reader / writer and uses it as a power source.
[0004]
In the contact IC card described above, the IC card is inserted and removed from the device in the middle of data writing, or the power required for the operation away from the communication area in the same way during the data writing in the non-contact IC card. If the data cannot be obtained, the data in the memory mounted on the IC card will be destroyed. The data in the memory is configured in units of a block having a predetermined data length, for example, 16 bytes, and it may be possible to simultaneously read / write these block data by one command processing. In some cases, it is necessary to guarantee data.
[0005]
To solve this problem, as a first solution, for example, when writing block data, for the block data designated for writing, the old block data that was valid before performing the writing process is stored in the nonvolatile memory. There is a data protection method based on old data backup in which data is temporarily stored in another area and then data is written. As shown in FIG. 12, when simultaneously writing a plurality of block data into a data block area composed of a plurality of block data, first, block data of a designated block number is reserved block data in the spare block area. Then, the block data of the designated block number is written in the data block area. As a result, even if the power supply is interrupted while data is being written, the block data before the write process is held in the spare block area, so that the data can be returned to the original state, and data guarantee is possible. Become.
[0006]
Also, as a second solution, there is a data protection method by holding validity information that secures two or more memory areas and also has validity information indicating which memory area is valid. To do. As shown in FIG. 13, two memory areas, a data block area A and a data block area B, are secured, and data validity determination information indicating which data is valid in the block data of each block number. I will keep it. When writing block data, check data validity judgment information, write new block data to invalid block data in the memory area, and then rewrite and update each valid / invalid information to write data. I do. Even in this case, when the power supply is interrupted, the block data that was valid before the writing process is retained, so the validity judgment information is set to the state before the writing process, so that the data is restored to the original state. It becomes possible to return to.
[0007]
[Problems to be solved by the invention]
The block data management method described above enables efficient memory management with a small storage area without requiring a large amount of data held in the nonvolatile memory.
[0008]
However, in the address management method for associating logical addresses with physical addresses, if the total number of data block areas and spare block areas is within 256 blocks, the block number in the address management area can be managed with 1 byte. However, when the number of blocks exceeding 256 blocks is handled, it is necessary to manage the block number in the address management area with a plurality of bytes such as 2 bytes and 3 bytes. For this reason, the memory capacity in the address management area is required to be twice or three times, which increases the chip size.
[0009]
The present invention provides an IC card capable of executing processing efficiently and at high speed while ensuring data guarantee at the time of power interruption even when handling such a large-capacity data block area and its information processing It aims to provide a method.
[0010]
[Means for Solving the Problems]
The present invention first stores data to be stored and held. 2 Store more than one storage data area and target data during writing process 2 One or more buffer areas and the storage data area Address information associating a logical address with a physical address and address information associating a logical address and a physical address with respect to the buffer area are respectively stored in predetermined physical addresses 2 A memory having at least two address management areas, and write data sent in correspondence with a command at the time of a write process to the memory is stored in the buffer area, and an address corresponding to the buffer area in the address management area Information and address information corresponding to the storage data area specified by the command. Each other There is provided an IC card comprising memory control means for rewriting and updating an address management area.
[0011]
Second, the memory includes an address holding area for holding target address information at the time of update processing in the address management area, and 2 A buffer determination flag area for storing validity information of a buffer area indicating which one of two or more buffer areas is valid, and a parameter area for storing in-writing information indicating that the writing process is in progress The memory control means based on the logical address specified by the command at the time of the write process. 2 A storage data area and a buffer area to be written are selected from two or more storage data areas and a buffer area, validity information for specifying the target area is stored in the buffer determination flag area, and the command in the address management area is used. The physical address corresponding to the logical address of the designated storage data area and the physical address corresponding to the buffer area are temporarily held in the address holding area, the in-write processing information is set in the parameter area, and the buffer Based on the validity information of the determination flag area, after performing an update process that rewrites the physical address corresponding to the storage data area and the physical address corresponding to the buffer area in the address management area of the valid target area, To restore the information during the writing process to its original state. And butterflies.
[0012]
Third, the memory control means determines whether or not the writing process is completed based on the information during the writing process, and stores the data in the parameter area when the process is resumed when the writing process is not completed normally. Based on the updated total block number and updated block number of the physical address, the address information held in the address holding area, and the validity information of the buffer determination flag area, the unprocessed physical address The update process is completed.
[0013]
Fourth, the present invention stores data to be stored and held 2 One or more storage data areas and target data during read processing 2 is stored One or more buffer areas and the storage data area Address information associating a logical address with a physical address and address information associating a logical address and a physical address with respect to the buffer area are respectively stored in predetermined physical addresses 2 A memory having at least two address management areas, and address information corresponding to the storage data area specified by a command in the address management area at the time of read processing from the memory Because Address corresponding to the buffer area information There is provided an IC card comprising memory control means for rewriting and updating an address management area, reading read data stored in the updated buffer area, and then returning the address management area to its original state. .
[0014]
Fifth, the memory includes an address holding area for holding target address information at the time of update processing in the address management area, and 2 A buffer determination flag area for storing validity information of the buffer area indicating which one of the two or more buffer areas is valid, and a parameter area for storing information during reading processing indicating that the reading processing is in progress And the memory control means at the time of the read process based on the logical address specified by the command. 2 A storage data area and a buffer area to be read are selected from two or more storage data areas and buffer areas, validity information designating the target area is stored in the buffer determination flag area, and the buffer area in the address management area Is temporarily held in the address holding area, the information being read is set in the parameter area, and the address management area of the effective target area is set based on the validity information of the buffer determination flag area After updating the physical address corresponding to the logical address of the storage data area specified by the command in the above to the physical address corresponding to the buffer area, after reading the read data stored in the buffer area after the update A thing corresponding to the held buffer area After the restoration process to restore the address, and returning the read processing in the information to the original state.
[0015]
Sixth, the memory control means determines whether or not the reading process is completed based on the information during the reading process, and if the reading process is not completed normally, stores it in the parameter area when the process is resumed. Based on the total number of restored blocks of the physical address and the number of restored blocks, the address information held in the address holding area, and the validity information of the buffer determination flag area, the unprocessed physical address The restoration process is completed.
[0016]
Seventh, the present invention Address information that associates two or more storage data areas for storing data to be stored, two or more buffer areas for storing target data at the time of write processing, and a logical address and a physical address related to the storage data area And two or more address management areas each storing address information associating a logical address and a physical address related to the buffer area at a predetermined physical address. When writing data to the memory in the IC card, The control unit in the IC card Storing write data sent in response to a command in a buffer area of the memory; The control unit is Based on the logical address specified in the command, 2 Selecting a storage data area and a buffer area to be written from two or more storage data areas and a buffer area, and storing validity information specifying the target area in a buffer determination flag area; and The control unit is Temporarily holding a physical address corresponding to a logical address of a storage data area designated by the command and a physical address corresponding to the buffer area in an address holding area in an address management area for storing address information of the memory; , The control unit is A step of setting in-writing information indicating that the writing process is in progress; The control unit is Based on the validity information of the buffer determination flag area, the physical address corresponding to the storage data area and the physical address corresponding to the buffer area in the address management area of the valid target area are rewritten to each other to rewrite the address management area. Performing the update process; The control unit is An information processing method for an IC card, comprising: returning the in-write information to the original state after the update process.
[0017]
The present invention eighthly, Two or more storage data areas for storing data to be stored and held, two or more buffer areas for storing target data at the time of read processing, and a logical address and a physical address for the storage data area are associated with each other. Address information and two or more address management areas each storing address information for associating a logical address and a physical address related to the buffer area at a predetermined physical address When reading data from the memory in the IC card, The control unit in the IC card Based on the logical address specified in the command 2 Selecting a storage data area and a buffer area to be read from two or more storage data areas and a buffer area, and storing validity information specifying the target area in a buffer determination flag area; The control unit is Temporarily holding a physical address corresponding to the buffer area in the address holding area in an address management area for storing address information of the memory; The control unit is A step of setting reading process in-process information indicating that the reading process is in progress; The control unit is Based on the validity information of the buffer determination flag area, the physical address corresponding to the logical address of the storage data area specified by the command in the address management area of the valid target area is rewritten to the physical address corresponding to the buffer area. Performing update processing of the address management area, The control unit is Performing a restoration process of restoring the physical address corresponding to the held buffer area after reading the read data stored in the updated buffer area; The control unit is An information processing method for an IC card, comprising: returning the in-reading information to an original state after the restoration processing.
[0018]
In the present invention, at the time of writing processing to the memory, write data sent corresponding to the command is stored in the buffer area, and the address information corresponding to the buffer area in the address management area and the storage data area designated by the command are stored. The address management area is updated by rewriting the corresponding address information. At this time, the specified storage data area and buffer area to be written are selected from one or more storage data areas and buffer areas, and the validity information indicating the target area is stored in the buffer determination flag area. Based on the validity information of the determination flag area, the address management area of the valid target area is updated. This eliminates the need to store the write data itself in the buffer area and then transfer it to the storage data area. The write process can be completed simply by updating the address information after storing the write data in the buffer area. Therefore, the write data added to the command packet can be stored in the buffer area substantially simultaneously with the data transmission process, and the process can be executed efficiently and at high speed. In addition, even when the power is interrupted, the writing process can be restored and completed from the state before the process interruption after the power is restored, so that an error or loss of data can be prevented and data guarantee can always be ensured. Furthermore, it is possible to prevent the memory capacity for system control such as the address management area used for the writing process from greatly increasing even for a memory having a large data area.
[0019]
Also, during the process of reading data to the memory, the address management area is updated by rewriting the address information corresponding to the storage data area specified by the command in the address management area and the address information corresponding to the buffer area. After reading the read data stored in the buffer area, the address management area is restored to the original state. At this time, the storage data area and the buffer area to be read specified from the one or more storage data areas and the buffer area are selected, and the validity information indicating the target area is stored in the buffer determination flag area. Based on the validity information of the determination flag area, the address management area of the valid target area is updated. This eliminates the need to copy and read the read data itself from the storage data area to the buffer area, and by updating the address information and reading the read data from the updated buffer area, the address information can be restored. Since the read process is completed, the read data stored in the buffer area can be read and added to the response packet almost simultaneously with the data transmission process, and the process can be executed efficiently and at high speed. . Further, even when the power is interrupted, after the power is restored, the reading process can be restored and completed from the state before the interruption of processing, so that an error or loss of data can be prevented and data guarantee can always be ensured. Further, even for a memory having a large capacity data area, it is possible to prevent the memory capacity for system control such as an address management area used for the reading process from being greatly increased.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a non-contact type IC card system to which an information processing method according to an embodiment of the present invention is applied. Data transmission / reception between the IC card 101 and the reader / writer 102 that reads / writes data from / to the IC card 101 is performed by an electromagnetic induction method using antennas 103 and 104, respectively. The reader / writer 102 creates transmission data to the IC card 101 internally and transmits the data to the IC card 101 through the antenna 104 as a modulation signal. The IC card 101 existing in the communication area receives data modulated by the antenna 103. The received data is demodulated by the demodulator 105 and sent to the controller 106.
[0021]
The control unit 106 is configured by a processor such as a CPU, for example, analyzes received data according to a control program stored in the control memory ROM 107, and receives received data from a memory such as an EEPROM (Electrically Erasable Programmable ROM) or FeRAM (Ferroelectronic RAM). Processing such as storage in the non-volatile memory 109 is performed. The reception data is stored directly in the nonvolatile memory 109 when a memory having a high writing speed such as FeRAM is used as the nonvolatile memory 109. Further, the received data may be temporarily written in a transmission / reception buffer in the RAM 108.
[0022]
Thereafter, the received data is read and written in the non-volatile memory 109 to generate transmission data for response. This transmission data is modulated by the modulation unit 110 via the control unit 106, and this modulated signal is transmitted from the antenna 103 to the reader / writer 102.
[0023]
The non-volatile memory 109 of the IC card 101 shown in FIG. 1 has a file configuration as shown in FIG. 2 in a logical memory space viewed from the reader / writer 102. That is, a data block area 1401 (corresponding to a storage data area) in which data required by the user is stored, and a spare block area in which data specified when data is read / written from the reader / writer 102 to the IC card 101 are stored. 1402 (corresponding to a buffer area) and an address management area 1403 in which address information for associating a logical memory space with a physical memory space in the nonvolatile memory 109 of the IC card 101 is stored. Further, the nonvolatile memory 109 stores a parameter area 1404 for storing various parameters including information in writing process and information in reading process used for data update, and address management to be updated in the update process of the address management area 1403. A buffer determination flag area 1405 for storing a flag indicating validity information for designating an area is provided.
[0024]
In the present embodiment, in the case of managing data in units of blocks with respect to the nonvolatile memory 109 of the IC card 101, an example of a logical configuration in a large-capacity memory in which the total number of blocks exceeds 256 blocks and an information processing method thereof It is shown. In this example, the total number of data block areas 1401 and spare block areas 1402 exceeds 256 blocks. In this embodiment, the number of blocks in the data block area 1401 is 480 blocks, and the number of blocks in the spare block area 1402 is 32 blocks. However, the number of blocks is not limited thereto.
[0025]
Each of the data block area 1401 and the spare block area 1402 is configured to store a plurality of block data each having a predetermined data length, for example, a block unit of 16 bytes, based on the logical block number. In the example of FIG. 2, the data block area 1401 stores logical block data of 480 indicated by logical block numbers 00, 01, 02,..., 1DF, and the spare block area 1402 has logical block number 1E0. 32 spare block data indicated by 1E1,..., 1FF are stored. In the description of the present embodiment, values indicating the addresses of blocks on the memory such as logical block numbers and physical block numbers, values of data stored in each area, and values such as flags are expressed in hexadecimal numbers. To do.
[0026]
In the block configuration as shown in FIG. 2, since the total number of blocks in the data block area 1401 and the spare block area 1402 exceeds 256, the management block number in the address management area 1403 can be managed with 1 byte as it is. Can not. Therefore, in this embodiment, since the total number of blocks in the data block area and the number of blocks in the spare block area is 256 × 2 or less, as shown in FIG. Divide into two areas. That is, two data block areas A1501 and B1502, two spare block areas A1503 and B1504, and address information that associates the logical memory space and the physical memory space of each area are stored. The address management area A1505 and address management area B1506, a parameter area 1507, and a buffer determination flag area 1508 are included. In FIG. 3, the area is divided into two areas, but it may be divided into three or more areas, or may be divided into an appropriate number of areas according to the total number of data block areas and spare block areas.
[0027]
In the case of the block configuration of FIG. 3, each block data is managed by an area-specific logical block number defined for each of a plurality of divided areas, instead of the logical block number shown in FIG. That is, the data block area A1501 and the data block area B1502 store 240 logical block data indicated by area-specific logical block numbers 00, 01, 02,... EF in the respective areas, and the spare block area A1503. The spare block area B1504 stores 16 spare block data indicated by logical block numbers F0, F1,..., FF in each area.
[0028]
The reader / writer 102 can read / write data from / to the data block area A 1501 and the data block area B 1502 in the nonvolatile memory 109 mounted on the IC card 101. In this case, the address management area to be updated is selected by the flag of the buffer determination flag area 1508, and the logical block number for each area of the logical block data to be read / written in the corresponding data block area A1501 or data block area B1502 is set. Data is read and written by specifying. It is also possible to specify a plurality of logical block numbers with a single command. For example, by designating logical block numbers 00 and 01 for each area, data can be simultaneously read from and written to a plurality of logical block data. It can be carried out.
[0029]
In the present embodiment, in the data write process, the write designation block data added to the write command is reserved from the spare block 0 data in the spare block area A 1503 or spare block area B 1504 substantially simultaneously with the received data transmission process. Block F data is stored in order. That is, when two block data are simultaneously written, the first designated block data added to the write command is spare block 0 data, and the second designated block data is spare block 1 data. Will be stored.
[0030]
Furthermore, in the data reading process, block data of the logical block number for each area specified by the read command is sequentially transmitted from the spare block 0 data to the spare block F data in the spare block area A 1503 or spare block area B 1504 during the transmission process. Stored. Then, the control unit 106 performs transmission data transmission processing by adding block data to the read response while reading the block data in order from the spare block 0 data when returning the read response.
[0031]
At this time, the nonvolatile memory 109 has a file configuration as shown in FIG. 4 in a physical memory space that is an actual memory configuration. The physical memory space includes an address management area A1601 and an address management area B1602, and a data area A1603 and a data area B1604. The address management area A1601 is a data block address management area A1611 for managing the block number of the logical block data, a spare block address management area A1612 for managing the block number of the spare block data, and data guarantee at the time of power interruption. A block number holding area A1613 in which block numbers are recorded when block data writing processing and reading processing are performed is configured. Similarly, the address management area B1602 includes a data block address management area B1614, a spare block address management area B1615, and a block number holding area B1616.
[0032]
The nonvolatile memory 109 also stores a parameter area 1605 for storing various parameters including information in writing process and information in reading process used for data update, and update processing of each address management area A1601 and address management area B1602. Are provided with a buffer determination flag area 1606 for storing a flag for designating an address management area to be updated.
[0033]
In the present embodiment, the data area is divided into a plurality of parts, and the number of blocks in each of the data area A 1603 and the data area B 1604 is 256 blocks or less, so that each corresponding address management area A 1601 and address management area B 1602 has 1 byte. Can be managed with block numbers.
[0034]
The data block area A1501 and the spare block area A1503 in the logical memory space shown in FIG. 3 are associated with each block number in the address management area A1601 in the physical memory space shown in FIG. Are mixedly stored in the data area A1603. Similarly, the data block area B1502 and the spare block area B1504 in the logical memory space shown in FIG. 3 are associated with each block number in the address management area B1602 in the physical memory space shown in FIG. Both are stored in the data area B 1604 in a mixed manner.
[0035]
Also, the logical block data in the data block area A1501 in the logical memory space shown in FIG. 3 is the blocks in the data block address management area A1611 in the address management area A1601 in the physical memory space shown in FIG. They are recorded in the data area A1603 in association with each other. Further, the spare block data in the spare block area A1503 in the logical memory space shown in FIG. 3 are the blocks in the spare block address management area A1612 in the address management area A1601 in the physical memory space shown in FIG. They are recorded in the data area A1603 in association with each other. On the other hand, the logical block data in the data block area B1502 in the logical memory space shown in FIG. 3 is the block in the data block address management area B1614 in the address management area B1602 in the physical memory space shown in FIG. They are recorded in the data area B 1604 in association with each other. Further, the spare block data in the spare block area B1504 in the logical memory space shown in FIG. 3 is the blocks in the spare block address management area B1615 in the address management area B1602 in the physical memory space shown in FIG. They are recorded in the data area B 1604 in association with each other.
[0036]
Further, a block number holding area A1613 in the address management area A1601 includes a logical block number holding area A1621 that holds a logical block number specified by a command at the time of block data writing processing and reading processing, and a specified logical block number. Holds a physical block number holding area A 1623 for holding a physical block number corresponding to, and a spare block number for storing write data added to a command packet during write processing and read data added to a response packet during read processing And a spare block number holding area A1625. Similarly, the block number holding area B1616 in the address management area B1602 includes a logical block number holding area B1622, a physical block number holding area B1624, and a spare block number holding area B1626. In addition, in order to determine and confirm whether the block data values in the nonvolatile memory 109 are valid without error, error check information (parity data) 1607 is stored in each block data for each block. Is done.
[0037]
Next, the configuration and control contents of each address management area A1601, address management area B1602, and buffer determination flag area 1606 will be described with reference to FIG.
[0038]
In the data block address management area A1611, physical block numbers corresponding to the logical block number 00, the logical block number 01,..., And the logical block number DF are stored in order from the top. In FIG. 5, since 00 is stored as the physical block number corresponding to the logical block number 00 of the data block address management area A1611, the logical block 00 stored in the logical block number 00 in the logical memory space. Data is stored in physical block number 00 in the physical memory space. Similarly, since F1 is stored in the physical block number corresponding to the logical block number 01, the logical block 01 data stored in the logical block number 01 in the logical memory space is physically stored in the physical memory space. Stored in block number F1. Similarly, in the data block address management area B1614, physical block numbers corresponding to the logical block numbers 00 to DF are stored.
[0039]
The spare block address management area A 1612 and the spare block address management area B 1615 are similar to the data block address management area A 1611 and the data block address management area B 1614, respectively, and correspond to the logical block numbers F0 to FF. Each block number is stored. For example, since the physical block number corresponding to the logical block number F0 in the spare block address management area A1612 is 02, the spare block 0 data stored in the logical block number F0 in the logical memory space is In the physical memory space, the physical block number 02 is stored.
[0040]
As described above, in the present embodiment, the data block address management area A 1611 and the spare block address management area A 1612, the data block address management area B 1614 and the spare block address management area B 1615 are each 1-byte physical block numbers. Is stored.
[0041]
In this embodiment, since the total number of blocks in the data block area A1501 and the data block area B1502 exceeds 256 blocks and is 512 blocks or less, the logical block number holding area A1621 is a logical block composed of 2 bytes. Keep the number. In this logical block number holding area A1621, 16 logical block numbers can be stored and held. Then, the logical block number designated from the head is stored in accordance with the number of writing or reading block data and in accordance with the order of writing or reading. At this time, since the same data is stored in the logical block number holding area B1622, it does not have to be secured. Each logical block number holding area A 1621 and logical block number holding area B 1622 store values converted into logical block numbers of 256 blocks or less so that each corresponding data area A 1603 and data area B 1604 can be individually specified. You may make it do. The number of blocks that can be stored and held in each of the logical block number holding area A 1621 and the logical block number holding area B 1622 is not limited to 16.
[0042]
The physical block number holding area A 1623 and the physical block number holding area B 1624 can store and hold 16 1-byte physical block numbers. In the physical block number holding area A 1623 and the physical block number holding area B 1624, the logical block number specified from the top in accordance with the number of writing or reading block data and in accordance with the order of writing or reading, The physical block number associated with the address management area A1601 or the address management area B1602 is stored. The number of blocks that can be stored and held in the physical block number holding area A 1623 and the physical block number holding area B 1624 is not limited to 16.
[0043]
In the spare block number holding area A 1625 and the spare block number holding area B 1626, it is possible to store and hold 16 1-byte spare block numbers. In the spare block number holding area A 1625 and the spare block number holding area B 1626, block data added to the write command from the head in accordance with the number of writing or reading block data and in accordance with the order of writing or reading or The physical block number in the physical memory space corresponding to the logical block number of the spare block area A1503 or the spare block area B104 in the logical memory space in which the block data added to the read response is stored is stored. The number of blocks that can be stored and held in the spare block number holding area A 1625 and the spare block number holding area B 1626 is not limited to 16.
[0044]
By holding the logical block number, physical block number, and spare block number in this way, even if processing is interrupted due to power interruption during data writing or reading processing, the data is reliably transferred at the time of interruption or the original It is possible to return to the state, and data errors can be prevented.
[0045]
Next, command processing of this embodiment will be described with reference to the flowchart shown in FIG.
[0046]
When the IC card 101 starts receiving a command from the reader / writer 102 (step S1701), the IC card 101 determines which command is the received command (step S1702), and if it is a write command, receives the command. The added block data is stored in the spare block (step S1703). At this time, the write block data is stored in the block data of the physical block number indicated in the spare block address management area. Here, the same data is written in each of the spare block area A1503 and the spare block area B1504.
[0047]
If the received command is not a write command, step S1703 is skipped. After completion of command reception (step S1704), processing contents for each command are executed (step S1705). Here, as a result of confirming the received data (step S1706), if there is an error in the received data due to a malfunction in transmission or an abnormality is confirmed in the specified parameter, an error response is transmitted (step S1706). In step S1707, the process shifts to a command reception wait, or shifts to a command reception wait without transmitting an error response.
[0048]
If each process can be executed normally, the received command is determined (step S1708). If the received command is not a write command or a read command, response transmission is started (step S1711), and after the response transmission is completed (step S1714), the process shifts to command reception waiting. If the received command is a write command, a buffer determination flag area update process described later is performed (step S1709), and then an address management area update process corresponding to the write command is performed (step S1710). Thereafter, transmission of a response is started (step S1711), and after completion of response transmission (step S1714), the process proceeds to command reception waiting.
[0049]
If the received command is a read command, after updating the buffer determination flag area (step S1709), the address management area corresponding to the read command is updated (step S1711). Thereafter, transmission of a response is started (step S1711), and the response is transmitted while reading block data from the spare block rewritten by the update process (step S1712, step S1713). Then, transmission of the response is completed (step S1714), and after address management area restoration processing is performed (steps S1715 and S1716), the process shifts to a command reception wait state.
[0050]
Next, the buffer determination flag area update process shown in step S1709 of FIG. 6 will be described with reference to the flowchart shown in FIG.
[0051]
First, the logical block number designated by the command is extracted from the head (step S1801), and a determination process is performed to determine whether the M (M = 1, 2,...) Logical block number is F0 or more (step S1802). . In the present embodiment, since the number of blocks in each of the divided data block areas is F0, the specified write block corresponds to the data block area A1501 by the logical block number determination process in step S1802. Or whether it corresponds to the data block area B1502.
[0052]
If the designated logical block number is smaller than F0, 00 is written in the corresponding Mth buffer determination flag (step S1803), and if it is equal to or greater than F0, the corresponding Mth buffer determination. 01 is written in the flag (step S1804). Then, it is determined whether or not all the designated blocks have been completed (step S1805), and the processes of steps S1801 to S1804 are repeated until the process is completed, and the writing process to the buffer determination flag is performed for all the blocks designated by the command. To implement.
[0053]
FIG. 5 shows an example where a logical block to be written in the order of 0001, 00F2, 0000, and 00F3 is specified in the command. In this case, the flag value is stored in the buffer determination flag area 1606 in the order of 00, 01, 00, 01 by the update process of the buffer determination flag area.
[0054]
Next, the address management area update processing shown in step S1710 of FIG. 6 will be described with reference to the flowchart shown in FIG. First, as processing contents at the time of receiving a write command, logical block numbers 0001, 00F2, 0000, 00F3 are designated in the order of the block data of a total of two blocks one by one alternately in the data block area A1501 and the data block area B1502. A procedure for performing the writing process will be described. FIG. 5 shows a memory configuration in a state before receiving a write command and executing a write process.
[0055]
In the update process of the address management area, first, it is determined whether it is a write command process or a read command process (step S1901). If it is write command processing, logical block number holding processing is performed (step S1902). In this embodiment, the logical block numbers are recorded in the logical block number holding area A1621 shown in FIG. 5 in the order of the designated logical block numbers 0001, 00F2, 0000, and 00F3. Note that the logical block number may be similarly held in the logical block number holding area B1622.
[0056]
Subsequently, based on the value of the buffer determination flag held in the buffer determination flag area 1606, an area for holding and updating each block number is selected from either the address management area A1601 or the address management area B1602 (step S1903). Thereafter, the physical block number is held in the physical block number holding area A 1623 or B 1624 of the target area (step S 1904). The physical block numbers corresponding to the designated logical block numbers 0001, 00F2, 0000, and 00F3 are F1, F0, 00, and 13 indicated by bold lines in FIG. 5 from the data block address management areas A1611 and B1614. Block numbers are sequentially recorded in physical block number holding areas A1623 and B1624, respectively.
[0057]
Further, the spare block number is held in the spare block number holding area A1625 or B1626 of the target area (step S1905). In the example of FIG. 5, the physical block numbers of the first block and the third block in the spare block address management area A1612 before processing are 02 and 05 indicated by the thick line frame in the figure, and in the spare block address management area B1615. The physical block numbers of the second block and the fourth block are 11, F3 indicated by a bold frame in the drawing. Accordingly, these physical block numbers are stored in the spare block number holding areas A1625 and B1626, respectively. Further, the number of write blocks (corresponding to the number of write blocks and the total number of updated blocks) (N = 4) is held in the parameter area 1605 of the nonvolatile memory (step S1906).
[0058]
Next, the number of write processing counters (corresponding to the number of updated blocks) (M = 0) is incremented (+1) and the value (M = 1) is held in the parameter area 1605 of the nonvolatile memory (step S1907). Subsequently, the physical block number corresponding to the (M = 1) th write process is updated (step S1908). In the present embodiment, the physical block number 02 of the first spare block corresponding to the physical block number F1 corresponding to the first logical block number 01 in the data block address management area A1611 is written and updated. Furthermore, the spare block number corresponding to the (M = 1) -th write process is updated (step S1909). Here, the physical block number F1 of the corresponding first data block is written to the first physical block number 02 in the spare block address management area A1612, and the physical block numbers of the data block and the spare block are rewritten to each other.
[0059]
Thereafter, it is confirmed whether or not the write process is completed based on the write process in-progress information obtained from the number of write blocks and the write process counter (N = M) (step S1910). If not completed, the process returns to step S1907. The number of write processing counters is incremented (+1), and the physical block numbers of the second data block and the spare block in the target area are continuously rewritten to each other (steps S1907 to S1909). When the write process is completed, the write process counter number is cleared (M = 0) (step S1911), and the update process of the address management areas A1601 and B1602 is ended. FIG. 9 shows a memory configuration in a state where the writing process at this time is completed. Also, a response to the write command is transmitted after the address management area update processing is completed.
[0060]
The update process of the address management area is a block data writing process. That is, in the target area specified by the command in the divided data area, the block data to be written by the write command is temporarily stored in the spare block, and the logical block and spare block specified by the write command in the address management area The block data writing process is completed by rewriting the block number so that. The block number update process in the address management area can be performed at a higher speed than the block data write process in the conventional write process.
[0061]
In this embodiment, since the logical block number of the spare block area in which the block data designated at the time of the writing process is stored in each data area is fixed as F0 to FF, it always corresponds to the same logical block number. Thus, the block data is stored in the spare block area substantially in parallel with the transmission processing of the received data. High speed processing is realized.
[0062]
Further, when the power supply is interrupted in the middle of the writing process, the writing process is not completed, so the number of write processing counters (M) stored in the parameter area 1605 of the nonvolatile memory is not cleared (≠ 0). It becomes. Therefore, by checking the value of the number of write processing counters (M) when the power is restored, it is possible to check whether or not a power interruption has occurred during the writing process.
[0063]
When the writing process is not completed as described above, when the process is resumed, the number of write blocks and the number of write processing counters stored in the parameter area 1605, the block numbers held in the block number holding areas A1613 and B1616, Based on the value of the flag in the buffer determination flag area 1606, an update process of an unprocessed block number is performed to complete the write process.
[0064]
Next, as the processing contents at the time of receiving the read command, the logical block numbers 0001, 00F2, 0000, and 00F3 are designated in the order, and the block data of the data block area A1501 and the data block area B1502 are alternately alternated in total. A procedure for performing the reading process will be described.
[0065]
In the command determination process in step S1901 in FIG. 8, if it is a read command process, based on the value of the buffer determination flag held in the buffer determination flag area 1606 as in the case of the write command process described above, An area for holding and updating each block number is selected from either the address management area A1601 or the address management area B1602 (step S1912).
[0066]
Thereafter, the spare block number is held in the spare block number holding area A1625 or B1626 of the target area (step S1913). In the example of FIG. 5, the physical block numbers of the first block and the third block in the spare block address management area A1612 before processing are 02 and 05 indicated by the bold line frame in the figure, and in the spare block address management area B1615. The physical block numbers of the second block and the fourth block are 11, F3 indicated by the bold line frame in the figure. Accordingly, these physical block numbers are stored in the spare block number holding areas A1625 and B1626, respectively. Further, the number of read blocks (corresponding to the number of read blocks and the total number of restored blocks) (N = 4) is held in the parameter area 1605 of the nonvolatile memory (step S1914).
[0067]
Next, the number of read processing counters (corresponding to the number of restored blocks) (M = 0) is incremented (+1) and the value (M = 1) is held in the parameter area 1605 of the nonvolatile memory (step S1915). Subsequently, the spare block number corresponding to the (M = 1) th read process is updated (step S1916). Here, the physical block number F1 of the corresponding first data block is written and updated to the first physical block number 02 in the spare block address management area A1612.
[0068]
Thereafter, it is confirmed whether or not the read process is completed based on the read process in-progress information obtained from the number of read blocks and the read process counter (N = M) (step S1917). If not completed, the process returns to step S1915. Then, the number of read processing counters is incremented (+1) and the physical block number of the second spare block in the target area is continuously rewritten (steps S1915 and S1916). When the read process is completed, the update process of the address management areas A1601 and B1602 is terminated.
[0069]
Note that the number of write processing counters (M) and the number of read processing counters (M), the number of write blocks (N) and the number of read blocks (N) may be shared, or may be provided separately.
[0070]
Then, after completion of the address management area update process, a response to the read command is transmitted. The read block data added to the response to the read command is the block data of the physical block number specified in the spare block address management area A1612 or B1615, and is read sequentially from the spare block 0 data by the number of read blocks. Sent while. Then, after the response is transmitted, the address management area is restored. Thus, the physical block numbers in the spare block address management areas A1612 and B1615 are returned to the state before receiving the read command.
[0071]
The update process and the return process of the address management area are the block data read process. That is, in the target area specified by the command in the divided data area, the block number is rewritten so that the logical block specified by the read command in the address management area and the spare block are replaced, and the block is replaced by the spare block. The block data reading process is completed by reading the data and then rewriting the block numbers of the spare block and the logical block back to the original state. The block number update process and the return process in the address management area can be performed at a higher speed than the block data read process in the conventional read process.
[0072]
In this embodiment, since the logical block number of the spare block area in which the block data designated at the time of read processing is stored in each data area is fixed as F0 to FF, it always corresponds to the same logical block number. Thus, the read processing from the spare block area of the block data is performed almost simultaneously with the transmission processing of the transmission data. Speeding up is realized.
[0073]
Further, when the power supply is interrupted in the middle of the read process, the read process is not completed, and the read process counter number (M) stored in the parameter area 1605 of the nonvolatile memory is not cleared (≠ 0). It becomes. Therefore, by checking the value of the read processing counter number (M) when the power is restored, it is possible to check whether or not a power interruption has occurred during the reading process.
[0074]
Thus, when the read process is not completed, when the process is resumed, the number of read blocks and the read process counter stored in the parameter area 1605, the block numbers held in the block number holding areas A1613 and B1616, Based on the value of the flag in the buffer determination flag area 1606, update processing of an unprocessed block number is performed and the read processing is completed.
[0075]
As described above, in the present embodiment, in the data area divided into a plurality, the value of the buffer determination flag is read out for the holding process and the update process of each block number during the update process of the address management area. If the value is 00, only the address management area A1601 is processed, and if the value of the buffer determination flag is 01, only the address management area B1602 is processed.
[0076]
Here, the logical block number in the address management area A 1505 matches the logical block number in the logical memory space viewed from the reader / writer 102. On the other hand, the logical block number of the address management area B 1506 is managed and controlled as a value obtained by subtracting F0 from the logical block number in the logical memory space viewed from the reader / writer 102. For example, when 00F2 is designated as the second block designation by the write command, as a result of the judgment processing of the logical block number and F0, it is judged that the processing is for the address management area B1602, and control is performed. As a logical block number, an operation result of 00F2-00F0 = 0002 is obtained. Therefore, in this case, processing is performed as writing to the logical block 02 in the address management area B1602.
[0077]
In the description of the above processing procedure, the block data storage process in the spare block at the time of receiving the write command is to write the same data in the spare block area A 1503 and the spare block area B 1504. However, the present invention is not limited to this. Absent. For example, whether the write block designated based on the logical block number added to the command by the target area determination process performed in the buffer determination flag area update process corresponds to the data block area A, or the data block It may be determined whether the area corresponds to the area B and only the corresponding spare block area may be written.
[0078]
With the above processing, in this embodiment, when the total number of blocks exceeds 256 blocks when managing data in block units, such as when the logical block number of the data block area is defined up to 1DF in the memory space. Even in such a case, it is possible to efficiently perform processing related to writing and reading without significantly increasing the memory capacity of the address management area or the like. That is, according to the present embodiment, even for a nonvolatile memory having a large capacity data area, the power supply is interrupted during the block data read process and write process without requiring a large amount of system control memory capacity. Data can be guaranteed when it occurs, and processing can be executed more efficiently and at high speed.
[0079]
【The invention's effect】
As described above, according to the present invention, even when a large-capacity data block area is handled in an IC card, it is possible to execute processing efficiently and at high speed while ensuring data guarantee at the time of power interruption. Become.
[Brief description of the drawings]
FIG. 1 is a block diagram of an IC card system according to an embodiment of the present invention.
FIG. 2 is a memory configuration diagram in a logical memory space according to the present embodiment.
FIG. 3 is a memory configuration diagram in a divided logical memory space according to the present embodiment;
FIG. 4 is a memory configuration diagram in a physical memory space according to the present embodiment.
FIG. 5 is a configuration diagram of an address management area in a physical memory space according to the present embodiment.
FIG. 6 is a flowchart showing the flow of data processing according to the present embodiment.
FIG. 7 is a flowchart showing a flow of buffer determination flag area update processing according to the present embodiment;
FIG. 8 is a flowchart showing a flow of address management area update processing according to the embodiment;
FIG. 9 is a configuration diagram of an address management area in a physical memory space after a write process according to the present embodiment.
[Explanation of symbols]
101 IC card
102 Reader / Writer
103,104 antenna
105 Demodulator
106 Control unit
107 ROM
108 RAM
109 Nonvolatile memory
110 Modulator
1401 Data block area
1402 Spare block area
1403 Address management area
1404 Parameter area
1405 Buffer judgment flag area
1501 Data block area A
1502 Data block area B
1503 Spare block area A
1504 Spare block area B
1505 Address management area A
1506 Address management area B
1507 Parameter area
1508 Buffer judgment flag area
1601 Address management area A
1602 Address management area B
1603 Data area A
1604 Data area B
1605 Parameter area
1606 Buffer judgment flag area
1607 Error check information
1611 Data block address management area A
1612 Spare block address management area A
1613 Block number holding area A
1614 Data block address management area B
1615 Spare block address management area B
1616 Block number holding area B
1621 Logical block number holding area A
1622 Logical block number holding area B
1623 Physical block number holding area A
1624 Physical block number holding area B
1625 Spare block number holding area A
1626 Spare block number holding area B

Claims (8)

Address information that associates two or more storage data areas for storing data to be stored, two or more buffer areas for storing target data at the time of write processing, and a logical address and a physical address related to the storage data area And a memory having two or more address management areas each storing address information associating a logical address and a physical address related to the buffer area at a predetermined physical address ,
Write data sent in correspondence with a command is stored in the buffer area at the time of a write process to the memory, and address information corresponding to the buffer area in the address management area and the storage data area specified by the command Memory control means for renewing the address information corresponding to each other and updating the address management area;
An IC card characterized by comprising: The memory is provided with a address holding area for holding target address information during the updating process in the address management area, the effective buffer area indicating which area among the two or more buffer areas are valid A buffer determination flag area for storing sex information, and a parameter area for storing in-writing information indicating that the writing process is in progress,
Said memory controlling means, at the time of writing process, based on a logical address designated by the command, and select the storage data area and buffer area of the write target from the two or more storage data area and buffer area, the Validity information for designating a target area is stored in the buffer determination flag area, a physical address corresponding to a logical address of a storage data area designated by the command in the address management area, and a physical address corresponding to the buffer area, Is temporarily stored in the address holding area, the write processing information is set in the parameter area, and the storage data area in the address management area of the effective target area based on the validity information of the buffer determination flag area Correspond to the physical address and the buffer area. After the update processing for rewriting the physical address from each other, IC card according to claim 1, wherein the returning the writing process in the information to the original state.   The memory control means determines whether or not the writing process is completed according to the information during the writing process, and when the writing process is not completed normally, the memory control unit stores the parameter area when the process is resumed. The update processing of the unprocessed physical address is completed based on the total number of updated physical address blocks and the number of updated blocks, the address information held in the address holding area, and the validity information of the buffer determination flag area. The IC card according to claim 2, wherein: Two or more storage data areas for storing data to be stored and held, two or more buffer areas for storing target data at the time of read processing, and a logical address and a physical address for the storage data area are associated with each other. A memory having two or more address management areas each storing address information and address information associating a logical address and a physical address related to the buffer area at a predetermined physical address ;
During the read process from the memory, the address management area is updated by rewriting the address information corresponding to the buffer area with the address information corresponding to the storage data area specified by the command in the address management area, and this update Memory control means for returning the address management area to the original state after reading the read data stored in the later buffer area;
An IC card characterized by comprising: The memory is provided with a address holding area for holding target address information during the updating process in the address management area, the effective buffer area indicating which area among the two or more buffer areas are valid A buffer determination flag area for storing sex information, and a parameter area for storing in-read information indicating that the read process is in progress.
Said memory controlling means, at the time of reading process, on the basis of the logical address specified by the command, and select the storage data area and the buffer area to be read from the two or more storage data area and buffer area, the Validity information for designating a target area is stored in the buffer determination flag area, and a physical address corresponding to the buffer area in the address management area is temporarily held in the address holding area, and the information during reading processing is stored in the parameter The physical address corresponding to the logical address of the storage data area specified by the command in the address management area of the valid target area is set to the buffer area based on the validity information of the buffer determination flag area. Update processing to rewrite the physical address After the read data stored in the updated buffer area is read out and after performing a restoration process to restore the physical address corresponding to the held buffer area, the information during the read process is returned to the original state. The IC card according to claim 4.   The memory control means determines whether or not the read process is completed based on the information during the read process. If the read process is not completed normally, the memory control unit stores the parameter area when the process is resumed. Based on the total number of restored physical addresses and the number of restored blocks, the address information held in the address holding area, and the validity information of the buffer determination flag area, the restoration processing of the unprocessed physical address is completed. 6. The IC card according to claim 5, wherein: Address information that associates two or more storage data areas for storing data to be stored, two or more buffer areas for storing target data at the time of write processing, and a logical address and a physical address related to the storage data area And at the time of data write processing to the memory in the IC card having two or more address management areas each storing address information associating a logical address and a physical address related to the buffer area at a predetermined physical address ,
A control unit in the IC card stores write data sent corresponding to the command in the buffer area of the memory;
Wherein the control unit is based on a logical address designated by said command, select two or more storage data area and the storage data area and buffer area of the writing object from the buffer area, the validity information specifying the region of interest Storing in the buffer determination flag area;
In the address management area for storing the address information of the memory , the control unit uses the physical address corresponding to the logical address of the storage data area specified by the command and the physical address corresponding to the buffer area as an address holding area. Holding once, and
The controller sets information during the writing process indicating that the writing process is in progress; and
The control unit rewrites a physical address corresponding to the storage data area and a physical address corresponding to the buffer area in the address management area of the valid target area based on validity information of the buffer determination flag area. Performing an update process of the address management area;
The controller returning the in-write information to the original state after the update process;
An information processing method for an IC card, comprising: Two or more storage data areas for storing data to be stored and held, two or more buffer areas for storing target data at the time of read processing, and a logical address and a physical address for the storage data area are associated with each other. When reading data from a memory in an IC card having address information and address information that associates a logical address and a physical address related to the buffer area with two or more address management areas respectively stored in predetermined physical addresses ,
Efficacy controller in the IC card, selects the storage data area and the buffer area to be read out from two or more storage data area and the buffer area based on the logical address specified in the command, specifying the target region Storing information in a buffer determination flag area;
A step wherein said control unit is once held in the address management area for storing address information of the memory, a physical address corresponding to the buffer area in said address holding area,
The control unit setting read-in-process information indicating that it is in the middle of a read process;
Based on the validity information of the buffer determination flag area , the control unit corresponds to the buffer area a physical address corresponding to the logical address of the storage data area specified by the command in the address management area of the valid target area. Rewriting to a physical address to perform the update process of the address management area,
The controller performs a restoration process of restoring the physical address corresponding to the held buffer area after reading the read data stored in the updated buffer area;
The control unit returning the in-reading information to the original state after the restoration process;
An information processing method for an IC card, comprising:

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