JP3919435B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a salicide structure, and more particularly to a countermeasure for preventing contamination.
[0002]
[Prior art]
In recent years, in order to suppress the short channel effect associated with the miniaturization of MISFETs in a semiconductor device, a structure in which an impurity diffusion layer serving as a source / drain region of a MISFET is formed as shallow as possible has been adopted. On the other hand, if the impurity diffusion layer is shallow, the sheet resistance of the impurity diffusion layer increases, and it becomes difficult to manufacture a semiconductor device with high speed and low power consumption.
[0003]
Therefore, recently, the upper part of the source / drain region is a silicide that is a compound of refractory metal and silicon, such as a TiSi ₂ film that is a compound of Si and Ti, or a CoSi ₂ film that is a compound film of Si and Co. In many cases, salicide treatment that changes the film is performed.
[0004]
On the other hand, in the MISFET used for the I / O portion, a silicide film is generally not formed on the source / drain regions in order to ensure the gate oxide film resistance and ESD resistance. That is, there are a silicide formation region and a non-salicide formation region on one semiconductor substrate.
[0005]
4A to 4C and 5A to 5C are cross-sectional views showing a conventional manufacturing method for a semiconductor device having a silicide formation region and a non-silicide formation region on one semiconductor substrate. It is.
[0006]
First, in the process shown in FIG. 4A, after forming the shallow trench isolation 102 in the Si substrate 101, the N well 103a and the P well 103b in the silicide formation region Rsc are formed by the photolithography process and the ion implantation process. A well 103c in the silicide formation region Rns is formed. In the non-silicide formation region Rns, there are a P well and an N well, but only one well is shown for convenience. Thereafter, the threshold control impurities and the channel stopper impurities are implanted into the wells 103a, 103b, and 103c.
[0007]
Next, a silicon oxide film 104 is formed on the surface of the Si substrate 101 by thermal oxidation, and a non-doped polysilicon film 105a is further deposited. Then, by the photolithography process and the ion implantation process, boron (B) in the portion located in the PMISFET formation region and arsenic (As) in the portion located in the NMISFET formation region of the non-doped polysilicon film 105a, respectively. Introduce. Further, a barrier conductor film 105b such as TiN (titanium nitride), a metal film 105c made of W (tungsten), and a silicon nitride film 106 are sequentially deposited on the polysilicon film 105a.
[0008]
Next, in the step shown in FIG. 4B, the silicon nitride film 106, the metal film 105c, the barrier conductor film 105b, the polysilicon film 105a, and the silicon oxide film 104 are patterned by a photolithography process and a dry etching process. Then, a gate insulating film 113, a gate electrode 115, and an on-gate protective film 114 of MISFET are formed. Further, by a photolithography process and an ion implantation process, arsenic ions (As) are formed in portions located in the NMISFET formation region using the photoresist mask and the gate electrode 115 as a mask in both the silicide formation region Rsc and the non-silicide formation region Rns. the ^+), the portion located PMISFET formation region by implanting boron ions (B ^+), respectively, to form a self-aligned manner extension region 110 with respect to the gate electrode.
[0009]
Next, in the step shown in FIG. 4C, a CVD oxide film is deposited on the substrate and then etched back by anisotropic etching to form the gate insulating film 113, the gate electrode 115, and the on-gate protective film 114. Oxide film sidewalls 116 are formed on the side surfaces. Further, in the silicide formation region Rsc and the non-silicide formation region Rns, a portion located in the NMISFET formation region using the photoresist mask, the gate electrode 115, and the oxide film sidewall 116 as a mask by the photolithography process and the ion implantation process. Are implanted with arsenic ions (As ⁺ ) and boron ions (B ⁺ ) are implanted into the PMISFET formation region to form the high concentration source / drain regions 111 outside the extension region 110.
[0010]
Next, in the step shown in FIG. 5A, after depositing a CVD oxide film on the substrate, a photoresist film 109 is formed on the CVD oxide film so as to cover the non-silicide region Rns and open the silicide formation region Rsc. To do. Then, by wet etching using a hydrofluoric acid solution using the photoresist film 109 as a mask, a portion of the CVD oxide film located in the silicide formation region Rsc is selectively removed, and the reaction is prevented from covering the non-silicide region Rns. An oxide film 118 is formed.
[0011]
Next, in the step shown in FIG. 5B, the photoresist film 109 is removed by a plasma ashing process, and a cleaning process using a sulfuric acid / aqueous hydrogen peroxide solution.
[0012]
Next, a salicide process is performed in the process shown in FIG. At that time, after the residue is removed by washing with diluted hydrofluoric acid (DHF) or the like, a metal film such as a cobalt film (Co film) or a titanium film (Ti film) is deposited on the substrate. Then, heat treatment is performed in an N ₂ atmosphere to cause Co and Si to react to form a silicide layer 112 on top of the high concentration source / drain region 111.
[0013]
[Problems to be solved by the invention]
However, in the method of manufacturing a semiconductor device, when the CVD oxide film is etched with diluted hydrofluoric acid (DHF) and patterned in the step shown in FIG. There is a problem that a spot is generated on the region 111 and a good silicide layer is not formed on the spot 111. When the stain occurs, it cannot be removed unless excessive etching is performed in the DHF before depositing the Co film (or Ti film) shown in FIG. 5C. However, by performing excessive etching, the shallow trench isolation portion is removed. The oxide film and the reaction preventing oxide film covering the non-salicide region are etched, which may cause another problem.
[0014]
That is, if such a stain is generated by a process such as etching after removing the photoresist film, there is a possibility that various processes after that cannot be performed properly.
[0015]
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of appropriately performing various processes such as a salicide process by taking means for preventing the generation of a stain after a photoresist film removal process.
[0016]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device of the present invention, on the surface of the semiconductor layer on the substrate, a step of forming a stain-preventing oxide film (a), after said step (a), the surface of the stain-preventing oxide film (B) forming a coating insulating film capable of selective etching on the stain-preventing oxide film; and a photoresist film having a part of the semiconductor layer region opened on the coating insulating film. A step (c) of forming a film, a step (d) of etching the coating insulating film while leaving the stain-preventing oxide film using the photoresist film as a mask, and removing the photoresist film by ashing and washing And (e) removing the stain-preventing oxide film.
[0017]
By this method, when the photoresist film is removed, the stain-preventing oxide film is present, so that the subsequent process proceeds with the surface of the semiconductor layer being hydrophilic. Therefore, it can be avoided that the subsequent process is improperly performed due to a stain remaining on the semiconductor layer.
[0018]
In the step (a), by ashing treatment, ashing oxide film is formed on a surface portion of the semiconductor layer as oxide film for preventing the stain, in the step (b), by atmospheric pressure CVD, and with the coating insulating film by forming the oxidation film, it is possible to form a coating oxide film with a high stain preventive oxide film etching selectivity to each other.
[0019]
Then, the in step (d), by a vapor HF treatment, while leaving the ashing oxide film can be patterned on hexane monolayer.
[0020]
After the step (e), it is possible to form an appropriate silicide layer without generating an insufficient silicidation portion due to the presence of a stain by further including a step of siliciding the upper portion of the semiconductor layer. .
[0021]
The semiconductor layer is a source / drain region of a MISFET in a silicide formation region on the substrate. In the step (c), a portion covered with the photoresist film in the semiconductor layer region is a non-silicide formation region on the substrate. As a result, the coating insulating film can be used as a reaction preventing film covering the non-silicide formation region in the salicide process.
[0022]
When the semiconductor layer is a source / drain region of a MISFET having a polymetal gate structure or a metal gate structure, in the step (e), ashing with plasma and cleaning with a tetramethylammonium hydroxide solution are performed. By removing the photoresist film, the photoresist film can be removed without adversely affecting the metal portion.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIGS. 1A to 1C and FIGS. 2A to 2C illustrate a semiconductor device having a silicide formation region and a non-silicide formation region on a semiconductor substrate according to the first embodiment of the present invention. It is sectional drawing which shows a manufacturing method.
[0024]
First, after forming the shallow trench isolation 2 in the Si substrate 1 in the process shown in FIG. 1A, the N well 3a and the P well 3b in the silicide formation region Rsc are formed by a photolithography process and an ion implantation process. A well 3c in the silicide formation region Rns is formed. In the non-silicide formation region Rns, there are a P well and an N well, but only one well is shown for convenience. Thereafter, threshold control impurities and channel stopper impurities are implanted into the wells 3a, 3b, 3c.
[0025]
Next, a silicon oxide film 4 is formed on the surface of the Si substrate 1 by thermal oxidation, and a non-doped polysilicon film 5a to be a lower gate electrode is further deposited. Then, by the photolithography process and the ion implantation process, boron (B) in the portion located in the PMISFET formation region and arsenic (As) in the portion located in the NMISFET formation region in the non-doped polysilicon film 5a, respectively. Introduce. Further, a barrier conductor film 5b such as TiN (titanium nitride), a metal film 5c made of W (tungsten film) or the like serving as an upper gate electrode, and a silicon nitride film 6 are sequentially deposited on the polysilicon film 5a. .
[0026]
Next, in the step shown in FIG. 1B, the silicon nitride film 6, the metal film 5c, the barrier conductor film 5b, the polysilicon film 5a and the silicon oxide film 4 are patterned by a photolithography process and a dry etching process. Then, a gate insulating film 13, a gate electrode 15 and an on-gate protective film 14 of MISFET are formed. Further, arsenic ions (As) are formed in a portion located in the NMISFET formation region by using the photoresist mask and the gate electrode 15 in both the silicide formation region Rsc and the non-silicide formation region Rns by the photolithography process and the ion implantation process. the ^+), the portion located PMISFET formation region by implanting boron ions (B ^+), respectively, to form a self-aligned manner extension region 10 with the gate electrode.
[0027]
Next, in the step shown in FIG. 1C, a CVD oxide film is deposited on the substrate, and then etched back by anisotropic etching to form the gate insulating film 13, the gate electrode 15, and the on-gate protective film 14. Oxide film sidewalls 16 are formed on the side surfaces. Further, in the silicide formation region Rsc and the non-silicide formation region Rns, a portion located in the NMISFET formation region by using the photoresist mask, the gate electrode 15 and the oxide film sidewall 16 as a mask by the photolithography process and the ion implantation process. Are implanted with arsenic ions (As ⁺ ) and boron ions (B ⁺ ) are implanted into the PMISFET formation region to form the high concentration source / drain regions 11 outside the extension region 10.
[0028]
Next, in the step shown in FIG. 2A, the exposed silicon layer is formed on the substrate by an oxidation process using plasma in an oxygen atmosphere, that is, the same process as the ashing for removing the photoresist film. The surface portion is oxidized to form an ashing oxide film 17 having a thickness of about 5 nm, and a CVD oxide film having a thickness of about 50 nm is deposited on the substrate by atmospheric pressure CVD. As a result, a two-layer film composed of the ashing oxide film 17 and the CVD oxide film is formed on the high concentration source / drain regions 11 in the silicide formation region Rsc and the non-silicide formation region Rns.
[0029]
Next, a photoresist film 9 is formed on the CVD oxide film so as to cover the non-silicide region Rns and open the silicide formation region Rsc. Subsequently, by a vapor-phase hydrofluoric acid process using the photoresist film 9 as a mask, only a portion of the CVD oxide film located in the silicide formation region Rsc is selectively removed while the ashing oxide film 17 is left, and the non-silicide region A reaction preventing oxide film 18 covering Rns is formed. At this time, the ashing oxide film 17 remains on the high concentration source / drain region 11, and the surface of the ashing oxide film 17 is washed and dried in a hydrophilic state. It is possible to suppress the occurrence of spots in Since the etching selection ratio between the ashing oxide film 17 by the vapor-phase hydrofluoric acid treatment and the reaction preventing oxide film 18 made of the CVD oxide film is 100 or more, a sufficient time margin in the selective etching can be secured.
[0030]
Next, in the step shown in FIG. 2B, the photoresist film 9 is removed by plasma ashing and TMAH solution (tetramethylammonium hydroxide solution). According to the cleaning with the TMAH solution, it is possible to remove the ashed resist residue without dissolving the polymetal as in the case of using the sulfuric acid / aqueous ammonia solution. Therefore, even when the on-gate protective film 14 is not provided as in the present embodiment, no problem occurs.
[0031]
Next, in the step shown in FIG. 2C, the ashing oxide film 17 is removed in the silicide formation region Rsc by etching using a DHF liquid (H ₂ O: 50% HF = 500: 1), and the IPA liquid is used. After the surface of the high concentration source / drain region 11 is cleaned by a drying process, a metal film such as a cobalt film (Co film) or a titanium film (Ti film) is deposited on the substrate. Then, heat treatment is performed in an N ₂ atmosphere to cause Co and Si to react to form a silicide layer 12 on top of the high concentration source / drain region 11.
[0032]
According to the manufacturing method of this embodiment, the ashing oxide film 17 is formed on the surface of the high-concentration source / drain region 11 and the reaction preventing oxide film 18 is formed thereon in the step shown in FIG. A CVD oxide film is formed, and a laminated film of an ashing oxide film 17 and a CVD oxide film is formed on the high concentration source / drain region 11. Then, by the vapor-phase hydrofluoric acid treatment using the photoresist film 9 as a mask, the reaction is prevented by selectively removing only the portion of the CVD oxide film located in the silicide formation region Rsc while leaving the ashing oxide film 17 left. Since the working oxide film 18 is formed, the ashing oxide film 17 remains on the high concentration source / drain region 11. Therefore, even if cleaning and drying processes are performed thereafter, the surface of the ashing oxide film 17 is cleaned and dried in a hydrophilic state. Therefore, after the ashing oxide film 17 is removed in the silicide formation region Rsc, an appropriate silicide layer having almost no imperfect silicidation due to the stain is formed on the high concentration source / drain region 11 without the stain. 12 can be formed.
[0033]
(Second Embodiment)
3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
[0034]
Also in the present embodiment, the steps shown in FIGS. 1A to 1C are performed as in the first embodiment.
[0035]
Thereafter, in the step shown in FIG. 3A, a CVD oxide film having a thickness of about 50 nm is deposited on the substrate by atmospheric pressure CVD. Next, a photoresist film 9 is formed on the CVD oxide film so as to cover the non-silicide region Rns and open the silicide formation region Rsc. Subsequently, by a hydrofluoric acid treatment using the photoresist film 9 as a mask, only a portion of the CVD oxide film located in the silicide formation region Rsc is selectively removed, and the reaction preventing oxide film 18 covering the non-silicide region Rns is removed. Form. Further, after washing with water, washing is performed with O ₃ water (ozone water) or hydrogen peroxide water (H ₂ O ₂ ). The hydrofluoric acid treatment to O ₃ water treatment (or hydrogen peroxide solution treatment) are continuously performed in the same spin etch apparatus.
[0036]
At this time, a chemical oxide film 19 having a thickness of about 1 nm is formed on the high concentration source / drain region 11 by performing O ₃ water treatment (or hydrogen peroxide solution treatment). Since the surface of the chemical oxide film 19 is washed and dried in a hydrophilic state, the occurrence of spots on the high concentration source / drain region 11 can be suppressed.
[0037]
Next, in the step shown in FIG. 3B, the photoresist film 9 is removed by plasma ashing and TMAH solution. According to the cleaning with the TMAH solution, it is possible to remove the ashed resist residue without dissolving the polymetal as in the case of using the sulfuric acid / aqueous ammonia solution. Therefore, even when the on-gate protective film 14 is not provided as in the present embodiment, no problem occurs.
[0038]
Next, in the step shown in FIG. 3C, the chemical oxide film 19 is removed in the silicide formation region Rsc by etching using a DHF liquid (H ₂ O: 50% HF = 500: 1), and the IPA liquid is used. After the surface of the high concentration source / drain region 11 is cleaned by a drying process, a metal film such as a cobalt film (Co film) or a titanium film (Ti film) is deposited on the substrate. Then, heat treatment is performed in an N ₂ atmosphere to cause Co and Si to react to form a silicide layer 12 on top of the high concentration source / drain region 11.
[0039]
According to the manufacturing method of the present embodiment, in the step shown in FIG. 3A, only the portion of the CVD oxide film located in the silicide formation region Rsc is selectively removed, and then continuously in the same spin etch apparatus. Since the chemical oxide film 19 is formed on the high-concentration source / drain region 11 by performing O ₃ water treatment (or hydrogen peroxide water treatment), the high-concentration source / drain region 11 is formed in the meantime. There will be no stains. Further, even if a cleaning and drying process is performed in the subsequent processes, the surface of the chemical oxide film 19 is cleaned and dried in a hydrophilic state, so that the generation of spots on the high concentration source / drain region 11 is suppressed. can do. Therefore, after the chemical oxide film 19 is removed in the silicide formation region Rsc, an appropriate silicide layer having almost no imperfect silicidation due to the stain is formed on the high concentration source / drain region 11 without the stain. 12 can be formed.
[0040]
In each of the above embodiments, the silicide layer is provided only in the source / drain region, but the upper gate electrode may be formed of a silicide film instead of a metal film. In that case, without providing the protective film on the gate, the upper part of the polysilicon film constituting the lower gate electrode may be silicided simultaneously with the silicidation process of the source / drain region, or the silicidation process of the source / drain region. In another case, after performing a silicidation process on the upper part of the polysilicon film, the polycide film may be patterned to form a gate electrode composed of an upper gate electrode and a lower gate electrode.
[0041]
Further, the step of forming the ashing oxide film or the chemical liquid oxide film, which is the oxide film for preventing stains according to the present invention, is not limited to the case where the silicide layer is formed on the source / drain regions. The present invention can be applied to processing before or after the formation of the photoresist film to be used and the photoresist film to be a mask for ion implantation for forming the dual gate.
[0042]
In each of the above embodiments, the description and illustration of the process for forming the wiring layer is omitted, but a so-called SAC structure in which the contact is formed in a self-aligned manner with respect to the gate electrode after forming the interlayer insulating film. Can be taken. This is because, in any of the embodiments, an on-gate protective film made of a silicon nitride film and an oxide film sidewall are provided.
[0043]
In each of the above embodiments, a MISFET having a so-called LDD structure having an LDD region and a high concentration source / drain region has been described. However, the present invention is not limited to such an embodiment, The present invention can also be applied to a semiconductor device having source / drain regions.
[0044]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, the process for removing the photoresist film having the opening on the semiconductor layer is advanced while maintaining the surface state of the semiconductor layer hydrophilic. It is possible to provide a method of manufacturing a semiconductor device free from various problems caused by the above.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a process until a high concentration source / drain region is formed in a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 shows a reaction preventing film by patterning a CVD oxide film in the manufacturing process of the semiconductor device according to the first embodiment of the present invention; and further, a silicide layer is formed after forming a stain preventing oxide film. It is sectional drawing which shows the process until it forms.
FIG. 3 shows a reaction preventing film by patterning a CVD oxide film in a manufacturing process of a semiconductor device according to a second embodiment of the present invention; and further, a silicide layer is formed after forming a stain preventing oxide film. It is sectional drawing which shows the process until it forms.
FIG. 4 is a cross-sectional view showing a process until a high concentration source / drain region is formed in a conventional semiconductor device manufacturing process;
FIG. 5 is a cross-sectional view showing a process from patterning a CVD oxide film to form a reaction preventing film until a silicide layer is formed in a conventional semiconductor device manufacturing process.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Si substrate 2 Shallow trench isolation | separation 3a N well 3b P well 3c well 4 Silicon oxide film 5a Polysilicon film 5b Barrier conductor film 5c Metal film 6 Silicon nitride film 9 Photoresist film 10 Extension region 11 High concentration source / drain region 13 Gate Insulating film 14 Protective film on gate 15 Gate electrode 17 Ashing oxide film 18 Oxide film for reaction prevention 19 Chemical oxide film

Claims (6)

A step (a) of forming a stain-preventing oxide film on the surface of the semiconductor layer on the substrate;
After the step (a), a step (b) of forming a coating insulating film capable of selective etching with respect to the stain-preventing oxide film on the surface of the stain-preventing oxide film;
A step (c) of forming a photoresist film having an opening in a part of the semiconductor layer region on the covering insulating film;
Using the photoresist film as a mask, leaving the stain-preventing oxide film and etching the coating insulating film (d);
(E) removing the photoresist film by ashing and washing and then removing the stain-preventing oxide film. In the manufacturing method of the semiconductor device according to claim 1,
In the step (a), an ashing oxide film is formed on the surface portion of the semiconductor layer as the stain-preventing oxide film by ashing,
The step (b), the atmospheric pressure CVD method, a method of manufacturing a semiconductor device characterized by forming an oxidation film by the above coating insulating film. The method of manufacturing a semiconductor device according to claim 2.
In the step (d), by a vapor HF treatment, while leaving the ashing oxide film, a method of manufacturing a semiconductor device, which comprises patterning the upper hexane monolayer. In the manufacturing method of the semiconductor device according to claim 1,
After the step (e), the method further includes the step of siliciding the upper portion of the semiconductor layer. In the manufacturing method of the semiconductor device according to claim 4,
The semiconductor layer is a source / drain region of a MISFET in a silicide formation region on a substrate,
In the step (c), the part covered with the photoresist film in the semiconductor layer region is a non-silicide formation region on the substrate. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The semiconductor layer is a source / drain region of a MISFET having a polymetal gate structure or a metal gate structure,
In the step (e), a method of manufacturing a semiconductor device, wherein the photoresist film is removed by performing ashing with plasma and cleaning with a tetramethylammonium hydroxide solution.

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