JP3916159B2 - Flip chip connection by solder bump - Google Patents

Description

  The present invention relates to a flip-chip connection method using solder bumps in which solder bumps are formed on a substrate side and directly connected to a chip-side pad.

  In order to mount various modules for an ultra-high-speed communication system, it is important that the modules constituting the modules be mounted without degrading the electrical characteristics and that the high-speed and wide-band characteristics of the module can be maintained. In order to electrically connect an ultrahigh-speed IC to a high-density wiring board, a high-density mounting technique in which the connection length is as short as possible is required.

  It is known that the conventional wire bonding increases the floating inductance, and does not exhibit good characteristics in the high frequency region. In order to avoid such a problem, electrical connection using a fine solder bump is effective.

  The most common method of solder bump connection, controlled collapse chip connection, is a solder formed on a metal pad with good “solder wettability” on the chip side and a “ Connect using solder formed on pads with good solder wettability. That is, after the chip is aligned with the flip chip substrate, all the connections are completed by melting the solder.

In flip chip solder bump connection, solder bumps are formed on the IC chip side. For this reason, in such a method, assuming that an arbitrary IC chip is connected to the substrate, a very complicated process is required, resulting in poor productivity and high cost. That is, in order to form a flip chip connection, a process of forming bumps on the surface of the IC chip is added when the IC chip is in a wafer state. For this reason, it has been a big problem that the yield of IC chips falls and the price increases (Non-patent Document 1).
"Microelectronics Package Handbook", published in 1991, Japanese translation

The object of the present invention is to form bumps on the substrate side, and to form a tray that forms a partition layer made of a metal film with good wettability on the flip chip side as a receiving tray for preventing solder from flowing. It is an object of the present invention to provide a flip chip connection method using solder bumps which can be formed and directly connected to a substrate in a flip chip single state.

In order to solve the above-mentioned problem, the invention of claim 1 melts when a solder bump made of an alloy of Sn _1-x M _x (M: one or more metals other than Sn) is formed on a substrate. An insulating film having a composition of SiN _x O _1-x (0 ≦ x ≦ 1) is formed on a solder bump metal layer to be a solder bump , an opening 6A is formed in the insulating film 6, and the metal layer 5 in the opening 6A is formed. A separation layer of a metal film is formed on the insulating film 6, a fusion splicing metal layer is formed on the separation layer to be a solder for connection to a pad of the flip chip, and the flip chip and the substrate are This is a flip-chip connection method using solder bumps, which is characterized by being connected.
According to a second aspect of the present invention, in the flip chip connection method using solder bumps according to the first aspect, a laminated film containing Ti and Pt is used as the separation layer.
According to a third aspect of the present invention, in the flip chip connection method using solder bumps according to the first or second aspect of the present invention, as the connection solder, Sn _1-x M _x (M: one or more other than Sn) A metal alloy).
According to a fourth aspect of the present invention, in the flip chip connecting method using the solder bump according to the first aspect, a mask to be patterned is formed on the substrate, a metal film having a solder composition is deposited on the mask, and then An insulating film is formed on the metal film, and then the mask is removed to form a bump precursor A composed of the bump metal layer and the insulating film .
According to a fifth aspect of the present invention, in the flip-chip connection method according to the fourth aspect , an organic resist material is used as the patterning mask, and the mask is removed by a lift-off method.

  According to the present invention, a tray as a partition wall, that is, a metal film separation layer is formed on a normal bump metal. Further, the gold on the pad portion of the flip chip and a solder metal that can be melted are deposited thinly. After that, the flip chip is aligned with the substrate and then reflowed to perform flip chip connection.

According to the present invention, an insulating film such as SiO _2, SiN or SiON is inserted on a solder bump, a separation layer to be a partition layer is sandwiched thereon, and a flip chip pad is connected thereon. The solder can be formed to directly connect the flip chip and the substrate. In other words, according to the present invention, the ability to directly connect the substrate and the flip chip by solder bumps without forming bumps on the flip chip side contributes greatly to the cost reduction in the packaging of compound ultra-high speed semiconductor devices. To do.

  Hereinafter, embodiments of the present invention will be described together with knowledge obtained in making the present invention.

  When solder bumps are formed on the substrate and then directly connected to the flip chip pads, tin, which is the main component of the solder, is sucked into the gold of the flip chip pads and is not used. Therefore, it is possible to stop the reaction between Sn (tin) and Au (gold) by forming a tray as a partition layer, that is, a separation layer of a metal film, on the solder bump precursor.

  However, since the metal of the separation layer usually does not have a fusion property with gold, the substrate and the flip chip cannot be connected. Therefore, by forming a second solder layer mainly composed of tin on the separation layer, it is possible to fuse and connect the gold of the flip chip pad.

  However, even if such a process experiment was repeated, a satisfactory flip chip connection could not be obtained. The reason is that a large amount of solder is sucked into the gold during reflow because the solder metal for bump comes into contact with the gold pad on the flip chip side due to the pressurization at the time of temporary fixing. So-called “golden erosion” occurs, and satisfactory flip chip connection is not possible.

In order to avoid the above-mentioned problem, the wettability with tin such as SiO ₂ is poor after the deposition of the solder bump metal so that the bump solder metal and the gold on the flip chip side pad are not brought into contact with each other. In addition, it was expected that the use of a heat-resistant inorganic insulating film as a separation layer for both would be effective.

Based on the results of such studies, the present inventors have investigated the wettability with tin in the course of many experiments in order to form solder bumps, separation layers, and fusion spliced solder on the substrate all at once. An insulating film such as SiO ₂ or SiN or SiON is inserted as a poor inorganic material, and a laminated film of Ti and Pt is used as a separation layer thereon, and a solder metal for fusion splicing is simultaneously formed thereon. Thus, it has been found that a good flip chip connection can be formed by separating the solder bump metal and the fusion splicing metal, and the present invention has been made.

Next, examples of the present invention will be described. It should be noted that the following embodiment is merely an example, and various changes or improvements can be made without departing from the technical idea of the present invention.
[Example 1]

In this embodiment, as shown in FIG. 1, a wiring layer 2 of a single-layer wiring using metal is formed on a GaAs substrate for chip connection. After the wiring layer 2 is formed, SiO ₂ is laminated by a 100 nm sputtering method to form an insulating film 3 of SiO ₂ . The insulating film 3 is an inorganic insulating film. Further, after the opening is formed in the insulating film 3, the base 4 is formed.

Thereafter, as shown in FIG. 2, an organic resist material 31 is applied, and patterning is performed using the organic resist material 31, and openings 31 </ b> A are formed in the organic resist material 31 as shown in FIG. 3. In addition, Sn: 600 nm → Au: 20 nm was repeated 10 times to obtain a solder alloy film (composition: Sn _0.95 Au _0.05 , melting point: 217 ° C.) of about 6.2 μm as shown in FIG. Thus, the solder bump metal layer 5 was formed.

After the formation of the solder bump metal layer 5, as shown in FIG. 5, SiO ₂ was deposited by a 200 nm sputtering method to form an insulating film 6. The insulating film 6 is an inorganic material having poor wettability with tin so as not to contact the solder bump metal layer 5 and the gold on the flip chip side pad. After the formation of the insulating film 6, lift-off was performed using an organic solvent, and as shown in FIG. 6, a fine bump precursor A of 80 ^μmφ was formed.

Next, as shown in FIG. 7, using an organic resist material 32, patterning of 24 μm ^φ is performed to form an opening 32A. Thereafter, as shown in FIG. 8, to remove a portion of the insulating film 6 by dry etching to form an opening 6A of 24 [mu] m ^phi in the insulating film 6 of SiO _2. As a result, openings 6A are formed in the bump precursor A as shown in FIG.

Next, as shown in FIG. 10, by using an organic resist material 33, patterning is performed for 36 .mu.m ^phi, to form an opening 33A. Thereafter, as shown in FIG. 11, a tray of Ti (100 nm) / Pt (200 nm) / Au (20 nm), that is, a metal film separation layer 7 is formed. After the formation of the separation layer 7, as shown in FIG. 12, the fusion splicing metal layer 8 is formed by repeating Sn: 300 nm → Au: 10 nm four times to a solder alloy film thickness of about 1.3 μm. Thereafter, as shown in FIG. 13, lift-off was performed using an organic solvent to form a fine welded connection metal precursor B having a diameter of 36 μm ^φ .

  Thus, after forming the substrate 1 provided with the welded connection metal precursor B on the bump precursor A, as shown in FIG. 14, the flip chip 21 on which the pads 22 are formed is positioned on the substrate 1, The flip chip 21 is temporarily fixed to the substrate 1. Then, by a hydrogen plasma reflow method for removing the oxide film of the fusion splicing metal layer 8 which is the surface of the splicing connection metal precursor B, as shown in FIG. Flip chip connection was performed. In FIG. 15, the solder bump metal layer 5 is melted to become the solder alloy layer 5A, and the fusion splicing metal layer 8 is melted to become the solder alloy layer 8A.

In this example, for a sample whose electrical continuity was confirmed by TEG (test element group) connected in series with 80 bumps, the shape of minute bumps was observed with a scanning electron microscope, and the average height of 10 bumps was measured. Was 30 ± 2 μm.
[Example 2]

In the present embodiment, the reflow method is different from that of the first embodiment, and the rest is the same as that of the first embodiment. That is, a single layer wiring is formed on a GaAs substrate, and SiO ₂ is laminated by a 100 nm sputtering method, followed by patterning using an organic resist material. On top of that, Sn: 600 nm → Au: 20 nm was repeated 10 times to obtain a solder alloy film thickness (composition: Sn _0.95 Au _0.05 , melting point: 217 ° C.) of about 6.2 μm. Thereafter, SiO ₂ was deposited by a 200 nm sputtering method, lift-off was performed using an organic solvent, and a fine bump precursor of 80 μm ^φ was formed.

Next, patterning of 24 μm ^φ is performed using an organic resist material, and SiO ₂ is removed by dry etching to form an opening of 24 μm ^φ . Using an organic resist material, patterning is performed for 36 .mu.m ^phi, to form a separation layer with a Ti (100nm) / Pt (200nm ) / Au (20nm). Thereafter, Sn: 300nm → Au: 10nm repeated four times to form the solder alloy film thickness of about 1.3 .mu.m, perform lift-off using an organic solvent, to form a small weld connecting metal precursor 36 .mu.m ^phi .

  After the substrate is formed in this way, it is temporarily fixed to the chip, and the following is performed instead of the hydrogen plasma reflow method of the first embodiment. In other words, in this example, the chip is temporarily fixed to the chip, a flux solution (Solbond R5003) is applied to remove the oxide film on the surface of the welded connection metal, and the composition is made uniform by annealing at about 200 ° C. for 10 minutes. Went. Thereafter, the temperature was raised to 218 ° C. to perform reflow, and flip chip connection was performed.

In this example, for a sample whose electrical continuity was confirmed by TEGs connected in series with 80 bumps, the shape of micro bumps was observed with a scanning electron microscope, and the average height of 10 samples was 28 ± 4 μm. Met.
[Example 3]

In the present embodiment, the deposition of SiO ₂ is different from that in the first embodiment, and the others are the same as those in the first embodiment. In other words, after one layer of wiring is formed on the GaAs substrate, the following is performed in this embodiment. That is, SiO ₂ was deposited in Example 1 after the wiring was formed. In contrast, in the present embodiment, the SiN is deposited by 100nm sputtering, instead of SiO ₂ insulating film 3 of FIG. 1, to form an insulating film of SiN. Thereafter, patterning is performed using an organic resist material, and then Sn: 600 nm → Au: 20 nm is repeated 10 times to obtain a solder alloy of about 6.2 μm (composition: Sn _0.95 Au _0.05 , melting point 217 ° C) film thickness.

Thereafter, in Example 1, SiO ₂ was deposited. In contrast, in this example, SiN was deposited by a 200 nm sputtering method, and an SiN insulating film was formed instead of the SiO ₂ insulating film 6 in FIG. After depositing SiN, lift-off was performed using an organic solvent to form a fine bump precursor of 80 ^μmφ .

Next, patterning of 24 μm ^φ is performed using an organic resist material, and the SiN insulating film is removed by dry etching, so that an opening of 24 μm ^φ is formed. Using an organic resist material, patterning is performed for 36 .mu.m ^phi, to form a separation layer with a Ti (100nm) / Pt (200nm ) / Au (20nm). Thereafter, Sn: 300nm → Au: 10nm repeated four times to form the solder alloy film thickness of about 1.3 .mu.m, perform lift-off using an organic solvent, to form a small weld connecting metal precursor 36 .mu.m ^phi .

  After forming the substrate in this manner, the chip was temporarily fixed to the chip, and the flip chip connection was performed under the conditions of 220 ° C. and 3 min by the hydrogen plasma reflow method for removing the oxide film on the surface of the welded connection metal.

In this example, for a sample whose electrical continuity was confirmed by TEGs connected in series with 80 bumps, the shape of micro bumps was observed with a scanning electron microscope, and the average height of 10 samples was 30 ± 3 μm. Met.
[Example 4]

In the present embodiment, the solder bump metal layer 5 is different from that of the first embodiment, and the others are the same as those of the first embodiment. That is, a single layer wiring is formed on a GaAs substrate, and SiO ₂ is laminated by a 100 nm sputtering method, followed by patterning using an organic resist material.

After patterning, in Example 1, Sn: 600 nm → Au: 20 nm was repeated 10 times thereon. On the other hand, in this example, Sn: 900 nm → Au: 16 nm → In: 13 nm was repeated six times, and a solder alloy of about 5.5 μm (composition: Sn _0.95 Au _0.03 In _0.02 , melting point) : 215 ° C). That is, in this embodiment, the solder bump metal layer having the above-described solder alloy film thickness was used instead of the solder bump metal layer 5 shown in FIG.

Thereafter, SiO ₂ was deposited by a 200 nm sputtering method, lift-off was performed using an organic solvent, and a fine bump precursor of 80 μm ^φ was formed.

Next, patterning of 24 μm ^φ is performed using an organic resist material, and SiO ₂ is removed by dry etching to form an opening of 24 μm ^φ . Using an organic resist material, patterning is performed for 36 .mu.m ^phi, to form a separation layer with a Ti (100nm) / Pt (200nm ) / Au (20nm). Thereafter, Sn: 300nm → Au: 10nm repeated four times to form the solder alloy film thickness of about 1.3 .mu.m, perform lift-off using an organic solvent, to form a small weld connecting metal precursor 36 .mu.m ^phi .

  After forming the substrate in this manner, the chip was temporarily fixed to the chip, and the flip chip connection was performed under the conditions of 220 ° C. and 3 min by the hydrogen plasma reflow method for removing the oxide film on the surface of the welded connection metal.

  In this example, for a sample whose electrical continuity was confirmed by TEGs connected in series with 80 bumps, the shape of minute bumps was observed with a scanning electron microscope, and the average height of 10 samples was measured to be 25 ± 2 μm. Met.

As mentioned above, although embodiment and the Example of this invention were explained in full detail, specific structure is not restricted to embodiment and an Example. For example, in the above-described embodiment, SiO ₂ or SiN is used as the insulating film, but a SiON insulating film may be used instead.

It is sectional drawing explaining the base formation of Example 1. FIG. FIG. 4 is a cross-sectional view illustrating resist application in Example 1. 2 is a cross-sectional view showing resist pattern formation in Example 1. FIG. FIG. 3 is a cross-sectional view illustrating the multilayer film deposition of Sn—Au in Example 1. ₂ is a cross-sectional view illustrating SiO ₂ deposition in Example 1. FIG. 2 is a cross-sectional view showing a bump precursor of Example 1. FIG. 2 is a cross-sectional view showing resist pattern formation in Example 1. FIG. 3 is a cross-sectional view showing dry etching in Example 1. FIG. FIG. 3 is a cross-sectional view showing lift-off in Example 1. 2 is a cross-sectional view showing resist pattern formation in Example 1. FIG. 2 is a cross-sectional view showing formation of a separation layer in Example 1. FIG. FIG. 3 is a cross-sectional view illustrating the multilayer film deposition of Sn—Au in Example 1. FIG. 3 is a cross-sectional view showing lift-off in Example 1. FIG. 3 is a cross-sectional view showing the positioning of the flip chip of Example 1. FIG. 3 is a cross-sectional view illustrating flip chip connection according to the first embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Wiring layers 3 and 6 Insulating film 4 Base 5 Solder bump metal layer 7 Separation layer 8 Fusion splicing metal layer A Bump precursor B Welding connection metal precursor

Claims (5)

When a solder bump made of an alloy of Sn _1-x M _x (M: one or more metals other than Sn) is formed on the substrate (1), the solder bump metal layer (5) that melts to become a solder bump An insulating film (6) having a composition of SiN _x O _1-x (0 ≦ x ≦ 1) is formed thereon, an opening (6A) is formed in the insulating film (6), and a metal layer in the opening (6A) ( 5) and a separation layer (7) of the metal film is formed on the insulating film (6) ,
On the separation layer (7), a fusion splicing metal layer (8) serving as solder for connection to the pads (22) of the flip chip (21) is formed, and the flip chip (21) and the substrate (1) are formed. Flip chip connection method using solder bumps, characterized by connecting   The flip-chip connection method using solder bumps according to claim 1, wherein a laminated film containing Ti and Pt is used as the separation layer (7). As solder the connection, Sn _{1-x M x:} Flip with solder bumps as claimed in any one of claims 1 or 2, characterized by using the _(M one or more metals other than _Sn) alloy Chip connection method. Forming a mask for patterning on the substrate (1);
A metal film having a solder composition is deposited on the mask, and then an insulating film is formed on the metal film.
Thereafter, the mask is removed to form a bump precursor (A) composed of the bump metal layer (5) and the insulating film (6). Connection method. 5. The flip-chip connection method according to claim 4 , wherein an organic resist material is used as the patterning mask and the mask is removed by a lift-off method.

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