JP3909169B2 - System clock synchronizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system clock synchronizer. During processor hardware development, clock signal variation due to component rod variation occurs, so clock phase adjustment at the initial setting and at the time of shipment from the factory (set a predetermined state with the DIP switch) And then ship. Since this has to be manually set for each PWCB (print wiring circuit board), it was necessary to improve this.
[0002]
[Prior art]
FIG. 5 is a diagram showing a configuration example of a conventional system. In the figure, a duplex configuration of system 0 and system 1 is shown. In the system 0, 1 is a clock oscillator that generates a clock, 2 is a CPU that controls the clock, 3 is a clock control circuit that receives the output of the oscillator 1 and controls the clock, and receives a control signal from the CPU2.
[0003]
4 is a delay line that delays the output of the clock control circuit 3 for a predetermined time, 5 is a buffer that receives the output of the delay line 4 and outputs it to another system, 6 is a delay line that delays the output of the clock control circuit 3 for a predetermined time, and 7 is a delay line. This selector receives either the output of line 6 or a clock from another system and selects either one.
[0004]
A buffer 8 receives the output of the selector 7 and outputs a clock. A buffer 9 receives a clock from another system. The output is input to one input of the selector 7. The output of the buffer 8 is given to the synchronized device 20. As the synchronized device 20, for example, various I / O devices can be considered.
[0005]
On the other hand, the configuration of the system 1 system is the same as that of the system 0 system. That is, the clock oscillator 11, the CPU 12, the clock control circuit 13, the delay line 14, the buffer 15, the delay line 16, the selector 17, the buffer 18, and the buffer 19 are configured. Reference numeral 21 denotes a synchronized device that receives the output of the buffer 18 and is similar to the asynchronous device 20.
[0006]
In the system configured as described above, if the 0 system is an act system (active system) and the 1 system is a standby system (standby system), the selector 7 selects the output of the delay line 6 and sets the buffer 8 Is output via. On the other hand, in the 1-system, the selector 17 selects the 0-system clock input via the buffer 19 and outputs it via the buffer 18. At this time, the CPUs 2 and 12 control the delay amounts of the delay lines 4, 6, 14 and 16 so that the clocks of both systems are in phase. Then, either the 0 system or the 1 system is an act system, and the other is a standby system. In the normal operation state, the system 0 clock and the system 1 clock are synchronized as shown in the figure.
[0007]
The processor board of such a system takes the following steps from design to shipment.
(1) The delay of the clock is calculated at the time of trial design of the PWCB, and a certain degree of prediction is made so that the phases of both systems coincide. A delay line is inserted so that adjustment between the min / max values of the delay is possible, and a circuit that can be adjusted by the manufacturing circuit is provided.
[0008]
(2) At the time of prototype evaluation, an engineering note is set, and by adjusting the phase of the duplex system, a large frame of the delay line value considering the variation of the rod is determined.
(3) At the time of mass production design, the line value set in the trial evaluation is fixed.
[0009]
(4) Make final phase adjustments for mass-produced products and fix the work order. A cover is attached so that the factory setting cannot be changed in the field.
However, in the above case, if adjustment cannot be made by engineering due to technology changes of parts or variations in rods, it is necessary to change the circuit again. Also, if the timing is slightly different due to aging of parts, the value of the work order can never be adjusted in the field again, so it has to be returned to the factory and adjusted again.
[0010]
FIG. 6 is a diagram illustrating a detailed circuit example of the circuit delay generation unit. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, 4a and 4b constitute a delay line 4, 4a is a delay unit, and 4b is a dip switch. The clock control circuit 3 selects an appropriate delay according to the instruction from the CPU 2. The dip switch 4b corresponding to the selected delay is turned on and enters the buffer 5.
[0011]
This configuration is the same on the system 1 side. That is, 14a and 14b constitute a delay line 14, 14a is a delay unit, and 14b is a dip switch. The clock control circuit 13 selects an appropriate delay according to the instruction of the CPU 12. The dip switch 14b corresponding to the selected delay is turned on and enters the buffer 15.
[0012]
In this circuit, the timing of the buffers 5, 8, 9 and the delay 4a may change due to aging of the elements. The same can be said for the system 1 side.
[0013]
[Problems to be solved by the invention]
(1) Since phase adjustment is carried out by construction, human error may be incurred before shipment.
[0014]
(2) I would like to reduce the number of man-hours on the factory side for the above implementation.
(3) Timing may change due to aging of parts or variations in rods, and malfunction may occur after shipment.
[0015]
(4) Changes in parts / variations in rods may necessitate changes to the currently designed circuit.
(5) Since the clock cannot be adjusted after entering the field, if the work setting cover is accidentally removed and the setting value has been changed, it is necessary to adjust it again. Normally, a repair return (repair return) is required. Therefore, it is necessary to reduce the man-hours at the local / factory.
[0016]
(6) Although the clock speed is expected to increase in order to increase the speed of the circuit in the future, we want to inherit the basic circuit other than the delay line and realize the diversion of the circuit at the time of enhancement (improvement).
[0017]
The present invention has been made in view of such problems, and an object of the present invention is to provide a system clock synchronizer capable of automatically adjusting the phase of a duplex clock.
[0018]
[Means for Solving the Problems]
(1) FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 6 are denoted by the same reference numerals. In the figure, 4a is a delay element group from which a plurality of delay amounts are obtained in order to obtain a plurality of delays, and 4c is a decoder for selecting one delay element from these delay element groups. The output of the decoder 4c enters the buffer 5.
[0019]
Reference numeral 30 denotes a phase adjustment detection circuit as a phase detection unit that detects a phase difference between the own system clock and the other system clock and notifies the CPU 2 of the phase difference. The output clock of the selector 7 enters the phase adjustment detection circuit 30, and another phase clock is input to the phase adjustment detection circuit 30 via the buffer 9b.
[0020]
The output of the phase adjustment detection circuit 30 is notified to the CPU 2, and the CPU 2 receives the phase difference and controls the clock control circuit 3 to select a necessary delay element. A select signal is given to the decoders 4c and 6c. An output clock of another system is input to the phase adjustment detection circuit 30 via the buffer 9b. The output of the phase adjustment detection circuit 30 is input to the synchronized device 20.
[0021]
The above operation is the same for the system 1 system. That is, in the figure, 14a is a delay element group from which a plurality of delay amounts can be obtained in order to obtain a plurality of delays, and 14c is for selecting one delay element from these delay element groups by a selection signal from the CPU 12. It is a decoder. The output of the decoder 14c enters the buffer 15.
[0022]
Reference numeral 31 denotes a phase adjustment detection circuit as a phase detection unit that detects a phase difference between the own system clock and the other system clock and notifies the CPU 12 of the detected phase difference. The output clock of the selector 17 enters the phase adjustment detection circuit 31, and another system clock is input to the phase adjustment detection circuit 31 via the buffer 19b.
[0023]
The output of the phase adjustment detection circuit 31 is notified to the CPU 12, and the CPU 12 receives the phase difference and controls the clock control circuit 13 to select a necessary delay element. The output clock of another system is input to the phase adjustment detection circuit 31 via the buffer 19b. The output of the phase adjustment detection circuit 31 is input to the synchronized device 21. Reference numeral 40 denotes a Mate CC interface that directly connects the system 0 and the system 1, and exchanges phase information with each other.
[0024]
According to the configuration of the present invention, the CPU 2 selects a delay element 4a having a specific value and sends a delayed clock to the own system and the other system. The phase adjustment detection circuit 30 adjusts the phases of the own system and the other system and sends them to the CPU 2. The CPU 2 selects a necessary delay element according to the phase difference and outputs it from the decoder 4c. By performing such operations in the 0-system and the 1-system, respectively, it is possible to provide a system clock synchronizer that can automatically adjust the phase of the duplex system clock.
Further, according to the present invention, the circuit delay creating section stores the storage means for storing each delay amount when the dual system clock is synchronized. With this configuration, each delay amount is stored even when the system is down due to power-off or the like, so that a steady state can be quickly shifted to when the power is turned on.
[0026]
( 2 ) In Claim 2 , the circuit delay creating section includes a decoder that receives a plurality of delay outputs and a CPU that selects a delay amount to be input to the decoder.
[0027]
With this configuration, an optimum delay amount can be selected according to the phase difference between the 0-system clock and the 1-system clock.
( 3 ) Claim 3 is characterized in that a folding signal is provided in both systems in order to automate the phase adjustment.
[0028]
With this configuration, signals can be exchanged quickly between both systems.
( 4 ) According to a fourth aspect of the present invention, the phase detector receives a clock of its own system and a clock of another system, detects a phase difference between the two, and gives a detection result to the circuit delay generator.
[0029]
If comprised in this way, the signal according to the phase difference of an own system and another system can be given to a circuit delay production | generation part, and a phase difference can be made to correspond rapidly.
( 5 ) Claim 5 is characterized in that the wiring lengths of both systems are adjusted on the back wiring board of the duplex system.
[0030]
With this configuration, the delay can be made the same by aligning the lengths of the signal lines of each system.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a block diagram showing an embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, buffers 5, 9, 15, 19, 31, 32, 36, and 37 use three-state buffers, and control signals are connected to a common line so that they always operate as buffers.
[0032]
In the phase adjustment detection circuit 30, 31 is a buffer that receives a clock of its own device from D, and 32 is a buffer that receives a clock from C of another system. Reference numeral 33 denotes an exclusive OR gate (EOR gate) that receives the outputs of the buffers 31 and 32, and reference numeral 34 denotes a noise filter that receives the output of the EOR gate 33.
[0033]
An RS flip-flop 35 receives the output of the clock control circuit 3 at its R input (reset input), the output of the noise filter 34 at its C input (set input), and supplies the Q output to the clock control circuit 3. The output of the selector 7 is given to the buffers 36 and 37, the output of the buffer 36 is given from the C terminal to the synchronized device 20, and the output of the buffer 37 is given to the buffer 31 of its own device. The output of the buffer 36 is given to the synchronized device 20 and to the other system. The CPU 2, the clock control circuit 3, the delay element group 4a, and the decoder 4c constitute a circuit delay creating unit. The above configuration is the same for the system 1 system. The operation of the circuit thus configured will be described as follows.
[0034]
The features of the present invention are listed below.
1) The work order is deleted, and the delay value can be controlled from the CPU by the decoder.
[0035]
2) The delay adjustment is automated by the CPU, and the phase can be adjusted (matched) at any time even if the element changes with time.
3) It has a detection circuit for phase adjustment.
[0036]
4) Adjust the wiring length in BWB / PWCB.
5) Use the Mate CC interface to exchange phase information.
[0037]
6) The PWCB is a circuit with a built-in CPU, and each instruction is executed by the microprogram.
7) Using flash memory or memory with backup power supply, phase information is not lost even if there is an instantaneous power interruption of the device.
[0038]
The CPU 2 controls the clock control circuit 3 to select an appropriate value for the delay element group 4a. The selection result enters the decoder 4c, and the output of the decoder 4c enters the buffer 19 of the other system via the buffer 5. On the other hand, an appropriate value is selected from the delay element group 6 a and is output from the decoder 6 c and enters one input of the selector 7. The selector 7 receives a clock that has undergone phase adjustment of another system via the buffer 9. As described above, according to the present invention, the circuit delay generation unit includes a decoder that receives a plurality of delay outputs and a CPU that selects a delay amount to be input to the decoder. The optimum delay amount can be selected according to the phase difference.
[0039]
The selector 7 selects one of them and sends it to the phase adjustment detection circuit 30. In the phase adjustment detection circuit 30, the buffers 36 and 37 buffer and output the selector output, and the output of the buffer 36 is supplied as a clock to the asynchronous device, the main memory, or various I / O devices.
[0040]
The output of the buffer 37 enters the B terminal from the terminal D through the wiring 1 and enters the buffer 31. On the other hand, an output clock of another system is input to the buffer 32 via the wiring 2. Here, in order to make the delay by the signal line the same, the lengths of the wiring 1 and the wiring 2 are unified. This allows the delay to be the same by aligning the lengths of the signal lines of each system.
[0041]
The EOR gate 33 receives its own system clock and the other system clock, and takes the exclusive OR. As a result, “1” level is output when both phases are different. The output of the EOR gate 33 enters the C input of the flip-flop after the noise is removed by the noise filter 34. The noise filter 34 removes a waveform of a specific hazard level (for example, within 4 ns) that may be EOR-outputted for stabilizing the operation of the circuit.
[0042]
On the other hand, the clock before the phase adjustment of its own system is given to the R input of the flip-flop 35. The output (phase difference signal) of the flip-flop 35 is given to the CPU 2 via the clock control circuit 3.
[0043]
According to the present invention, a signal corresponding to the phase difference between the own system and another system can be given to the circuit delay creating unit, and the phase difference can be quickly matched.
The CPU 2 detects the number of counts per time and confirms whether or not there is a phase shift. Then, which delay element of the delay element groups 4a and 6a is selected is determined. Eventually, the output of the EOR gate 33 becomes “0”, and the self-system clock and the other-system clock are in phase. The above operation is the same in the first system.
[0044]
As described above, the phase synchronization adjustment is performed by adjusting the delay amount of the delay line 4 a by the decoder control from the CPU 2. Note that the value of the delay line is appropriately selected according to the clock speed in the system. In this example, the phase adjustment of the clock may be within a range of ± 5 ns.
[0045]
The Mate CC interface 40 has been conventionally provided, but is also used for clock adjustment. According to this, it is possible to quickly exchange signals between both systems.
[0046]
According to the present invention, the CPU 2 and 12 are provided with storage means, for example, a memory, for storing each delay amount when the dual system clock is synchronized. This memory is either flash memory or battery backed up memory. This memory records each delay amount when the dual system is synchronized, and stores each delay amount when the system goes down due to a momentary power interruption, etc. When it becomes, it can transfer to a steady state quickly.
[0047]
FIG. 3 is a diagram showing a phase shift between both systems. 1) shows a case where the phases of both systems are shifted. In the figure, A is a 0-system clock, B is a 1-system clock, and E is an output E of the EOR gate 33. In 1), the smaller the phase difference, the smaller the EOR output pulse width. Then, the counter of the subsequent stage is updated by this EOR output.
[0048]
2) shows a case where the phases of both systems are shifted. When the phase difference becomes 0, the EOR output is always “0” and the subsequent counter is not updated. 3) shows a case where the phases of both systems coincide with each other, and the EOR output is always “0” (L).
[0049]
FIG. 4 is a flowchart showing the operation of the CPU of the phase adjustment unit. First, when the power is turned on (S1), a clock is output from the oscillation source (oscillator 1) (S2). The apparatus checks whether the Mate system power supply is on and the own system is ACT (S3). If the Mate system power is on and the system is not ACT, the process ends at that point. If the Mate system power supply is on and the own system is ACT, the CPU 2 starts up and the microprogram starts operating (S4).
[0050]
First, the decoder input that can be designated by the delay line is set to all “0” (S5). In this state, the phase adjustment detection circuit 30 monitors the delay value (S6). The CPU 2 receives the comparison result based on the delay comparison result (S7). In this case, the sampling frequency is arbitrary depending on the circuit.
[0051]
Next, it is checked whether or not all the combinations of the decoders 4c have been completed (S8). If not, the decoder value is changed (S9), and the process returns to step S6 to monitor the delay value. If so, the clock control circuit 3 selects a synchronized decode value from the delay comparison circuit (phase adjustment detection circuit) 30 (S10).
[0052]
As a result, the decode value is reset (S11). Then, data is stored in the nonvolatile memory attached to the CPU 2 as a countermeasure when a failure occurs (S12). By storing the decoded value at this time, it is possible to quickly synchronize the clock phases of both systems without performing phase adjustment again even in the event of a momentary power interruption.
[0053]
In the present invention, as shown in FIG. 2, since all the synchronization can be optimized by the CPU and the microprogram, the clock synchronization is optimized from the time of design to the factory shipment or from the field.
[0054]
Thus, according to the present invention, the contribution from PWCB design to maintenance is large.
(1) There is no human error because phase adjustment is not performed by construction.
[0055]
(2) Factory side man-hours for the above implementation can be reduced.
(3) Timing changes due to aging of parts and variations of rods, and there is no possibility of malfunction occurring after shipment.
[0056]
(4) There is no need to worry about changes to the circuit currently designed due to component changes and rod variations.
(5) Since the clock can be adjusted after entering the field, even if the work setting cover is accidentally removed and the set value is changed, it can be automatically adjusted and there is no need to adjust again.
[0057]
(6) In the future, it is expected that the clock speed will be increased in order to increase the circuit speed. However, the basic circuit other than the delay line can be inherited, and the circuit at the time of enhancement can be used.
[0058]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to claim 1, in the system clock synchronizer having the duplicated system clock generator, the phase adjustment detection circuit adjusts the phases of the own system and the other system and sends them to the CPU. A system clock synchronizer capable of automatically adjusting the phase of a duplex clock by selecting a necessary delay element according to a phase difference and performing an operation of outputting from a decoder in each of the 0 system and the 1 system. Can be provided.
In addition, when the system clock of the duplex system is synchronized, storage means for storing each delay amount is stored in the circuit delay creating unit so that each delay amount is stored even when the system is down due to power-off or the like. Therefore, when the power is turned on, the steady state can be promptly shifted.
[0060]
( 2 ) According to claim 2 , the circuit delay generation unit includes a decoder that receives a plurality of delay outputs and a CPU that selects a delay amount to be input to the decoder, so that the 0-system and the 1-system An optimum delay amount can be selected according to the phase difference of the clock.
[0061]
( 3 ) According to the third aspect of the present invention, the signal can be exchanged between the two systems quickly by providing the folded signals in both the systems for the automatic phase adjustment.
( 4 ) According to claim 4 , the phase detector receives the own clock and the other clock, detects the phase difference between the two, and gives the detection result to the circuit delay creating unit. A signal corresponding to the phase difference between the system and the other system can be given to the circuit delay creating unit, and the phase difference can be quickly matched.
[0062]
( 5 ) According to claim 5 , by adjusting the wiring lengths of both systems on the back-wiring board of the duplex system, the lengths of the signal lines of each system are made uniform, so that the delay is made the same. be able to.
[0063]
As described above, according to the present invention, it is possible to provide a system clock synchronizer capable of automatically adjusting the phase of a duplex clock.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a block diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing a phase shift between both systems.
FIG. 4 is a flowchart showing the operation of the CPU of the phase adjustment unit.
FIG. 5 is a diagram illustrating a configuration example of a conventional system.
FIG. 6 is a diagram illustrating a detailed circuit example of a circuit delay creating unit;
[Explanation of symbols]
1,11 oscillator 2,12 CPU
3, 13 Clock control circuit 4a, 14a Delay element group 4c, 14a Decoder 5, 15 Buffer 6a, 16a Delay element group 6c, 16c Decoder 7, 17 Selector 9, 19 Buffer 9a, 9b, 19a, 19b Buffer 20, 21 Covered Synchronizers 30, 31 Phase adjustment detection circuit 40 Mate CC interface

Claims (5)

In a system clock synchronizer having a duplicated system clock generator,
A phase detector that receives a clock from another system and detects the phase of the clock of the own system and the other system;
A circuit delay generation unit incorporating a CPU that receives the output of the phase detection unit and controls the delay amount of the clock ; and
A mate CC interface that connects the act system and standby system CPU and exchanges phase information;
And a storage means for storing each delay amount when the dual system clock is synchronized is provided in the circuit delay creating unit,
The system delay synchronizer is configured so that a clock delay amount can be automatically set by a CPU. 2. The system clock synchronization apparatus according to claim 1, wherein the circuit delay generation unit includes a decoder that receives a plurality of delay outputs and a CPU that selects a delay amount to be input to the decoder . 2. The system clock synchronizer according to claim 1 , further comprising a folding signal in both systems for automatic phase adjustment . 2. The system clock synchronizer according to claim 1 , wherein the phase detector receives a self clock and a clock of another system, detects a phase difference between the two, and gives a detection result to the circuit delay generator. . 2. The system clock synchronizer according to claim 1, wherein the wiring lengths of both systems are adjusted on the back wiring board of the duplex system .

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