JP3905171B2 - Thermal shutdown circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a heat shut-off circuit for forcibly interrupting circuit operation from the viewpoint of ensuring the safety of circuit operation when various electronic circuits are in a temperature state of a predetermined value or more. It is related to the improvement of.
[0002]
[Prior art]
Conventionally, as a typical circuit of this type, for example, a circuit configured using a bipolar transistor as shown in FIG. 5 is known and well known.
The conventional circuit will be described generally with reference to FIG. 1. In this thermal cutoff circuit, a divided voltage obtained by dividing the voltage of the reference power supply 56 by resistors 57a and 57b is applied to the base of an npn transistor 55. The divided voltage is set to a voltage at which the npn transistor 55 becomes non-conductive at a temperature lower than a desired thermal cutoff temperature. By the way, the base-emitter voltage V of the npn transistor 55_beGenerally has a temperature coefficient of about −2 mV / ° C., so V_beSince the npn-type transistor 55 becomes conductive when the voltage divided by the resistors 57a and 57b falls below, the signal obtained at the output terminal 58 at this time is used as an output signal when a thermal interruption occurs. It is intended to be used.
[0003]
[Problems to be solved by the invention]
  by the way,MOSIn an integrated circuit, when using such a heat shut-off circuit, an extinction cut-off circuit using an npn transistor with a grounded emitter and a collector output as described above isMOSIt cannot be used as it is because of the relationship with the manufacturing process of the integrated circuit. For this reason, for example, even if an NMOS is used instead of the npn transistor, the variation due to the temperature of the so-called threshold voltage, which is a determinant of the thermal cutoff temperature, is large. It is not something that can be used.
[0004]
  The present invention has been made in view of the above circumstances,MOSIt is an object of the present invention to provide a heat shut-off circuit that can be incorporated in an integrated circuit and can perform heat shut-off with high accuracy. Another object of the present invention is to provide a highly reliable thermal cutoff circuit that can set the thermal cutoff temperature easily and with high accuracy.
[0005]
[Means for Solving the Problems]
  The thermal shutdown circuit according to the invention of claim 1 is:The gates of the first NMOS transistor and the second NMOS transistor are connected to each other, the drain and gate of the first NMOS transistor are connected to each other, and the bases and collectors of the first bipolar transistor and the second bipolar transistor are connected to each other. And the base and the collector are connected, and the first bipolar transistor and the second bipolar transistor form an N well region on the p-type substrate on which the NMOS transistor is formed, and the N well region P as part of + A pnp-type parasitic transistor formed by ion implantation using a drain or source for a PMOS transistor as an emitter, the N-well region as a base, and the p-type substrate as a collector, the first NMOS transistor The first bipolar transistor has a source and an emitter connected to each other, and the second NMOS transistor and the second bipolar transistor have a source and an emitter connected via a first resistor. The drains of the first NMOS transistor and the second NMOS transistor are connected to a first current source circuit, respectively, and the first current source circuit is connected to a predetermined positive power supply, The collectors of the first bipolar transistor and the second bipolar transistor are Each of the second bipolar transistors is connected to a predetermined negative power source, the emitter area of the second bipolar transistor is a predetermined multiple of the emitter area of the first bipolar transistor, and the conduction and non-conduction states of the second NMOS transistor It is possible to output as
  The thermal shutdown circuit according to the invention of claim 2 is the thermal shutdown circuit of claim 1, wherein the first current source circuit connects gates of the third NMOS transistor and the fourth NMOS transistor, The third NMOS transistor is in a diode connection state, the emitter of the pnp transistor in the diode connection state is connected to the source of the third NMOS transistor, the source of the fourth NMOS transistor, and the diode connection state The collector of the pnp-type transistor is connected via a second resistor, and a predetermined negative power source is connected to the connection point, while the current flowing through the drain of the fourth NMOS transistor is supplied to a current mirror circuit. Through the drains of the first NMOS transistor and the second NMOS transistor. Characterized by comprising configured to supply the down.
  According to a third aspect of the present invention, there is provided a thermal shutdown circuit that connects the gates of the first PMOS transistor and the second PMOS transistor and connects the drain and gate of the first PMOS transistor to each other. The bases and collectors of the transistor and the fourth bipolar transistor are connected to each other, and the base and the collector are connected to each other. The third bipolar transistor and the fourth bipolar transistor are connected to each other on the n-type substrate on which the PMOS transistor is formed. , A P well region is formed, and n is formed in a part of the P well region + An npn-type parasitic transistor formed by ion implantation using an NMOS transistor drain or source as an emitter, the P-well region as a base, and the n-type substrate as a collector, the first PMOS transistor The third bipolar transistor has a source and an emitter connected, and the second PMOS transistor and the fourth bipolar transistor have a source and an emitter connected via a first resistor. The drains of the first PMOS transistor and the second PMOS transistor are connected to a second current source circuit, respectively, and the second current source circuit is connected to a predetermined negative power supply, The collectors of the third and fourth bipolar transistors are The emitter area of the fourth bipolar transistor is a predetermined multiple of the emitter area of the third bipolar transistor, and the conduction / non-conduction state of the second PMOS transistor is used as a heat cutoff signal. It is possible to output.
  According to a fourth aspect of the present invention, in the thermal shutdown circuit according to the third aspect, the second current source circuit connects gates of the third PMOS transistor and the fourth PMOS transistor, The third PMOS transistor is in a diode connection state, and a diode is connected. The emitter of the npn-type transistor in the connected state is connected to the source of the third PMOS transistor, and the source of the fourth PMOS transistor and the collector of the npn-type transistor in the connected state of the diode are connected to the second And a predetermined positive power source is connected to the connection point, while a current flowing through the drain of the fourth PMOS transistor is supplied to the first PMOS transistor and the second PMOS transistor via a current mirror circuit. The PMOS transistor is configured to be supplied to the drain of the PMOS transistor.
[0006]
  In such a configuration,As these bipolar transistorsMOSBy using a parasitic transistor that can be formed in the transistor manufacturing process, the conventional problems in manufacturing are solved, and with the above-described configuration, the thermal cutoff temperature is the base-emitter of a bipolar transistor with little variation. It is expressed as a function of the inter-voltage and the area ratio of the emitter of the bipolar transistor, so that a desired thermal cutoff temperature can be easily set, and a thermal cutoff circuit with stable output characteristics unlike the conventional one is realized. Is.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a thermal shutdown circuit according to an embodiment of the present invention will be described with reference to FIGS. The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, a first example will be described with reference to FIG. First, to describe the configuration, this thermal shut-off circuit includes pnp-type first and second transistors (indicated as “Q1” and “Q2” in FIG. 1, respectively) 1 and 2 and an NMOS third transistor. And the fourth transistor (indicated as “Q3” and “Q4” in FIG. 1, respectively) 3, 4,Current source circuit25 is connected between positive and negative power supplies as will be described later.
[0008]
  That is, one terminal of each of the first and second current sources 26 and 27 is the first power supply terminal.28aThe other end of the first current source 26 is connected to the drain of the third transistor 3 and the other end of the second current source 27 is connected to the fourth power source (not shown). Are connected to the drains of the transistors 4 respectively. The gates of the third and fourth transistors 3 and 4 are connected to each other, and the gate and the drain of the fourth transistor 4 are connected to each other. The drain of the third transistor 3 is connected to the output terminal 29 of the heat cutoff circuit.
[0009]
On the other hand, the bases of the first and second transistors 1 and 2 are connected to each other and the collectors are connected to each other. Further, the base and collector of the second transistor 2 are connected to each other, and this connection point is connected to the second power supply terminal 28b, and is connected to a negative power supply (not shown) via the second power supply terminal 28b. It has come to be.
The emitter of the first transistor 1 is directly connected to the source of the third transistor 3 via the first resistor 30, and the emitter of the second transistor 2 is directly connected to the source of the fourth transistor 4. It has become so.
[0010]
  Here, the first and second transistors 1 and 2 use p-type substrates.MOSA general transistor structure formed in a process or a so-called parasitic transistor structure is used. Among the transistor structures, a so-called parasitic transistor structure is formed, for example, as shown in FIG. 2 by forming an N well region 36 in a p-type substrate 35 and implanting p + ions on the surface thereof. When a PMOS source 37 or drain 38 (drain 38 in the example of FIG. 2) is an emitter, an N-well region 36 is a base, and a p-type substrate 35 is a collector, a pnp transistor as a parasitic transistor However, the first and second transistors 1 and 2 are formed as described above.
[0011]
Further, in the embodiment of the present invention, the emitter area of the first transistor 1 is set to S._Q1, The emitter area of the second transistor 2 is S_Q2Then, the area ratio is S_Q1: S_Q2= N: 1 so that each emitter portion (p in FIG.⁺The size of the source 37 or drain 38) formed by ion implantation is set.
[0012]
Next, the operation in such a configuration will be generally described, and then the operation will be specifically described analytically.
First, in the heat shut-off circuit having the above-described configuration, the third transistor 3 is in a non-conductive state at a temperature lower than the set heat shut-off temperature. Therefore, the output terminal 29 is not in the heat shut-off state. A voltage close to a substantially positive power supply voltage is output as the meaning thermal shutoff signal. On the other hand, when the ambient temperature exceeds the set heat shut-off temperature, the third transistor 3 becomes conductive, so that a predetermined negative voltage close to a substantially negative power supply voltage is applied to the output terminal 29. It is output as a signal.
[0013]
  Next, if such an operation is described analytically, first,Current source circuit25, assuming that the same current I is supplied to the third and fourth transistors 3 and 4, respectively, the following equations regarding the gate potentials of the third and fourth transistors 3 and 4 are used. The relationship (1) is established.
[0014]
V_be2+ V_gs4= V_be1+ R1 × I + V_gs3... (1)
[0015]
  Here, Vbe2 is the base-emitter voltage of the second transistor 2, Vgs4 is the gate-source voltage of the fourth transistor 4, and Vbe1 is the base-emitter voltage of the first transistor 1. , Vgs3 represent the gate-source voltage of the third transistor 3, respectively. R1 is the resistance value of the first resistor 30, and I is as described above.Current source circuit25 is a constant current value supplied from 25.
[0016]
Then, the gate-source voltage V of the third transistor 3_gs3And the gate-source voltage V of the fourth transistor 4_gs4At a temperature lower than the temperature at which this thermal shutdown circuit operates._gs3<V_gs4Is set to be
By the way, considering that the base-emitter voltage of the bipolar transistor can be expressed as a function of so-called thermal voltage, collector current and reverse collector saturation current, the above equation (1) can be rewritten as 2).
[0017]
V_t× ln (I₂× N / I₁) + V_gs4= R1 × I + V_gs3... (2)
[0018]
Here, V_tIs the so-called thermal voltage, I₁Is the emitter current of the first transistor 1, I₂Represents the emitter current of the second transistor 2, and N is the magnification of the emitter area of the first transistor 1 when the emitter area of the second transistor 2 is 1, as described above. Moreover, ln means a natural logarithm.
In this equation (2), if the temperature change of the current I is ignored, V_tHas a positive temperature coefficient, so as the ambient temperature rises, V_gs3And V_gs4It can be said that the difference between is small. And V_gs3= V_gs4Then, the third transistor 3 becomes conductive and enters a heat cutoff state. In this state, the emitter currents of the first and second transistors 1 and 2 are I₁= I₂It becomes. If the above formula (2) is rearranged using this relational expression, the following formula (3) is obtained.
[0019]
(K × T / q) × lnN = R1 × I (3)
[0020]
Further, when the equation (3) is solved for the absolute temperature T, the following equation (4) can be obtained.
[0021]
T = (q × R1 × I) / (K × lnN) (4)
[0022]
  Here, q is an electron unit charge, and K is a Boltzmann constant. That is, the absolute temperature T obtained by the equation (4) is the heat shut-off temperature, and when this temperature is exceeded, the heat shut-off circuit enters a heat shut-off state, and a predetermined voltage is output to the output terminal 29 as a heat shut-off on signal. Will be. From the above equation (4), the thermal cutoff temperature T is determined by the magnitude of R1, the emitter area magnification N,Current source circuitIt can be said that a desired temperature can be obtained by appropriately selecting the magnitude of the current I supplied from the circuit 25.
[0023]
  Next, a second example will be described with reference to FIG. First, the circuit configuration in the second example will be described. The second example is more specifically configured on the basis of the basic circuit shown as the first example, and includes a heat cutoff output unit 40,Current source circuitIt is roughly divided into 25,Current source circuit25 further comprises a current generator 41 and a current mirror 42. The thermal shutdown output unit 40 includes npn-type fifth and sixth transistors (indicated as “Q5” and “Q6” in FIG. 3) 5 and 6, and seventh and eighth transistors that are PMOS transistors, respectively. (In FIG. 3, they are expressed as “Q7” and “Q8”, respectively) 7, 8 and the first resistor 30, and the fifth and sixth transistors 5 and 6 Corresponding to the first and second transistors 1 and 2 in the circuit shown in FIG. 1, the seventh and eighth transistors 7 and 8 are the third and fourth transistors in the circuit shown in FIG. This corresponds to the transistors 3 and 4.
[0024]
That is, the collectors of the fifth and sixth transistors 5 and 6 are connected to each other and to the first power supply terminal 28a, so that a positive power supply voltage from a positive power supply (not shown) is applied. . The bases of the fifth and sixth transistors 5 and 6 are connected to each other, and the sixth transistor 6 is in a so-called diode connection state in which a base and a collector are connected.
The emitter of the fifth transistor 5 is directly connected to the source of the seventh transistor 7 via the first resistor 30, and the emitter of the sixth transistor 6 is directly connected to the source of the eighth transistor 8. ing.
[0025]
Since the fifth and sixth transistors 5 and 6 are npn-type unlike the first and second transistors 1 and 2 in FIG. 1, in the configuration shown in FIG. The type substrate 35 is replaced with an n-type substrate, the N well region 36 is replaced with a P well region, and the source 37 and drain 38 are replaced with p.⁺N instead of formation by ion implantation⁺By forming by ion implantation, it is basically obtained as a so-called parasitic transistor as shown in FIG.
[0026]
The gates of the seventh and eighth transistors 7 and 8 are connected to each other, while the output terminal 29 is connected to the drain of the seventh transistor 7 and the ninth mirror constituting the current mirror section 42 is connected. The drain of the transistor 9 is connected. In the eighth transistor 8, the gate and the drain are connected to each other, and the connection point is connected to the drain of the tenth transistor 10 constituting the current mirror unit 42.
[0027]
  Current source circuit25 includes a current generator 41 that generates a constant current, and a current mirror unit 42 that includes a so-called current mirror circuit for allowing the constant current generated by the current generator 41 to flow to the heat cutoff output unit 40. It will be. The current mirror unit 42 is configured by ninth to twelfth transistors 9 to 12 which are NMOS transistors. That is, the gates of the ninth to twelfth transistors 9 to 12 are connected to each other, and the gate of the eleventh transistor 11 is connected to the drain. The sources of the ninth to twelfth transistors 9 to 12 are connected to each other and to a negative power supply (not shown) via the second power supply terminal 28b. The drain of the eleventh transistor 11 is the drain of the thirteenth transistor 13 which is a PMOS transistor constituting the current generator 41, and the drain of the twelfth transistor 12 is a PMOS transistor which constitutes the current generator 41. The drains of the fourteenth transistors 14 are connected to the drains of the fourteenth transistors 14 so that the current from the current generator 41 is also passed through the ninth and tenth transistors 9 and 10.
[0028]
The current generator 41 includes thirteenth and fourteenth transistors 13 and 14 that are PMOS transistors, a fifteenth transistor 15 that is a pnp transistor, and a second resistor 43. The gates of the fourteenth transistors 13 and 14 are connected to each other, and the gate and the drain of the fourteenth transistor 14 are connected to each other.
The source of the thirteenth transistor 13 is connected to the first power supply terminal 28a via the second resistor 43, and the source of the fourteenth transistor 14 is connected to the diode 15 in the diode-connected state. Connected to the emitter. The fifteenth transistor 15 has a base and a collector connected to each other and to the first power supply terminal 28a.
[0029]
Next, the operation in this configuration will be described.
The operation in this thermal shut-off circuit is basically the same, although there is a voltage difference due to the fact that the transistor has the opposite polarity to that shown in FIG.
In other words, below the predetermined thermal cutoff temperature, the seventh transistor 7 becomes non-conductive, and a negative voltage substantially equal to the negative power supply voltage is output to the output terminal 29 as a thermal cutoff off signal.
On the other hand, when the ambient temperature exceeds a predetermined heat cutoff temperature and the seventh transistor 7 becomes conductive, a predetermined positive voltage is outputted as a heat cutoff ON signal as the voltage at the output terminal 29.
[0030]
Here, when the current I supplied to the current mirror unit 42 by the thirteenth and fourteenth transistors 13 and 14 in the current generation unit 41 is obtained, the gate potentials of the thirteenth and fourteenth transistors 13 and 14 are equal. Therefore, the following equation (5) is established.
[0031]
R2 × I + V_gs13= V_be+ V_gs14... (5)
[0032]
In the above formula, R2 is the resistance value of the second resistor 43, and V_gs13Is the gate-source voltage of the thirteenth transistor 13 and V_gs14Is the gate-source voltage of the fourteenth transistor 14 and V_beIs the base-emitter voltage of the fifteenth transistor 15.
And V_gs13= V_gs14Is set, the following equation (6) can be obtained.
[0033]
I = V_be/ R2 (6)
[0034]
In the second example, since the equations (1) to (4) are established in the same manner as described above with reference to FIG. 1, the equation (6) is changed to the equation (4) shown above. ) Is substituted and rearranged, the following equation (7) can be obtained.
[0035]
T = (R1 / R2) × (q × V_be) / (K × lnN) (7)
[0036]
Therefore, in the case of the circuit shown in the second example, the thermal cutoff temperature T (unit: unit) can be selected by appropriately selecting the resistance values R1, R2 and the emitter area ratio N of the fifth and sixth transistors 5, 6. : Absolute temperature) can be set to a desired value.
[0037]
Next, a third example will be described with reference to FIG.
The same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described.
This third example shows a configuration example when the present invention is applied to a so-called stable power supply circuit.
Since the stabilized power supply circuit 45 has a known and well-known configuration, its configuration and operation will be generally described.
In the stabilized power circuit 45, the output control transistor 24, which is a PMOS transistor, and voltage dividing resistors 46a and 46b are connected in series between positive and negative power supplies (not shown), while the voltage dividing resistors 46a and 46b. A signal corresponding to the difference between the divided voltage and the reference voltage Vref is output by the error amplifier 47, and the output control transistor 24 is controlled by the bias control transistor 23, which is an NMOS transistor, according to the output of the error amplifier 47. It is the composition which becomes.
[0038]
For example, when the output voltage at the output terminal 48 decreases for some reason and the divided voltage becomes smaller than the reference voltage Vref, the error amplifier 47 generates a positive voltage corresponding to the difference between the reference voltage Vref and the divided voltage. As a result, the bias control transistor 23 becomes conductive according to the output voltage of the error amplifier 47, and the gate voltage of the output control transistor 24 is lowered. Therefore, since the bias of the output control transistor 24 becomes larger, the current flowing through the voltage dividing resistors 46a and 46b is increased, so that the decrease of the divided voltage, that is, the decrease of the output voltage is compensated. Yes.
When the output voltage rises and the divided voltage becomes larger than the reference voltage Vref, the error amplifier 47 outputs a negative voltage corresponding to the difference between the reference voltage Vref and the divided voltage, and the bias control transistor 23. Changes to a non-conductive state in accordance with the magnitude of the voltage, whereby the gate voltage of the output control transistor 24 is raised. For this reason, the output current decreases, and the rise of the divided voltage, that is, the rise of the output voltage is suppressed.
[0039]
  On the other hand, the thermal shutdown circuit basically has the circuit configuration shown in FIG. 3 except that a transistor different from the transistor in the circuit configuration shown in FIG. 3 is used. That is, the heat shut-off circuit in the third example is obtained by replacing the npn-type transistor in FIG. 3 with a pnp-type transistor, the PMOS transistor with an NMOS transistor, and the NMOS transistor with a PMOS transistor. 40,Current source circuitIs divided roughly into 25,Current source circuitReference numeral 25 denotes a current generating unit 41 and a current mirror unit 42. The same constituent elements as those shown in FIG. 1 or FIG. 3 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
[0040]
The heat shutoff output unit 40 has exactly the same circuit configuration as shown in FIG. 1, and the drain of the third transistor 3, which is an NMOS transistor, controls the output of the stabilized power supply circuit 45 via the inverting amplifier 49. The transistor 24 is connected to the gate.
The current mirror unit 42 is obtained by replacing the NMOS transistor in the configuration shown in FIG. 3 with a PMOS transistor. The 16th to 19th transistors 16 to 19 are the 9th to 12th transistors 9 to 9 in FIG. This corresponds to 12.
Further, the twentieth and twenty-first transistors 20 and 21 of the current generator 41 are replaced with the thirteenth and fourteenth transistors 13 and 14 of FIG. 3, and the twenty-second transistor 22 is replaced with the fifteenth transistor 15 of FIG. , Respectively.
[0041]
In such a configuration, the current I generated in the current generator 41 and supplied to the third and fourth transistors 3 and 4 via the current mirror 42 is obtained by the above equation (6). This is the same as the example shown in FIG.
The heat cutoff temperature T is determined by the previous equation (7) as in the example shown in FIG.
Therefore, when the ambient temperature is lower than the thermal cutoff temperature, the third transistor 3 is in a non-conductive state, and a positive voltage is applied to the inverting amplifier 49. Therefore, the inverting amplifier 49 has a predetermined low level. Output state. In this state, the inverting amplifier 49 is not capable of driving the output control transistor 24, and the output control transistor 24 is subjected to drive control by the error amplifier 47 and the bias control transistor 23 as described above. It will be.
On the other hand, when the ambient temperature exceeds the thermal cutoff temperature, the third transistor 3 is turned on, and a positive predetermined voltage is output from the inverting amplifier 49. Therefore, the output control transistor 24 is set in the reverse bias state. The output control transistor 24 is completely inactive, the operation of the stabilized power supply circuit 45 is stopped, and the heat is cut off.
[0042]
【The invention's effect】
  As described above, according to the present invention,MOSSo-called bipolar transistors that can be formed in the transistor manufacturing processMOSSince the thermal shutdown circuit was configured to be combined with the transistor,MOSWhen a transistor is formed, a bipolar transistor can be manufactured by the same procedure, and an efficient manufacturing can be performed without complicating the manufacturing process. Moreover, with bipolar transistorsMOSBy combining with a transistor, twoMOSThe ratio of the emitter areas of bipolar transistors connected in series toMOSWith the resistance connected between the transistor and the bipolar transistor as a parameter, the thermal cutoff temperature can be easily set to a desired value. In particular, the resistance and emitter area ratios can be set with high precision by the integrated circuit manufacturing process, so unlike the conventional case, the heat cutoff temperature can be set with high accuracy, and a highly reliable thermal cutoff circuit. Can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first circuit example of a thermal shutdown circuit in an embodiment of the present invention.
FIG. 2 is a schematic diagram schematically showing the structure of a pnp transistor used in the circuit shown in FIG.
FIG. 3 is a circuit diagram showing a second circuit example of the thermal shutdown circuit in the embodiment of the present invention.
FIG. 4 is a circuit diagram showing a third circuit example of the thermal shutdown circuit in the embodiment of the present invention.
FIG. 5 is a circuit diagram showing a conventional circuit example.
[Explanation of symbols]
23 ... Bias control transistor
24 ... Output control transistor
25 ...Current source circuit
26: First current source
27. Second current source
30: First resistance
40 ... Thermal shutdown output
41 ... Current generator
42 ... Current mirror section
43 ... Second resistance

Claims (4)

Connecting the gates of the first NMOS transistor and the second NMOS transistor, and connecting the drain and gate of the first NMOS transistor;
Connecting the bases and collectors of the first bipolar transistor and the second bipolar transistor, and connecting the base and collector;
The first bipolar transistor and the second bipolar transistor form an N-well region in a p-type substrate on which the NMOS transistor is formed, and a p-type electrode is formed in a part of the N-well region. + A pnp-type parasitic transistor formed by using a drain or source for a PMOS transistor formed by ion implantation as an emitter, using the N-well region as a base, and using the p-type substrate as a collector;
A source and an emitter are connected to the first NMOS transistor transistor and the first bipolar transistor,
A source and an emitter of the second NMOS transistor and the second bipolar transistor are connected via a first resistor,
The drains of the first NMOS transistor and the second NMOS transistor are respectively connected to a first current source circuit, and the first current source circuit is connected to a predetermined positive power source,
The collectors of the first bipolar transistor and the second bipolar transistor are respectively connected to a predetermined negative power source,
The emitter area of the second bipolar transistor is a predetermined multiple of the emitter area of the first bipolar transistor;
A thermal shutdown circuit characterized in that the conduction and non-conduction states of the second NMOS transistor can be output as a thermal shutdown signal. The first current source circuit includes:
The gates of the third NMOS transistor and the fourth NMOS transistor are connected to each other, and the third NMOS transistor is set in a diode connection state.
An emitter of a pnp transistor in a diode connection state is connected to a source of the third NMOS transistor;
While connecting the source of the fourth NMOS transistor and the collector of the diode-connected pnp transistor via a second resistor, a predetermined negative power source is connected to the connection point,
The current flowing through the drain of the fourth NMOS transistor is supplied to the drains of the first NMOS transistor and the second NMOS transistor through a current mirror circuit. Thermal shutdown circuit as described. Connecting the gates of the first PMOS transistor and the second PMOS transistor and connecting the drain and gate of the first PMOS transistor;
Connecting the bases and collectors of the third bipolar transistor and the fourth bipolar transistor, and connecting the base and collector;
The third bipolar transistor and the fourth bipolar transistor form a P-well region in the n-type substrate on which the PMOS transistor is formed, and an n-type substrate is formed on a part of the P-well region. + An npn-type parasitic transistor formed by using the drain or source for an NMOS transistor formed by ion implantation as an emitter, the P-well region as a base, and the n-type substrate as a collector;
A source and an emitter are connected to the first PMOS transistor and the third bipolar transistor,
The second PMOS transistor and the fourth bipolar transistor have a source and an emitter connected via a first resistor,
The drains of the first PMOS transistor and the second PMOS transistor are connected to a second current source circuit, respectively, and the second current source circuit is connected to a predetermined negative power source,
The collectors of the third bipolar transistor and the fourth bipolar transistor are respectively connected to a predetermined positive power source,
The emitter area of the fourth bipolar transistor is a predetermined multiple of the emitter area of the third bipolar transistor;
A thermal shutdown circuit characterized in that the conduction and non-conduction states of the second PMOS transistor can be output as a thermal shutdown signal. The second current source circuit includes:
The gates of the third PMOS transistor and the fourth PMOS transistor are connected to each other, the third PMOS transistor is in a diode connection state,
Connecting the emitter of a diode-connected npn transistor to the source of the third PMOS transistor;
While connecting the source of the fourth PMOS transistor and the collector of the npn transistor in the diode connection state via a second resistor, a predetermined positive power source is connected to the connection point,
The current flowing through the drain of the fourth PMOS transistor is supplied to the drains of the first PMOS transistor and the second PMOS transistor via a current mirror circuit. Thermal shutdown circuit as described.

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