JP3902342B2 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP3902342B2 JP3902342B2 JP28662998A JP28662998A JP3902342B2 JP 3902342 B2 JP3902342 B2 JP 3902342B2 JP 28662998 A JP28662998 A JP 28662998A JP 28662998 A JP28662998 A JP 28662998A JP 3902342 B2 JP3902342 B2 JP 3902342B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor device
- wires
- alignment mark
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/2076—Diameter ranges equal to or larger than 100 microns
Description
【0001】
【発明の属する技術分野】
本発明はオン抵抗を可及的に低減した半導体装置に関する。
【0002】
【従来の技術】
高速動作が要求される電子回路装置、例えば自動車の衝突安全装置として用いられるエアバッグの制御装置は衝突した時の衝撃を衝撃センサで検出しこの出力によりガス発生装置を作動させてエアバッグを膨らませ衝突の反動で前方に飛び出そうとする乗員を支えて安全を図っている。
この衝撃センサからの信号は一旦マイクロコンピュータを用いた制御回路に入力されて誤動作を防止しているが信号処理時間を可及的に短縮するためパルス応答速度が高速の半導体スイッチング素子が用いられる。
またコントローラ上のジョイステイックなどのマニピュレータや操作ボタンを操作して被制御部を遠隔操作するとき操作に対して被制御部を敏感に応答させることができるとコントローラの操作と被制御部の動作とを一体化させることができるためこのような部分にも高速の半導体スイッチング素子が一般的に用いられている。
このような高速半導体スイッチング素子は素子本体のパルス応答速度が高速であることが必要であるが素子本体を外装した状態での動作も重要である。
半導体スイッチング素子としてトランジスタの一例を図4及び図5から説明する。
図において1は半導体ペレットで、内部にトランジスタ素子が形成された半導体ペレット本体2の一方の面にコレクタ領域と接続されたコレクタ電極3を形成し他の面にベース領域とエミッタ領域にそれぞれ接続された導電ランド2a、2bを形成し、さらにこの導電ランド2a、2b部分を窓明けして絶縁被膜5で被覆して窓明け部分に露呈した導電ランド2a、2b部分でベース電極6、エミッタ電極7を形成している。
8は半導体ペレット1を接着剤(図示せず)を介してマウントしたアイランド、9は3本一組のリードで、図示例では一本のリード9aはアイランド8に電気的に接続され他のリード9b、9cは一端がアイランド8の近傍に配置されている。
10、11はそれぞれ半導体ペレット1上のベース電極6とリード9b間エミッタ電極7とリード9c間を接続するワイヤ、12は半導体ペレット1を含む主要部分を外装した樹脂を示す。
この半導体装置に用いられる半導体ペレット1はパルス応答特性が高速のものが用いられる。
また主電流が流れるワイヤ11は動作電流に対して十分大きな径のワイヤが用いられる。
例えばセンサやマニュピレータの出力を伝達する場合、動作電流値が0.3mAのものでは金線の場合直径25μmで十分でアルミニウム線でも直径50μmで十分である。
ところで半導体装置のスイッチング動作は完全に導通、遮断するものと導通領域で電流変化させるものとがあり、前者は消費電力が小さくて済むが動作速度がやや劣るという欠点があり、後者は常に電流が流れるため消費電力が大きいが高速動作できるという特徴がある。
一方自動車のように外部ノイズが大きい環境では最大振幅で信号をスイッチングさせ外部ノイズに対する信頼性を高めている。
そのため小電流動作の半導体装置でもオンオフ動作させているが半導体ペレット1として十分高速動作可能なものを用いても樹脂外装されたものではリード9a、9c間のオン抵抗が大きく回路時定数が高くなって高速動作できないことがあった。
この原因を調べたところリード9aとリード9cの間で直列接続されたアイランド8、コレクタ電極3、半導体ペレット1、エミッタ電極7、ワイヤ11のそれぞれの間の接続部のうち、エミッタ電極7とワイヤ11の間の抵抗値が大きく、しかもばらつきも大きいことが分かった。
ワイヤ11自体のの抵抗値が1mΩ未満であるのに対して接続部の抵抗値は50〜100mΩと大きな値を示していた。
そのため図6に示すようにエミッタ電極7の平面形状を大きくし多数本(図示例では3本)のワイヤ11a、11b、11cをエミッタ電極7とリード9cの間で並列接続してエミッタ電極7での接触抵抗を小さくしている。
これにより半導体装置全体のオン抵抗を下げることが出来、高速動作が可能となった。
【0003】
【発明が解決しようとする課題】
しかしながらこのようにエミッタ電極7を大きくしてワイヤ11を多数本並列接続することによりオン抵抗の低減はできたがそのばらつきが大きくスイッチング動作させた場合、規格を外れるものがあって更なる改善が望まれていた。
この問題を改善するには並列接続されるワイヤ11の本数を増加すればよいがワイヤの使用量が増大しコストが上昇するという問題もあった。
また高価な金線に代えて安価なアルミニウム線を用いることもできるがアルミニウムは金に比して電気抵抗が大きいため線径を太くせざるを得ず、エミッタ電極7を更に広くしなければならないという問題もあり直ちにワイヤの本数を増加させることはできなかった。
【0004】
【課題を解決するための手段】
本発明は上記課題の解決を目的として提案されたもので、半導体ペレット上に形成された少なくとも一つの電極パッドに複数本のワイヤを電気的に接続した半導体装置において、上記半導体ペレット上に、電極パッド上での各ワイヤの接続位置を示す目合わせマークを形成したことを特徴とする半導体装置を提供する。
これにより、複数本のワイヤのそれぞれの接続位置の精度を高めることができ、半導体ペレット本体からエミッタ電極に集電された電流を各ワイヤに均等に配分することが出来、そのばらつきを抑えることができる。
【0005】
【発明の実施の形態】
本発明による半導体装置は半導体ペレット上に形成された少なくとも一つの電極パッドに複数本のワイヤのそれぞれの接続位置を示す目合わせマークを形成したことを特徴とするが、この目合わせマークは、導電パッド上のワイヤの接続位置が、ワイヤの他端からみた半導体ペレットのオン抵抗が最小となる位置を示すように設定される。
また、半導体ペレット本体の表面を被覆する絶縁被膜の要部を開口させて目合わせマークを形成することができる。
さらにはワイヤとワイヤの間でワイヤの引き出し方向と平行に第1の目合わせマークを形成し、ワイヤ接続部の配列方向端部に第2の目合わせマークを形成することができる。
【0006】
【実施例】
以下に本発明の実施例を図1から説明する。図において、図4乃至図6と同一物には同一符号を付し重複する説明を省略する。
図中、本発明による装置は主電流が流れるエミッタ電極7の周縁にこの電極7に接続される3本のワイヤ11a、11b、11cのそれぞれの一端の接続位置を示す目合わせマーク13a、13b、13cを形成した点で図6装置と明らかに相異する。
この目合わせマーク13a、13b、13cは絶縁被膜5を窓明けして絶縁被膜5と下地の色のコントラストで表示することができ、アルミニウムの蒸着膜で形成されたエミッタ電極7をこの窓明け部分に露呈させればコントラストを高めることができる。
またこの目合わせマーク13a、13b、13cの内、2つの目合わせマーク13a、13bは矩形状エミッタ電極7の長辺に配置されて、各ワイヤ11a、11b、11cに電極7上の電流密度がほぼ均等に分散するように各ワイヤ11の間隔を指定し、残りの目合わせマーク13cは短辺の中間に形成される。
半導体ペレット本体2内でエミッタ領域を突き抜けてエミッタ電極7に供給される電流はワイヤ11に集中するため、ワイヤ11接続部直下に電流が集中し、この接続部から離れた部分では電流はエミッタ電極7を面方向に移動してワイヤ11に到る。
そのため、エミッタ領域内を通過する電流の密度が不均一となり、エミッタ電極7内の電流の移動経路によっても抵抗値が異なる。
そのため目合わせマーク13a、13bは絶縁被膜5に隠れた部分を含むエミッタ電極の形状や半導体ペレット本体の内部構造などを考慮して配列位置が設定される。 仮に図2点線で示すように均等に分割された3つの領域に、ワイヤ11が位置ずれして接続された場合、各ワイヤ11の接続状態が同じであっても、間隔が隔たっているワイヤ11a、11b間の図示斜線部分はそれぞれのワイヤ11a、11bまでの距離が長くなり電気抵抗が上昇する。
このようにワイヤ11の接続位置がずれることによって電気抵抗が変化する。
本発明では図3に示すように、目合わせマーク13a、13bによって分割された3つの領域内の目合わせマーク13cで指定された位置にワイヤ11a、11b、11cを接続することによってエミッタ領域内の電流密度が均一になり、エミッタ電極7から各ワイヤ11に流入する電流も一様にできるため、エミッタ電極7と各ワイヤ11の接続抵抗を可及的に減少させそのばらつきを小さくできる。
このようにエミッタ電極7上での各ワイヤ11の接続位置が正確に設定されるため、ワイヤボンディング位置を画像認識により自動設定する場合だけでなく、予めボンデイング位置を指定してこの指定データにより自動ボンデイングする場合でも、ワイヤの接続位置が正確に設定できそのばらつきがなく、エミッタ電極7から3本のワイヤ11にほぼ均等に配分でき、接続抵抗のばらつきを抑えることが出来る。
具体的には外径寸法が5×6mm、エミッタ電極7の寸法が2.0×1.5mm、耐電圧40Vの半導体ペレットのエミッタ電極7に直径300μmのアルミニウム線を3本接続して電流1mAで動作させたとき、目合わせマークがない状態ではオン抵抗が50〜100mΩと、抵抗値が高い上、ばらつきが大きかったものが、目合わせマーク13を形成し、この目合わせマーク13で指定された位置にワイヤ11を接続することにより、オン抵抗を6〜11mΩに低減でき、しかもそのばらつきを抑えることができ、安定した高速スイッチング動作が可能な半導体装置を実現できた。
尚、本発明は上記実施例にのみ限定されるものではなく、例えばトランジスタだけでなくサイリスタなどスイッチング素子一般に適用できる。
また、目合わせマーク13を絶縁被膜5の窓明けあるいは切り欠きなどにより形成するだけでなく、絶縁被膜5とは別に印刷やレーザ光による穿孔などによっても形成することが出来る。
【0007】
【発明の効果】
以上のように本発明によれば、オン抵抗の低減を目的として半導体ペレットと外部リードとを複数本のワイヤで接続した半導体装置のオン抵抗を低減しさらにそのばらつきを抑えることが出来る。
【図面の簡単な説明】
【図1】 本発明の実施例を示す半導体装置の一部断面平面図
【図2】 従来のワイヤの接続状態を示す要部平面図
【図3】 本発明のワイヤの接続状態を示す要部平面図
【図4】 半導体装置の一例を示す側断面図
【図5】 半導体装置の一例を示す側断面図
【図6】 図4半導体装置のオン抵抗を低減する手段を説明する要部平面図
【符号の説明】
1 半導体ペレット
7 電極パッド
11a ワイヤ
11b ワイヤ
11c ワイヤ
13a 目合わせマーク
13b 目合わせマーク
13c 目合わせマーク[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with reduced on-resistance as much as possible.
[0002]
[Prior art]
Electronic circuit devices that require high-speed operation, such as airbag control devices used as collision safety devices for automobiles, detect impacts when a collision occurs with an impact sensor, and operate the gas generator by this output to inflate the airbag. It supports the occupants who are about to jump forward due to the reaction of the collision to ensure safety.
A signal from the impact sensor is once inputted to a control circuit using a microcomputer to prevent malfunction, but a semiconductor switching element having a high pulse response speed is used to shorten the signal processing time as much as possible.
In addition, when operating the manipulator such as a joystick on the controller and the operation button to remotely control the controlled unit, the controlled unit can respond sensitively to the operation and the operation of the controlled unit Therefore, a high-speed semiconductor switching element is generally used for such a portion.
Such a high-speed semiconductor switching element needs to have a high pulse response speed of the element body, but operation in a state where the element body is packaged is also important.
An example of a transistor as a semiconductor switching element will be described with reference to FIGS.
In the figure,
8 is an island in which the
The
The
For example, when transmitting the output of a sensor or manipulator, a diameter of 25 μm is sufficient for a gold wire if the operating current value is 0.3 mA, and a diameter of 50 μm is sufficient for an aluminum wire.
By the way, the switching operation of the semiconductor device is completely conductive and interrupted, and the current is changed in the conductive region. The former has a drawback that the power consumption is small but the operation speed is slightly inferior, and the latter always has a current. Since it flows, power consumption is large, but it can operate at high speed.
On the other hand, in an environment where there is a large amount of external noise, such as an automobile, the signal is switched at the maximum amplitude to improve the reliability against external noise.
For this reason, even a semiconductor device operating at a small current is turned on / off, but even if a
As a result of investigating the cause, the
While the resistance value of the
Therefore, as shown in FIG. 6, the
As a result, the on-resistance of the entire semiconductor device can be lowered, and high-speed operation is possible.
[0003]
[Problems to be solved by the invention]
However, the on-resistance can be reduced by enlarging the
In order to improve this problem, the number of
In addition, an inexpensive aluminum wire can be used instead of an expensive gold wire. However, since aluminum has a larger electric resistance than gold, the wire diameter must be increased, and the
[0004]
[Means for Solving the Problems]
The present invention has been proposed for the purpose of solving the above problems. In a semiconductor device in which a plurality of wires are electrically connected to at least one electrode pad formed on a semiconductor pellet, an electrode is formed on the semiconductor pellet. Provided is a semiconductor device characterized in that an alignment mark indicating a connection position of each wire on a pad is formed.
As a result, the accuracy of the connection position of each of the plurality of wires can be increased, and the current collected from the semiconductor pellet body to the emitter electrode can be evenly distributed to each wire, thereby suppressing variations. it can.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device according to the present invention is characterized in that alignment marks indicating respective connection positions of a plurality of wires are formed on at least one electrode pad formed on a semiconductor pellet. The connection position of the wire on the pad is set so as to indicate a position where the on-resistance of the semiconductor pellet viewed from the other end of the wire is minimized.
Also, the alignment mark can be formed by opening the main part of the insulating coating covering the surface of the semiconductor pellet body.
Furthermore, a first alignment mark can be formed between the wires in parallel to the wire drawing direction, and a second alignment mark can be formed at the end of the wire connection portion in the arrangement direction.
[0006]
【Example】
An embodiment of the present invention will be described below with reference to FIG. In the figure, the same components as those in FIGS. 4 to 6 are denoted by the same reference numerals, and redundant description is omitted.
In the drawing, the apparatus according to the present invention is provided with
The alignment marks 13a, 13b, and 13c can display the
Of these
The current supplied to the
Therefore, the density of the current passing through the emitter region becomes non-uniform, and the resistance value varies depending on the current moving path in the
Therefore, the alignment positions of the alignment marks 13a and 13b are set in consideration of the shape of the emitter electrode including the portion hidden in the insulating
As described above, the electrical resistance is changed by shifting the connection position of the
In the present invention, as shown in FIG. 3, the
Thus, since the connection position of each
Specifically, three aluminum wires having a diameter of 3 μm are connected to the
The present invention is not limited to the above-described embodiments, and can be applied to general switching elements such as thyristors as well as transistors.
Further, the alignment mark 13 can be formed not only by opening or notching the insulating
[0007]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the on-resistance of the semiconductor device in which the semiconductor pellet and the external lead are connected by a plurality of wires for the purpose of reducing the on-resistance, and to further suppress the variation.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional plan view of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a plan view of a main part showing a connection state of a conventional wire. FIG. 4 is a side sectional view showing an example of a semiconductor device. FIG. 5 is a side sectional view showing an example of a semiconductor device. FIG. 6 is a plan view of an essential part for explaining means for reducing on-resistance of the semiconductor device. [Explanation of symbols]
DESCRIPTION OF
Claims (5)
上記半導体ペレット上に、電極パッド上での各ワイヤの接続位置を示す目合わせマークを形成したことを特徴とする半導体装置。In a semiconductor device in which a plurality of wires are electrically connected to at least one electrode pad formed on a semiconductor pellet,
A semiconductor device characterized in that an alignment mark indicating a connection position of each wire on the electrode pad is formed on the semiconductor pellet.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28662998A JP3902342B2 (en) | 1998-10-08 | 1998-10-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28662998A JP3902342B2 (en) | 1998-10-08 | 1998-10-08 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000114307A JP2000114307A (en) | 2000-04-21 |
JP3902342B2 true JP3902342B2 (en) | 2007-04-04 |
Family
ID=17706896
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28662998A Expired - Fee Related JP3902342B2 (en) | 1998-10-08 | 1998-10-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3902342B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4591886B2 (en) | 2004-07-21 | 2010-12-01 | ローム株式会社 | Power supply circuit device using semiconductor device |
JP2013017360A (en) | 2011-07-06 | 2013-01-24 | Toshiba Corp | Semiconductor device, dc-dc converter, and image receiver |
JP6901902B2 (en) | 2017-04-27 | 2021-07-14 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
-
1998
- 1998-10-08 JP JP28662998A patent/JP3902342B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2000114307A (en) | 2000-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0409173B1 (en) | Semiconductor ic device having an improved interconnection structure | |
JP3051011B2 (en) | Power module | |
KR960000693A (en) | Electric power steering circuit | |
US7230324B2 (en) | Strobe light control circuit and IGBT device | |
JP3410969B2 (en) | Semiconductor device | |
JPH05160290A (en) | Circuit module | |
JP3902342B2 (en) | Semiconductor device | |
JP4595470B2 (en) | Chip-on-film circuit board and image display device using the chip-on-film circuit board | |
JP3279842B2 (en) | Power semiconductor device | |
JP3658946B2 (en) | Power transistor mounting structure | |
US6020631A (en) | Method and apparatus for connecting a bondwire to a bondring near a via | |
JPH0644109Y2 (en) | IC package | |
KR20010074816A (en) | Thermal head and thermal head unit | |
JP3203157B2 (en) | Hybrid integrated circuit device | |
JP4710131B2 (en) | Semiconductor device | |
JPH10150120A (en) | Printed wiring board, bga type lsi package and electronic device | |
JP3248117B2 (en) | Semiconductor device | |
JPH0748539B2 (en) | Hybrid integrated circuit device | |
JP2005353976A (en) | Electronic device | |
JP3205100B2 (en) | Thermal print head | |
JP2006109665A (en) | Integrated circuit device having overcurrent detecting function | |
JPH05226568A (en) | Semiconductor device | |
JP3172292B2 (en) | Hybrid integrated circuit device | |
EP0430239A1 (en) | Resin molded semiconductor device having tab kept at desired electric potential | |
JPS5845974A (en) | Thermal head |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20050324 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20050511 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050819 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061201 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20061205 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20061228 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110112 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110112 Year of fee payment: 4 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110112 Year of fee payment: 4 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110112 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120112 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130112 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130112 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140112 Year of fee payment: 7 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |