JP3900233B2 - Light receiving element and built-in light receiving element - Google Patents

Description

【００５８】
なお、Ｐ型エピタキシャル層１４２内には、不純物濃度が変化している領域（オートドープ層１４２ａ）があるため、この表１に示すように、空乏層幅はＰ型エピタキシャル層１４２幅よりも薄くなる。
【００５９】
また、この測定による、大光量時の応答速度と空乏層内の電界強度との関係を図９に実測値として示す。この図９に示すように、空乏層内の電界強度が強くなるに従って応答速度が速くなっており、その依存性はシミュレーション結果と一致している。従って、大光量を照射した時の応答速度はおおよそ空乏層内の電界強度によって律され、空乏層幅には殆ど因らない。これは、シミュレーションにおいて応答速度が低下している場合のキャリア分布を示した図１０（ａ）からも分かるように、キャリアの蓄積は接合付近（深さ２μｍ程度で起きるため、キャリアの蓄積はこの接合付近での電界強度に大きく依存すると考えられることからも説明される。
【００６０】
一方、上記表１に示すように、空乏層幅が狭まると、小光量を照射した時の応答速度が低下する。これは、空乏層が狭まることにより容量成分が上昇するため、および空乏層よりも下で発生したキャリアが拡散で移動する距離が長くなるためである。
【００６１】
以上のように、図３の構造のフォトダイオードにおいて、Ｐ型エピタキシャル層１４２の厚みを薄くして空乏層内の電界強度を強くすることにより、大光量時の応答速度を向上させることができる。しかし、Ｐ型エピタキシャル層１４２を薄くしすぎると、小光量時の応答速度が低下するため、書き込み時の大光量および読み出し時の小光量を照射したときに要求される応答速度の両方の観点から、最適な層厚を設定する必要がある。
【００６２】
（実施形態１）
図３は、本実施形態の受光素子の構造を示す断面図である。
【００６３】
本実施形態の受光素子と図３の構造を有する従来の受光素子とは、同様の方法により作製することができるが、大きく異なる点は、Ｐ型エピタキシャル層（高抵抗結晶成長層）１４２の層厚と比抵抗である。本実施形態では、このＰ型エピタキシャル層１４２の層厚および比抵抗を、下記式を満足するように設定する。
【００６４】
Ｅｄ＞０．３Ｖ／μｍ
但し、Ｅｄはフォトダイオードに動作逆バイアス電圧を印加した時に空乏層１６０内に生じる平均電界強度である。
【００６５】
このように空乏層内の電界強度を設定する理由は以下の通りである。空乏層内の電界強度を強めることにより、接合付近に存在する光キャリアを押し流す力を大きくして、フォトダイオードに大光量の光が入射したときにキャリアの蓄積による応答速度の低下を抑制することができる。現在、書き込み対応ＣＤ用ピックアップの性能としては、６倍速書き込みが要求されている。上述した図９によれば、空乏層内の電界強度を０．３Ｖ／μｍ以上に設定することにより、６倍速書き込みに必要な応答速度を実現することができる。
【００６６】
さらに、書き込み対応のフォトダイオードには、書き込み時だけではなく読み出し時の応答速度も重要であり、３２倍速読み出しの性能が要求されている。上記表１の実験データから見積もった空乏層幅と小光量時の応答速度の関係を図１２に示す。ここで、３２倍速の応答速度を得るためには応答周波数が２３ＭＨｚ以上であることが必要であり、これを満たすためにはフォトダイオードの１ｄＢ落ちの周波数が１５ＭＨｚ以上であることが必要である。この図１２によれば、空乏層幅を５μｍ以上に設定することにより、３２倍速読み出しに必要な応答速度を実現することができる。
【００６７】
なお、上記書き込み時および読み出し時に必要な応答速度を充分満足させるために、空乏層内の電界強度を０．３Ｖ／μｍ以上とし、かつ、空乏層幅を５μｍ以上とするためには、Ｐ型エピタキシャル層１４２の層厚を１３μｍ以上１７μｍ以下とし、その比抵抗を１００Ωｃｍ以上１５００Ωｃｍ以下とするのが好ましい。なお、この層厚および比抵抗の範囲は本発明者らの実験データから決定したものである。
【００６８】
さらに、Ｐ型半導体基板１４１の不純物濃度は、Ｐ型エピタキシャル層１４２の表面における不純物濃度の１０³倍を越えない濃度とするのが好ましい。これは、Ｎ型エピタキシャル層の形成までの工程において、基板内の不純物が抜け出してその表面に形成されるＰ型エピタキシャル層１４２（不純物濃度が一定の層１４２ｂ）の表面に付着することによってオートドープ層が形成されるのを防ぐためである。例えば、１ｋΩの高比抵抗を有するＰ型エピタキシャル層１４２を形成する場合には、Ｐ型半導体基板１４１の不純物濃度は約１Ωｃｍとする。この理由は、Ｐ型エピタキシャル層１４２の表面に形成されるオートドープ層の不純物濃度と、Ｐ型半導体基板１４１の不純物濃度との間に、およそ１：１０００という関係が成立するからである。従って、Ｐ型半導体基板１４１の不純物濃度を、Ｐ型エピタキシャル層１４２の表面における不純物濃度の設定値の１０００倍を越えない濃度とすれば、仮に不純物のオートドープが発生しても、結果として得られるＰ型エピタキシャル層の表面での不純物濃度が所定の設定値を越えることはない。また、アノード抵抗を下げるためには、基板比抵抗はオートドープが起こらない範囲で低い方が望ましい。例えば基板比抵抗の下限を１Ωｃｍとすると、受光素子を安定して量産するためには基板比抵抗の上限を２０Ωｃｍ以下にするのが望ましい。
【００６９】
さらに、基板の裏面にアノード電極を設けて、表面側の分離拡散領域上に設けたアノード電極と電気的に接続すれば、表面側のみにアノード電極を設けた場合に比べて、より一層アノード抵抗を下げて応答速度の向上を図ることができる。
【００７０】
（実施形態２）
図１３は、本実施形態の受光素子の構造を示す断面図である。この図において、アノード電極、カソード電極、配線および保護膜等は省略されている。
【００７１】
この受光素子は、図１３（ａ）に示すように、Ｐ型半導体基板１０３上にＰ型埋め込み拡散層１０９、Ｐ型エピタキシャル層１０４およびＮ型エピタキシャル層１１０が形成されている。Ｎ型エピタキシャル層１１０はＰ型分離拡散層１０７およびＰ型分離埋め込み拡散層１０８により複数の領域に分割され、各分割領域とその下のＰ型エピタキシャル層１０４との接合によりフォトダイオードが構成されている。Ｐ型エピタキシャル層１０４は、図１３（ａ）のｃ−ｃ’線部分の不純物プロファイルを示す図１３（ｂ）に示すように、基板側から連続的に不純物濃度が減少するオートドープ層（はい上がり層）１０４ａと比抵抗が一定の層１０４ｂとからなる。
【００７２】
この受光素子と実施形態１の受光素子とにおいて、大きく異なる点は、Ｐ型半導体基板１０３とｐ型エピタキシャル層１０４との間に、Ｐ型埋め込み拡散層１０９を設けた点である。受光素子の作製においては、Ｐ型半導体基板１０３上にボロンを拡散してＰ型埋め込み拡散層１０９を形成し、その上に結晶成長によりＰ型エピタキシャル層を形成する。その後は、従来と同様に行うことができる。
【００７３】
実施形態１の受光素子においては、Ｐ型エピタキシャル層の層厚および比抵抗を最適化しても、得られる性能は、書き込み６倍速および読み出し３２倍速程度までである。これは、空乏層内の電界強度を強めるために空乏層幅を狭くすることにより、容量成分が増加すること、および基板の比較的深い位置で発生したキャリアが拡散により移動する距離が長くなることによる。また、これは、読み出し時のみではなく、書き込み時の応答速度を律する要因ともなっている。
【００７４】
そこで、本実施形態では、Ｐ型半導体基板１０３とＰ型エピタキシャル層１０４との間にＰ型埋め込み拡散層１０９を形成することにより、基板の比較的深い位置で発生したキャリアに対してＰ型埋め込み拡散層１０９がポテンシャルバリアとして働くようにして、応答速度を向上させることを検討した。
【００７５】
まず、この埋め込み拡散層１０９がどのように機能するのかについて、デバイスシミュレーションにより検討を行った。フォトダイオード部の濃度プロファイルが図１４（ａ）、図１４（ｂ）、図１４（ｃ）に示すような３つの構造に対して、７８０ｎｍ、３００μＷのパルス光に対して、１％の応答時間（光電流が９０％から１％になるまでの時間）ｔｆ（９０％→１％）を下記表２に示す。なお、この表２において、埋め込み層幅とは、Ｐ型埋め込み拡散層１０９のピーク不純物濃度の位置から、その表面側の濃度が１０¹⁴ｃｍ^-3である位置までの幅である。
【００７６】
【表２】

【００７７】
ここで、１％の応答時間は、基板から拡散によって移動するキャリアで決定される。プロファイル（ａ）と（ｂ）ではＰ型半導体基板１０３、Ｐ型埋め込み拡散層１０９およびＰ型エピタキシャル層１０４の不純物濃度は等しいが、Ｐ型埋め込み拡散層１０９の幅のみを異ならせてある。
【００７８】
このプロファイル（ａ）と（ｂ）の構造では、（ｂ）の方が応答速度が大きく向上しているため、Ｐ型埋め込み拡散層１０９の幅が広くて、Ｐ型埋め込み拡散層１０９の作り出すポテンシャルバリアが大きな勾配を持たないような場合には、応答速度向上の効果が得られないことがわかる。
【００７９】
また、プロファイル（ｂ）と（ｃ）の構造では、Ｐ型半導体基板１０３の濃度（比抵抗）以外のプロファイルは全て同じにしてある。この（ｂ）と（ｃ）から、Ｐ型半導体基板１０３の濃度によって大きく応答速度が変化することがわかる。
【００８０】
ここで、図１５（ａ）に上記プロファイル（ｃ）の構造に対してパルス幅１０μｓｅｃのパルス光照射後２ｎｓｅｃにおける電子濃度分布を示し、図１５（ｂ）に上記プロファイル（ｂ）の構造に対してパルス幅１０μｓｅｃのパルス光照射後２ｎｓｅｃにおける電子濃度分布を示す。この図は、フォトダイオード部の断面を示す図であり、ドット密度が高いほど電子濃度が高いことを示している。また、図中の実線は、Ｐ型埋め込み拡散層１０９の濃度ピークを示している。なお、表面付近全体の電子濃度が高くなっているのは、カソード抵抗を下げるためにＮ型の高濃度注入層を設けているためである。
【００８１】
図１５（ａ）に示すように、基板比抵抗が高く、ポテンシャルバリアが十分の高さを持つプロファイル（ｃ）の構造の場合には、Ｐ型埋め込み拡散層１０９よりも深い位置のキャリアがバリアを越えることができず、キャリアが溜まっていることが分かる。これに対して、図１５（ｂ）に示すように、ポテンシャルバリアの高さが十分ではないプロファイル（ｂ）の構造の場合には、キャリアが表面側に流れ出して、Ｐ型埋め込み拡散層１０９のピーク濃度付近にも分布していることが分かる。従って、プロファイル（ｂ）の構造において応答速度が低下するのは、Ｐ型埋め込み拡散層１０９よりも基板側で発生したキャリアがポテンシャルバリアを越えて遅い電流成分として寄与するためである。
【００８２】
以上のように、図１３に示すＰ型埋め込み拡散層１０９を設けた受光素子においては、Ｐ型埋め込み拡散層１０９がそれよりも基板側で発生したキャリアにとってポテンシャルバリアとして働く。このため、Ｐ型埋め込み拡散層１０９よりも基板側で発生したキャリアがポテンシャルバリアを越えて表面側に移動することができず、基板内で再結合して消滅する。また、Ｐ型埋め込み拡散層１０９の濃度ピーク部分から空乏層１０６の間の領域で発生したキャリアは、Ｐ型埋め込み拡散層１０９の大きな濃度勾配による内蔵電界によって加速され、拡散による場合に比べて速く空乏層端に移動する。これらのことから、書き込み対応フォトダイオードの書き込み時および読み出し時の応答速度を共に高速化することができる。この高速化の効果は、Ｐ型埋め込み拡散層１０９がＰ型半導体基板１０３に対して十分な濃度差および勾配を有することにより、さらに向上する。
【００８３】
次に、Ｐ型エピタキシャル層１０４の層厚を変化させることにより空乏層１０６幅を変化させたプロファイルに対してシミュレーションを行った。フォトダイオード部の濃度プロファイルが図１４（ｂ）に示すような構造に対して、Ｐ型高抵抗エピタキシャル層の層厚を変化させて、３５０μｗの光照射を行ったときの応答時間（光電流が９０％から１０％になるまでの時間）ｔｆ（９０％→１０％）を下記表３に示す。
【００８４】
【表３】

【００８５】
また、図１６（ａ）に、Ｐ型エピタキシャル層１０４の層厚を１５μｍとして空乏層１０６内の電界強度を０．４２Ｖ／μｍとした構造に対してパルス幅１０μｓｅｃのパルス光照射時におけるフォトダイオード部の電子濃度分布を示し、図１６（ｂ）に、Ｐ型エピタキシャル層１０４の層厚を２０μｍとして空乏層１０６内の電界強度を０．２１Ｖ／μｍとした構造に対してパルス幅１０μｓｅｃのパルス光照射時におけるフォトダイオード部の電子濃度分布を示す。この図は、フォトダイオード部の断面を示す図であり、ドット密度が高いほど電子濃度が高いことを示している。また、図中の実線は、Ｐ型埋め込み拡散層１０９の濃度ピークを示している。なお、表面付近全体の電子濃度が高くなっているのは、カソード抵抗を下げるためにＮ型の高濃度注入層を設けているためである。
【００８６】
この図から分かるように、層厚が２０μｍの場合には、空乏層１０６付近にキャリアの蓄積が起こっている。従って、Ｐ型エピタキシャル層が厚くなると空乏層が広がって、空乏層内の電界強度が弱まるために電荷の蓄積が起こり、応答速度の低下につながる。
【００８７】
図１７に、空乏層１０６内の電界強度と、７８０ｎｍ、３００μＷのパルス光に対する１０％の応答時間（カソード電流が１０％になるまでの時間）ｔｆ（０％→９０％）との関係を示す。この図から分かるように、本実施形態において、Ｐ型エピタキシャル層１０４の層厚および比抵抗を、下記式を満足するように設定することにより、次期書き込み対応フォトダイオードとして要求される１２倍速書き込み性能（ｔｆが４ｎｓ以下）を実現することができる。
【００８８】
Ｅｄ＞０．３Ｖ／μｍ
但し、Ｅｄはフォトダイオードに動作逆バイアス電圧を印加した時に空乏層１０６内に生じる平均電界強度である。これは、シミュレーション結果に示すように、空乏層内の電界強度を強めることにより、接合付近に存在する光キャリアを流す力を大きくして、フォトダイオードに大光量の光が入射したときにキャリアの蓄積による応答速度の低下を抑制することができるからである。
【００８９】
上記書き込み時の性能を実現するために空乏層内の電界強度を０．３Ｖ／μｍ以上とし、かつ、フォトダイオードの容量の上昇を抑えるためには、Ｐ型エピタキシャル層１０４の層厚を９μｍ以上１７μｍ以下とし、その比抵抗を１００Ωｃｍ以上１５００Ωｃｍ以下とするのが好ましい。なお、このエピタキシャル層の層厚の範囲は表３のシミュレーションデータから決定したものであり、比抵抗の範囲も本発明者らのシミュレーション結果から決定したものである。また、エピタキシャル層の層厚の下限を９μｍとしているのは、図１４（ｂ）から、エピタキシャル層厚が９μｍよりも薄くなるとＮ型エピタキシャル層１１０とＰ型エピタキシャル層１０４の接合濃度がオートドープ層１０４ａの影響で高くなり、接合容量が増えて応答速度が低下するためである。
【００９０】
さらに、本実施形態において、Ｐ型埋め込み拡散層１０９をポテンシャルバリアとして十分機能させるためには、Ｐ型埋め込み拡散層１０９のピーク不純物濃度がＰ型半導体基板１０３の不純物濃度の１００倍以上とするのが好ましい。その理由は、以下の通りである。
【００９１】
Ｐ型埋め込み拡散層１０９がＰ型半導体基板１０３に対して十分な拡散電位を持たない場合には、Ｐ型埋め込み拡散層１０９よりも基板側で発生したキャリアが熱エネルギーによってＰ型埋め込み拡散層１０９を越えてＰＮ接合に達し、応答速度を低下させる要因となる。動作温度の約１０℃〜１００℃の熱エネルギーが０．０３ｅＶ〜０．０４ｅＶであるので、これよりも十分に大きい拡散電位を持つ必要がある。基板側で発生したキャリアの表面側への流れ込みを抑えるために、Ｐ型埋め込み拡散層１０９を越えてくるキャリアを１０％以下とするには、Ｐ型埋め込み拡散層１０９がＰ型半導体基板１０３に対して０．１Ｖ以上の電位を有する必要がある。これは、Ｅｅ（ｅＶ）の熱エネルギーを有する電子がＥｂ（ｅＶ）のポテンシャルバリアを乗り越える確率ｐが
ｐ＝Ｅｘｐ（−Ｅｂ／Ｅｅ）
であるため、
ｐ＝Ｅｘｐ（−Ｅｂ／０．０４）＜０．１
Ｅｂ＞−０．０４×ｌｏｇ（０．１）＝０．１
となるからである。
【００９２】
ここで、不純物濃度と拡散電位との関係を図１８に示す。この図１８から分かるように、Ｐ型埋め込み拡散層１０９とＰ型半導体基板１０３との間に電位０．１Ｖ以上の電位差を与えるためには、Ｐ型埋め込み拡散層１０９のピーク不純物濃度をＰ型半導体基板１０３の不純物濃度の１００倍以上に設定する必要がある。すなわち、Ｐ型埋め込み拡散層１０９のピーク不純物濃度をＰ型半導体基板１０３の不純物濃度の１００倍以上に設定することにより、Ｐ型埋め込み拡散層１０９よりも基板側で発生するキャリアによる応答速度の低下を改善することができる。
【００９３】
さらに、Ｐ型半導体基板１０３の不純物濃度とＰ型埋め込み拡散層１０９のピーク不純物濃度との差が大きいほど、ポテンシャルバリアとしての効果は高くなる。ここで、基板の不純物濃度を下げるためにはＦＺ（Ｆｌｏａｔ Ｚｏｎｅ）法により作製した基板の方が有利であるが、この場合にはウェハ強度が弱く、欠陥による歩留まり低下が生じるおそれがある。これに対して、ＣＺ（Ｃｚｏｃｈｒａｌｓｋｉ）法で作製した基板の場合には、欠陥による歩留まりの低下を防ぐことができるので好ましい。なお、ＣＺ法で作成可能な最も高い基板比抵抗は、５０Ωｃｍであるので、２０Ωｃｍから５０Ωｃｍの比抵抗を有するＣＺ基板を用いるのが好ましい。これは、比抵抗の上限を５０Ωｃｍとすると、受光素子を安定量産するためには下限が２０Ωｃｍとなるからである。
【００９４】
また、Ｐ型半導体基板１０３に対して十分高い不純物濃度（１００倍以上）を与えるためには、Ｐ型埋め込み拡散層１０９のピーク不純物濃度を１×１０¹⁷ｃｍ^-3以上にするのが好ましい。
【００９５】
さらに、Ｐ型埋め込み拡散層１０９は、層厚および比抵抗の制御性の観点からは、イオン注入により形成するのが有利である。しかし、１×１０¹⁷ｃｍ^-3以上という高濃度のイオンを注入した場合、欠陥による歩留まりの低下が生じるおそれがある。このような欠陥による歩留まりの低下を防ぐためには、塗布拡散によりＰ型埋め込み拡散層１０９を形成するのが好ましい。
【００９６】
さらに、パルス光に対する１％の応答時間を改善するためには、Ｐ型埋め込み拡散層１０９の濃度プロファイルを以下のように設定するのが好ましい。
【００９７】
Ｘｕ＜３８μｍ
但し、Ｘｕはフォトダイオード表面から、Ｐ型埋め込み拡散層１０９の基板側でＰ型埋め込み拡散層１０９のピーク不純物濃度の１００分の１の濃度となっている位置までの厚さである。これは、光が入射して吸収され、その強度が１％以下になる部分よりも浅いところにポテンシャルバリアを形成しなければ応答の遅いキャリアを十分に消すことができず、応答速度を向上させる効果が十分に得られないからである。ここで、ＣＤ−ＲＯＭに使用される波長７８０ｎｍの光がＳｉに入射して１％の強度となる深さは３８μｍであるため、フォトダイオード表面から、Ｐ型埋め込み拡散層１０９の基板側でＰ型埋め込み拡散層１０９のピーク不純物濃度の１００分の１の濃度となっている位置までの厚さを３８μｍ以下に設定するのが好ましい。
【００９８】
なお、実施形態２の受光素子においても、図３に示した実施形態１の構造と同様に、同一基板上のＰ型分離拡散層１０７およびＰ型分離埋め込み拡散層１０８によってフォトダイオード部とは分離されたＮ型エピタキシャル層の領域に、信号処理回路を形成して回路内蔵型受光素子とすることにより、ピックアップシステムの小型化を図り、コストダウンを実現することができる。
【００９９】
さらに、このような回路内蔵型受光素子において、図１９に示すように、フォトダイオード部以外の一部にＰ型エピタキシャル層３０表面から、Ｐ型埋め込み拡散層４を形成するのが好ましい。これにより、Ｐ型分離埋め込み拡散層７の下側の抵抗を下げてアノード抵抗を下げることができ、さらにフォトダイオードの高速化を図ることができる。また、回路部の基板抵抗を下げることにより、ラッチアップを防ぐこともできる。なお、この図１９において、１はＰ型半導体基板、３０はＰ型高抵抗エピタキシャル層であり、そのうち、２は比抵抗一定の層、３はオートドープ層である。また、５は空乏層、６はＮ型コレクタ領域、８はＮ型エピタキシャル層、９はＰ型分離拡散層、１０はＮ型コレクタコンタクト領域、１１はＰ型ベース領域、１２はＮ型エミッタ領域、１４はカバー膜、１５はカソードコンタクト、１６はアノードコンタクト、１７はトランジスターのコンタクト、２２はカソードコンタクト領域、８０はフォトダイオード形成部、９０は回路形成部を示す。
【０１００】
なお、上記実施形態においてはＰ型を第１導電型、Ｎ型を第２導電型としたが、Ｎ型を第１導電型、Ｐ型を第２導電型とすることも可能である。
【０１０１】
【発明の効果】
以上詳述したように、本発明によれば、第１導電型半導体基板の上にそれよりも不純物濃度が低い第１導電型半導体層を有する積層基板を用い、その上にフォトダイオードを形成した構造において、その第１導電型半導体層の層厚および比抵抗を調節して空乏層幅を薄くすることにより、フォトダイオードの印加バイアス電圧を変化させなくても空乏層内の電界強度を強くすることができる。その結果、接合付近で電界によってキャリアを押し流す力が強くなり、大光量時のキャリアの蓄積による応答速度の低下を防ぐことができる。
【０１０２】
但し、空乏層幅が狭くなると、容量成分の増加、および空乏層よりも下側で発生したキャリアが拡散により進む距離が長くなるため、小光量時の応答速度が低下するおそれがある。よって、読み出し時の小光量および書き込み時の大光量の両方に対して要求される応答速度を満足することができるように、第１導電型半導体層の層厚および比抵抗を調節して、所望の仕様を実現することができる。
【０１０３】
また、本発明によれば、第１導電型半導体基板とそれよりも不純物濃度が低い第２の第１導電型半導体層との間に、不純物濃度が高い第２の第１導電型半導体層を設けることにより、この第２の第１導電型半導体層を基板側で発生したキャリアに対してポテンシャルバリアとして機能させることができる。よって、拡散により長い距離を移動する遅い電流成分を除くことができる。また、第２の第１導電型半導体層のピーク不純物濃度の部分よりも表面側で発生したキャリアは、第２の第１導電型半導体層の内蔵電界によって加速されるため、空乏層端まで速くたどり着く。よって、応答速度をさらに向上させることができる。
【０１０４】
このように、本発明によれば、書き込み対応のフォトダイオードにおいて、書き込みのための大光量入射時にキャリアの蓄積による応答速度の低下を克服し、さらに、読み出しのための小光量入射時および書き込みのための大光量入射時の応答速度の改善を同時に実現することができる受光素子および回路内蔵型受光素子が提供される。
【図面の簡単な説明】
【図１】従来の受光素子の構成を示す図であり、（ａ）はその断面構造を示し、（ｂ）は（ａ）のａ−ａ’線部分の不純物濃度を示す。
【図２】従来の受光素子における基板比抵抗と応答速度（カットオフ周波数）との関係を示す図である。
【図３】実施形態１および従来の受光素子の断面構造を示す図である。
【図４】図１の構造の受光素子について、フォトダイオードの応答速度（カットオフ周波数）の入射光量依存性を実験した結果を示す図である。
【図５】図１の構造の受光素子について、フォトダイオードに小光量を入射したときのポテンシャル分布の時間変化をシミュレーションした結果を示す図である。
【図６】図１の構造の受光素子について、フォトダイオードに大光量を入射したときのポテンシャル分布の時間変化をシミュレーションした結果を示す図である。
【図７】図１の構造の受光素子について、フォトダイオードに大光量を入射したときのキャリア密度分布の時間変化をシミュレーションした結果を示す図である。
【図８】シミュレーションに用いたフォトダイオードの構成を示す図であり、（ａ）はその断面構造を示し、（ｂ）は（ａ）のｂ−ｂ’線部分の不純物濃度を示す。
【図９】図８の構造の受光素子について、フォトダイオードの空乏層内の電界強度と応答速度との関係をシミュレーションした結果および実測した結果を示す図である。
【図１０】（ａ）および（ｂ）は、図８の構造の受光素子について、フォトダイオードのキャリア密度分布の時間変化を示す図である。
【図１１】（ａ）および（ｂ）は、図８の構造の受光素子について、光を照射していないときと光入射時とにおけるフォトダイオードの電界強度分布を示す図である。
【図１２】図３の構造の受光素子について、フォトダイオードに小光量を入射したときの応答速度（カットオフ周波数）の空乏層幅依存性を示す図である。
【図１３】実施形態２の受光素子の構成を示す図であり、（ａ）はその断面構造を示し、（ｂ）は（ａ）のｃ−ｃ’線部分の不純物濃度を示す。
【図１４】（ａ）〜（ｃ）は、図１３の構造の受光素子について、シミュレーションに用いたフォトダイオードの深さ方向の不純物濃度分布を示す図である。
【図１５】（ａ）および（ｂ）は、図１４（ｃ）および（ｂ）の不純物プロファイルを有するフォトダイオードについて、パルス幅１０μｓｅｃのパルス光照射後２ｎｓｅｃにおけるキャリアの平面分布をシミュレーションした結果を示す図である。
【図１６】 （ａ）および（ｂ）は、Ｐ型エピタキシャル層の層厚を１５μｍおよび２０μｍとしたフォトダイオードについて、パルス幅１０μｓｅｃのパルス光照射時におけるキャリアの平面分布をシミュレーションした結果を示す図である。
【図１７】図１３の構造の受光素子について、大光量入射時におけるフォトダイオードの空乏層内の電界強度と応答速度をシミュレーションした結果を示す図である。
【図１８】不純物濃度勾配により生じる拡散電位と不純物濃度との関係を示す図である。
【図１９】本発明の一実施形態である回路内蔵型受光素子の構成を示す図である。
【符号の説明】
１、８４、１０３、１４１ Ｐ型半導体基板
２、１０４ｂ 比抵抗が一定の層
３、１０４ａ、１４２ａ オートドープ層
４ Ｐ型埋め込み拡散層
５、８６、１０６、１６０ 空乏層
６ Ｎ型コレクタ領域
７、８８、１０８ Ｐ型分離埋め込み拡散層
８、８５、１１０、１４３ Ｎ型エピタキシャル層
９、８７、１０７、１４４ Ｐ型分離拡散層
１０ Ｎ型コレクタコンタクト領域
１１、１４７ Ｐ型ベース領域
１２、１４８ Ｎ型エミッタ領域
１４ カバー膜
１５ カソードコンタクト
１６ アノードコンタクト
１７ トランジスターのコンタクト
２２ カソードコンタクト領域
３０、１０４、１４２ Ｐ型エピタキシャル層
８０、１８０ フォトダイオード形成部
９０、１９０ 回路形成部
１０９ Ｐ型埋め込み拡散層
１４２ｂ 不純物濃度が一定の層
１４５ Ｎ型コンタクト領域
１４６ Ｎ型埋め込み領域
１４９ シリコン酸化膜
１５０ａ、１５０ｂ、１５０ｃ 電極配線層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a light receiving element and a circuit built-in light receiving element used for an optical pickup capable of writing.
[0002]
[Prior art]
Conventionally, an optical pickup is used in an optical disk device such as a CD-ROM or a DVD (digital video disk). In recent years, the speed of this optical disc apparatus has been increasing, and a large amount of data such as moving images has been handled at a high speed. In such a background, the demand for high speed optical pickup is very strong.
[0003]
Recently, writable optical disk devices such as CD-R / RW and DVD-R / RAM have also appeared. In this writable optical disc apparatus, information is written by changing the color of the dye on the disc by the heat of the laser, etc., so that a high power laser is irradiated onto the optical disc and the reflected light is incident on the photodiode. For this reason, the light quantity of the laser irradiated to the photodiode at the time of writing becomes very large compared with the time of reading. Even in such a writable optical disc medium, the demand for high speed is very strong.
[0004]
FIG. 1 shows the structure of a conventional photodiode disclosed in Japanese Patent Laid-Open No. 9-153605. In this photodiode, as shown in FIG. 1A, a second conductivity type epitaxial layer 85 is formed on a first conductivity type semiconductor substrate 84. The second conductivity type epitaxial layer 85 is divided into a plurality of regions by the first conductivity type diffusion layers 87 and 88, and a photodiode is formed by joining each divided region and the first conductivity type semiconductor substrate 84 therebelow. .
[0005]
In a photodiode having such a structure, the factors that determine the response speed are the CR time constant determined by the capacitance (C) and resistance (R) of the photodiode, and the carriers generated on the substrate side from the depletion layer move by diffusion. There is a movement distance when doing.
[0006]
Therefore, in this prior art, the impurity concentration of the first conductivity type semiconductor substrate 84 is set low as shown in FIG. 1B showing the impurity concentration profile of the line aa ′ in FIG. The depletion layer 86 extending in the first conductivity type semiconductor substrate 84 is easily expanded. Thereby, the junction capacitance of the photodiode can be reduced, the CR time constant can be reduced, and the response speed of the photodiode can be increased. Furthermore, since the depletion layer extends deeper to the substrate side, the distance traveled by diffusion of carriers generated at a relatively deep position is shortened, so that the response speed can be increased.
[0007]
However, if the substrate specific resistance is further increased in order to further increase the response speed of the photodiode, the series resistance on the anode side caused by the substrate specific resistance will increase. For this reason, the R component of the CR time constant that determines the response of the photodiode increases, and conversely the response speed decreases. That is, as the substrate specific resistance is increased, the C component of the CR time constant that governs the response speed of the photodiode can be reduced. Therefore, as shown in FIG. The response speed of the diode (the cutoff frequency of the photodiode) can be improved. However, when the substrate specific resistance is further increased, the R component due to the anode resistance in particular increases, so that the response speed of the photodiode decreases as shown in FIG.
[0008]
Therefore, in order to further increase the speed of the photodiode, for example, in Japanese Patent Application Laid-Open No. 61-154063, a P-type high resistance crystal growth layer 142 is formed on a P-type low resistance substrate 141 as shown in FIG. There has been proposed a structure in which a photodiode is formed on the laminated substrate. The high-resistance crystal growth layer 142 includes an auto-doped layer 142a whose impurity concentration continuously decreases from the low-resistance substrate 141 side and a layer 142b whose impurity concentration is constant. In this prior art, the depletion layer 160 is easily spread on the substrate side by the high resistance crystal growth layer 142, and the junction capacitance is lowered. Furthermore, the series resistance on the anode side is lowered by the P-type low resistance substrate 141 located deeper where the depletion layer 160 extends. As a result, both the C component and the R component that govern the response speed of the photodiode are lowered to increase the response speed. In FIG. 3, 143 is an N-type epitaxial layer, 144 is a P-type isolation diffusion layer, 145 is an N-type contact region, 146 is an N-type buried region, 147 is a P-type base region, 148 is an N-type emitter region, 149 Is a silicon oxide film, 150a, 150b and 150c are electrode wiring layers, 180 is a photodiode forming part for detecting signal light, and 190 is a circuit forming part for processing the detected signal.
[0009]
In order to improve the response speed using the multilayer substrate, it is necessary to sufficiently expand the depletion layer in the high resistance layer to reduce the junction capacitance. Therefore, the specific resistance of the high-resistance layer is increased to 1000 Ωcm, which is the upper limit that can be controlled by epitaxial growth, and the thickness of the high-resistance layer 142 is increased to about 20 μm in which the depletion layer spreads over the high-resistance layer 142b having a constant concentration ( It is desirable that the high-resistance layer 142b having a constant concentration be about 13 μm. This is because when the region where the depletion layer of the high resistance layer does not spread increases, the series resistance on the anode side increases, which hinders the improvement of the response speed.
[0010]
[Problems to be solved by the invention]
By the way, in the optical pickup for writing, the amount of light irradiated from the laser to the optical disk increases in proportion to the writing speed, so that the amount of laser light incident on the photodiode as the reflected light also increases. If the amount of light incident on the photodiode exceeds a certain amount, there arises a problem that the response speed of the photodiode decreases.
[0011]
FIG. 4 shows the result of examining the dependence of the response speed (cutoff frequency) of the photodiode on the amount of incident light with respect to the structure of FIG. As shown in FIG. 4, when the amount of light incident on the photodiode exceeds a certain amount, the response speed (cutoff frequency) of the photodiode decreases. In addition, the response speed is more likely to decrease when the substrate specific resistance is higher than when the substrate specific resistance is low.
[0012]
The present invention has been made to solve such problems of the prior art, and in a light receiving element used for a write-capable optical pickup or the like, when a small amount of light is incident on a photodiode and writing is performed. It is an object of the present invention to provide a light receiving element and a circuit built-in type light receiving element that can increase the response speed when a large amount of light is incident.
[0013]
[Means for Solving the Problems]
The light receiving element of the present invention includes a first conductive semiconductor substrate, a first conductive semiconductor layer formed on the first conductive semiconductor substrate and having an impurity concentration lower than that of the first conductive semiconductor substrate, A second conductivity type semiconductor layer formed on the one conductivity type semiconductor layer; and the second conductivity type semiconductor formed to reach the surface of the first conductivity type semiconductor layer from the surface of the second conductivity type semiconductor layer. A first conductivity type diffusion layer that divides the layer into a plurality of second conductivity type semiconductor regions, and detects signal light by joining the second conductivity type semiconductor region and the first conductivity type semiconductor layer below the second conductivity type semiconductor region. A light receiving element having a plurality of photodiode portions, and an average electric field strength of a depletion layer formed in the first conductivity type semiconductor layer when a reverse bias voltage is applied to the photodiode portion is 0.3 V / Μm or more so that the first conductivity type semiconductor layer Layer thickness 13μm to 17μm And resistivity is 100Ωcm to 1500Ωcm Therefore, the above-mentioned purpose is achieved.
[0016]
The specific resistance of the first conductive type semiconductor substrate is preferably 1 Ωcm or more and 20 Ωcm or less.
[0017]
It is preferable that an electrode is provided on the back surface of the first conductivity type semiconductor substrate, and the electrode is electrically connected to an anode electrode provided on the surface side of the second conductivity type semiconductor layer.
[0018]
The light receiving element of the present invention includes a first conductive semiconductor substrate, a first first conductive semiconductor layer formed on the first conductive semiconductor substrate, and having a higher impurity concentration than the first conductive semiconductor substrate. A second first conductive type semiconductor layer formed on the first first conductive type semiconductor layer and having an impurity concentration lower than that of the first conductive type semiconductor substrate; and the second first conductive type semiconductor layer. A second conductive type semiconductor layer formed thereon, and formed so as to reach the surface of the second first conductive type semiconductor region from the surface of the second conductive type semiconductor layer; A first conductivity type diffusion layer that is divided into a plurality of second conductivity type semiconductor regions, and detects signal light by joining the second conductivity type semiconductor region and the second first conductivity type semiconductor layer below the second conductivity type semiconductor region A plurality of photodiode sections are configured, and a reverse bias voltage is applied to the photodiode sections. As pressurized above average electric field strength of the depletion layer formed in the second first-conductivity type semiconductor layer when the is 0.3V / [mu] m or more, the Second Layer thickness of the first conductivity type semiconductor layer Is 9 μm or more and 17 μm or less, and the specific resistance is 100 Ωcm or more and 1500 Ωcm or less. Therefore, the above-mentioned purpose is achieved.
[0021]
It is preferable that the impurity concentration of the first conductivity type semiconductor substrate is 1/100 or less of the peak impurity concentration of the first first conductivity type semiconductor layer.
[0022]
The first conductivity type semiconductor substrate is preferably formed by a CZ method and has a specific resistance of 20 Ωcm or more and 50 Ωcm or less.
[0023]
The peak impurity concentration of the first first conductivity type semiconductor layer is 1 × 10 ¹⁷ cm ^-3 The above is preferable.
[0024]
The first first conductivity type semiconductor layer is preferably formed by coating diffusion.
[0025]
In the region where the impurity concentration increases from the first conductivity type semiconductor substrate side to the surface in the first first conductivity type semiconductor layer, the impurity concentration is the first first conductivity type semiconductor layer. It is preferable that a portion which is 1/100 of the highest impurity concentration has a depth of 38 μm or less from the surface of the second conductivity type semiconductor layer.
[0026]
The light receiving element with a built-in circuit of the present invention is Said In the light receiving element, in a region different from the photodiode portion of the second conductivity type semiconductor layer, By the photodiode part A signal processing circuit unit for processing the detected signal is provided, thereby achieving the above object.
[0027]
The first conductivity type semiconductor layer or the second first conductivity type semiconductor layer is formed on at least a part of a portion of the first conductivity type semiconductor layer or the second first conductivity type semiconductor layer different from the photodiode portion. It is preferable to have the 1st conductivity type high concentration diffusion layer formed from the surface of this.
[0028]
The operation of the present invention will be described below.
[0029]
In the present invention, by using the laminated substrate in which the first conductivity type semiconductor layer having a lower impurity concentration is formed on the first conductivity type semiconductor substrate, the capacitance and anode resistance of the photodiode are reduced, Improves response speed with a small amount of light during reading. Furthermore, even if a large amount of light at the time of writing is incident, the depletion layer width is limited by reducing the layer thickness of the first conductivity type semiconductor layer so that the response speed does not decrease due to flattening of the potential as in the prior art, Increase the electric field strength in the depletion layer. Here, the required electric field strength in the depletion layer is set to 0.3 V / μm or more from the response speed at the time of a large light amount required for the photodiode for writing (for example, writing 6 times speed).
[0030]
Furthermore, the required depletion layer width is set to 5 μm or more from the response speed at the time of small light quantity required for the photodiode for writing (for example, 32 times reading speed).
[0031]
In order to satisfy these settings, it is preferable that the thickness of the first conductivity type semiconductor layer is 13 μm or more and 17 μm or less and the specific resistance is 100 Ωcm or more and 1500 Ωcm or less. This thickness includes the thickness of the auto-dope layer.
[0032]
Further, in order to reduce the anode resistance and increase the speed of the photodiode, it is preferable to make the substrate specific resistance as low as possible. However, if the substrate specific resistance is too low, impurity auto-doping from the substrate to the first conductivity type semiconductor layer occurs in the crystal growth process of the second conductivity type semiconductor layer, thereby reducing the response speed. If the specific resistance of the first conductivity type semiconductor substrate is set to 1 Ωcm or more and 20 Ωcm or less, it is possible to suppress the influence of such auto-doping to a negligible level.
[0033]
Furthermore, if an anode electrode is provided on the back surface of the substrate and is electrically connected to the anode electrode provided on the separation diffusion region on the front surface side, the anode resistance is further increased compared to the case where the anode electrode is provided only on the front surface side. Can be lowered.
[0034]
In another aspect of the present invention, a laminated substrate in which a first conductivity type semiconductor layer (first first conductivity type semiconductor layer) having a higher impurity concentration is formed on a first conductivity type semiconductor substrate. , First A first conductivity type semiconductor layer (second first conductivity type semiconductor layer) having an impurity concentration lower than that of the conductivity type semiconductor layer is provided. When viewed from the substrate side, the high-concentration first first conductivity type semiconductor layer acts as a potential barrier, so that the carriers generated on the substrate side beyond the first first conductivity type semiconductor layer exceed the PN junction. Cannot be reached and disappears by recombination within the substrate. Therefore, it is possible to cut a slow current component due to carriers generated in the substrate, and to increase the response speed. Furthermore, since the concentration difference between the first first conductivity type semiconductor layer and the second first conductivity type semiconductor layer becomes large, the built-in electric field is strengthened, and the response speed is improved.
[0035]
Furthermore, it is preferable to set the required electric field strength in the depletion layer to 0.3 V / μm or more from the response speed (for example, 12 times writing speed) required for a photodiode for writing.
[0036]
Furthermore, the layer thickness of the second first-conductivity-type-semiconductor layer is 9 μm or more and 17 μm or less, and the specific resistance is 100 Ωcm, from the response speed (for example, 12 times writing speed) required for a photodiode for writing. The above is preferably 1500 Ωcm or less. Moreover, it is preferable that the depletion layer width is 3 μm or more from the response speed at the time of reading with a small amount of light.
[0037]
Furthermore, if the impurity concentration of the first conductivity type semiconductor substrate is set to 1/100 or less of the peak impurity concentration of the first first conductivity type semiconductor layer, the substrate is larger than the first first conductivity type semiconductor layer when the amount of light is large. It is possible to sufficiently reduce the rate at which carriers generated on the side reach the PN junction.
[0038]
Furthermore, it is preferable that the first conductivity type semiconductor substrate is formed by a CZ method in which defects are hardly formed. Then, by setting the substrate specific resistance to the highest specific resistance that can be created by the CZ method, for example, from 20 Ωcm to 50 Ωcm, the potential barrier on the substrate side in the first first conductivity type semiconductor layer can be increased. Therefore, the rate at which the carrier generated in the substrate exceeds the potential barrier can be made sufficiently small to increase the response speed.
[0039]
Further, the peak impurity concentration of the first first conductivity type semiconductor layer is set to 1 × 10. ¹⁷ cm ^-3 As described above, it is preferable to have a sufficiently high impurity concentration (100 times or more) with respect to the substrate.
[0040]
Furthermore, it is preferable that the first first conductivity type semiconductor layer is formed by coating diffusion in which defects are hardly formed.
[0041]
Further, in the region where the impurities are rising from the substrate side toward the surface in the first first conductivity type semiconductor layer, the portion whose impurity concentration is 1 / 100th of the highest impurity concentration is from the surface. Setting the depth to 38 μm or less is effective for improving the response speed.
[0042]
In the light receiving element with a built-in circuit according to the present invention, a signal processing circuit unit for processing a detected signal is provided in a region of the second conductive type semiconductor layer separated from the photodiode unit by the first conductive type diffusion layer. Therefore, the pickup system can be downsized.
[0043]
Furthermore, the first conductive type semiconductor layer or the first first conductive type semiconductor layer formed from the surface of the first conductive type semiconductor layer below the P type isolation diffusion layer connected to the anode electrode around the photodiode and the signal processing circuit unit. If a conductive type high-concentration diffusion layer is provided, it is possible to set the required low anode resistance from the response speed at the time of a large light amount required for the write-corresponding photodiode. Furthermore, it is possible to prevent latch-up of the circuit.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0045]
As described above, when the conventional photodiode having the structure shown in FIGS. 1 and 3 is used as a writing photodiode, there is a problem that the response speed is lowered when a large amount of light is incident.
[0046]
The inventors of the present invention used device simulation to analyze changes in carrier concentration and potential with time when a large amount of light is incident. As a result, a large amount of carriers generated when a large amount of light is incident accumulates near the junction, which flattens the potential and weakens the force that pushes the carrier to the junction. It turns out that it falls. FIG. 5 and FIG. 6 show the results of simulating the temporal change of the potential in the photodiode when a small amount of light corresponding to reading and a large amount of light corresponding to writing six times are incident on the photodiode. In addition, FIG. 7 shows the result of simulating the change in carrier density over time during irradiation with a large amount of light. The simulations of FIGS. 5 to 7 were performed on the structure of FIG.
[0047]
As shown in FIG. 5, no potential change occurs near the junction when a small amount of light is incident. On the other hand, when a large amount of light is incident, as shown in FIG. 6, the substrate potential rises with time after the light is incident. Further, FIG. 7 shows that carriers are accumulated from the vicinity of the PN junction to the substrate when a large amount of light is incident. This is because a large amount of optical carriers are generated in the depletion layer and the substrate when a large amount of light is incident, thereby raising the substrate potential. Then, since the electric field strength is weakened in the vicinity of the junction, the force that pushes carriers is weakened, and carriers are further accumulated to raise the substrate potential. By repeating this, the potential in the vicinity of the junction is flattened, and carriers move by diffusion over a long distance, resulting in a decrease in response speed.
[0048]
In the following, the reason why the present inventors have analyzed the cause of the accumulation of carriers in this way and explained how the present invention was achieved will be described.
[0049]
From FIG. 4 described above, it can be seen that the lower the substrate specific resistance, the smaller the rate of decrease in response speed when the amount of light is large. Since the applied reverse bias voltage is the same, the smaller the substrate specific resistance, the narrower the depletion layer width and the stronger the electric field strength applied in the depletion layer. As the electric field strength increases, the force that pushes the carriers in the vicinity of the junction also increases, and carriers are less likely to accumulate. Therefore, it can be considered that the lower the substrate specific resistance, the faster the response speed when the amount of light is large, although the depletion layer width is narrow.
[0050]
Therefore, in order to investigate the influence of the electric field strength in the depletion layer on the response speed of the photodiode when a large amount of light (350 μW) is incident, a device simulation was performed. This simulation was performed using the structure as shown in FIG. 8A and the impurity concentration profile as shown in FIG. 8B (the bb ′ line portion in FIG. 8A). This photodiode has a structure in which a P-type high resistance layer 182 is formed on a P-type low resistance substrate 181 and an N-type semiconductor layer 183 is stacked thereon. The N-type semiconductor layer 183 is divided into a plurality of regions by P-type diffusion layers 184 and 185. As shown in FIG. 8B, the impurity profile of this photodiode is such that the depletion layer is formed between the substrate and the P-type because the concentration change of the P-type low-resistance substrate 181 and the P-type high-resistance layer 182 is stepped. It extends to the interface with the high resistance layer 182. Further, since the substrate specific resistance is sufficiently low, the influence of the anode resistance can be ignored.
[0051]
The response when the photodiode was irradiated with a large amount of pulsed light was obtained by simulation, and the applied reverse bias voltage was changed to examine the dependence of the response speed on the electric field strength. FIG. 9 shows the result of determining the dependence of the response time tf (90% → 10%) on the electric field strength by simulation. Note that tf (90% → 10%) is the time from when the photodiode is irradiated with pulsed light until the photocurrent decreases from 90% of the maximum value to 10%. As shown in FIG. 9, the response speed of the photodiode is slowed by the weakening of the electric field strength in the depletion layer.
[0052]
Further, in order to investigate the cause of the decrease in response speed, FIG. 10 shows the results of examining the time change after irradiation with pulsed light having a pulse width of 10 μsec for the carrier density distribution in the depth direction in the photodiode. FIG. 10A shows a case where the electric field strength in the depletion layer is 0.16 V / μm, and FIG. 10B shows a case where the electric field strength in the depletion layer is 0.4 V / μm. As shown in FIG. 10A, when the electric field strength in the depletion layer is weak, a large amount of carriers accumulates in the vicinity of the junction (depth of about 2 μm) immediately after the pulse light irradiation, for example, in the very vicinity of the junction. ¹² cm ^-3 Have accumulated careers. It can be seen that the response time of the photodiode is lowered because the time taken for the accumulated carriers to be swept to the N-type semiconductor layer side is as slow as 10 ns or more. On the other hand, as shown in FIG. 10B, when the electric field strength in the depletion layer is strong, the carrier concentration in the vicinity of the depletion layer hardly changes, and no carrier accumulation occurs.
[0053]
In addition, FIG. 11A and FIG. 11B show electric field intensity distributions when light is not irradiated and immediately after irradiation with pulsed light having a pulse width of 10 μsec. As shown in FIG. 11A, when the electric field strength in the depletion layer is 0.16 V / μm and carrier accumulation occurs, the electric field strength near the junction is further weakened by the carrier accumulation. Thereby, it can be seen that the force for sweeping the accumulated carriers to the N-type semiconductor layer side is weakened, and the response speed becomes very slow. On the other hand, as shown in FIG. 11B, when the electric field strength in the depletion layer is 0.4 V / μm and no carrier accumulation occurs, the electric field strength in the depletion layer is the same as that at the time of light irradiation. There is almost no change when light is not irradiated.
[0054]
From the above, it has been found that the reason why the response speed decreases during irradiation with a large amount of light (writing) is that carriers accumulate near the junction and can be improved by increasing the electric field strength in the depletion layer.
[0055]
However, in an actual photodiode, if the applied reverse bias voltage is increased in order to increase the electric field strength in the depletion layer, noise due to fluctuations in the applied voltage also increases, so that the applied voltage cannot be changed greatly. Further, since the power supply is shared with the LSI in the device, the applied voltage cannot be changed greatly. Therefore, in the conventionally known photodiode having the structure shown in FIG. 3, by reducing the thickness of the P-type epitaxial layer (P-type high-resistance crystal growth layer) 142, the width of the depletion layer is limited, and the electric field strength in the depletion layer is reduced. Can be strengthened.
[0056]
In the structure of FIG. 3, the results of measuring the response when a large amount of light and a small amount of light are irradiated are shown in Table 1 below for a photodiode actually manufactured by changing the layer thickness of the P-type epitaxial layer 142. At the same time, the depletion layer width at each layer thickness and the electric field strength in the depletion layer are also shown.
[0057]
[Table 1]

[0058]
Since the P-type epitaxial layer 142 includes a region where the impurity concentration changes (auto-doped layer 142a), as shown in Table 1, the depletion layer width is thinner than the P-type epitaxial layer 142 width. Become.
[0059]
Moreover, the relationship between the response speed at the time of a large light quantity and the electric field strength in the depletion layer by this measurement is shown as an actual measurement value in FIG. As shown in FIG. 9, the response speed increases as the electric field strength in the depletion layer increases, and the dependence is consistent with the simulation results. Therefore, the response speed when a large amount of light is irradiated is roughly determined by the electric field strength in the depletion layer, and hardly depends on the width of the depletion layer. As can be seen from FIG. 10 (a) showing the carrier distribution when the response speed is lowered in the simulation, the carrier accumulation occurs near the junction (the depth is about 2 μm. This is also explained from the fact that it is considered to be largely dependent on the electric field strength in the vicinity of the junction.
[0060]
On the other hand, as shown in Table 1 above, when the depletion layer width is narrowed, the response speed when a small amount of light is irradiated decreases. This is because the capacitance component increases due to the narrowing of the depletion layer, and the distance traveled by diffusion of carriers generated below the depletion layer increases.
[0061]
As described above, in the photodiode having the structure shown in FIG. 3, the response speed under a large amount of light can be improved by reducing the thickness of the P-type epitaxial layer 142 and increasing the electric field strength in the depletion layer. However, if the P-type epitaxial layer 142 is made too thin, the response speed at the time of small light quantity decreases, so from the viewpoint of both the response speed required when irradiating a large light quantity at the time of writing and a small light quantity at the time of reading. ,Optimal Layer thickness Need to be set.
[0062]
(Embodiment 1)
FIG. 3 is a cross-sectional view showing the structure of the light receiving element of this embodiment.
[0063]
The light receiving element of this embodiment and the conventional light receiving element having the structure shown in FIG. 3 can be manufactured by the same method. The main difference is that the P-type epitaxial layer (high resistance crystal growth layer) 142 is different. Layer thickness And resistivity. In the present embodiment, the P-type epitaxial layer 142 is Layer thickness And the specific resistance is set so as to satisfy the following equation.
[0064]
Ed> 0.3V / μm
However, Ed is an average electric field strength generated in the depletion layer 160 when an operating reverse bias voltage is applied to the photodiode.
[0065]
The reason for setting the electric field strength in the depletion layer is as follows. By increasing the electric field strength in the depletion layer, the force to push the optical carriers existing near the junction is increased, and the response speed drop due to the accumulation of carriers is suppressed when a large amount of light is incident on the photodiode. Can do. Currently, as a performance of a write-capable CD pickup, 6 × speed writing is required. According to FIG. 9 described above, by setting the electric field strength in the depletion layer to 0.3 V / μm or more, it is possible to realize a response speed required for 6 × speed writing.
[0066]
Furthermore, the response speed at the time of reading as well as at the time of writing is important for the photodiode corresponding to writing, and the performance of 32-times speed reading is required. FIG. 12 shows the relationship between the depletion layer width estimated from the experimental data in Table 1 above and the response speed when the amount of light is small. Here, in order to obtain a response speed of 32 times speed, the response frequency needs to be 23 MHz or more, and in order to satisfy this, the 1 dB drop frequency of the photodiode needs to be 15 MHz or more. According to FIG. 12, by setting the depletion layer width to 5 μm or more, it is possible to realize the response speed required for 32-times speed reading.
[0067]
In order to sufficiently satisfy the response speed required at the time of writing and reading, the electric field strength in the depletion layer is set to 0.3 V / μm or more and the depletion layer width is set to 5 μm or more. Of the epitaxial layer 142 Layer thickness Is preferably 13 μm or more and 17 μm or less, and the specific resistance is preferably 100 Ωcm or more and 1500 Ωcm or less. In addition, this Layer thickness The range of specific resistance is determined from the experimental data of the present inventors.
[0068]
Further, the impurity concentration of the P-type semiconductor substrate 141 is 10% of the impurity concentration on the surface of the P-type epitaxial layer 142. ^Three It is preferable that the concentration does not exceed twice. This is because, in the process up to the formation of the N-type epitaxial layer, impurities in the substrate escape and adhere to the surface of the P-type epitaxial layer 142 (layer 142b having a constant impurity concentration) formed on the surface. This is to prevent the layer from being formed. For example, when the P-type epitaxial layer 142 having a high specific resistance of 1 kΩ is formed, the impurity concentration of the P-type semiconductor substrate 141 is about 1 Ωcm. This is because a relationship of approximately 1: 1000 is established between the impurity concentration of the auto-doped layer formed on the surface of the P-type epitaxial layer 142 and the impurity concentration of the P-type semiconductor substrate 141. Therefore, if the impurity concentration of the P-type semiconductor substrate 141 is set to a concentration that does not exceed 1000 times the set value of the impurity concentration on the surface of the P-type epitaxial layer 142, even if auto-doping of impurities occurs, the result is obtained. The impurity concentration on the surface of the P-type epitaxial layer to be formed does not exceed a predetermined set value. In order to reduce the anode resistance, it is desirable that the substrate specific resistance is as low as possible without causing autodoping. For example, if the lower limit of the substrate specific resistance is 1 Ωcm, it is desirable that the upper limit of the substrate specific resistance is 20 Ωcm or less in order to stably mass-produce the light receiving element.
[0069]
Furthermore, if an anode electrode is provided on the back surface of the substrate and is electrically connected to the anode electrode provided on the separation diffusion region on the front surface side, the anode resistance is further increased compared to the case where the anode electrode is provided only on the front surface side. The response speed can be improved by lowering.
[0070]
(Embodiment 2)
FIG. 13 is a cross-sectional view showing the structure of the light receiving element of this embodiment. In this figure, the anode electrode, cathode electrode, wiring, protective film and the like are omitted.
[0071]
In this light receiving element, as shown in FIG. 13A, a P-type buried diffusion layer 109, a P-type epitaxial layer 104, and an N-type epitaxial layer 110 are formed on a P-type semiconductor substrate 103. The N-type epitaxial layer 110 is divided into a plurality of regions by a P-type isolation diffusion layer 107 and a P-type isolation buried diffusion layer 108, and a photodiode is formed by joining each division region and the P-type epitaxial layer 104 therebelow. Yes. As shown in FIG. 13B, which shows the impurity profile of the cc ′ line portion of FIG. 13A, the P-type epitaxial layer 104 is an auto-doped layer (yes (Rising layer) 104a and a layer 104b having a constant specific resistance.
[0072]
A significant difference between this light receiving element and the light receiving element of the first embodiment is that a P type buried diffusion layer 109 is provided between the P type semiconductor substrate 103 and the p type epitaxial layer 104. In manufacturing the light receiving element, boron is diffused on the P-type semiconductor substrate 103 to form a P-type buried diffusion layer 109, and a P-type epitaxial layer is formed thereon by crystal growth. Thereafter, it can be carried out in the same manner as in the prior art.
[0073]
In the light receiving element of the first embodiment, the P-type epitaxial layer Layer thickness Even if the specific resistance is optimized, the obtained performance is up to about 6 × writing speed and 32 × reading speed. This is because the capacitance component increases by narrowing the width of the depletion layer in order to increase the electric field strength in the depletion layer, and the distance that carriers generated in a relatively deep position of the substrate move by diffusion increases. by. This is also a factor that regulates the response speed at the time of writing as well as at the time of reading.
[0074]
Therefore, in this embodiment, the P-type buried diffusion layer 109 is formed between the P-type semiconductor substrate 103 and the P-type epitaxial layer 104, so that the P-type buried with respect to carriers generated at a relatively deep position of the substrate. It was studied to improve the response speed by causing the diffusion layer 109 to act as a potential barrier.
[0075]
First, how the buried diffusion layer 109 functions was examined by device simulation. For the three structures shown in FIGS. 14A, 14B, and 14C, the concentration profile of the photodiode portion is 1% response time to 780 nm, 300 μW pulsed light. (Time until the photocurrent is changed from 90% to 1%) tf (90% → 1%) is shown in Table 2 below. In Table 2, the buried layer width means that the concentration on the surface side is 10 from the position of the peak impurity concentration of the P-type buried diffusion layer 109. ¹⁴ cm ^-3 Is the width to the position.
[0076]
[Table 2]

[0077]
Here, the response time of 1% is determined by carriers moving from the substrate by diffusion. In the profiles (a) and (b), the P-type semiconductor substrate 103, the P-type buried diffusion layer 109, and the P-type epitaxial layer 104 have the same impurity concentration, but only the width of the P-type buried diffusion layer 109 is different.
[0078]
In the structures of the profiles (a) and (b), since the response speed is greatly improved in (b), the width of the P-type buried diffusion layer 109 is wide, and the potential generated by the P-type buried diffusion layer 109 is large. It can be seen that the effect of improving the response speed cannot be obtained when the barrier does not have a large gradient.
[0079]
In the structures of profiles (b) and (c), the profiles other than the concentration (specific resistance) of the P-type semiconductor substrate 103 are all the same. From (b) and (c), it can be seen that the response speed varies greatly depending on the concentration of the P-type semiconductor substrate 103.
[0080]
Here, FIG. 15A shows the electron concentration distribution at 2 nsec after irradiation with pulse light having a pulse width of 10 μsec with respect to the structure of profile (c), and FIG. 15B shows the structure of profile (b). The electron concentration distribution at 2 nsec after irradiation with pulse light having a pulse width of 10 μsec is shown. This figure is a diagram showing a cross section of the photodiode portion, and shows that the higher the dot density, the higher the electron concentration. Further, the solid line in the figure indicates the concentration peak of the P-type buried diffusion layer 109. The reason why the electron concentration near the entire surface is high is that an N-type high concentration injection layer is provided in order to reduce the cathode resistance.
[0081]
As shown in FIG. 15A, in the case of the profile (c) structure in which the substrate specific resistance is high and the potential barrier is sufficiently high, carriers at a position deeper than the P-type buried diffusion layer 109 are barriers. It can be seen that the carrier has accumulated. On the other hand, as shown in FIG. 15B, in the case of the structure of the profile (b) where the height of the potential barrier is not sufficient, carriers flow out to the surface side, and the P-type buried diffusion layer 109 It can be seen that it is also distributed near the peak concentration. Therefore, the reason why the response speed is lowered in the structure of the profile (b) is that carriers generated on the substrate side of the P-type buried diffusion layer 109 contribute to the slow current component beyond the potential barrier.
[0082]
As described above, in the light receiving element provided with the P-type buried diffusion layer 109 shown in FIG. 13, the P-type buried diffusion layer 109 functions as a potential barrier for carriers generated on the substrate side. For this reason, carriers generated on the substrate side with respect to the P-type buried diffusion layer 109 cannot move to the surface side beyond the potential barrier, and recombine and disappear in the substrate. The carriers generated in the region between the concentration peak portion of the P-type buried diffusion layer 109 and the depletion layer 106 are accelerated by the built-in electric field due to the large concentration gradient of the P-type buried diffusion layer 109, and are faster than in the case of diffusion. Move to the edge of the depletion layer. For these reasons, the response speed at the time of writing and reading of the write-enabled photodiode can be increased. This speed-up effect is further improved when the P-type buried diffusion layer 109 has a sufficient concentration difference and gradient with respect to the P-type semiconductor substrate 103.
[0083]
Next, the P-type epitaxial layer 104 Layer thickness A simulation was performed on a profile in which the width of the depletion layer 106 was changed by changing. In contrast to the structure in which the concentration profile of the photodiode portion is as shown in FIG. Layer thickness Table 3 below shows the response time (time from 90% to 10% of the photocurrent) tf (90% → 10%) when 350 μw of light irradiation was performed while changing.
[0084]
[Table 3]

[0085]
FIG. 16A shows the P-type epitaxial layer 104. Layer thickness Is an electron concentration distribution in the photodiode portion when irradiated with pulsed light having a pulse width of 10 μsec with respect to a structure in which the electric field intensity in the depletion layer 106 is 0.42 V / μm with a thickness of 15 μm, Of the epitaxial layer 104 Layer thickness The electron concentration distribution of the photodiode portion when irradiated with pulsed light having a pulse width of 10 μsec is shown for a structure in which the electric field intensity in the depletion layer 106 is 0.21 V / μm with a thickness of 20 μm. This figure is a diagram showing a cross section of the photodiode portion, and shows that the higher the dot density, the higher the electron concentration. Further, the solid line in the figure indicates the concentration peak of the P-type buried diffusion layer 109. The reason why the electron concentration near the entire surface is high is that an N-type high concentration injection layer is provided in order to reduce the cathode resistance.
[0086]
As you can see from this figure, Layer thickness Is 20 μm, carriers accumulate near the depletion layer 106. Therefore, when the P-type epitaxial layer becomes thick, the depletion layer expands, and the electric field strength in the depletion layer is weakened, so that charge accumulation occurs, leading to a decrease in response speed.
[0087]
FIG. 17 shows the relationship between the electric field intensity in the depletion layer 106 and 10% response time (time until the cathode current reaches 10%) tf (0% → 90%) with respect to 780 nm, 300 μW pulsed light. . As can be seen from this figure, in this embodiment, the P-type epitaxial layer 104 Layer thickness And by setting the specific resistance so as to satisfy the following formula, it is possible to realize the 12 × speed writing performance (tf of 4 ns or less) required for the next writing photodiode.
[0088]
Ed> 0.3V / μm
However, Ed is an average electric field strength generated in the depletion layer 106 when an operating reverse bias voltage is applied to the photodiode. This is because, as shown in the simulation results, by increasing the electric field strength in the depletion layer, the force to flow optical carriers existing near the junction is increased, and when a large amount of light is incident on the photodiode, This is because a decrease in response speed due to accumulation can be suppressed.
[0089]
In order to realize the above-described performance during writing, the electric field strength in the depletion layer is set to 0.3 V / μm or more, and in order to suppress the increase in the capacitance of the photodiode, the P-type epitaxial layer 104 Layer thickness Is preferably 9 μm to 17 μm, and the specific resistance is preferably 100 Ωcm to 1500 Ωcm. Note that this epitaxial layer Layer thickness This range is determined from the simulation data of Table 3, and the specific resistance range is also determined from the simulation results of the present inventors. Also, the epitaxial layer Layer thickness The lower limit of 9 μm is that the junction concentration of the N-type epitaxial layer 110 and the P-type epitaxial layer 104 becomes higher due to the influence of the auto-doped layer 104a when the epitaxial layer thickness is thinner than 9 μm from FIG. This is because the junction capacity increases and the response speed decreases.
[0090]
Furthermore, in this embodiment, in order to make the P-type buried diffusion layer 109 sufficiently function as a potential barrier, the peak impurity concentration of the P-type buried diffusion layer 109 is set to 100 times or more the impurity concentration of the P-type semiconductor substrate 103. Is preferred. The reason is as follows.
[0091]
When the P-type buried diffusion layer 109 does not have a sufficient diffusion potential with respect to the P-type semiconductor substrate 103, carriers generated on the substrate side of the P-type buried diffusion layer 109 are caused by thermal energy to cause the P-type buried diffusion layer 109. Exceeds the threshold and reaches the PN junction, which causes a reduction in response speed. Since the thermal energy at the operating temperature of about 10 ° C. to 100 ° C. is 0.03 eV to 0.04 eV, it is necessary to have a diffusion potential sufficiently higher than this. In order to suppress the flow of carriers generated on the substrate side to the surface side, the P-type buried diffusion layer 109 is formed on the P-type semiconductor substrate 103 in order to reduce the carrier exceeding the P-type buried diffusion layer 109 to 10% or less. On the other hand, it is necessary to have a potential of 0.1 V or more. This is because the probability p that electrons having thermal energy of Ee (eV) get over the potential barrier of Eb (eV)
p = Exp (-Eb / Ee)
Because
p = Exp (−Eb / 0.04) <0.1
Eb> −0.04 × log (0.1) = 0.1
Because it becomes.
[0092]
Here, the relationship between the impurity concentration and the diffusion potential is shown in FIG. As can be seen from FIG. 18, in order to give a potential difference of 0.1 V or more between the P-type buried diffusion layer 109 and the P-type semiconductor substrate 103, the peak impurity concentration of the P-type buried diffusion layer 109 is changed to P-type. It is necessary to set the impurity concentration of the semiconductor substrate 103 to 100 times or more. That is, by setting the peak impurity concentration of the P-type buried diffusion layer 109 to 100 times or more the impurity concentration of the P-type semiconductor substrate 103, the response speed is lowered due to carriers generated on the substrate side of the P-type buried diffusion layer 109. Can be improved.
[0093]
Furthermore, the greater the difference between the impurity concentration of the P-type semiconductor substrate 103 and the peak impurity concentration of the P-type buried diffusion layer 109, the higher the effect as a potential barrier. Here, in order to reduce the impurity concentration of the substrate, a substrate manufactured by the FZ (Float Zone) method is more advantageous. However, in this case, the wafer strength is weak and there is a possibility that the yield decreases due to defects. On the other hand, in the case of a substrate manufactured by a CZ (Czochralski) method, yield reduction due to defects can be prevented, which is preferable. Since the highest substrate specific resistance that can be produced by the CZ method is 50 Ωcm, it is preferable to use a CZ substrate having a specific resistance of 20 Ωcm to 50 Ωcm. This is because if the upper limit of the specific resistance is 50 Ωcm, the lower limit is 20 Ωcm for stable mass production of the light receiving elements.
[0094]
In order to give a sufficiently high impurity concentration (100 times or more) to the P-type semiconductor substrate 103, the peak impurity concentration of the P-type buried diffusion layer 109 is set to 1 × 10. ¹⁷ cm ^-3 It is preferable to make it above.
[0095]
Furthermore, the P-type buried diffusion layer 109 is Layer thickness From the viewpoint of controllability of the specific resistance, it is advantageous to form by ion implantation. But 1x10 ¹⁷ cm ^-3 When such a high concentration of ions is implanted, the yield may be reduced due to defects. In order to prevent a decrease in yield due to such defects, it is preferable to form the P-type buried diffusion layer 109 by coating diffusion.
[0096]
Furthermore, in order to improve the response time of 1% with respect to the pulsed light, it is preferable to set the concentration profile of the P-type buried diffusion layer 109 as follows.
[0097]
Xu <38μm
However, Xu is the thickness from the surface of the photodiode to the position on the substrate side of the P-type buried diffusion layer 109 where the concentration is 1/100 of the peak impurity concentration of the P-type buried diffusion layer 109. This is because, if the potential barrier is not formed in a portion shallower than the portion where the light is incident and absorbed and becomes less than 1%, carriers with slow response cannot be sufficiently erased, and the response speed is improved. This is because a sufficient effect cannot be obtained. Here, the depth at which light having a wavelength of 780 nm used for the CD-ROM is incident on Si and becomes 1% is 38 μm. Therefore, from the surface of the photodiode, the depth of P on the substrate side of the P-type buried diffusion layer 109 is increased. It is preferable to set the thickness of the mold buried diffusion layer 109 to a position where the concentration is 1/100 of the peak impurity concentration to 38 μm or less.
[0098]
In the light receiving element of the second embodiment as well, the photodiode portion is separated by the P-type isolation diffusion layer 107 and the P-type isolation buried diffusion layer 108 on the same substrate, similarly to the structure of the first embodiment shown in FIG. By forming a signal processing circuit in the region of the N-type epitaxial layer thus formed as a light receiving element with a built-in circuit, the pickup system can be downsized and the cost can be reduced.
[0099]
Further, in such a circuit built-in light receiving element, it is preferable to form the P type buried diffusion layer 4 from the surface of the P type epitaxial layer 30 in a part other than the photodiode portion as shown in FIG. As a result, the lower resistance of the P-type isolation buried diffusion layer 7 can be lowered to lower the anode resistance, and the speed of the photodiode can be increased. Further, latch-up can be prevented by lowering the substrate resistance of the circuit portion. In FIG. 19, 1 is a P-type semiconductor substrate, 30 is a P-type high-resistance epitaxial layer, 2 is a layer with a constant specific resistance, and 3 is an auto-doped layer. 5 is a depletion layer, 6 is an N-type collector region, 8 is an N-type epitaxial layer, 9 is a P-type isolation diffusion layer, 10 is an N-type collector contact region, 11 is a P-type base region, and 12 is an N-type emitter region. , 14 is a cover film, 15 is a cathode contact, 16 is an anode contact, 17 is a transistor contact, 22 is a cathode contact region, 80 is a photodiode forming portion, and 90 is a circuit forming portion.
[0100]
In the above embodiment, the P type is the first conductivity type and the N type is the second conductivity type. However, the N type may be the first conductivity type and the P type may be the second conductivity type.
[0101]
【The invention's effect】
As described above in detail, according to the present invention, a multilayer substrate having a first conductivity type semiconductor layer having an impurity concentration lower than that on a first conductivity type semiconductor substrate is used, and a photodiode is formed thereon. In the structure, the first conductive type semiconductor layer Layer thickness Further, by adjusting the specific resistance and reducing the width of the depletion layer, the electric field strength in the depletion layer can be increased without changing the bias voltage applied to the photodiode. As a result, the force that pushes carriers by the electric field in the vicinity of the junction becomes strong, and it is possible to prevent a decrease in response speed due to the accumulation of carriers when the amount of light is large.
[0102]
However, when the width of the depletion layer is narrowed, the capacity component increases and the distance traveled by the carriers generated below the depletion layer becomes longer, which may reduce the response speed when the light quantity is small. Therefore, in order to satisfy the response speed required for both the small light amount at the time of reading and the large light amount at the time of writing, Layer thickness And the specific resistance can be adjusted to achieve the desired specifications.
[0103]
According to the present invention, the second first conductive semiconductor layer having a high impurity concentration is provided between the first conductive semiconductor substrate and the second first conductive semiconductor layer having a lower impurity concentration. By providing the second conductive semiconductor layer, the second conductive semiconductor layer can function as a potential barrier against carriers generated on the substrate side. Therefore, it is possible to remove a slow current component that travels a long distance by diffusion. In addition, since the carriers generated on the surface side of the second impurity region of the first conductivity type semiconductor layer are accelerated by the built-in electric field of the second conductivity type semiconductor layer, the carriers are quickly reached to the end of the depletion layer. Arrive. Therefore, the response speed can be further improved.
[0104]
As described above, according to the present invention, the write-enabled photodiode overcomes the decrease in the response speed due to the accumulation of carriers when a large amount of light for writing is incident. Therefore, a light receiving element and a circuit built-in type light receiving element capable of simultaneously improving the response speed when a large amount of light is incident are provided.
[Brief description of the drawings]
1A and 1B are diagrams showing a configuration of a conventional light receiving element, in which FIG. 1A shows a cross-sectional structure thereof, and FIG. 1B shows an impurity concentration at a line aa ′ in FIG.
FIG. 2 is a diagram showing the relationship between substrate resistivity and response speed (cut-off frequency) in a conventional light receiving element.
3 is a view showing a cross-sectional structure of the first embodiment and a conventional light receiving element;
4 is a diagram showing a result of an experiment on the dependence of the response speed (cutoff frequency) of a photodiode on the amount of incident light with respect to the light receiving element having the structure of FIG. 1; FIG.
5 is a diagram showing a result of simulating a temporal change in potential distribution when a small amount of light is incident on a photodiode for the light receiving element having the structure of FIG. 1; FIG.
6 is a diagram illustrating a result of simulating a temporal change in potential distribution when a large amount of light is incident on a photodiode with respect to the light receiving element having the structure of FIG. 1;
7 is a diagram showing a result of simulating a change in carrier density distribution over time when a large amount of light is incident on a photodiode in the light receiving element having the structure of FIG. 1; FIG.
FIGS. 8A and 8B are diagrams showing a configuration of a photodiode used in the simulation, in which FIG. 8A shows the cross-sectional structure thereof, and FIG.
FIGS. 9A and 9B are diagrams showing the results of simulating and actually measuring the relationship between the electric field intensity in the depletion layer of the photodiode and the response speed for the light receiving element having the structure of FIG.
FIGS. 10A and 10B are diagrams showing temporal changes in the carrier density distribution of photodiodes in the light receiving element having the structure of FIG.
11A and 11B are diagrams showing the electric field intensity distribution of the photodiode when the light is not irradiated and when the light is incident on the light receiving element having the structure of FIG.
12 is a diagram showing the depletion layer width dependence of the response speed (cut-off frequency) when a small amount of light is incident on a photodiode in the light receiving element having the structure of FIG. 3;
FIGS. 13A and 13B are diagrams showing a configuration of a light receiving element according to the second embodiment, in which FIG. 13A shows the cross-sectional structure thereof, and FIG.
FIGS. 14A to 14C are diagrams showing impurity concentration distributions in the depth direction of the photodiodes used in the simulation for the light receiving element having the structure of FIG.
FIGS. 15A and 15B show the results of simulating the planar distribution of carriers at 2 nsec after irradiation with pulsed light having a pulse width of 10 μsec for the photodiodes having the impurity profiles of FIGS. 14C and 14B. FIGS. FIG.
FIGS. 16A and 16B are views of a P-type epitaxial layer. Layer thickness It is a figure which shows the result of having simulated the planar distribution of the carrier at the time of pulse light irradiation of 10 microseconds of pulse width about the photodiode which made 15 micrometers and 20 micrometers.
17 is a diagram showing the results of simulating the electric field strength and response speed in the depletion layer of the photodiode when a large amount of light is incident on the light receiving element having the structure of FIG.
FIG. 18 is a diagram showing a relationship between a diffusion potential generated by an impurity concentration gradient and an impurity concentration.
FIG. 19 is a diagram showing a configuration of a light receiving element with a built-in circuit according to an embodiment of the present invention.
[Explanation of symbols]
1, 84, 103, 141 P-type semiconductor substrate
2, 104b Layer with constant resistivity
3, 104a, 142a Auto dope layer
4 P-type buried diffusion layer
5, 86, 106, 160 Depletion layer
6 N-type collector region
7, 88, 108 P-type isolation buried diffusion layer
8, 85, 110, 143 N-type epitaxial layer
9, 87, 107, 144 P-type isolation diffusion layer
10 N-type collector contact region
11, 147 P-type base region
12, 148 N-type emitter region
14 Cover membrane
15 Cathode contact
16 Anode contact
17 Transistor contact
22 Cathode contact area
30, 104, 142 P-type epitaxial layer
80, 180 Photodiode formation part
90, 190 Circuit forming part
109 P-type buried diffusion layer
142b Layer with constant impurity concentration
145 N-type contact region
146 N-type buried region
149 Silicon oxide film
150a, 150b, 150c Electrode wiring layer

Claims (11)

A first conductivity type semiconductor substrate;
A first conductive semiconductor layer formed on the first conductive semiconductor substrate and having an impurity concentration lower than that of the first conductive semiconductor substrate;
A second conductivity type semiconductor layer formed on the first conductivity type semiconductor layer;
First conductivity type diffusion formed to reach the surface of the first conductivity type semiconductor layer from the surface of the second conductivity type semiconductor layer and dividing the second conductivity type semiconductor layer into a plurality of second conductivity type semiconductor regions With layers and
A light receiving element in which a plurality of photodiode portions for detecting signal light are configured by joining the second conductive type semiconductor region and the first conductive type semiconductor layer below the second conductive type semiconductor region;
The first conductive semiconductor layer so that an average electric field strength of a depletion layer formed in the first conductive semiconductor layer is 0.3 V / μm or more when a reverse bias voltage is applied to the photodiode portion. The light receiving element has a layer thickness of 13 μm to 17 μm and a specific resistance of 100 Ωcm to 1500 Ωcm . The light receiving element according to claim 1 , wherein a specific resistance of the first conductive type semiconductor substrate is 1 Ωcm or more and 20 Ωcm or less.   The electrode according to claim 1 or 2, wherein an electrode is provided on a back surface of the first conductive type semiconductor substrate, and the electrode is electrically connected to an anode electrode provided on the surface side of the second conductive type semiconductor layer. The light receiving element of description. A first conductivity type semiconductor substrate;
A first first conductive semiconductor layer formed on the first conductive semiconductor substrate and having an impurity concentration higher than that of the first conductive semiconductor substrate;
A second first conductive semiconductor layer formed on the first first conductive semiconductor layer and having an impurity concentration lower than that of the first conductive semiconductor substrate;
A second conductivity type semiconductor layer formed on the second first conductivity type semiconductor layer;
A first conductive layer is formed so as to reach the surface of the second first conductive semiconductor region from the surface of the second conductive semiconductor layer, and divides the second conductive semiconductor layer into a plurality of second conductive semiconductor regions. A conductive diffusion layer, and
A plurality of photodiode portions for detecting signal light are configured by joining the second conductivity type semiconductor region and the second first conductivity type semiconductor layer below the second conductivity type semiconductor region,
As the average electric field strength of a depletion layer formed in the second first-conductivity-type semiconductor layer upon application of the reverse bias voltage to the photodiode part becomes 0.3V / [mu] m or more, the second A light-receiving element in which the layer thickness of the first conductivity type semiconductor layer is set to 9 μm or more and 17 μm or less and the specific resistance is set to 100 Ωcm or more and 1500 Ωcm or less . The light receiving element according to claim 4 , wherein an impurity concentration of the first conductivity type semiconductor substrate is 1/100 or less of a peak impurity concentration of the first first conductivity type semiconductor layer. 6. The light receiving element according to claim 4, wherein the first conductivity type semiconductor substrate is formed by a CZ method and has a specific resistance of 20 Ωcm or more and 50 Ωcm or less. 7. The light receiving element according to claim 5, wherein a peak impurity concentration of the first first conductivity type semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or more. The light receiving element according to claim 4, wherein the first first conductivity type semiconductor layer is formed by coating diffusion. In the region where the impurity concentration increases from the first conductivity type semiconductor substrate side to the surface in the first first conductivity type semiconductor layer, the impurity concentration is the first first conductivity type semiconductor layer. 9. The light receiving element according to claim 5 , wherein a portion of the first impurity concentration which is 1 / 100th of the highest impurity concentration has a depth of 38 μm or less from the surface of the second conductivity type semiconductor layer. The light receiving element according to any one of claims 1 to 9, in a region different from the photodiode portion of the second conductive type semiconductor layer, the signal processing for processing the signal detected I by the said photodiode unit A light receiving element with a built-in circuit having a circuit portion. The first conductivity type semiconductor layer or the second first conductivity type semiconductor layer is formed on at least a part of a portion of the first conductivity type semiconductor layer or the second first conductivity type semiconductor layer different from the photodiode portion. The light receiving element with a built-in circuit according to claim 10 , further comprising a first conductivity type high concentration diffusion layer formed from the surface of the first conductive type.

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