JP3893317B2 - Serial transfer control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial transfer control method.
[0002]
[Prior art]
For example, in an audio device in which an amplifier, a tuner, a compact disc player, and the like are integrated, when a user performs an operation of switching to a tuner by a selector switch provided in the amplifier during playback of a compact disc, a mechanical switch mechanism is used. It is known that when switching is performed, noise is generated and the circuit is affected.
[0003]
Therefore, conventionally, the entire control including I / O switching of devices such as a compact disc player and a tuner is performed by a microcomputer, and specifically, it is often performed by a microcomputer control program shown below.
[0004]
1. Mute the volume on the output channel connected to the compact disc player.
2. Switch the output channel connected to the compact disc player to the tuner.
3. Unmute the volume on the output channel.
[0005]
The control procedure in these audio devices is carried out via a serial bus connecting the microcomputer and peripheral chips.
[0006]
In an IC chip including a conventional microcomputer and a peripheral chip, the chip address and the IC have a one-to-one correspondence, and similarly, one register and the subaddress and data byte related to the register have a one-to-one correspondence.
[0007]
In serial control using a conventional serial bus, if processing that should be nested (nested structure) such as “mute output volume mute → cancel mute” as in the previous example is executed, the data on the serial bus The transfer had to be performed at least twice.
[0008]
In other words, the above-mentioned example of “muting → switching → muting cancellation” is generalized.
[0009]
1. Register φ is set from 1 → 0 by data byte DBφ ・ ・ ・ Process 1
2. Register n + 1 is set from 0 to 1 by data byte DBδ... Processing 2
3. The setting of the register φ is returned from 0 → 1 by the data byte DBn + 1... Processing 1 ′
This is the case when processing like this is performed.
[0010]
The simplest possible data transfer case is
This is a three-time transfer in which processing 1, processing 2, and processing 1 ′ are sequentially performed.
[0011]
Alternatively, two transfers may be considered in which processing 1 and processing 2 are performed at the same time, and processing 1 + processing 2 and processing 1 ′ are performed, or processing 2 and processing 1 ′ are performed at the same time, and processing 1 and processing 2 + processing 1 ′ are performed.
[0012]
In the previous example, processing 1 and processing 1 ′ are nesting processing, and it is not possible to assume processing 1 + processing 2 + processing 1 ′ on the premise that the register (sub address) and the data byte associated therewith have a one-to-one correspondence. Is possible.
[0013]
Further, when the target control of the previous example is further expanded and the stage corresponding to the process 2 is multistage, or when the control corresponding to the process 1 and the process 1 ′ that are paired overlaps or exists separately, the subaddress The number of addresses increases, and since it is necessary to transfer each control data a plurality of times, at least two times, to complete the target processing, it generally takes a lot of processing time and man-hours for programming.
[0014]
One bus having such characteristics is I ² Cbus (registered trademark).
[0015]
In the I ² Cbus having the relationship of register: subaddress (data byte) = 1: 1, in principle, after transferring the chip address, subaddress, and data byte as a set to the serial bus, the transfer end data is transferred to the serial bus. In principle, it is necessary to shift to the next control. However, for the sake of easy programming, if only the data bytes that are the setting data are transferred, the sub-address address is automatically incremented by one. A function called increment mode is implemented.
[0016]
However, under the condition that different registers are set while being shifted on the time axis, there is no difference that data transfer to the serial bus is required multiple times.
[0017]
[Problems to be solved by the invention]
An object of the present invention is to define a register: subaddress when two specific subaddresses and specific data bytes, such as SAφ, DBφ and SAn + 1, DBn + 1, which are located on the time axis acting on the same register are defined. (Data byte) = 1: n can be accessed in a relationship, that is, when one-to-many access is performed, so that independent control to a register different from the above should be nested in the middle of the time axis Is to provide a serial control method for transferring data on a serial bus at a time.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, in the serial bus transfer control method of the present invention,
A controlling device, a register device, and a plurality of controlled devices are connected to each other via a serial bus, and the controlling device sends a series of control instructions via the register device to the plurality of controlled devices. In the serial transfer control method for serial transfer to the controlling device,
When there is a control instruction that can serially transfer the series of control instructions to the same register in the register device based on the contents of each control instruction, the control side device uses the same register in the register device. To determine whether transfer to
The series of control commands is rearranged with reference to the determined control command, and the rearranged control commands are serially transferred to the same register.
[0019]
In addition, a control instruction that acts on the register δ that exists in a position sandwiched between the plurality of control instructions that acts on the same register φ in the register device is sandwiched between transition states of the register φ. Rearranged
By transferring to the serial bus as the series of control commands belonging to one chip address transmitted by the control side device, it is possible to solve the problem even in processing that requires more man-hours. .
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
FIG. 1 is a schematic diagram for explaining the basic concept of the present invention.
[0022]
In FIG. 1, even if the chip addresses CA and IC have a one-to-one correspondence, as shown in FIG. 1, two subaddresses SAφ, data byte DBφ, subaddress SAn + 1, and data byte DBn + 1 may act on one register φ. If specified, the registers φ can be accessed together without generating different chip addresses CA.
[0023]
Then, the setting of the register executed at the subaddress SAδ or SAn or the like located between the generation time axes of the two subaddresses SA and data bytes DB is sandwiched between the setting states of the register φ set at SAφ and SAn + 1. This indicates that transfer can be performed with one chip address CA.
[0024]
In other words, it shows that the number of times of data transfer to the serial bus is completed once when performing the serial control achieved by sequentially performing on the time axis.
[0025]
However, under the above conditions, SAδ and SAn have a one-to-one correspondence with each register.
[0026]
Further, in order to clarify the difference from the present invention, a schematic diagram for explaining the basic concept of the prior art for comparing the case where the sub address SA and the data byte DB used in FIG. As shown in FIG.
[0027]
As in FIG. 1, the conventional control content shown in FIG. 2 is an example of control in which serial transfer is performed four times in total for the three registers φ, δ, and n, but the chip address before all the sub-addresses. 1 is different from FIG. 1 in that CA exists.
[0028]
In other words, as described in the description of the prior art, the number of data transfers to the serial bus is required to be at least 2 times, and usually 3 times.
[0029]
Next, the configuration will be described.
FIG. 3 is a diagram showing a main configuration of a control unit and a device affected by control in a computer system to which the present invention is applied.
[0030]
The control unit 40 performs control related to input / output from the device D1 connected to the device Dn via the I / O interface 43 and operations specific to each device, for example, tuning to a designated channel by a tuner.
[0031]
Control relating to input / output and operations specific to each device is executed by a program stored in the local program memory 42.
[0032]
When a user input instruction from the input unit 30 is received by the central processing unit 20, this program is read from the local program memory 42, transmitted to the data transfer control unit 41, and executed. Is done.
[0033]
The data transfer control unit 41 sequentially transfers data related to the processing to the register 44 in accordance with the processing program read from the local program memory 42.
[0034]
When the data transferred from the data transfer control unit 41 is input / output control data related to the devices D1 to Dn, the register 44 transmits the data to the corresponding devices D1 to Dn via the I / O interface 43. The instructed process is executed.
[0035]
In FIG. 3, the serial control program is shown as an embedded program in the local program memory 42 in order to simplify the description of the present embodiment. However, in the case where the serial control program is stored in an external storage device such as a hard disk drive. However, the serial control method of the present invention is applicable.
[0036]
FIGS. 4 to 6 are diagrams showing specific operation sites and examples of parameter displacement in each device when the concept of serial control described in FIG. 1 is applied to the computer system of FIG.
[0037]
First, when the serial control processing procedure shown in FIG. 4 is generalized,
{Control A + (Control B) + (Control C) + Control A ′}
[0038]
In FIG. 4, the data bytes DBφ and DBn + 1 execute a parameter displacement paired with the register φ.
[0039]
The register φ operates the device D1.
[0040]
At this time, the data byte DBδ existing at the position sandwiched between the data byte DBφ and the data byte DBn + 1 executes the parameter displacement for the register δ, and the data byte DBn also executes the parameter displacement for the register n.
[0041]
The register δ operates the device D2, and the register n operates the device Dn.
[0042]
When looking at the parameter displacement of each working device, the parameter displacement relating to the device D2 and the device Dn is displaced in the transition state of the parameter which is a pair of the device D1.
[0043]
In FIG. 4, for simplification of description, regarding the subaddress SA that should exist immediately before each data byte DB, only the subaddress SAφ existing before the data byte DBφ is illustrated and sequentially generated after the subaddress SAφ. The subaddress SA that is paired with each data byte DB is omitted.
[0044]
FIG. 5 is an expanded view of the example described with reference to FIG. 4 and shows an example of an action site and a parameter change in each device when there are a plurality of control sites for nesting.
[0045]
When generalizing the serial control processing procedure shown in FIG.
[Control A + {Control B + (Control C) + (Control D) + Control B ′} + Control A ′]
It can be expressed in the form of
[0046]
In FIG. 5, the data byte DBφ and the data byte DBn + 2 execute the parameter displacement paired with the register φ.
[0047]
Register φ operates device D1.
[0048]
At this time, the data byte DB1 and the data byte DBn + 1 execute the parameter displacement paired with the register 1.
[0049]
Register 1 operates device D2.
[0050]
The data byte DBδ existing at the position between the parameter transition state of the register φ and the parameter transition state of the register 1 executes the parameter displacement with respect to the register δ. Similarly, the data byte DBn also performs the parameter displacement with respect to the register n. Execute.
[0051]
Register δ acts on device D3, and register n acts on device Dn.
[0052]
When looking at the parameter displacement of each working device, the parameter displacement relating to the device D3 and the device Dn is displaced in the transition state of the parameter which is the pair of the device D2.
[0053]
Further, the parameter transition that forms the pair of the device D2 is displaced in the parameter transition that forms the pair of the device D1.
[0054]
In FIG. 5, as in the description of FIG. 4, for the subaddress SA that should exist immediately before each data byte DB, only the subaddress SAφ that exists before the data byte DBφ is illustrated, and the subaddress SAφ is sequentially generated after the subaddress SAφ. The subaddress SA that is paired with each data byte DB is omitted.
[0055]
FIG. 6 is a diagram showing that the register φ and the register 1 in the two parameter transition states described in FIG. 5 can be executed without being strictly nested.
[0056]
4 and 5,
{Control A + (Control B) + (Control C) + Control A ′}
[Control A + {Control B + (Control C) + (Control D) + Control B ′} + Control A ′]
[0057]
As described above, the case of parentheses without mathematical contradiction has been explained, but this is for ease of understanding.
[0058]
Therefore, as shown in FIG.
Control A + Control C + Control B + Control A ′ + Control C ′
As described above, when performing paired processing on two or more registers, the present invention can be applied even if the nesting processing format is not strictly adopted, and does not violate the condition of one-time transfer.
[0059]
【Example】
Next, a case where the serial control method of the present invention is applied will be specifically described with reference to the drawings.
[0060]
Example 1
An embodiment of device (source) switching at the time of selector switch operation in an audio apparatus in which an amplifier, a tuner, a graphic equalizer, a compact disc player, and the like are applied, to which the pattern shown in FIG. 4 is applied, will be described.
[0061]
In the pattern shown in FIG. 4, for example, the data byte BDφ and the data byte DBn + 1 correspond to a register related to the input channel volume of the amplifier from each device.
[0062]
In the pattern shown in FIG. 4, for example, the data byte BDδ corresponds to a register setting related to output channel switching from the compact disc player to the tuner.
[0063]
The remaining data bytes DBn in the pattern shown in FIG. 4 correspond to register settings related to ON / OFF of the graphic equalizer that sets the strength of the reproduction frequency band suitable for the output information of the switched tuner, for example.
[0064]
Under the above conditions, the user switches the input channel to the tuner from the performance state of the compact disc being played on the compact disc player by operating the selector switch of the amplifier, and adjusts the strength of the frequency band suitable for the data output from the tuner. For the purpose of transmitting the output from the tuner to the speakers, each register is changed between the sources with reduced noise by changing the settings as shown below in order to make sure that no noise is generated during the process. Can be switched.
[0065]
(Program generation conditions)
As a result of the user's operation of the selector switch, the mute program is transferred into the serial bus with the chip address CA.
[0066]
(Program structure)
The outline of the mute program has the following structure.
1. The data byte DBφ mutes the volume on the input channel of the amplifier by the subaddress SAφ following the chip address CA (hereinafter, the subaddress SA is omitted).
2. Data byte DBφ The following data byte DBδ switches the output channel of the compact disc player to the output channel of the tuner.
3. The data byte DBn following the data byte DBδ turns on the setting of the graphic equalizer that sets the strength of the reproduction frequency band suitable for the output information of the switched tuner.
4). The data byte DBn + 1 following the data byte DBn releases the volume mute on the input channel of the amplifier set by 1 above.
[0067]
With the above program generation conditions and program structure, serial bus control can be implemented by serial bus transfer derived from a single chip address when the present invention is applied.
[0068]
FIG. 7 is a schematic diagram showing the effect of switching the input source with muting and the volume level of each source along with the time axis.
[0069]
FIG. 7 is shown in order to understand the effect of the (Example 1) more visually.
[0070]
As described above, when the present invention is applied to the first embodiment, the transition from the playback state by the compact disc player to the playback of the tuner after the adjustment of the playback frequency band by the graphic equalizer has occurred. It is possible to carry out the operation accurately and in a short time without accompanying.
[0071]
(Example 2)
An embodiment will be described on the basis of a configuration diagram in which antenna diversity adapted to the present invention is adapted to attempt optimum reception by switching in response to the intensity of radio waves transmitted from two or more antennas. .
[0072]
In FIG. 8, for example, the device 1 has a function of switching between the antenna ANT1 and the antenna ANT2, and the device 2 is configured by a function of supplying information to the device 1 for switching between the antenna ANT1 and the antenna ANT2.
[0073]
Under the above conditions, while the receiver initializes the device 1, the antenna ANT1 or the antenna ANT2 of the device 1 is received under the situation that the receiver receives, for example, the radio field strengths of the antenna ANT1 and the antenna ANT2 are similar. Assume that there is a request to temporarily switch the antenna ANT1 or the antenna ANT2 of the device 1 to either the antenna ANT1 or the antenna ANT2 of the device 1 in order to perform the switching smoothly.
[0074]
At this time, when the device 2 tries to switch between the antenna ANT1 and the antenna ANT2 with reference to, for example, a specific register of the device 1 through the bus 2,
Adapting the present invention when the receiver sets the device 1 via the bus 1, the specific register fixing → the device 1 setting → the specific register release stage control is performed once via the bus 1. Can be implemented.
[0075]
As described above, when the present invention is applied to the second embodiment, it is possible to select an antenna that emits an optimal radio wave output for a receiver that exists at a certain position in a short time.
[0076]
【The invention's effect】
Since the present invention is as described above, the following effects can be obtained.
[0077]
According to the serial control method of the present invention, in serial control which requires that setting changes for a plurality of registers are sequentially shifted on the time axis, a control element composed of a plurality of chip addresses is added to a serial bus. Since it is possible to transfer data once to the serial bus by one chip address regardless of the step transfer, it is possible to reduce the time required to complete the target control.
[0078]
Further, the programming man-hour when writing the predetermined serial control program can be reduced, and more efficient programming can be performed as compared with the conventional case.
[0079]
In other words, in other words, the number of programming steps is small, which leads to the compression of individual serial control program capacity. In particular, in the case of a microcomputer embedded program, more serial control programs can be incorporated than before. it can.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining a basic concept of the present invention.
FIG. 2 is a schematic diagram for explaining the basic concept of the prior art compared with FIG. 1;
FIG. 3 is a diagram showing a main configuration of a control unit and a device affected by control in a computer system to which the present invention is applied.
4 is a diagram showing an example of an action site and a parameter displacement in each device when the configuration described in FIG. 1 is made to correspond to an apparatus in a computer system to which the present invention described in FIG. 3 is applied.
FIG. 5 is a diagram showing an example of an action part and an example of a parameter change in each device when there are a plurality of control parts that are subjected to nesting by extending the example described in FIG. 4;
FIG. 6 is a diagram illustrating that a register in the two parameter transition states described in FIG. 5 can be executed without necessarily being nested.
FIG. 7 is a schematic diagram showing the effect of switching the input source with muting along with the volume level of each source along with the time axis.
FIG. 8 is a configuration diagram in a case where antenna diversity is constructed in which optimum reception is attempted by switching appropriately according to the intensity of radio waves transmitted from two or more antennas.
[Explanation of symbols]
10 Serial Bus 20 Central Processing Unit 30 Input Unit 40 Serial Control Unit 41 Data Transfer Control Unit 42 Local Program Memory 43 I / O Interface 44 Register 50 Output Unit

Claims (2)

A controlling device, a register device, and a plurality of controlled devices are connected to each other via a serial bus, and the controlling device sends a series of control instructions via the register device to the plurality of controlled devices. In the serial transfer control method for serial transfer to the controlling device,
When there is a control command that can serially transfer the series of control commands to the same register in the register device based on the contents of each control command, the controlling device uses the same register in the register device. To determine whether transfer to
A serial transfer control method comprising rearranging the series of control commands based on the determined control command, and serially transferring the rearranged control commands to the same register. A control instruction that acts on the register δ that exists in a position sandwiched between the plurality of control instructions that acts on the same register φ in the register device is inserted between the transition states of the register φ. Rearrange to
2. The serial transfer control method according to claim 1, wherein the serial transfer is transferred to the serial bus as the series of control commands belonging to one chip address transmitted by the control side device.

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