JP3891609B2 - 並べ換え装置 - Google Patents

並べ換え装置 Download PDF

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Publication number
JP3891609B2
JP3891609B2 JP20138496A JP20138496A JP3891609B2 JP 3891609 B2 JP3891609 B2 JP 3891609B2 JP 20138496 A JP20138496 A JP 20138496A JP 20138496 A JP20138496 A JP 20138496A JP 3891609 B2 JP3891609 B2 JP 3891609B2
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JP
Japan
Prior art keywords
register
contents
rearrangement
reordering
input register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20138496A
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English (en)
Japanese (ja)
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JPH09106342A (ja
Inventor
ルビー・ビー・リー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
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Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH09106342A publication Critical patent/JPH09106342A/ja
Application granted granted Critical
Publication of JP3891609B2 publication Critical patent/JP3891609B2/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/762—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
JP20138496A 1995-08-01 1996-07-31 並べ換え装置 Expired - Fee Related JP3891609B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/509,867 US6381690B1 (en) 1995-08-01 1995-08-01 Processor for performing subword permutations and combinations
US509,867 1995-08-01

Publications (2)

Publication Number Publication Date
JPH09106342A JPH09106342A (ja) 1997-04-22
JP3891609B2 true JP3891609B2 (ja) 2007-03-14

Family

ID=24028413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20138496A Expired - Fee Related JP3891609B2 (ja) 1995-08-01 1996-07-31 並べ換え装置

Country Status (3)

Country Link
US (1) US6381690B1 (fr)
EP (1) EP0757312A1 (fr)
JP (1) JP3891609B2 (fr)

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WO1999048025A2 (fr) 1998-03-18 1999-09-23 Koninklijke Philips Electronics N.V. Dispositif de traitement de donnees et procede de calcul de la transformee en cosinus discrets d'une matrice
US6041404A (en) * 1998-03-31 2000-03-21 Intel Corporation Dual function system and method for shuffling packed data elements
US6952478B2 (en) * 2000-05-05 2005-10-04 Teleputers, Llc Method and system for performing permutations using permutation instructions based on modified omega and flip stages
US6922472B2 (en) * 2000-05-05 2005-07-26 Teleputers, Llc Method and system for performing permutations using permutation instructions based on butterfly networks
WO2001089098A2 (fr) 2000-05-05 2001-11-22 Lee Ruby B Procede et systeme de realisation de permutations avec des instructions de permutation de bits
US7620832B2 (en) * 2000-09-20 2009-11-17 Mips Technologies, Inc. Method and apparatus for masking a microprocessor execution signature
US7711763B2 (en) 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US7237097B2 (en) * 2001-02-21 2007-06-26 Mips Technologies, Inc. Partial bitwise permutations
US7162621B2 (en) * 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US7181484B2 (en) * 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
US7318145B1 (en) 2001-06-01 2008-01-08 Mips Technologies, Inc. Random slip generator
US7739319B2 (en) * 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
US7624138B2 (en) 2001-10-29 2009-11-24 Intel Corporation Method and apparatus for efficient integer transform
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7631025B2 (en) * 2001-10-29 2009-12-08 Intel Corporation Method and apparatus for rearranging data between multiple registers
US7725521B2 (en) * 2001-10-29 2010-05-25 Intel Corporation Method and apparatus for computing matrix transformations
US20040054877A1 (en) 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7685212B2 (en) * 2001-10-29 2010-03-23 Intel Corporation Fast full search motion estimation with SIMD merge instruction
US7039795B2 (en) * 2002-06-14 2006-05-02 Texas Instruments Incorporated System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data
US7202872B2 (en) * 2003-10-29 2007-04-10 Via Technologies, Inc. Apparatus for compressing data in a bit stream or bit pattern
US7783690B2 (en) * 2005-07-07 2010-08-24 International Business Machines Corporation Electronic circuit for implementing a permutation operation
WO2007057832A2 (fr) * 2005-11-15 2007-05-24 Nxp B.V. Appareil et procede de traitement de donnees
US20070226469A1 (en) * 2006-03-06 2007-09-27 James Wilson Permutable address processor and method
US8156310B2 (en) * 2006-09-11 2012-04-10 International Business Machines Corporation Method and apparatus for data stream alignment support
GB2443439B (en) * 2006-10-30 2009-06-03 Imagination Tech Ltd Digital electronic binary rotator and reverser
US8285766B2 (en) 2007-05-23 2012-10-09 The Trustees Of Princeton University Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor
US7673120B2 (en) * 2007-06-27 2010-03-02 Texas Instruments Incorporated Inter-cluster communication network and heirarchical register files for clustered VLIW processors
US8078836B2 (en) 2007-12-30 2011-12-13 Intel Corporation Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
WO2011121795A1 (fr) * 2010-03-31 2011-10-06 Telefonaktiebolaget L M Ericsson (Publ) Décaleur de données et son procédé de commande, multiplexeur, tamiseur de données et trieur de données
US20120278591A1 (en) * 2011-04-27 2012-11-01 Advanced Micro Devices, Inc. Crossbar switch module having data movement instruction processor module and methods for implementing the same
US20140013082A1 (en) * 2011-12-30 2014-01-09 Intel Corporation Reconfigurable device for repositioning data within a data word
US20170161069A1 (en) * 2015-12-08 2017-06-08 Knuedge, Inc. Microprocessor including permutation instructions
US20170185413A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Processing devices to perform a conjugate permute instruction
US10255462B2 (en) 2016-06-17 2019-04-09 Arm Limited Apparatus and method for obfuscating power consumption of a processor
US20190272175A1 (en) * 2018-03-01 2019-09-05 Qualcomm Incorporated Single pack & unpack network and method for variable bit width data formats for computational machines
US11204738B1 (en) * 2020-06-03 2021-12-21 Arm Limited Apparatus and method for performing bit permutation operations

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US4085447A (en) * 1976-09-07 1978-04-18 Sperry Rand Corporation Right justified mask transfer apparatus
US4545032A (en) * 1982-03-08 1985-10-01 Iodata, Inc. Method and apparatus for character code compression and expansion
US4567572A (en) * 1983-02-22 1986-01-28 The United States Of America As Represented By The Director Of The National Security Agency Fast parallel sorting processor
US4816817A (en) * 1985-06-28 1989-03-28 Hewlett-Packard Company Line mover for bit-mapped display
GB2189970B (en) * 1986-05-01 1990-03-28 British Broadcasting Corp Data conversion
JPS6398729A (ja) 1986-10-15 1988-04-30 Fujitsu Ltd バレルシフタ
JPS63292185A (ja) 1987-05-25 1988-11-29 日本電気株式会社 デジタル入出力回路
US4980853A (en) * 1988-03-04 1990-12-25 Chips And Technologies, Inc. Bit blitter with narrow shift register
JP2527458B2 (ja) * 1988-03-04 1996-08-21 富士通株式会社 デ―タ転送制御装置
DE3832328A1 (de) * 1988-09-23 1990-03-29 Broadcast Television Syst Speicheranordnung fuer digitale signale
JP2633331B2 (ja) * 1988-10-24 1997-07-23 三菱電機株式会社 マイクロプロセッサ
US5268858A (en) * 1991-08-30 1993-12-07 Cyrix Corporation Method and apparatus for negating an operand
US5471628A (en) * 1992-06-30 1995-11-28 International Business Machines Corporation Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode
US5524256A (en) * 1993-05-07 1996-06-04 Apple Computer, Inc. Method and system for reordering bytes in a data stream
US5390135A (en) * 1993-11-29 1995-02-14 Hewlett-Packard Parallel shift and add circuit and method
FR2721463A1 (fr) * 1994-06-17 1995-12-22 Trt Telecom Radio Electr Système de transmission comportant au moins deux liaisons pour relier un émetteur et un récepteur et récepteur convenant à un tel système.

Also Published As

Publication number Publication date
US6381690B1 (en) 2002-04-30
JPH09106342A (ja) 1997-04-22
EP0757312A1 (fr) 1997-02-05

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