JP3888211B2 - Electronic component manufacturing method - Google Patents

Electronic component manufacturing method Download PDF

Info

Publication number
JP3888211B2
JP3888211B2 JP2002115822A JP2002115822A JP3888211B2 JP 3888211 B2 JP3888211 B2 JP 3888211B2 JP 2002115822 A JP2002115822 A JP 2002115822A JP 2002115822 A JP2002115822 A JP 2002115822A JP 3888211 B2 JP3888211 B2 JP 3888211B2
Authority
JP
Japan
Prior art keywords
resin
sealing
coating
semiconductor element
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002115822A
Other languages
Japanese (ja)
Other versions
JP2003309134A (en
Inventor
知幸 園田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2002115822A priority Critical patent/JP3888211B2/en
Publication of JP2003309134A publication Critical patent/JP2003309134A/en
Application granted granted Critical
Publication of JP3888211B2 publication Critical patent/JP3888211B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing electronic parts, which ensures thinness in a shape as much as possible after resin sealing, and improves productivity by shortening the coating time of a sealing resin, and provide electronic parts. <P>SOLUTION: The resin sealing of a semiconductor element mounted on a substrate comprises: a process for forming a resin bank 9a by the continuous coating of a sealing resin 9 close to the inner side of a resin frame 3 that serves as a flow prevention frame, by jetting out the sealing resin 9 from a coating nozzle 8a; and a process for forming a resin coating for covering the entire surface in the resin frame 3 with the sealing resin 9, by repeatedly moving the coating nozzle 8a inward, being in contact with the resin bank 9a, in a state where the jetting of the sealing resin 9 has been halted. Thus, the use of a large diameter coating nozzle is possible, which contributes to shortening the coating time and reducing the thickness of the shape after resin sealing. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子を基板に実装しこの半導体素子を樹脂封止して成る電子部品製造方法に関するものである。
【０００２】
【従来の技術】
半導体装置など半導体素子を基板に実装した構成の電子部品の製造工程では、基板に実装された半導体素子を被覆して保護するための樹脂封止が行われる。この樹脂封止方法として、流動状態の封止樹脂を塗布ノズルによって基板に実装された半導体素子の上面を覆って塗布する方法が知られている。この方法によれば、モールドプレスを用いるモールド成型方法と比較して、簡便な設備で樹脂封止が行えるという利点がある。
【０００３】
ところで近年、ＩＣカード内蔵の用途など、薄型の半導体装置が用いられるようになってきていることから、樹脂封止工程においても、封止後の厚みを極力薄くすることが求められている。この方策として、塗布ノズルとして細径ノズルを用い樹脂封止のための樹脂塗布時の塗布流量を小さくして、塗布ピッチを微細にすることにより、できるだけ均一で薄い樹脂層を形成することが行われていた。
【０００４】
【発明が解決しようとする課題】
しかしながら上記従来の方法では、塗布流量が少ないことから所要量の塗布を行うのに長時間を要して生産性の向上が阻害されるとともに、塗布後に流動状態の樹脂の表面張力によって塗布面の中央部が周囲よりも高くなる凸形状となり易く、樹脂封止後の形状を所定の薄さに確保することが困難であるという問題点があった。
【０００５】
そこで本発明は、樹脂封止後の形状を極力薄型に確保するとともに、封止樹脂の塗布時間を短縮して生産性を向上させることができる電子部品製造方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
請求項１記載の電子部品製造方法は、半導体素子を基板に実装しこの半導体素子を樹脂封止して成る電子部品を製造する電子部品製造方法であって、上面に前記半導体素子の実装位置を囲んで封止樹脂の塗布範囲外への流動を防止する流動防止枠が形成された基板に前記半導体素子を実装する半導体素子実装工程と、封止樹脂を吐出する塗布ノズルによって前記流動防止枠の内側へ流動状態の封止樹脂を供給することにより前記半導体素子を封止樹脂で覆って封止する樹脂封止工程とを含み、前記樹脂封止工程において、前記塗布ノズルから封止樹脂を吐出させながらこの塗布ノズルを移動させることにより流動防止枠の内周近傍に封止樹脂が連続した堤状に塗布された樹脂堤を形成する樹脂堤形成動作と、塗布ノズルからの封止樹脂の吐出を停止した状態で塗布ノズルを前記樹脂堤に接触させた後にこの塗布ノズルを樹脂堤の内側方向へ移動させる動作を反復することにより流動防止枠内全面を封止樹脂で覆う樹脂被覆形成動作とを行う。
【０００８】
本発明によれば、半導体素子実装後の樹脂封止工程において、塗布ノズルから封止樹脂を吐出させながらこの塗布ノズルを流動防止枠の内周に沿って移動させることにより流動防止枠の内周近傍に封止樹脂が連続した堤状に塗布された樹脂堤を形成する樹脂堤形成動作と、塗布ノズルからの封止樹脂の吐出を停止した状態で塗布ノズルを樹脂堤に接触させた後に樹脂堤の内側方向へ移動させる動作を反復して流動防止枠内全面を封止樹脂で覆う樹脂被覆形成動作とを行うことにより、大径の塗布ノズルの使用を可能にして塗布時間を短縮できるとともに、塗布面の中央部の高さを低く保って封止後の形状を薄型にすることができる。
【０００９】
【発明の実施の形態】
次に本発明の実施の形態を図面を参照して説明する。図１（ａ）は本発明の一実施の形態の電子部品の平面図、図１（ｂ）は本発明の一実施の形態の電子部品の断面図、図２、図３、図４は本発明の一実施の形態の電子部品製造方法の工程説明図、図５は本発明の一実施の形態の電子部品の断面図である。
【００１０】
本実施の形態に示す電子部品製造方法は、半導体素子を基板に実装しこの半導体素子を樹脂封止して成る電子部品を製造するものである。図１は、樹脂封止前の電子部品を示している。図１（ａ）、（ｂ）に示すように、基板１の上面には半導体素子５の実装に先だって予め実装位置の周囲を囲んで樹脂枠３が形成されている。樹脂枠３は、流動状態の封止樹脂を塗布する際に封止樹脂の塗布範囲外への不要な流動を防止する流動防止枠として機能する。基板１の実装位置には、接着剤４を介して半導体素子５が実装されている。半導体素子５の上面の外部接続用の電極６と基板１上面の電極２とは、ボンディングワイヤ７によって接続されている（半導体素子実装工程）。
【００１１】
次に、図２、図３、図４を参照して、図１に示す電子部品を樹脂封止して電子部品を完成させる樹脂封止工程について説明する。なお、図２、図３、図４においては、電極２、電極６およびボンディングワイヤ７の図示を省略している。図２（ａ）において、基板１の上面の塗布範囲（樹脂枠３の内側）の上方には、封止樹脂９を吐出するディスペンサ８が位置している。
【００１２】
次いで、図２（ｂ）に示すようにディスペンサ８の塗布ノズル８ａは、塗布範囲内の塗布開始点ＰＳ（図３（ａ）参照）に移動する。そして塗布ノズル８ａから流動状態の封止樹脂９を吐出させながら、図３（ａ）に示す塗布軌跡に従って樹脂枠３の内周に沿って移動することにより、塗布軌跡上に封止樹脂９を塗布する。この塗布動作においては、所要塗布量に応じて塗布軌跡を順次内側へ向かってずらしながら塗布を反復し、所要量の封止樹脂９を塗布する。これにより図２（ｃ）、図３（ｂ）に示すように、樹脂枠３の内周近傍には封止樹脂９が連続した堤状に塗布された樹脂堤９ａが形成される（樹脂堤形成動作）。
【００１３】
この樹脂堤形成においては、塗布範囲内の中央部分には封止樹脂９は塗布されず、半導体素子５の上面は露呈状態のままである。またこの塗布動作においては塗布高さを均一にする必要がないことから、塗布条件として太径の塗布ノズル８ａを高速で移動させる高速塗布が採用可能となっている。
【００１４】
次に図４を参照して、樹脂枠３内全面を封止樹脂９で覆う樹脂被覆形成動作について説明する。ここでは、塗布ノズル８ａからの封止樹脂９の吐出を停止した状態で、図４（ａ）に示す塗布軌跡に従って塗布ノズル８ａを樹脂堤９ａに接触させた後に樹脂堤９ａの内側方向へ移動させる動作を反復する。すなわち、図４（ｂ）に示すように、樹脂堤９ａの上面近傍の封止樹脂９を塗布ノズル８ａの先端部に付着させ、塗布ノズル８ａの移動によって半導体素子５の上面まで掻き寄せる。そしてこの封止樹脂９の掻き寄せを樹脂枠３内側の全範囲について反復することにより、図４（ｃ）に示すように、樹脂枠３内全面は封止樹脂９によって覆われる（樹脂被覆形成動作）。またこの樹脂形成動作は、封止樹脂９の吐出量を調整する必要がないので、高速で行うことができる。
【００１５】
図５は、このようにして製造された電子部品の断面を示している。本実施の形態では、上述のように樹脂枠３内への塗布ノズル８ａによる封止樹脂９の塗布において、樹脂枠３の内周近傍に樹脂堤９ａを形成するようにしており塗布範囲の中央部分には封止樹脂９が吐出されないことから、樹脂枠３内全面に封止樹脂９を吐出する従来の塗布方法による塗布形状、すなわち樹脂枠３内で封止樹脂９が表面張力によって盛り上がり中央部分が周囲よりも高くなる凸形状を避けることができる。
【００１６】
従って、樹脂封止後の封止樹脂９の塗布高さｈ１は、図５に示すように樹脂枠３とほぼ同じ高さに抑えられて、過度に高くなることがない。これにより、樹脂封止後の電子部品の厚み寸法を極力小さく抑えて薄型の電子部品を実現することが可能となっている。また、本実施の形態によれば、封止樹脂９の塗布形状（上下方向の断面形状）は、中央部近傍が周囲よりも低い凹形状となっている。このため、同一樹脂量で比較した場合、基板１に対して曲げ外力が作用した場合における電子部品全体の曲げ剛性が増大し、破壊に対する強度が向上するという効果を併せて得ることができる。
【００１７】
【発明の効果】
本発明によれば、半導体素子実装後の樹脂封止工程において、塗布ノズルから封止樹脂を吐出させながらこの塗布ノズルを流動防止枠の内周に沿って移動させることにより流動防止枠の内周近傍に封止樹脂が連続した堤状に塗布された樹脂堤を形成する樹脂堤形成動作と、塗布ノズルからの封止樹脂の吐出を停止した状態で塗布ノズルを樹脂堤に接触させた後に樹脂堤の内側方向へ移動させる動作を反復して流動防止枠内全面を封止樹脂で覆う樹脂被覆形成動作とを行うようにしたので、大径の塗布ノズルの使用を可能にして塗布時間を短縮できるとともに、塗布面の中央部の高さを低く保って封止後の形状を薄型にすることができる。
【図面の簡単な説明】
【図１】（ａ）本発明の一実施の形態の電子部品の平面図
（ｂ）本発明の一実施の形態の電子部品の断面図
【図２】本発明の一実施の形態の電子部品製造方法の工程説明図
【図３】本発明の一実施の形態の電子部品製造方法の工程説明図
【図４】本発明の一実施の形態の電子部品製造方法の工程説明図
【図５】本発明の一実施の形態の電子部品の断面図
【符号の説明】
１ 基板
３ 樹脂枠
５ 半導体素子
８ａ 塗布ノズル
９ 封止樹脂
９ａ 樹脂堤[0001]
BACKGROUND OF THE INVENTION
The present invention, a semiconductor element mounted on the substrate in which relates the semiconductor device in the electronic component manufacturing how made by resin sealing.
[0002]
[Prior art]
In a manufacturing process of an electronic component having a configuration in which a semiconductor element such as a semiconductor device is mounted on a substrate, resin sealing for covering and protecting the semiconductor element mounted on the substrate is performed. As this resin sealing method, there is known a method of applying a sealing resin in a fluid state so as to cover an upper surface of a semiconductor element mounted on a substrate by an application nozzle. According to this method, there is an advantage that resin sealing can be performed with simple equipment as compared with a molding method using a mold press.
[0003]
By the way, since thin semiconductor devices have been used in recent years, such as applications incorporating an IC card, it is required to reduce the thickness after sealing as much as possible even in the resin sealing step. As a measure for this, it is possible to form a resin layer that is as uniform and thin as possible by using a small-diameter nozzle as the application nozzle, reducing the application flow rate during resin application for resin sealing, and reducing the application pitch. It was broken.
[0004]
[Problems to be solved by the invention]
However, in the above conventional method, since the coating flow rate is small, it takes a long time to perform the required amount of coating, and the improvement in productivity is hindered. There is a problem that the central portion tends to be a convex shape higher than the surrounding, and it is difficult to secure the shape after resin sealing to a predetermined thickness.
[0005]
The present invention is to ensure the shape after the resin sealing as much as possible thin, and an object thereof is to provide an electronic component manufacturing how that can improve the productivity by shortening the coating time of the sealing resin .
[0006]
[Means for Solving the Problems]
The electronic component manufacturing method according to claim 1 is an electronic component manufacturing method for manufacturing an electronic component formed by mounting a semiconductor element on a substrate and sealing the semiconductor element with a resin, wherein the mounting position of the semiconductor element is formed on an upper surface. A semiconductor element mounting step of mounting the semiconductor element on a substrate on which a flow prevention frame is formed to prevent the flow of the sealing resin from outside the coating range of the sealing resin, and the flow prevention frame is formed by a coating nozzle that discharges the sealing resin. A resin sealing step of covering and sealing the semiconductor element with a sealing resin by supplying a sealing resin in a fluid state to the inside, and discharging the sealing resin from the coating nozzle in the resin sealing step and a resin dam forming operation for forming a resin bank in which the inner circumference near the sealing resin is applied to the continuous bank-like flow prevention frame by the coating nozzle moves while, the sealing resin from the coating nozzle vomit The resin coating forming operation of covering the entire surface of the flow prevention frame with the sealing resin by repeating the operation of moving the coating nozzle in the inner direction of the resin bank after the coating nozzle is brought into contact with the resin bank in a stopped state. Do.
[0008]
According to the present invention, in the resin sealing step after mounting the semiconductor element, the inner periphery of the anti-flow frame is moved by moving the application nozzle along the inner periphery of the anti-flow frame while discharging the sealing resin from the application nozzle. Resin embankment forming operation to form a resin bank with a sealing resin continuously applied in the vicinity of the sealing resin, and the resin after contacting the coating nozzle to the resin bank with the discharge of the sealing resin from the coating nozzle stopped It is possible to use a large-diameter coating nozzle and shorten the coating time by repeating the movement to the inside of the bank and performing the resin coating forming operation to cover the entire surface of the anti-flow frame with sealing resin. The shape after sealing can be made thin by keeping the height of the central portion of the coated surface low.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. 1A is a plan view of an electronic component according to an embodiment of the present invention, FIG. 1B is a cross-sectional view of the electronic component according to an embodiment of the present invention, and FIGS. 2, 3, and 4 are books. Process explanatory drawing of the electronic component manufacturing method of one Embodiment of this invention, FIG. 5: is sectional drawing of the electronic component of one Embodiment of this invention.
[0010]
The electronic component manufacturing method shown in the present embodiment manufactures an electronic component formed by mounting a semiconductor element on a substrate and sealing the semiconductor element with resin. FIG. 1 shows an electronic component before resin sealing. As shown in FIGS. 1A and 1B, a resin frame 3 is formed on the upper surface of the substrate 1 so as to surround the periphery of the mounting position in advance of mounting the semiconductor element 5. The resin frame 3 functions as a flow prevention frame that prevents unnecessary flow outside the application range of the sealing resin when applying the sealing resin in a fluid state. A semiconductor element 5 is mounted on the mounting position of the substrate 1 via an adhesive 4. The external connection electrode 6 on the upper surface of the semiconductor element 5 and the electrode 2 on the upper surface of the substrate 1 are connected by a bonding wire 7 (semiconductor element mounting step).
[0011]
Next, with reference to FIGS. 2, 3, and 4, a resin sealing step of completing the electronic component by sealing the electronic component shown in FIG. 1 will be described. 2, 3, and 4, the illustration of the electrode 2, the electrode 6, and the bonding wire 7 is omitted. In FIG. 2A, a dispenser 8 that discharges the sealing resin 9 is positioned above the application range (inside the resin frame 3) on the upper surface of the substrate 1.
[0012]
Next, as shown in FIG. 2B, the application nozzle 8a of the dispenser 8 moves to the application start point PS within the application range (see FIG. 3A). Then, while discharging the sealing resin 9 in a fluid state from the application nozzle 8a, the sealing resin 9 is moved onto the application locus by moving along the inner periphery of the resin frame 3 according to the application locus shown in FIG. Apply. In this application operation, the application is repeated while sequentially shifting the application locus inward according to the required application amount, and the required amount of sealing resin 9 is applied. As a result, as shown in FIGS. 2C and 3B, a resin bank 9a in which a sealing resin 9 is applied in a continuous bank shape is formed in the vicinity of the inner periphery of the resin frame 3 (resin bank). Forming operation).
[0013]
In this resin bank formation, the sealing resin 9 is not applied to the central portion within the application range, and the upper surface of the semiconductor element 5 remains exposed. Further, since it is not necessary to make the coating height uniform in this coating operation, high-speed coating in which the large-diameter coating nozzle 8a is moved at high speed can be employed as a coating condition.
[0014]
Next, with reference to FIG. 4, a resin coating forming operation for covering the entire surface of the resin frame 3 with the sealing resin 9 will be described. Here, in a state where the discharge of the sealing resin 9 from the coating nozzle 8a is stopped, the coating nozzle 8a is brought into contact with the resin bank 9a in accordance with the coating locus shown in FIG. Repeat the action to be performed. That is, as shown in FIG. 4B, the sealing resin 9 in the vicinity of the upper surface of the resin bank 9a is attached to the tip of the coating nozzle 8a, and is scraped to the upper surface of the semiconductor element 5 by the movement of the coating nozzle 8a. Then, by repeating the scraping of the sealing resin 9 for the entire range inside the resin frame 3, as shown in FIG. 4C, the entire surface of the resin frame 3 is covered with the sealing resin 9 (resin coating formation). Operation). Further, this resin forming operation can be performed at high speed because it is not necessary to adjust the discharge amount of the sealing resin 9.
[0015]
FIG. 5 shows a cross section of the electronic component manufactured in this way. In the present embodiment, in the application of the sealing resin 9 into the resin frame 3 by the application nozzle 8a as described above, the resin bank 9a is formed in the vicinity of the inner periphery of the resin frame 3, and the center of the application range. Since the sealing resin 9 is not discharged to the portion, the application shape by the conventional application method in which the sealing resin 9 is discharged to the entire surface of the resin frame 3, that is, the sealing resin 9 rises due to the surface tension in the resin frame 3. A convex shape in which the portion is higher than the surrounding can be avoided.
[0016]
Therefore, the application height h1 of the sealing resin 9 after resin sealing is suppressed to substantially the same height as the resin frame 3 as shown in FIG. 5, and does not become excessively high. Thereby, it is possible to realize a thin electronic component by minimizing the thickness dimension of the electronic component after resin sealing. Moreover, according to this Embodiment, the application | coating shape (sectional shape of an up-down direction) of the sealing resin 9 is a concave shape where the center part vicinity is lower than the circumference | surroundings. For this reason, when compared with the same resin amount, the bending rigidity of the entire electronic component when a bending external force is applied to the substrate 1 is increased, and the effect of improving the strength against breakage can be obtained.
[0017]
【The invention's effect】
According to the present invention, in the resin sealing step after mounting the semiconductor element, the inner periphery of the anti-flow frame is moved by moving the application nozzle along the inner periphery of the anti-flow frame while discharging the sealing resin from the application nozzle. Resin levee forming operation to form a resin levee coated in the shape of a continuous bank of sealing resin in the vicinity, and after applying the coating nozzle to the resin dam in a state where discharge of the sealing resin from the coating nozzle is stopped, the resin The operation to move the inside of the bank is repeated to perform the resin coating forming operation that covers the entire surface of the anti-flow frame with sealing resin, enabling the use of a large-diameter coating nozzle and shortening the coating time In addition, the height of the central portion of the coated surface can be kept low, and the shape after sealing can be made thin.
[Brief description of the drawings]
1A is a plan view of an electronic component according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of an electronic component according to an embodiment of the present invention. FIG. 2 is an electronic component according to an embodiment of the present invention. FIG. 3 is a process explanatory diagram of an electronic component manufacturing method according to an embodiment of the present invention. FIG. 4 is a process explanatory diagram of an electronic component manufacturing method according to an embodiment of the present invention. Sectional drawing of the electronic component of one embodiment of this invention
DESCRIPTION OF SYMBOLS 1 Substrate 3 Resin frame 5 Semiconductor element 8a Coating nozzle 9 Sealing resin 9a Resin bank

Claims (1)

半導体素子を基板に実装しこの半導体素子を樹脂封止して成る電子部品を製造する電子部品製造方法であって、上面に前記半導体素子の実装位置を囲んで封止樹脂の塗布範囲外への流動を防止する流動防止枠が形成された基板に前記半導体素子を実装する半導体素子実装工程と、封止樹脂を吐出する塗布ノズルによって前記流動防止枠の内側へ流動状態の封止樹脂を供給することにより前記半導体素子を封止樹脂で覆って封止する樹脂封止工程とを含み、前記樹脂封止工程において、前記塗布ノズルから封止樹脂を吐出させながらこの塗布ノズルを移動させることにより流動防止枠の内周近傍に封止樹脂が連続した堤状に塗布された樹脂堤を形成する樹脂堤形成動作と、塗布ノズルからの封止樹脂の吐出を停止した状態で塗布ノズルを前記樹脂堤に接触させた後にこの塗布ノズルを樹脂堤の内側方向へ移動させる動作を反復することにより流動防止枠内全面を封止樹脂で覆う樹脂被覆形成動作とを行うことを特徴とする電子部品製造方法。An electronic component manufacturing method for manufacturing an electronic component formed by mounting a semiconductor element on a substrate and sealing the semiconductor element with a resin, wherein the mounting position of the semiconductor element is surrounded on the upper surface and outside the coating range of the sealing resin A semiconductor element mounting step of mounting the semiconductor element on a substrate on which a flow prevention frame for preventing flow is formed, and a sealing resin in a fluid state is supplied to the inside of the flow prevention frame by a coating nozzle that discharges the sealing resin and a resin sealing step of sealing over the semiconductor element with a sealing resin by, in the resin sealing step, by moving the coating nozzle while discharging the sealing resin from the coating nozzle A resin bank forming operation for forming a resin bank in which sealing resin is applied in a continuous bank shape in the vicinity of the inner periphery of the flow prevention frame, and the application nozzle in the state where the discharge of the sealing resin from the coating nozzle is stopped. Electronic component manufacturing characterized by performing a resin coating forming operation of covering the entire surface of the flow prevention frame with a sealing resin by repeating the operation of moving the coating nozzle toward the inside of the resin bank after contacting the bank Method.
JP2002115822A 2002-04-18 2002-04-18 Electronic component manufacturing method Expired - Fee Related JP3888211B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002115822A JP3888211B2 (en) 2002-04-18 2002-04-18 Electronic component manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002115822A JP3888211B2 (en) 2002-04-18 2002-04-18 Electronic component manufacturing method

Publications (2)

Publication Number Publication Date
JP2003309134A JP2003309134A (en) 2003-10-31
JP3888211B2 true JP3888211B2 (en) 2007-02-28

Family

ID=29396944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002115822A Expired - Fee Related JP3888211B2 (en) 2002-04-18 2002-04-18 Electronic component manufacturing method

Country Status (1)

Country Link
JP (1) JP3888211B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4641837B2 (en) 2005-03-17 2011-03-02 株式会社リコー Resin discharge nozzle and resin sealing method

Also Published As

Publication number Publication date
JP2003309134A (en) 2003-10-31

Similar Documents

Publication Publication Date Title
JP3056192B1 (en) Method of manufacturing mounting board with solder resist layer having bumps formed on electrode pads
TWI500131B (en) Method of forming substrate for semiconductor element and semiconductor device
TWI345281B (en) Methods and systems for advanced solder bumping
JP2010521587A5 (en)
JP4243487B2 (en) Apparatus and method for accurately sealing flip chip interconnects
TWI521661B (en) Lead frame board, method of forming the same, and semiconductor device
JP3544970B2 (en) COF tape carrier, semiconductor element, semiconductor device
KR20240023575A (en) Method of manufacturing semiconductor device
EP3485511B1 (en) Method of manufacturing flexible electronic circuits having conformal material coatings
JP3888211B2 (en) Electronic component manufacturing method
TW201232703A (en) Method of manufacturing wiring board
JP3888284B2 (en) Electronic component manufacturing method
US7588965B2 (en) Stencil and method for depositing material onto a substrate
TWI482251B (en) Lead frame and method of manufacturing
US7906421B2 (en) Method for applying solder to redistribution lines
US6943439B2 (en) Substrate and fabrication method of the same
KR20240012567A (en) Manufacturing method and paste application device for electronic components
TWI423416B (en) Integrated circuit support for low profile wire bond
JPH09213725A (en) Semiconductor device
JP4308698B2 (en) Semiconductor device
JP2009188264A (en) Bump formation method
WO2006046806A1 (en) Method of supplying flux to semiconductor device
JP2835329B2 (en) Semiconductor element sealing method
JP2005150446A (en) Method for manufacturing electronic part
JPH08203909A (en) Bump forming method of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050325

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20050706

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051018

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060905

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061017

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061120

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091208

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101208

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101208

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111208

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111208

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121208

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121208

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131208

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees