JP3887755B2 - Method, computer and storage medium for reducing frequency of video clock - Google Patents

Description

  The present invention relates to power management, and more particularly to a technique that enables power saving by lowering the frequency of a video clock (Vclk). Vclk is a timing signal for displaying on the display device, and includes a timing signal for outputting display data on an LCD (Liquid Crystal Display) in units of pixels, for example.

  Conventionally, a technique for reducing the power consumption of an electronic circuit by lowering or stopping the frequency of a clock has been used. In recent years, the power consumption of a CPU (Central Processing Unit) has increased in particular, so that the CPU frequency is reduced or stopped depending on the amount of processing required. On the other hand, the frequency of a video clock related to a display device such as an LCD tends to increase due to an increase in resolution and the number of display colors, and power consumption increases accordingly. However, when the frequency of the video clock is lowered, flicker or the like occurs and the display quality is lowered. Techniques for reducing the video clock or reducing the refresh rate of the display device include the following. Note that lowering the refresh rate is not equivalent to lowering Vclk. Leave Vclk as it is and lengthen the horizontal or vertical blanking period, or lower the frequency of Vclk, which is the basis of all clocks related to display, while keeping the number of clocks applied to the horizontal and vertical blanking periods constant Thus, the refresh rate can be lowered. However, in order to reduce the power consumption, it is effective to lower the frequency of Vclk. In the present application, it is assumed that the refresh rate is lowered by lowering Vclk.

  In US Pat. No. 5,524,249, when the power supply of the display device is stopped in a suspended state, a standby state, or the like, Pclk (substantially the same as the video clock) is stopped and Mclk (memory clock: driving frequency of the video controller) is stopped. The technique of lowering the frequency of the is disclosed. However, there is no description of lowering or stopping Pclk in a normal state other than the power saving mode such as a suspend state or a standby state, and simultaneously lowering Pclk and Mclk in the normal state.

  US Pat. No. 5,615,376 discloses stopping VCLK (video clock) during horizontal and vertical blanking periods and lowering MCLK when there is no access to the frame buffer. However, there is no description of lowering VCLK during a normal display period and lowering VCLK and MCLK simultaneously in a normal state.

  Japanese Patent Application Laid-Open No. 7-64665 discloses a case where various information data are not written to the display memory within a predetermined time and the stored contents are not changed, or when a drop in power supply voltage is detected, or when a sleep state is entered. Discloses that the display timing on the LCD is delayed. However, there is no description about countermeasures such as flicker caused by delaying display timing, or delaying display timing so as not to affect display contents.

  Japanese Patent Application Laid-Open No. 7-239463 discloses a refresh operation in an active matrix type display device with several frames (upper frame) for a part of the display device per frame (for example, every fourth row out of all 20 rows). In this example, it is disclosed that it is performed over 4 frames). Here, the refresh operation as described above is performed as a countermeasure against flicker, but such an operation is not sufficient. Furthermore, it is necessary to change the circuit on the panel side.

  JP-A-6-342148 discloses a ferroelectric liquid crystal display device in order to substantially speed up the moving of a cursor, smooth scrolling, moving image display such as multi-window or video moving image display even at a low frame frequency. It is disclosed that only the scanning line in which the image information is changed is refreshed. This uses a characteristic unique to a ferroelectric liquid crystal display device.

  Japanese Patent Application Laid-Open No. 9-5789 discloses a technique for preparing a liquid crystal display device that can rewrite any one of all pixels and lowering the drive frequency of the display device. The driving frequency is selected according to the display color, or a moving image or a still image. It also discloses that the power consumption is optimized for each display image by changing the drive frequency between an image that is likely to cause flicker and an image that is less likely to occur regardless of whether it is a still image or a moving image. As for the display color, luminance is also taken into consideration. However, there is a need for a special liquid crystal display device that can rewrite any one of all pixels.

  JP-A-8-179269 distinguishes positive display with a bright background color and negative display with a dark background color from display data in order to prevent occurrence of flicker. In the positive display, the frame frequency is increased and the negative display is performed. Discloses reducing the frame frequency. However, only two stages, negative or positive, can be determined, and the specific timing for changing the frame frequency and the specific method for changing are not described in detail.

  An object of the present invention is to change the frequency of the video clock so as not to affect the display quality.

  Another object is to further reduce power consumption.

  In order to reduce the frequency of the video clock, the present invention performs the following steps. That is, a step of detecting an opportunity to lower the frequency of the video clock, and a frequency of the video clock within a range in which a circuit using the video clock (PLL (Phase Lock Loop) circuit in the embodiment) can follow the frequency fluctuation. The step of lowering and the step of lowering the frequency of the video clock are repeated until the frequency of the video clock changed by the step reaches a predetermined frequency. It is possible to prevent the display content from being disturbed due to the disturbed operation of the PLL circuit or the like.

  In another aspect of the invention, detecting the opportunity to reduce the frequency of the video clock to reduce the frequency of the video clock, and during the vertical blanking period of the display device using the video clock, Reducing the frequency of the video clock to a predetermined frequency and holding the reduced video clock frequency at the predetermined frequency until the video clock frequency needs to be changed. Even in a portable computer using a liquid crystal display device, there is a vertical blanking period in preparation for connection to a CRT. During this time, no display operation is performed. Therefore, if the frequency of the video clock is changed during this time, power saving can be achieved without causing any disturbance in the display content.

  In the third aspect of the present invention, in order to lower the frequency of the video clock, the step of detecting the timing for lowering the frequency of the video clock, and the display color on the screen of the display device are set to colors that make the flicker less noticeable The step of changing and the step of reducing the frequency of the video clock are performed. Conventionally, there has been a technique for changing the driving frequency based on the display color (Japanese Patent Laid-Open No. 9-5789). However, with this technique, the frequency of the video clock cannot be lowered forever. This is because, for example, in the environment of Windows 95 (trademark of Miscrosoft), display colors that make flicker stand out when the video clock frequency is lowered are often used. Cannot be achieved. Therefore, in order to achieve power saving, it is necessary to lower the video clock frequency after changing the display screen to a color in which flicker is not noticeable. This is considered to be particularly effective when the battery level of the portable computer is low while a relatively static application such as a word processor is being executed.

  An opportunity to lower the frequency of the video clock may be detected according to the type of application of the window displayed on the screen of the display device. For example, there is a case where an application whose display contents are not frequently changed is executed, and an application window whose display contents frequently change is not displayed in the foreground.

  It is also conceivable that the trigger is detected by changing the size of the window of interest displayed on the screen of the display device and specified in advance. For example, when the application window whose display contents change frequently is minimized, the frequency of the video clock can be lowered.

  Furthermore, it is conceivable that the trigger is detected by a change in user operation frequency. For example, when mouse or keyboard input is frequently performed, it is necessary to prevent the movement of the mouse cursor or the like from causing the user to feel stress, and thus the frequency of the video clock cannot be lowered. However, when the mouse or keyboard input is below a predetermined level, the video clock frequency can be lowered.

  The trigger can be detected by a change in processing contents of the processor. Usually, when the number of instructions executed by the processor decreases, the change in the display screen also decreases. Therefore, by detecting this, the frequency of the video clock can be lowered.

  It is also conceivable to lower the drive frequency of the video controller together with the video clock frequency. Some prior art discloses lowering the frequency of Mclk with the stop of the video clock, but this is not the case when performing a normal display operation. It does not show the decrease in the frequency of the video clock and the decrease in the drive frequency of the video controller during the normal display period, which is the main object of the present invention.

  The above is a description of the processing steps in the present invention, but the present invention can be implemented in a program or a circuit that executes the above processing steps, or a combination thereof. The program is stored in a storage medium such as a CD-ROM, a floppy disk, or a ROM.

  An example of the processing of the present invention will be described with reference to FIG. Here, an example of processing in a computer employing a window system that is widely used at present is shown. First, an opportunity to change the frequency of Vclk is detected (step 110). Specifically, the activation of an application or the like is detected by hooking a window message and inspecting the window message. A window message is related to the unit of work of the application that is processed by the window procedure. For example, by using SetWindowsHookEx (), which is an API (Application Program Interface) of Windows 95, a message filter function (hook function) for performing a specific process in response to a specific message can be introduced into the system. By using this function, you can monitor the essay sent to the window procedure using SendMessage () (hook with hook type WH_CALLWNDPROC), and the message immediately after calling GetMessage () or PeekMessage (). Can be monitored (hook type WH-GETMESSAGE hook). Active window switching can be detected by monitoring WM_ACTIVATE and WM_ACTIVEAPP messages.

  In the first embodiment, it is determined whether to change the frequency of Vclk according to the name of the application of the window displayed on the screen (step 120). If the frequency of Vclk is not changed, the process returns to step 110. In Windows 95, the window class is defined to be unique in the system for each window, and the name of the application can be easily found by using a correspondence table between the window class name and the application name. Even if the dialog box or the like is not registered in the correspondence table, the application name can be determined by following the ownership relationship of the windows and inspecting higher-order windows. This is described in detail below. When the window displayed on the screen is first examined, the application name can be known by examining the title or window class name of the window opened on the desktop. The window title can be found by using the Windows 95 API GetWindowText (). The window class name can also be obtained from the API GetClassName (). Further, in the second and subsequent processing of this step, by examining the window message, it is possible to know the application name such as a newly activated window or a terminated window.

  If the name of the application is known, it can be determined whether or not a high-speed Vclk is required depending on the nature of the application. That is, a game with a moving image or an application for displaying a video requires a high-speed Vclk, but a relatively static application such as a word processor or a spread sheet may use a Vclk that does not cause flicker. Therefore, as an example, it is conceivable that the frequency of Vclk is defined for each application, and the Vclk of the application that requires the fastest Vclk among the applications of the displayed window is adopted.

  As another example, applications that may be executed are classified into an application group that requires a high-speed Vclk and an application group that requires a low-speed Vclk, and all displayed applications are low-speed. If the application is acceptable for Vclk, the speed is changed to low speed Vclk. On the other hand, when a high-speed Vclk is required for an application to be displayed, a high-speed Vclk is adopted.

  Such a definition may be implemented by the user or may be registered in advance by the manufacturer for an application to be pre-installed when the computer is shipped.

  In the above, Vclk is specified for each application. However, when judging by the window class name, if an application has several windows or a child window is created, the application The question arises as to what is. At this time, by using GetWindow () and GetParent (), which are APIs of Windows 95, the caller's parent window can be examined from a child window such as a dialog box. This can be used to know the application name.

  In this way, when the frequency of Vclk is changed, there are cases where the frequency increases and decreases, and the processing differs depending on either (step 130). Naturally, when a new window for displaying a moving image or the like is generated on the screen or brought to the front, the frequency of Vclk must be increased (step 160). In this case, if the frequency of Vclk is not increased as soon as possible, flicker occurs or display content is interrupted, resulting in a decrease in usability.

  On the other hand, when the frequency of Vclk is decreased, the usability does not decrease even if the frequency is not decreased immediately. Therefore, the user is notified that the frequency of Vclk is to be lowered (step 140). This step is optional. The notification may be performed by displaying a pop-up window to the user or by voice. In addition to simply reducing the Vclk frequency, it is also possible to notify that the Vclk frequency can be further lowered by further changing the display color, thereby reducing the power consumption. When the frequency of Vclk is lowered, flicker occurs as a side effect. However, humans feel flicker only in specific cases, and there are color schemes that make flicker less likely to be felt. For example, colors and black and white created by combining only the three primary colors RGB (red, green, and blue) that do not include halftones are less likely to cause flicker. In addition, the color scheme called high contrast (white) in the screen design in Windows 95 hardly causes flicker. Therefore, the frequency of Vclk can be further lowered by changing the color of each part of the displayed window to a color combination that does not make flickering feel. FIG. 2 shows an outline of processing when color change is performed. Although the color may be changed without notifying the user, it may be misunderstood as a failure or the like, so it is preferable to notify at least once.

  The processing in FIG. 2 can be performed independently. For example, the trigger in FIG. 2 is that the user's command or user interaction has not been performed for a predetermined time, the screen update has not been performed for a predetermined time, It is conceivable that the noticed window that has been set is in the background.

  Then, a process of actually reducing the frequency of Vclk is performed (step 150). This process will be described in detail later. Then, it is determined whether or not the process is to be ended.

  In the above, the case where the frequency of Vclk is changed according to the application name of the window has been described, but this is not the only reason for changing the frequency of Vclk. For example, if it is possible to detect the frequency of user operation by hooking a window message related to the mouse or keyboard (WM_KEYDOWN message, WM_LBOTTONDOWN, etc.) When it is determined that the operation is not performed so much, it is conceivable to reduce the frequency of Vclk. Monitoring of mouse and keyboard events can be realized not only by window messages but also by monitoring hardware interrupts at the device driver level.

  Furthermore, a change in the size of a window, such as minimizing or maximizing a notable window specified in advance, can also be detected by monitoring the window message WM_SIZE. If the window of interest is, for example, an application window that displays a moving image, the frequency of Vclk may be lowered if the window becomes smaller than a predetermined size. Further, when the window of interest is an application window such as a word processor, when the window is maximized, the frequency of Vclk may be lowered.

  Further, it is possible to examine the bitmap of the entire desktop screen or the application window in the foreground, and set the Vclk frequency so as not to cause flicker depending on the contents.

  Further, a register called MSR (Model Specific Register) is prepared in the Pentium (trademark of Intel), and the number of execution instructions and the number of execution I / O instructions of the processor can be known from this register. By acquiring the number of execution instructions, the number of execution I / O instructions, and the like from the MSR, it is possible to detect the processing content, execution state, and load state of the processor. For example, when the number of execution instructions is small, the effective number of drawing instructions should normally be small, so the frequency of Vclk can be lowered. Therefore, it is possible to change the frequency of Vclk with the execution status of the processor as an opportunity.

  Then, before describing the process of actually reducing the frequency of Vclk (step 150), the configuration of the computer 1 will be described with reference to FIG. In the computer 1, a processor 3 and a video controller 7 are connected to a bus 5. The processor 3 may be connected to the bus 5 via a peripheral circuit. The bus 5 operates with a bus clock (Bus CLK). The video controller 7 is connected to the frame buffer 29 and LVDS 1 (Low Voltage Differential Signal 19). The video controller 7 is supplied with a base clock from the outside. The LVDS1 (19) connected to the video controller 7 is a transmission side, and is connected to the LVDS2 (25) on the reception side. The PLL3 (21) is connected to the LVDS1 (19), and the PLL4 (23) is connected to the LVDS2 (23). The output of the LVDS2 (25) is connected to the gate driver 31 and the data driver 33, and the LCD panel 27 is driven by the gate driver 31 and the data driver 33. Note that LVDS1 and LVDS2 can be replaced by equivalent devices such as PanelLink (trademark of Silicon Image Inc.) that serialize multi-bit pixel data and transmit it to the LCD panel 27.

  The video controller 7 includes PLL1 (9) and PLL2 (11), a bus interface 13, an LCD output circuit 17, and a control circuit 15 other than that. PLL1 (9) supplies the memory clock Mclk to the control circuit 15, PLL2 (11) supplies Vclk to the LCD output circuit 17, the control circuit 15 operates with Mclk, and the LCD output circuit 17 operates with Vclk. . The bus interface 13 operates with a bus clock. The bus interface 13 and the control circuit 15 are connected, and the control circuit 15 and the LCD output circuit 17 are connected.

  Now, the operation of the computer 1 in FIG. 3 will be described. The processor 1 transmits data and instructions necessary for drawing to the video controller 7 via the bus 5. The bus interface 13 of the video controller 7 communicates with the bus 5 and passes necessary information to the control circuit 15. The control circuit 15 performs reading / writing of the frame buffer 29, drawing processing, and control of the video controller 7. The control circuit 15 outputs the contents of the frame buffer 29 to the LCD output circuit 17 in order to periodically refresh the LCD panel 27. The LCD output circuit 17 outputs the displayed RGB data as Vclk, and also outputs a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync. LVDS1 (19) converts an RGB digital signal into one serial differential voltage signal for R, G, and B for transmission against EMI, and transmits a clock signal supplied from PLL3 (21). Is working with. On the other hand, the LVDS2 (25) on the receiving side receives the signal from the LVDS1 (19) and outputs RGB data to the data driver using Vclk. Further, the Hsync signal and the Vsync signal are output to the gate driver 31. Here, the LVDS2 (25) uses the clock signal from the PLL4 (23) in order to accurately capture the signal sent from the LVDS1 (19) and output the signal with Vclk.

  The operations of the data driver 33, the gate driver 31, and the LCD 27 are the same as usual, and the gate driver 31 scans the LCD panel 27 one by one on the gate line. Data is written to each gate line one by one, and necessary data is written to the LCD panel 27 as a whole.

  As described above, Vclk is used in the LCD output circuit 17, the LVDS1 (19) and the LVDS2 (25), and the data driver 33. In the configuration shown in FIG. 3, when the frequency of Vclk is lowered, the operation of PLL3 (21) and PLL4 (23) is affected. This is because PLL3 (21) oscillates using Vclk or a signal synchronized with Vclk. In particular, when the oscillation of the PLL3 (21) connected to the LVDS1 (19) is disturbed, the influence is exerted on the subsequent circuit. Therefore, if the oscillation of PLL3 (21) is not stable, the displayed image is also affected.

  Therefore, in the present invention, Vclk is changed so that it becomes a desired frequency little by little within a range that can be followed by PLL3 (21). This process is shown in FIG. As described above, the trigger for lowering the frequency of Vclk is detected (step 210), and the frequency of Vclk is lowered with a width that the PLL can follow (step 220). For example, in the case of a PLL that can follow up to a maximum of 5%, the frequency of Vclk is lowered by a width of 5% or less per time. For example, this step 220 is performed once per frame. The lowered Vclk frequency is repeated until a desired frequency is reached (step 230). Note that steps 220 and 230 can be performed by software or by the control circuit 15.

  By doing so, the oscillation of the PLL3 (21) is not disturbed, so that the confusion is not propagated to the circuits after the LVDS2 (23), the display content is not disturbed, and the usability is not deteriorated. Note that the PLL frequency is generally specified by three parameters of the numerator, denominator, and frequency divider. If the value to be set next is as close as possible to the current parameter configuration, each parameter becomes the phase of the PLL. A large oscillation of the PLL due to the time difference of the timing loaded in the detector can be suppressed. For example, if the refresh rate is 60 Hz with “numerator = 15, denominator = 23”, instead of setting “numerator = 30, denominator = 43” to achieve 59 Hz, approximately “numerator = 15, denominator = 22 "is preferred.

  FIG. 3 shows an example of the computer 1, which is an example of a computer having a particularly high resolution (for example, XGA). In the case of such a resolution, for example, Vclk is 65 MHz and Mclk is 84 MHz.

  Further, as shown in FIG. 5, it is also possible to configure a circuit after the computer 1 ′ video controller. Elements that are functionally similar to those depicted in FIG. 3 are given the same reference numerals. Here, the output of the LCD output circuit 17 is output to the data driver 33 and the gate driver 31 as they are. The output of the LCD output circuit 17 follows Vclk. A difference from the circuit of FIG. 3 is that the video controller 41 has a built-in frame buffer 29, but this is not a significant problem in the present invention. In such a configuration, the resolution is not as high as in the case of FIG. 3 and is, for example, about SVGA (800 × 600), for example, Vclk = 40 MHz and Mclk = 58 MHz.

  In the configuration as shown in FIG. 5, the RGB data of the LCD output circuit 17 is directly output to the data driver 33, and the Hsync signal and the Vsync signal are directly output to the gate driver 31. In such a configuration, it is not necessary to worry about the LVDS PLL, but if the Vclk frequency is lowered while the data driver 33 and the gate driver 31 are performing the drawing operation, the control circuit 15 changes the LCD. Data delivery to the output circuit 17 is disturbed, and as a result, display contents are disturbed. Therefore, in the present invention, Vclk is changed during the vertical blanking period. Since the Hsync signal Vsync signal is generated by dividing Vclk by a counter, it can follow Vclk as long as Vclk changes continuously.

  That is, even if the trigger for lowering the frequency of Vclk is detected (step 310 in FIG. 6), the frequency is not lowered immediately, the vertical blanking period is detected, and the frequency of Vclk is set to a predetermined frequency during that period. Lower (step 320). The frequency of Vclk is held until the next frequency change (step 330). Note that steps 320 and 330 may be implemented by software, or may be implemented by the control circuit 15.

  In more detail, step 320 is referred to as a front porch period and a back porch period before the Vsync signal during the vertical blanking period in FIG. 7, and preferably the Vclk frequency is changed during the front porch period. carry out. However, when implemented by software, only the timing of the Vsync signal may be known, so it may be changed to the back porch period so as not to disturb the Hsync signal. When it is performed by the control circuit 15 or when it is performed by another circuit, each timing can be detected.

  In addition, as described above, the frequency of Vclk is lower than the frequency of Mclk. Normally, Mclk is not only the bandwidth (frequency) required for Vclk but also the bandwidth required for frame buffer refresh and processor and video controller. Designed with width (frequency) added. Therefore, when the frequency of Vclk is lowered, there is a margin in Mclk. This margin can be allocated to the processor or video controller, but when the Vclk frequency is actually lowered, it is not a period in which drawing is frequently performed. Therefore, the amount of reduction in the Vclk frequency can reduce Mclk. Is possible. Furthermore, since it is not a period in which drawing is frequently performed, it is possible to reduce the frequency of Mclk more than the amount of reduction of the frequency of Vclk.

  The video clock could be changed so as not to affect the display quality.

  In addition, the power consumption could be further reduced.

It is a figure showing the processing flow of this invention. It is the figure which showed the detailed processing flow of step 130 of FIG. It is a figure of the 1st structural example of the computer in this invention. It is the figure which showed the detailed processing flow of step 140 of FIG. It is a figure of the 2nd structural example of the computer in this invention. It is the figure which showed the detailed processing flow of step 140 of FIG. (A) shows display timing, (b) is a figure showing a horizontal synchronizing signal, (c) is a figure showing a vertical synchronizing signal, and is a figure for demonstrating a front porch period and a back porch period. It is.

Explanation of symbols

1 Computer 3 Processor 5 Bus 7 Video Controller 9 PLL 1
11 PLL2
13 Bus interface 15 Control circuit 17 LCD output circuit 19 LVDS1
21 PLL3
23 PLL4
25 LVDS2
27 LCD panel 29 Frame buffer 31 Gate driver 33 Data driver 41 Video controller

Claims (4)

In a computer having a display device in which an LCD output circuit is directly connected to a data driver and a gate driver, a method of reducing the frequency of a video clock, which is a basic clock signal for displaying on the display device,
Detecting an opportunity to lower the frequency of the video clock;
In response to detecting the trigger, reducing the frequency of the video clock to a predetermined frequency during a vertical blanking period;
After performing the lowering step includes the step of holding the frequency of the video clock to the next frequency change,
A method in which the trigger is detected by changing the size of a window of interest that is displayed on a screen of a display device and specified in advance .   The method of claim 1, wherein lowering the video clock frequency comprises changing the video clock frequency during a front porch. A computer having a display device in which an LCD output circuit is directly connected to a data driver and a gate driver,
A detector for detecting an opportunity to lower a frequency of a video clock that is a basic clock signal for displaying on the display device;
In response to the detection of the trigger by the detector, a controller for lowering the video clock frequency to a predetermined frequency during a vertical blanking period and holding the video clock frequency until the next frequency change is provided. ,
A computer in which the trigger is displayed on a screen of a display device and detected by changing the size of a window of interest designated in advance . A recording in which a computer having a display device in which the LCD output circuit is directly connected to the data driver and the gate driver is recorded with a program for reducing the frequency of the video clock, which is a basic clock signal for display on the display device A medium, wherein the program is
Detecting an opportunity to lower the frequency of the video clock;
In response to detecting the trigger, reducing the frequency of the video clock to a predetermined frequency during a vertical blanking period;
After performing the step of lowering, holding the frequency of the video clock until the next frequency change;
To the computer ,
A recording medium in which the trigger is displayed on a screen of a display device and detected by changing the size of a window of interest designated in advance .

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