JP3882878B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, in particular, an SRAM and a manufacturing method thereof.
[0002]
[Background]
FIG. 32 is a plan view of a conventional SRAM memory cell disclosed in Japanese Patent Laid-Open No. 9-45796. Active regions 112a, 112b, 112c, and 112d are formed on the main surface of the silicon substrate 111. The source and drain regions of the active regions 112a and 112b are n-type, and those of the active regions 112c and 112d are p-type. The active regions 112a, 112b, 112c, and 112d are separated from other active regions by the field oxide region 113, respectively.
[0003]
The first conductive layer 116a extends from the active region 112c to the active region 112a. The first conductive layer 116a includes the load transistor Q ₆ And driver transistor Q _Four It becomes a gate electrode.
[0004]
The second conductive layer 116b branches from the first conductive layer 116a on the field oxide region 113 and extends in the direction of the active region 112b.
[0005]
The third conductive layer 116c passes from the active region 112b to the active region 112d, bends on the field oxide region 113, and extends in the direction of the active region 112c. The third conductive layer 116c includes the load transistor Q _Five And driver transistor Q _Three It becomes a gate electrode. Access transistor Q ₁ , Q ₂ The illustration is omitted.
[0006]
33 is a cross-sectional view taken along line AA of the SRAM memory cell in FIG. In the silicon substrate 111, a p-type well 110a and an n-type well 110b are formed. An active region 112a is formed in the p-type well 110a, and an active region 112c is formed in the n-type well 110b. The active region 112a and the active region 112c are separated by a field oxide region 113.
[0007]
A second conductive layer 116 b is formed on the field oxidation region 113. A sidewall insulating film 117 is formed on the side surface of the second conductive layer 116b.
[0008]
[Problems to be solved by the invention]
The conventional SRAM shown in FIG. 32 has two problems. First, the first problem will be explained.
[0009]
The SRAM shown in FIG. 32 is formed by laminating a conductive layer or an insulating layer on the main surface of the silicon substrate 111. For this lamination, a mask alignment process is indispensable. In the mask alignment process, there is a possibility that a mask alignment shift will occur. FIG. 34 is a plan view of the memory cell when the mask alignment is shifted in the y-axis direction when forming the first conductive layer 116a, the second conductive layer 116b, and the third conductive layer 116c. 35 is a cross-sectional view taken along the line AA of the SRAM memory cell in FIG.
[0010]
Referring to FIGS. 34 and 35, a part of second conductive layer 116b and sidewall insulating film 117 overlap with a region that should originally become active region 112a. For this reason, the driver transistor Q _Four The gate width of the gate electrode is W by design, but actually becomes w smaller than W. Therefore, an imbalance occurs in the β ratio (capacity ratio between the driver transistor and the transfer transistor) of the memory cell, and the characteristics of the SRAM deteriorate.
[0011]
Therefore, the mask misalignment must be taken into consideration when designing the layout of the SRAM. That is, referring to FIG. 33, even if mask misalignment occurs, the width of field oxide region 113 is sufficiently large so that second conductive layer 116b and sidewall insulating film 117 are positioned on field oxide region 113. Must be bigger. However, this is contrary to the demand for miniaturization of memory cells.
[0012]
Next, the second problem will be described. FIG. 36 shows the end of the active region 112c of FIG. The active region 112c is a region surrounded by a solid line 119 by design. However, because of the bird's beak 118, the active region 112c is actually a region surrounded by a dotted line 120. In particular, since the active region is narrow at the end of the active region 112c and oxidation is performed from three directions during LOCOS oxidation, the effective active region becomes small as shown in FIG. The active region 112c is in contact with the upper layer wiring. Therefore, when the area of the active region 112c is reduced, a margin is reduced when contacting the upper layer wiring.
[0013]
The present invention has been made to solve the above-described problems, and provides a semiconductor memory device capable of miniaturizing a memory cell without causing an imbalance in the β ratio of the memory cell and a method for manufacturing the same. The task is to do.
[0014]
In addition to the above object, an object of the present invention is to provide a semiconductor memory device that can satisfactorily make contact with an upper layer wiring and a manufacturing method thereof.
[0015]
[Means for Solving the Problems]
The present invention is a semiconductor memory device having memory cells including first and second load transistors and first and second driver transistors, a semiconductor substrate having a main surface, a first substrate formed on the main surface, A first load transistor active region serving as an active region of the load transistor, a second load transistor active region formed on the main surface and serving as an active region of the second load transistor, and formed on the main surface. A first driver transistor active region serving as an active region of the driver transistor; a second driver transistor active region formed on the main surface; and a second driver transistor active region serving as an active region of the second driver transistor; A first element isolation region that separates the load transistor active region from the first driver transistor active region, and a first load transistor A first conductive layer extending from the transistor active region to the first driver transistor active region and serving as a gate electrode of the first load transistor and the first driver transistor, and a first conductive layer on the first element isolation region. And a second conductive layer branched from the conductive layer and electrically connected to the second driver transistor active region. The width of the second conductive layer located on the first element isolation region is smaller than the width of the first conductive layer. Furthermore, the present invention is electrically connected to the first load transistor active region, passes over the second load transistor active region, and further extends to the second driver transistor active region. And a third conductive layer to be a gate electrode of the second driver transistor.
[0016]
The width of the second conductive layer located on the first element isolation region of the semiconductor memory device according to the present invention is smaller than the width of the first conductive layer. Therefore, the width of the second conductive layer can be made smaller than when the width of the second conductive layer located on the first element isolation region is the same as or larger than the width of the first conductive layer. Since the width of the second conductive layer can be reduced, even if the mask misalignment in forming the first conductive layer, the second conductive layer, and the third conductive layer is taken into consideration, the first element isolation region The width can be reduced. Therefore, according to the present invention, the memory cell can be miniaturized without causing an imbalance in the β ratio of the memory cell.
[0017]
The present invention is a semiconductor memory device having memory cells including first and second load transistors and first and second driver transistors, a semiconductor substrate having a main surface, a first substrate formed on the main surface, A first load transistor active region serving as an active region of the load transistor, a second load transistor active region formed on the main surface and serving as an active region of the second load transistor, and formed on the main surface. A first driver transistor active region serving as an active region of the driver transistor; a second driver transistor active region formed on the main surface; and a second driver transistor active region serving as an active region of the second driver transistor; A first element isolation region that separates the load transistor active region from the first driver transistor active region, and a first load transistor A first conductive layer extending from the transistor active region to the first driver transistor active region and serving as a gate electrode of the first load transistor and the first driver transistor, and a first conductive layer on the first element isolation region. And a second conductive layer branched from the conductive layer and electrically connected to the second driver transistor active region. The width of the second conductive layer located on the first element isolation region is the minimum dimension width in the processing dimension rule of the second conductive layer. Furthermore, the present invention is electrically connected to the first load transistor active region, passes over the second load transistor active region, and further extends to the second driver transistor active region. And a third conductive layer to be a gate electrode of the second driver transistor.
[0018]
In the semiconductor memory device according to the present invention, the width of the second conductive layer located on the first element isolation region is the minimum dimension width according to the processing dimension rule of the second conductive layer. Therefore, the width of the first element isolation region can be reduced even when the mask misalignment when forming the first conductive layer, the second conductive layer, and the third conductive layer is taken into consideration.
[0019]
The semiconductor memory device according to the present invention includes a sidewall insulating film formed on a side surface of the second conductive layer on the first driver transistor active region side, and is located on the first element isolation region. The distance between the second conductive layer and the first driver transistor active region is the sum of the alignment error value and the width of the sidewall insulating film when the first, second, and third conductive layers of the memory cell are patterned. Larger is preferred.
[0020]
In this way, it is possible to prevent the second conductive layer and the sidewall insulating film from being positioned on the first driver transistor active region. As described above, when the second conductive layer and the sidewall insulating film are located on the first driver transistor active region, the gate width of the gate electrode of the first driver transistor becomes smaller than the design value. As a result, the β ratio of the memory cells is unbalanced, and the characteristics of the semiconductor memory device are deteriorated.
[0021]
In the semiconductor memory device according to the present invention, the distance between the second conductive layer located on the first element isolation region and the first load transistor active region is the second distance located on the first element isolation region. The distance between the conductive layer and the first driver transistor active region is preferably smaller.
[0022]
When the second conductive layer and the sidewall insulating film are located on the first driver transistor active region, the β ratio of the memory cell is affected. Even if the second conductive layer and the sidewall insulating film are located on the first load transistor active region and the gate width of the load transistor is reduced, the β ratio of the memory cell is not affected. For this reason, the distance between the second conductive layer and the first load transistor active region can be made smaller than the distance between the second conductive layer and the first driver transistor active region. Therefore, the width of the first element isolation region can be reduced and the memory cell can be miniaturized.
[0023]
In the semiconductor memory device according to the present invention, the pattern of the first and second conductive layers is preferably h-shaped, and the pattern of the third conductive layer is preferably 7-shaped. The h shape means that the pattern of the first and second conductive layers has an alphabetic “h” shape, and the 7 shape means that the pattern of the third conductive layer has a numeric “7” shape. It is.
[0024]
In the semiconductor memory device according to the present invention, the width of the active region of the contact region electrically connected to the third conductive layer in the first load transistor active region is preferably larger than the width of other portions. .
[0025]
In this way, the area of the contact region can be increased, and even if a bird's beak is formed, the area of the contact region can be made an area capable of contacting the upper layer wiring.
[0026]
In the semiconductor memory device according to the present invention, a memory cell array including the memory cells is formed on the main surface, and a second element for separating the memory cells in the first row and the memory cells in the second row of the memory cell array The pattern of the first, second and third conductive layers of the memory cells in the second row is provided with an isolation region, and the pattern of the first, second and third conductive layers of the memory cells in the first row is A pattern rotated by 180 degrees around an axis perpendicular to the main surface is preferred.
[0027]
In this way, punch-through between the first and second load transistor active regions of the memory cells in the first row and the first and second load transistor active regions of the memory cells in the second row is performed. Can be prevented.
[0028]
In the semiconductor memory device according to the present invention, a memory cell array including the memory cells is formed on the main surface, and a second element for separating the memory cells in the first row and the memory cells in the second row of the memory cell array A pattern of first, second and third conductive layers of the memory cells in the second row, and a pattern of first, second and third conductive layers of the memory cells in the first row; Are preferably mirror images. If the mirror image is used, the pattern becomes simple, and the margin for mask displacement (left and right direction) can be increased.
[0029]
A method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device having memory cells including first and second load transistors and first and second driver transistors, the main surface of the semiconductor substrate Forming a device isolation region, a first load transistor active region, a second load transistor active region, a first driver transistor active region, and a second driver transistor active region, and a conductive layer covering the main surface. Forming the conductive layer, and patterning the conductive layer to form first, second, and third conductive layers. The first conductive layer extends from the first load transistor active region to the first driver transistor active region, and the first conductive layer becomes a gate electrode of the first load transistor and the first driver transistor, The second conductive layer is branched from the first conductive layer on the element isolation region and extends to the second driver transistor active region, and the second conductive layer is located on the element isolation region. The width is smaller than the width of the first conductive layer, the third conductive layer extends from the second load transistor active region to the second driver transistor active region, and the third conductive layer is the second conductive layer. It becomes the gate electrode of the load transistor and the second driver transistor. The method of manufacturing a semiconductor memory device further includes a step of electrically connecting the second conductive layer to the second driver transistor active region and a third conductive layer electrically connecting to the first load transistor active region. And a step of performing.
[0030]
In the method of manufacturing a semiconductor memory device according to the present invention, it is preferable to include a step of forming a sidewall insulating film on the side surface of the second conductive layer on the first driver transistor active region side.
[0031]
In the method of manufacturing a semiconductor memory device according to the present invention, the step of patterning the conductive layer may be performed by determining whether the distance between the second conductive layer located on the first element isolation region and the first driver transistor active region is a memory. It is preferable that the value be larger than the sum of the alignment error value at the time of pattern formation of the first, second and third conductive layers of the cell and the width of the sidewall insulating film.
[0032]
In the method of manufacturing a semiconductor memory device according to the present invention, in the step of patterning the conductive layer, the width of the second conductive layer located on the element isolation region is set to the minimum dimension width on the processing dimension rule of the second conductive layer. It is preferable that
[0033]
In the method of manufacturing a semiconductor memory device according to the present invention, in the step of patterning the conductive layer, the distance between the second conductive layer located on the first element isolation region and the first load transistor active region is It is preferable that the distance is smaller than the distance between the second conductive layer located on one element isolation region and the first driver transistor active region.
[0034]
In the method of manufacturing a semiconductor memory device according to the present invention, the step of forming the first load transistor active region includes the step of forming a contact region electrically connected to the third conductive layer in the first load transistor active region. It is preferable that the width of the active region be larger than the width of other portions.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
{Description of planar structure}
FIGS. 1 and 16 are plan views showing a part of the SRAM memory cell array according to the first embodiment of the present invention. FIG. 1 shows an element formation layer. FIG. 16 shows a wiring layer formed on the element formation layer of FIG. First, the structure shown in FIG. 1 will be described in order from the lower layer with reference to FIGS.
[0036]
FIG. 2 is a plan view showing patterns of the p-type well 10a, the n-type well 10b, and the p-type well 10c. FIG. 3 is a plan view showing a state in which patterns of the p-type well 10a, the n-type well 10b, and the p-type well 10c are formed on the main surface of a silicon substrate 28 that is an example of a semiconductor substrate.
[0037]
FIG. 4 is a plan view showing patterns of the active regions 12a to 12i and the field oxide region 13. As shown in FIG. Each of the active regions 12a to 12i is separated from other active regions by a field oxide region 13. FIG. 5 is a plan view showing a state in which the pattern shown in FIG. 4 is formed on the main surface of the silicon substrate 28 shown in FIG.
[0038]
FIG. 6 is a plan view showing patterns of the first conductive layer 16a, the second conductive layer 16b, and the third conductive layer 16c in the word lines 14a and 14b and the four memory cell formation regions 15a to 15d. The word lines 14a and 14b, the first conductive layer 16a, the second conductive layer 16b, and the third conductive layer 16c are made of, for example, polysilicon. The first conductive layer 16a and the second conductive layer 16b form an “h” shape, and the third conductive layer 16c forms a “7” shape.
[0039]
Patterns of the first conductive layer 16a, the second conductive layer 16b, and the third conductive layer 16c in the memory cell formation region 15a and the first conductive layer 16a, the second conductive layer 16b, and the second conductive layer 16b in the memory cell formation region 15b The pattern of the third conductive layer 16c has a mirror image relationship. Further, the pattern of the first conductive layer 16a, the second conductive layer 16b, and the third conductive layer 16c in the memory cell formation region 15c and the first conductive layer 16a and the second conductive layer 16b in the memory cell formation region 15d. The pattern of the third conductive layer 16c has a mirror image relationship.
[0040]
FIG. 7 is a plan view showing a state in which the pattern shown in FIG. 6 is formed on the main surface of the silicon substrate 28 shown in FIG. Focusing on the memory cell formation region 15a, the arrangement relationship of the first conductive layer, the second conductive layer, the third conductive layer, and the word line with respect to the active region will be described. The first conductive layer 16a extends from the active region 12d to the active region 12a, and the load transistor Q ₆ And driver transistor Q _Four It becomes a gate electrode.
[0041]
The second conductive layer 16b branches from the first conductive layer 16a on the field oxide region 13, and is electrically connected to the active region 12b through the contact hole 18b. The width of the second conductive layer 16b located on the field oxide region 13 is smaller than the width of the first conductive layer 16a.
[0042]
The third conductive layer 16c is electrically connected to the active region 12d through the contact hole 18a, passes over the active region 12e, and further extends onto the active region 12b. The third conductive layer 16c includes a load transistor Q _Five And driver transistor Q _Three It becomes a gate electrode.
[0043]
The word line 14a extends from the active region 12a to the active region 12b, and the transfer transistor Q ₂ And Q ₁ It becomes a gate electrode. Since the arrangement relationship of the first conductive layer, the second conductive layer, the third conductive layer, and the word line with respect to the active regions of the memory cell formation regions 15b to 15d is the same as that in the memory cell formation region 15a, the description thereof is omitted. .
[0044]
FIG. 1 shows active regions 12 a to 12 on the main surface of the silicon substrate 28 shown in FIG. 7 using the word lines 14 a and 14 b and the first conductive layer 16 a, the second conductive layer 16 b and the third conductive layer 16 c as masks. It is a top view which shows the state which formed the source region and the drain region in 12i. The hatched regions of the active regions 12a to 12i are a source region and a drain region. The source and drain regions of the active regions 12a to 12c and 12g to 12i are n-type, and the source and drain regions of the active regions 12d to 12f are p-type.
[0045]
The first conductive layer, the second conductive layer, the third conductive layer, the word line, and the contact hole of these memory cells are formed by the following process. After forming the structure shown in FIG. 5, a conductive layer such as polysilicon covering the main surface of the silicon substrate is formed. Next, the conductive layer is patterned to form a first conductive layer, a second conductive layer, a third conductive layer, and a word line. Using the first conductive layer, the second conductive layer, the third conductive layer, and the word line as a mask, ions are implanted into the main surface of the silicon substrate to form a source region and a drain region. An insulating layer such as a silicon oxide film covering the main surface of the silicon substrate is formed. A contact hole for electrically connecting the second conductive layer to the active region of the second driver transistor and a contact hole for electrically connecting the third conductive layer to the first load transistor active region Are formed in the insulating layer.
[0046]
The description of the structure shown in FIG. 1 is as described above. Next, the structure shown in FIG. 16 will be described in order from the bottom layer with reference to FIGS.
[0047]
FIG. 8 is a plan view showing patterns of the contact holes 18a to 18j. FIG. 9 is a plan view showing a pattern of local wiring composed of the drain connection wirings 30 a and 30 b and the contact pad 32. FIG. 10 is a plan view showing a state where the patterns shown in FIGS. 8 and 9 are formed on the main surface of the silicon substrate 28 shown in FIG. However, portions other than the active regions 12a to 12i in the structure shown in FIG. 1 are omitted. Also, the hatched lines indicating the source and drain regions of the active regions 12a to 12i are omitted. Some of the plurality of contact holes shown in FIG. 8 are omitted. The contact pads 32 shown in FIG. 9 are omitted.
[0048]
Referring to FIG. 10, the drain connection wiring electrically connects the drain regions of the active region. For example, paying attention to the drain connection wiring 30a, the drain connection wiring 30a is electrically connected to the drain region of the active region 12a through the contact hole 18c, and is electrically connected to the drain region of the active region 12d through the contact hole 18a. .
[0049]
FIG. 11 is a plan view showing patterns of the contact holes 40a to 40f. FIG. 12 is a plan view showing a pattern of a wiring layer composed of the wirings 34 a to 34 e and the contact pads 36. The wirings 34a to 34e and the contact pads 36 are made of, for example, aluminum or an aluminum alloy obtained by mixing copper or the like with aluminum. FIG. 13 is a plan view showing a state in which the patterns shown in FIGS. 11 and 12 are formed on the main surface of the silicon substrate 28 shown in FIG. However, the contact holes 40c and 40d shown in FIG. 11 and the contact pad 36 shown in FIG. 12 are omitted.
[0050]
The wirings 34a to 34e are electrically connected to the source region of the active region. For example, when attention is paid to the wiring 34a, the wiring 34a is electrically connected to the source region of the active region 12a through the contact pad 32 (not shown) in the contact portion 40a. Here, the wiring 34a is electrically connected to the ground line Vss. When attention is paid to the wiring 34c, the wiring 34c is electrically connected to the source region of the active region 12d through a contact pad 32 (not shown) in the contact portion 40b. Here, the wiring 34c is connected to the power source V. _DD And are electrically connected.
[0051]
FIG. 14 is a plan view showing patterns of the via holes 42a and 42b. FIG. 15 is a plan view showing patterns of the bit lines 38a to 38d. The bit lines 38a to 38d are made of, for example, aluminum or an aluminum alloy obtained by mixing copper with aluminum.
[0052]
FIG. 16 is a plan view showing a state in which the patterns shown in FIGS. 14 and 15 are formed on the main surface of the silicon substrate 28 shown in FIG. Bit lines 38a to 38d are electrically connected to the active region. For example, when attention is paid to the bit line 38a, the bit line 38a is electrically connected to the active region 12a through the via hole 42a, the contact pad 36 (not shown), the contact hole 40c, the contact pad 32, and the contact hole 18i. .
[0053]
{Description of equivalent circuit}
FIG. 17 is an equivalent circuit diagram of the SRAM memory cell shown in FIGS. Load transistor Q _Five And driver transistor Q _Three And an inverter, and load transistor Q ₆ And driver transistor Q _Four And an inverter. These inverters are electrically connected to form a flip-flop.
[0054]
Transfer transistor Q ₂ Source / drain of the load transistor Q ₆ And driver transistor Q _Four Are electrically connected to the output of the inverter and the bit line BL. Transfer transistor Q ₂ The gate electrode is electrically connected to the word line WL.
[0055]
Load transistor Q _Five And Q ₆ The source of the power supply V _DD Is electrically connected. Driver transistor Q _Three And Q _Four Source of ground wire V _SS Is electrically connected.
[0056]
Transfer transistor Q ₁ Source / drain of the load transistor Q _Five And driver transistor Q _Three Are electrically connected to the output of the inverter and the bit line (/ BL). Transfer transistor Q ₁ The gate electrode is electrically connected to the word line WL.
[0057]
{Description of cross-sectional structure}
FIG. 18 is a cross-sectional view of the SRAM memory cell shown in FIGS. 1 and 16 taken along line AA.
[0058]
A p-type well 10 a and an n-type well 10 b are formed on the main surface of the silicon substrate 28. An active region 12a is formed in the p-type well 10a, and an active region 12d is formed in the n-type well 10b. The active region 12a and the active region 12d are separated by a field oxide region 13 which is a field oxide film.
[0059]
A gate electrode 44 is formed on the active region 12a. The gate electrode 44 is formed of the transfer transistor Q shown in FIG. ₂ Part of the word line 14a. A second conductive layer 16 b is formed on the field oxide region 13. Sidewall insulating films 48a and 48b are formed on the side surfaces of the second conductive layer 16b.
[0060]
An interlayer insulating film 25 made of, for example, a silicon oxide film is formed on the main surface of the silicon substrate 28 so as to cover the gate electrode 44, the second conductive layer 16b, and the like. Contact holes 18 a, 18 c and 18 i are formed in the interlayer insulating film 25. The contact hole 18i exposes the source / drain region of the active region 12a, the contact hole 18c exposes the drain region of the active region 12a, and the contact hole 18a exposes the drain region of the active region 12d.
[0061]
On the interlayer insulating film 25, a drain connection wiring 30a and a contact pad 32 are formed. One end of the drain connection wiring 30a is electrically connected to the drain region of the active region 12a through the contact hole 18c. The other end of the drain connection wiring 30a is electrically connected to the drain region of the active region 12d through the contact hole 18a. Contact pad 32 is electrically connected to the source / drain region of active region 12a through contact hole 18i.
[0062]
An interlayer insulating film 29 made of, for example, a silicon oxide film is formed so as to cover the drain connection wiring 30a and the contact pad 32.
[0063]
On the interlayer insulating film 29, wirings 34a, 34b, 34c and contact pads 36 are formed. A contact hole 40 c that exposes the contact pad 32 is formed in the interlayer insulating film 29. The contact pad 36 is electrically connected to the contact pad 32 through the contact hole 40c.
[0064]
An interlayer insulating film 35 made of, for example, a silicon oxide film is formed so as to cover the wirings 34a, 34b, 34c and the contact pads 36. A contact hole 42a for exposing the contact pad 36 is formed in the interlayer insulating film 35.
[0065]
A bit line 38 a is formed on the interlayer insulating film 35. Bit line 38a is electrically connected to contact pad 36 through contact hole 42a. Therefore, the bit line 38a is electrically connected to the source / drain region of the active region 12a via the contact holes 42a, 40c, 18i.
[0066]
{Description of effect}
(Effect 1)
Referring to FIG. 1, in the first embodiment, the width W of second conductive layer 16b located on field oxide region 13 is shown. ₁ Is the width W of the first conductive layer 16a. ₂ Smaller than. Therefore, the width W of the second conductive layer 16b positioned on the field oxide region 13 correspondingly. ₁ Can be reduced. Therefore, the field misalignment in the formation of the first conductive layer, the second conductive layer, and the third conductive layer is taken into consideration so as not to cause an unbalance in the β ratio of the memory cell. Width W of oxidized region 13 _Three Can be reduced. As described above, according to the first embodiment, the memory cell can be miniaturized without causing an imbalance in the β ratio of the memory cell.
[0067]
(Effect 2)
Referring to FIG. 18, in the first embodiment, a distance L between second conductive layer 16b located on field oxide region 13 and active region 12a. ₁ Are the alignment error value Ae and the width W of the sidewall insulating film 48a during pattern formation of the first, second and third conductive layers. _Four And is greater than the sum. For example, L ₁ Is 0.25 μm, Ae is 0.1 μm, W _Four Is 0.1 μm.
[0068]
In this way, it is possible to reliably prevent the second conductive layer 16b and the sidewall insulating film 48a from being positioned on the active region 12a. When the second conductive layer 16b and the sidewall insulating film 48a are located on the active region 12a, the driver transistor Q shown in FIG. _Four The gate width is smaller than the design value. As a result, the β ratio of the memory cell is unbalanced, and the characteristics of the SRAM are deteriorated.
[0069]
(Effect 3)
FIG. 19 shows the end 39 of the active region 12d shown in FIG. At the end 39, the drain connection wiring 30a shown in FIG. 18 is electrically connected, or the third conductive layer 16c shown in FIG. 1 is electrically connected.
[0070]
The active region 12d is a region surrounded by the solid line 41 by design. However, because of the bird's beak 46, the active region 12 d is actually a region surrounded by a dotted line 43.
[0071]
In the first embodiment, the width W of the end portion 39. _Five Is the width W of the other part ₆ Has been bigger. In this way, the area of the end 39 can be increased, and even if the bird's beak 46 is formed, the area of the end 39 can be satisfactorily brought into contact with the drain connection wiring 30a and the third conductive layer 16c. Can be.
[0072]
[Second Embodiment]
FIG. 20 is a plan view showing a part of the element formation layer of the SRAM memory cell array according to the second embodiment of the present invention. FIG. 21 is a cross-sectional view of the SRAM memory cell shown in FIG. 20, taken along line AA.
[0073]
The difference from the first embodiment is the position of the second conductive layer 16b. Since the structure other than this is the same as the structure of the first embodiment, the description is omitted by giving the same reference numerals.
[0074]
Referring to FIG. 18, in the first embodiment, the distance L between the second conductive layer 16b and the active region 12d. ₂ Is the distance L between the second conductive layer 16b and the active region 12a. ₁ And the same.
[0075]
On the other hand, referring to FIG. 21, in the second embodiment, the distance L between the second conductive layer 16b and the active region 12d. ₂ Is the distance L between the second conductive layer 16b and the active region 12a. ₁ Have been smaller.
[0076]
The second conductive layer 16b and the sidewall insulating film 48b are located on the active region 12d, and the load transistor Q shown in FIG. ₆ Even if the gate width is reduced, the β ratio of the memory cell is not affected. Therefore, the distance L between the second conductive layer 16b and the active region 12d ₂ Is the distance L between the second conductive layer 16b and the active region 12a. ₁ Can be smaller. Therefore, the width W of the field oxide region 13 _Three And the memory cell can be miniaturized.
[0077]
In the second embodiment, since the structure other than the position of the second conductive layer 16b is the same as the structure of the first embodiment, the effects 1 to 3 of the first embodiment described above are obtained. Arise.
[0078]
[Third Embodiment]
{Description of planar structure}
FIG. 22 is a plan view showing a part of an SRAM memory cell array according to the third embodiment of the present invention, and shows an element formation layer. The structure shown in FIG. 22 will be described in order from the lower layer with reference to FIGS.
[0079]
FIG. 23 is a plan view showing patterns of the active regions 52a to 52i and the field oxide region 53. As shown in FIG. Each of the active regions 52a to 52i is separated from other active regions by a field oxide region 53. The difference from the pattern shown in FIG. 4 is the shape of the active regions 52d to 52i. That is, the positions of the contact region 57 with the third conductive layer and the contact region 59 with the second conductive layer are different.
[0080]
FIG. 24 is a plan view showing a state in which the pattern shown in FIG. 23 is formed on the main surface of the silicon substrate 68 on which the patterns of the p-type well 50a, the n-type well 50b, and the p-type well 50c are formed.
[0081]
FIG. 25 is a plan view showing patterns of the first conductive layer 56a, the second conductive layer 56b, and the third conductive layer 56c in the word lines 54a and 54b and the memory cell formation regions 55a to 55d. The word lines 54a and 54b, the first conductive layer 56a, the second conductive layer 56b, and the third conductive layer 56c are made of, for example, polysilicon. The first conductive layer 56a and the second conductive layer 56b form an “h” shape, and the third conductive layer 56c forms a “7” shape.
[0082]
The patterns of the first conductive layer 56a, the second conductive layer 56b, and the third conductive layer 56c in the memory cell formation regions 55b and 55d in the second row of the memory cell array are in the first row of the memory cell array. The pattern of the first conductive layer 56a, the second conductive layer 56b, and the third conductive layer 56c in the memory cell formation regions 55a and 55c is an axis perpendicular to the surface on which the pattern is formed (the main surface of the silicon substrate 68). The pattern is rotated 180 degrees around the center.
[0083]
26 is a plan view showing a state in which the pattern shown in FIG. 25 is formed on the main surface of the silicon substrate 68 shown in FIG. The arrangement relationship of the first conductive layer, the second conductive layer, the third conductive layer, and the word line with respect to the active regions of the memory cell formation regions 55a and 55c is the same as that of the memory cell formation regions 15a and 15c shown in FIG. It is. The arrangement relationship of the first conductive layer, the second conductive layer, the third conductive layer, and the word line with respect to the active regions of the memory cell formation regions 55b and 55d is different from that of the memory cell formation regions 15b and 15d shown in FIG. . The difference will be described by paying attention to the memory cell formation region 55b.
[0084]
The first conductive layer 56a extends from the active region 52e to the active region 52h, and the load transistor Q ₆ And driver transistor Q _Four It becomes a gate electrode.
[0085]
The second conductive layer 56 b branches from the first conductive layer 56 a on the field oxide region 53 and is electrically connected to the contact region 59 through the contact hole 58 b. The width of the second conductive layer 56b located on the field oxide region 53 is smaller than the width of the first conductive layer 56a.
[0086]
In the contact region 57, the third conductive layer 56c is electrically connected through the contact hole 58a, passes over the active region 52d, and further extends onto the active region 52g. The third conductive layer 56c includes a load transistor Q _Five And driver transistor Q _Three It becomes a gate electrode.
[0087]
The word line 54b extends from the active region 52h to the active region 52g, and the transfer transistor Q ₂ And Q ₁ It becomes a gate electrode.
[0088]
FIG. 22 shows active regions 52a to 52d on the main surface of the silicon substrate 68 shown in FIG. 26 using the word lines 54a and 54b and the first conductive layer 56a, the second conductive layer 56b, and the third conductive layer 56c as masks. It is a top view which shows the state which formed the source region and the drain region in 52i. The hatched regions of the active regions 52a to 52i are a source region and a drain region. The source and drain regions of the active regions 52a to 52c and 52g to 52i are n-type, and the source and drain regions of the active regions 52d to 52f are p-type. The description of the structure shown in FIG. 22 is as described above. The wiring formed on the element formation layer shown in FIG. 22 has the same structure as the wiring of the first embodiment shown in FIG.
[0089]
{Description of cross-sectional structure}
27 is a cross-sectional view of the SRAM memory cell shown in FIG. 22 taken along line BB. FIG. 28 is a cross-sectional view of the SRAM memory cell shown in FIG. 22 taken along line CC.
[0090]
27 and 28, a p-type well 50a, an n-type well 50b, and a p-type well 50c are formed on the main surface of the silicon substrate 68. Active regions 52d and 52e are formed in the n-type well 50b. The active regions 52d and 52e are separated into two regions by a field oxide region 53.
[0091]
Referring to FIG. 27, a third conductive layer 56 c is formed on active region 52 d, and a part of third conductive layer 56 c is located on field oxide region 53. A second conductive layer 56b is formed on the field oxide region 53 at the boundary between the n-type well 50b and the p-type well 50a.
[0092]
Referring to FIG. 28, a third conductive layer 56 c is formed on active region 52 e, and a part of third conductive layer 56 c is located on field oxide region 53. A second conductive layer 56b is formed on the field oxide region 53 at the boundary between the n-type well 50b and the p-type well 50c.
[0093]
{Description of effect}
The third embodiment has the same effects (effects 1 to 3) as the first embodiment, and also has the specific effects described below.
[0094]
Referring to FIG. 22, the pattern of first conductive layer 56a, second conductive layer 56b, and third conductive layer 56c in memory cell formation region 55b is the same as that of first conductive layer 56a in memory cell formation region 55a. The patterns of the second conductive layer 56 b and the third conductive layer 56 c are rotated by 180 degrees about an axis perpendicular to the main surface of the silicon substrate 68. With this structure, punch-through can be prevented in the regions indicated by D and E below the field oxidation region 53.
[0095]
That is, the active region 52d of the memory cell formation region 55b and the active region 52d of the memory cell formation region 55a are opposed to each other at a region indicated by D. In the active region 52d of the memory cell formation region 55b, the third conductive layer 56c of the memory cell formation region 55b is located in the entire region facing the active region 52d of the memory cell formation region 55a. For this reason, referring to FIG. 27, a region between the source or drain of the memory cell formation region 55b (region indicated by hatching) and a region serving as the source or drain of the memory cell formation region 55a (region indicated by hatching). Includes a third conductive layer 56c in addition to the field oxidation region 53, and accordingly the distance L _Three Can be long. The same applies to the region indicated by E in FIGS.
[0096]
FIG. 29 is a cross-sectional view of the SRAM memory cell shown in FIG. 1 taken along line BB. FIG. 30 is a cross-sectional view of the SRAM memory cell shown in FIG. 1 taken along line CC. With this structure, punch-through can be prevented in the region indicated by E under the field oxidation region 53. However, punch-through is likely to occur in the region indicated by D below the field oxidation region 53.
[0097]
That is, referring to FIG. 1, active region 12e in memory cell formation region 15b and active region 12e in memory cell formation region 15a are opposed to each other in a region indicated by E. Of the active region 12e of the memory cell formation region 15b, the third conductive layer 16c of the memory cell formation region 15b is located in the entire region facing the active region 12e of the memory cell formation region 15a. The third conductive layer 16c of the memory cell formation region 15a is located in the entire region of the active region 12e of the memory cell formation region 15a that faces the active region 12e of the memory cell formation region 15b. For this reason, referring to FIG. 30, the region between the source or drain of the memory cell formation region 15b (the region indicated by hatching) and the region serving as the source or drain of the memory cell formation region 15a (the region indicated by hatching) Since there are two third conductive layers 16c in addition to the field oxidation region 13, the distance L is accordingly increased. _Four L shown in FIG. _Four Can be longer than
[0098]
However, referring to FIG. 1, the active region 12d of the memory cell formation region 15b and the active region 12d of the memory cell formation region 15a face each other in a region indicated by D. Of the active region 12d of the memory cell formation region 15b, the third conductive layer 16c of the memory cell formation region 15b is not located in the entire region facing the active region 12d of the memory cell formation region 15a. In addition, the third conductive layer 16c of the memory cell formation region 15a is not located in the entire region of the active region 12d of the memory cell formation region 15a that faces the active region 12d of the memory cell formation region 15b.
[0099]
For this reason, referring to FIG. 29, the region between the source or drain of the memory cell formation region 15b (the region indicated by hatching) and the region serving as the source or drain of the memory cell formation region 15a (the region indicated by hatching). Only has a field oxide region 13 and a distance L _Three Can not be long. Therefore, punch-through is likely to occur in the region indicated by D.
[0100]
On the other hand, in the third embodiment, as described above, in the region indicated by D in FIG. 27, the distance L is the same as the third conductive layer 56c is located. _Three Can be made longer and punch-through can be prevented.
[0101]
[Fourth Embodiment]
FIG. 31 is a plan view showing a part of the element formation layer of the SRAM memory cell array according to the fourth embodiment of the present invention. The difference from the third embodiment is the position of the second conductive layer 56b. That is, in the fourth embodiment, the distance L between the second conductive layer 56b and the active region 52d. _Five Is the distance L between the second conductive layer 56b and the active region 52a. ₆ Have been smaller. Since the structure other than this is the same as that of the third embodiment, the description thereof is omitted by giving the same reference numerals.
[0102]
The second conductive layer 56b and the sidewall insulating film are located on the active region 52d, and the load transistor Q ₆ Even if the gate width is reduced, the β ratio of the memory cell is not affected. Therefore, the distance L between the second conductive layer 56b and the active region 52d _Five Is the distance L between the second conductive layer 56b and the active region 52a. ₆ Can be smaller. Therefore, the width W of the field oxidation region 53 ₇ And the memory cell can be miniaturized.
[0103]
In the fourth embodiment, since the structure other than the position of the second conductive layer 56b is the same as that of the third embodiment, the effect 3 of the third embodiment described above is produced.
[Brief description of the drawings]
FIG. 1 is a plan view showing a part of an element formation layer of an SRAM memory cell array according to a first embodiment of the present invention;
FIG. 2 is a plan view showing an SRAM well pattern according to the first embodiment of the present invention;
FIG. 3 is a plan view showing a state in which a well pattern is formed on the main surface of a silicon substrate used in the SRAM according to the first embodiment of the present invention;
FIG. 4 is a plan view showing patterns of an active region and a field oxide region of the SRAM according to the first embodiment of the present invention.
FIG. 5 is a plan view showing a state in which active region and field oxide region patterns are formed on the main surface of a silicon substrate used in the SRAM according to the first embodiment of the present invention;
FIG. 6 is a plan view showing patterns of the first conductive layer, the second conductive layer, and the third conductive layer in the SRAM word line and memory cell formation region according to the first embodiment of the present invention; .
FIG. 7 shows a first conductive layer, a second conductive layer, and a third conductive layer on a main surface of a silicon substrate used in the SRAM according to the first embodiment of the present invention. It is a top view which shows the state in which the pattern of the layer was formed.
FIG. 8 is a plan view showing a contact hole pattern of the SRAM according to the first embodiment of the present invention;
FIG. 9 is a plan view showing drain connection wirings and contact pad patterns of the SRAM according to the first embodiment of the present invention;
FIG. 10 is a plan view showing a state in which a drain connection wiring pattern is formed on the main surface of a silicon substrate used in the SRAM according to the first embodiment of the invention;
FIG. 11 is a plan view showing a contact hole pattern of the SRAM according to the first embodiment of the present invention;
FIG. 12 is a plan view showing the wiring and contact pad patterns of the SRAM according to the first embodiment of the present invention;
FIG. 13 is a plan view showing a state in which a part of the wiring pattern is formed on the main surface of the silicon substrate used in the SRAM according to the first embodiment of the present invention;
FIG. 14 is a plan view showing a via hole pattern of the SRAM according to the first embodiment of the present invention;
FIG. 15 is a plan view showing a bit line pattern of the SRAM according to the first embodiment of the present invention;
FIG. 16 is a plan view showing a part of the wiring of the SRAM memory cell array according to the first embodiment of the present invention;
FIG. 17 is an equivalent circuit diagram of the SRAM according to the first embodiment of the present invention.
18 is a cross-sectional view of the SRAM memory cell shown in FIGS. 1 and 16 taken along line AA. FIG.
FIG. 19 is a plan view showing an end portion of the active region shown in FIG. 1;
FIG. 20 is a plan view showing a part of the element formation layer of the SRAM memory cell array according to the second embodiment of the present invention;
21 is a cross-sectional view of the SRAM memory cell shown in FIG. 20, taken along line AA. FIG.
FIG. 22 is a plan view showing a part of an element formation layer of an SRAM memory cell array according to a third embodiment of the present invention;
FIG. 23 is a plan view showing patterns of an active region and a field oxide region of an SRAM according to a third embodiment of the present invention.
FIG. 24 is a plan view showing a state where active region and field oxide region patterns are formed on the main surface of a silicon substrate used in an SRAM according to a third embodiment of the present invention;
FIG. 25 is a plan view showing patterns of a first conductive layer, a second conductive layer, and a third conductive layer in an SRAM word line and memory cell formation region according to a third embodiment of the present invention; .
FIG. 26 shows a first conductive layer, a second conductive layer, and a third conductive layer in a word line and a memory cell formation region on a main surface of a silicon substrate used in an SRAM according to a third embodiment of the invention; It is a top view which shows the state in which the pattern of the layer was formed.
27 is a cross-sectional view of the SRAM memory cell shown in FIG. 22 taken along line BB.
28 is a cross-sectional view of the SRAM memory cell shown in FIG. 22 cut along line CC.
29 is a cross-sectional view of the SRAM memory cell shown in FIG. 1 cut along the line BB. FIG.
30 is a cross-sectional view of the SRAM memory cell shown in FIG. 1 cut along line CC. FIG.
FIG. 31 is a plan view showing a part of an element formation layer of an SRAM memory cell array according to a fourth embodiment of the present invention;
FIG. 32 is a plan view of a conventional SRAM memory cell;
33 is a cross-sectional view taken along the line AA of the SRAM memory cell in FIG. 32;
FIG. 34 is a plan view of a memory cell when mask alignment is shifted in the y-axis direction when forming a first conductive layer, a second conductive layer, and a third conductive layer.
35 is a cross-sectional view taken along the line AA of the SRAM memory cell in FIG. 34;
36 is a plan view showing an end portion of the active region in FIG. 32;
[Explanation of symbols]
12a to 12i active region
13 Field oxide film
15a-15d Memory cell formation region
16a First conductive layer
16b Second conductive layer
16c third conductive layer
18a Contact hole
18b Contact hole
28 Silicon substrate

Claims (9)

A semiconductor memory device comprising a memory cell array having a plurality of memory cells including first and second load transistors and first and second driver transistors,
The memory cell is
A semiconductor substrate having a main surface;
A first load transistor active region formed on the main surface and serving as an active region of the first load transistor;
A second load transistor active region formed on the main surface and serving as an active region of the second load transistor;
A first driver transistor active region formed on the main surface and serving as an active region of the first driver transistor;
A second driver transistor active region formed on the main surface and serving as an active region of the second driver transistor;
A first element isolation region formed on the main surface and separating the first load transistor active region and the first driver transistor active region;
A first conductive layer extending from above the first load transistor active region to the first driver transistor active region and serving as a gate electrode of the first load transistor and the first driver transistor;
A second conductive layer branched from the first conductive layer on the first element isolation region and electrically connected to the second driver transistor active region;
With
The width of the second conductive layer located on the first element isolation region is smaller than the width of the first conductive layer,
further,
Electrically connected to the first load transistor active region, passing over the second load transistor active region, and further extending to the second driver transistor active region, the second load transistor and the A third conductive layer serving as a gate electrode of the second driver transistor;
The memory cell array includes:
A second element isolation region formed on the main surface and separating a memory cell in a first row and a memory cell in a second row of the memory cell array;
The second load transistor active region of the memory cells in the first row is opposed to the first load transistor active region of the memory cells in the second row via the second element isolation region. A first region to
The pattern of the third conductive layer of the memory cells in the first row traverses over the first region;
The second load transistor active region of the memory cell in the first row is formed under the pattern of the third conductive layer of the memory cell in the first row on the first region. Not
The second load transistor active region of the memory cell in the second row is opposed to the first load transistor active region of the memory cell in the first row through the second element isolation region. A second region to
The pattern of the third conductive layer of the memory cells in the second row traverses over the second region;
The second load transistor active region of the memory cell in the second row is formed under the pattern of the third conductive layer of the memory cell in the second row on the second region. Not
In the first region, a part of the third conductive layer of the memory cell in the first row is lifted onto the second element isolation region,
In the second region, a part of the third conductive layer of the memory cell in the second row is lifted onto the second element isolation region. In claim 1,
The patterns of the first, second and third conductive layers of the memory cells in the second row are the same as the patterns of the first, second and third conductive layers of the memory cells in the first row. A semiconductor memory device having a pattern rotated by 180 degrees about an axis perpendicular to. A semiconductor memory device comprising a memory cell array having a plurality of memory cells including first and second load transistors and first and second driver transistors,
The memory cell is
A semiconductor substrate having a main surface;
A first load transistor active region formed on the main surface and serving as an active region of the first load transistor;
A second load transistor active region formed on the main surface and serving as an active region of the second load transistor;
A first driver transistor active region formed on the main surface and serving as an active region of the first driver transistor;
A second driver transistor active region formed on the main surface and serving as an active region of the second driver transistor;
A first element isolation region formed on the main surface and separating the first load transistor active region and the first driver transistor active region;
A first conductive layer extending from above the first load transistor active region to the first driver transistor active region and serving as a gate electrode of the first load transistor and the first driver transistor;
A second conductive layer branched from the first conductive layer on the first element isolation region and electrically connected to the second driver transistor active region;
With
The width of the second conductive layer located on the first element isolation region is smaller than the width of the first conductive layer,
further,
Electrically connected to the first load transistor active region, passing over the second load transistor active region, and further extending to the second driver transistor active region, the second load transistor and the A third conductive layer serving as a gate electrode of the second driver transistor;
The memory cell array includes:
A second element isolation region formed on the main surface and separating a memory cell in a first row and a memory cell in a second row of the memory cell array;
The second load transistor active region of the memory cell in the first row is opposed to the second load transistor active region of the memory cell in the second row through the second element isolation region. A first region to
The pattern of the third conductive layer of the memory cells in the first row traverses over the first region;
The second load transistor active region of the memory cell in the first row is formed under the pattern of the third conductive layer of the memory cell in the first row on the first region. Not
The second load transistor active region of the memory cell in the second row is opposed to the second load transistor active region of the memory cell in the first row through the second element isolation region. A second region to
The pattern of the third conductive layer of the memory cells in the second row traverses over the second region;
The second load transistor active region of the memory cell in the second row is formed under the pattern of the third conductive layer of the memory cell in the second row on the second region. Not
In the first region, a part of the third conductive layer of the memory cell in the first row is lifted onto the second element isolation region,
In the second region, a part of the third conductive layer of the memory cell in the second row is lifted onto the second element isolation region. In claim 3,
The pattern of the first, second, and third conductive layers of the memory cells in the second row and the pattern of the first, second, and third conductive layers of the memory cells in the first row are mirror images. A semiconductor memory device having a relationship of In any one of Claims 1-4,
The semiconductor memory device, wherein a width of the second conductive layer located on the first element isolation region is a minimum dimension width according to a processing dimension rule of the second conductive layer. In any one of Claims 1-5,
A sidewall insulating film formed on a side surface of the second conductive layer on the first driver transistor active region side;
The distance between the second conductive layer located on the first element isolation region and the first driver transistor active region is the pattern formation of the first, second and third conductive layers of the memory cell. A semiconductor memory device having a value larger than a sum of an alignment error value and a width of the sidewall insulating film. In any one of Claims 1-6,
The distance between the second conductive layer located on the first element isolation region and the first load transistor active region is the same as that between the second conductive layer located on the first element isolation region and the first load transistor active region. A semiconductor memory device smaller than the distance from the first driver transistor active region. In any one of Claims 1-7,
A semiconductor memory device, wherein the pattern comprising the first and second conductive layers has an h shape, and the pattern of the third conductive layer has a seven shape. In any one of Claims 1-8,
Of the first load transistor active region, the width of the active region of the contact region electrically connected to the third conductive layer is larger than the width of the other portion.

Images