JP3877862B2 - Axon circuit with continuous pulse delay function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an axon circuit having a function of delaying pulses propagating on an axon in an asynchronous pulse neural network system.
[0002]
[Prior art]
In recent years, information processing using pulse timing in the neural circuit of the brain has attracted attention. An asynchronous pulse neural network model that realizes such spatiotemporal information processing and is suitable for VLSI (Very Large Scale Integrated circuit) has been proposed. For example,
(1) M.M. Hanagata and Y.H. Horio: “A Modified Asynchronous Pulse Neural Network Model for VLSI Implementation,” in Proc. 1997 International Symposium on Nonlinear Theory and its Applications (NOLTA '97), pp. 849-852
(2) K. Yasuda, M .; Hanagata, R .; Kasahara and Y.K. Horio: “Analog Circuit Implementation of Asynchronous Pulse Neural Network Model,” in Proc. 1997 International Symposium on Nonlinear Theory and its Applications (NOLTA '97), pp. 853-856.
[0003]
In addition, as a refractory neuron circuit, (3) R.R. Sarpeskar, L.M. Watts, andC. Mead, "Refractory Neuron Circuits," CNS Technical Report, CNS-TR-92-08, California Institute of Technology, Pasadena, 1992.
[0004]
Such an asynchronous pulse neural network model requires an axon circuit having an analog delay in order to handle a delay of continuous time.
[0005]
[Problems to be solved by the invention]
As described above, the conventional method requires an axon circuit having an analog delay in order to handle a continuous time delay, and there is no technically satisfactory one.
In view of the above situation, an object of the present invention is to provide an axon circuit having a continuous pulse delay function having a delay circuit that can adjust a delay time by an analog voltage and delays a pulse timing.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
[1] In an axon circuit having a delay function of pulses propagating on an axon in an asynchronous pulse neural network system, a switched current circuit that converts an input voltage into a current and outputs the current and controls the output current by a reset voltage And a delay circuit having a refractory neuron circuit having a capacitor that is connected to the output of the switched current circuit and charged by the output current, and the output current flows into the capacitor, and the voltage across the capacitor Is delayed and raised by the refractory neuron circuit, and the voltage across the capacitor is used as the reset input of the switched current circuit, the current of the capacitor is cut off, generating a delay pulse, and the delay time of this pulse Corresponds to the charging time of the capacitor. The Tsu reset input, a current flowing in the capacitor is obtained as an analog controlled.
[0007]
[2] In the axon circuit having the continuous pulse delay function as described in [1] above, each pulse in the pulse train from the previous neuron is delayed by the delay circuit, and after shaping the delayed pulse, the post-neuron It is intended to be transmitted to.
[3] In the axon circuit having the continuous pulse delay function described in [2], the pulse timing is stored by setting the maximum delay time of the single delay circuit to be the same as the absolute refractory period of the neuron model. It is a thing.
[0008]
[4] In the axon circuit having the continuous pulse delay function described in [2], a long delay is obtained by connecting the delay circuits in multiple stages.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is an explanatory diagram of ideal axon propagation showing an embodiment of the present invention. FIG. 1 (a) shows a pre-neuron output waveform, and FIG. 1 (b) shows a post-neuron input waveform.
[0010]
As shown in FIG. 1 (a), a pulse propagating on the axon is transmitted to the rear neuron after a certain delay time D as shown in FIG. 1 (b). Must be configured to
Since the asynchronous pulse neural network model places importance on pulse timing as analog information, it is necessary to handle a delay of continuous time. Therefore, a delay circuit that can adjust the delay time by an analog voltage and delays the pulse timing is required, and an axon circuit is provided using the delay circuit.
[0011]
The delay circuit is composed of a refractory neuron circuit using a switched current circuit. First, the switched current circuit and the refractory neuron circuit will be described sequentially.
FIG. 2 is a switched current circuit diagram showing an embodiment of the present invention, and FIG. 3 is an operation waveform diagram of the switched current circuit.
[0012]
In FIG. 2, M1, M2 and M3 are MOS transistors (MOS switches) constituting a current mirror circuit, the source of the MOS transistor M1 is grounded, and a bias voltage V _bias is applied to its gate. Then, MOS transistors M4 and M6 are added to the current mirror circuit. M5 is a dummy transistor (dummy switch) for avoiding clock feedthrough. Furthermore, the input voltage V _in via the inverter IN1 to the gate of the MOS transistor M4, the reset voltage V _reset is applied via the inverter IN2 for MOS transistor M6. The output current I _out is obtained from the drain of the MOS transistor M3.
[0013]
The operation of this switched current circuit will be described below with reference to FIGS.
First, as shown in FIG. 3 (a), when the input voltage V _in rises, as shown in FIG. 3 (c), the MOS transistor M4 is turned ON, the gate-source of the MOS transistor M2 and M3 voltage V _gs is equal (V _gs 2 = V _gs 3). Here, the same shape ratio of the MOS transistors M2 and M3, if MOS transistor M3 is operating in the saturation region, the bias voltage V _bias, the bias current I _bias which can be adjusted, to the drain of the MOS transistor M3 The output current I _out (= I _bias ) is output as shown in FIG.
[0014]
Further, as shown in FIG. 3 (a), when the input voltage V _in falls, as shown in FIG. 3 (c), the MOS transistor M4 is turned OFF, the gate-source capacitance of the MOS transistor M3 Thus, the gate-source voltage V _gs 3 is held (V _gs 3 = V _gs 2), and the output current I _out continues to flow _{out as} shown in FIG. Next, as shown in FIG. 3B, when the reset voltage V _reset rises, as shown in FIG. _3D , the MOS transistor M6 is turned on. As a result, the gate-source voltage of the MOS transistor M3 becomes V _gs 3 = 0 [V], and the output current I _out is cut off as shown in FIG.
[0015]
That is, the switched current circuit converts an input voltage V _in the current output, the output current is a circuit configuration that is controlled by the reset voltage V _reset.
Next, the refractory neuron circuit will be described.
FIG. 4 is a refractory neuron circuit diagram showing an embodiment of the present invention, and FIG. 5 is an operation waveform diagram of the refractory neuron circuit.
[0016]
In FIG. 4, MP, MC3, MC4, MC5, MRS, MBP, M ref is, MOS transistors, C _m, the C _ref respectively are each capacitor.
The operation of this refractory neuron circuit will be described below with reference to FIGS.
First, as shown in FIG. 5 (a), the input current I _in is the flow into the capacitor C _m, as shown in FIG. 5 (b), the voltage V _m across capacitor C _m is increased. Since the voltage V _m is the gate voltage of the MOS transistor MP, when the voltage exceeds the threshold voltage of the MOS transistor MP, a current I _pw controlled by the voltage V _pw applied to the gate of the MOS transistor MBP flows. Since the MOS transistors MC3 and MC4 has a current mirror, current I _p flows into the capacitor C _m, abruptly V _m increases.
[0017]
On the other hand, since the MOS transistors MC4 and MC5 are also current mirrors, I _ref flows into the capacitor C _ref and the voltage V _n also increases simultaneously as shown in FIG. 5C.
Since the voltage V _n controls the gate voltage of the transistor MRS, the voltage V _n is eventually turned on, and as shown in FIG. 5B, the charge of the capacitor C _m is discharged and the voltage V _m also decreases. Further, as shown in FIG. 5C, the voltage V _n also decreases.
[0018]
This refractory neuron circuit applies the switched current circuit shown in FIG. 2 to the input section. As a result, when the voltage pulse V _in is input, the outflow current from the switched current circuit until the voltage V _m rapidly rises, then, the current is cut off by the voltage V _m.
Next, a delay circuit (an axon circuit having a continuous pulse delay) showing an embodiment of the present invention will be described.
[0019]
FIG. 6 is a delay circuit diagram showing an embodiment of the present invention.
This delay circuit uses the above-described switched current circuit as an input part of the above-described refractory neuron circuit.
In this figure, MB, MC1 and MC2 are MOS transistors constituting a current mirror circuit, the source of the MOS transistor MB is grounded, and a bias voltage V _bias is applied to its gate. Then, MOS transistors (MOS switches) MSW1 and MSW2 are added to the current mirror circuit. MDM1 is a dummy transistor (dummy switch) for avoiding clock feedthrough. Furthermore, the input voltage V _in via the inverter IN1 to the gate of the MOS transistor MSW1 is, the reset voltage V _m is applied through an inverter IN2 to MOS transistor MSW2. An output is obtained from the drain of the MOS transistor MC2.
[0020]
Conventionally, a switched current circuit switches current by controlling a MOS switch with a synchronized two-phase clock. However, the switched current circuit of the present invention includes two MOS transistors (MOS transistors). By providing the switches MSW1 and MSW2, one switch MSW1 plays a role of switching current, and the other switch MSW2 plays a role of resetting current. That is, the current pulse width is adjusted by the opening / closing timing of the two switches MSW1 and MSW2.
[0021]
As a result, the voltage pulse V _in is input, the current determined by the bias voltage V _bias flows into the capacitor C _m, voltage V _m across capacitor C _m is increased delayed by refractory neuron circuit. Since this voltage V _m is further used as a reset input of the switched current circuit, the current of the capacitor C _m is cut off and a delay pulse V _m is generated.
[0022]
Further, since the pulse delay time of which corresponds to the charging time of the capacitor C _m, the bias voltage V _bias, since the current flowing into the capacitor C _m can be analogically controlled, even analog regulation delay time realized Is possible.
Next, simulation results of this delay circuit will be described.
The delay circuit was designed by the MOSIS 0.5 μm CMOS process (HP) and simulated by HSPICE.
[0023]
Simulation results when the bias voltage V _bias is changed are shown in FIGS.
As described above, it can be confirmed that the delay circuit of the present invention realizes a delay of continuous time with the pulse timing preserved.
FIG. 7 shows a simulation result (part 1) of the delay circuit.
[0024]
Here, FIG. 7A shows the input pulse V _in , FIG. 7B shows the delay pulse V _m , FIG. 7C shows the refractory pulse V _ref , and the bias voltage V _bias = 1.0 (V). V _r = 1.0 (V), V _pw = 1.6 (V), and V _leak = 0.8 (V).
FIG. 8 shows a simulation result (part 2) of the delay circuit.
Here, FIG. 8A shows the input pulse V _in , FIG. 8B shows the delay pulse V _m , FIG. 8C shows the refractory pulse V _ref , and the bias voltage V _bias = 1.1 (V). V _r = 1.0 (V), V _pw = 1.6 (V), and V _leak = 0.8 (V).
[0025]
FIG. 9 is a simulation result (part 3) of the delay circuit.
Here, FIG. 9A shows the input pulse V _in , FIG. 9B shows the delay pulse V _m , FIG. 9C shows the refractory pulse V _ref , and the bias voltage V _bias = 3.3 (V). V _r = 1.0 (V), V _pw = 1.33 (V), and V _leak = 0.8 (V).
Next, the axon circuit will be described.
[0026]
FIG. 10 is an axon circuit diagram having a continuous pulse delay function showing an embodiment of the present invention.
In this figure, 1, 2,..., N are the delay circuits described above, and the waveform shaping circuit 5 is a known circuit. In the waveform shaping circuit 5, M15, M16, M17, M18, M19, and M20 are MOS transistors, _Cp is a capacitor, and _Vpl is a voltage applied to the gate of the MOS transistor M15.
[0027]
As shown in this figure, the axon circuit having the continuous pulse delay function includes a first delay circuit 1, a second delay circuit 2,..., An nth delay that delays each pulse in the pulse train from the previous neuron. The delay circuit n and the delayed pulse are shaped by the waveform shaping circuit 5 and then transmitted to the subsequent neuron.
Here, the timing of the pulse is preserved by setting the maximum delay time of the single delay circuit to be the same as the absolute refractory period of the neuron model. In addition, a long delay is possible by connecting delay circuits in multiple stages.
[0028]
FIG. 11 is a diagram (part 1) showing a simulation result by HSPICE of an axon circuit in which two stages of delay circuits are connected.
11A shows the input pulse V _in , FIG. 11B shows the propagation pulse V _m1 , FIG. 11C shows the propagation pulse V _m2 , and FIG. 11D shows the output pulse V _out. Voltage V _bias = 1.05 (V), V _r = 1.0 (V), V _pw = 1.6 (V), V _leak = 0.8 (V), V _pl = 1.0 (V) It is.
[0029]
FIG. 12 is a diagram (part 2) showing a simulation result by HSPICE of an axon circuit in which two stages of delay circuits are connected.
12A shows the input pulse V _in , FIG. 12B shows the propagation pulse V _m1 , FIG. 12C shows the propagation pulse V _m2 , and FIG. 12D shows the output pulse V _out. Voltage V _bias = 1.15 (V), V _r = 1.0 (V), V _pw = 1.6 (V), V _leak = 0.8 (V), V _pl = 1.0 (V) It is.
[0030]
FIG. 13 is a diagram (part 3) showing a simulation result by HSPICE of an axon circuit in which two stages of delay circuits are connected.
13A shows the input pulse V _in , FIG. 13B shows the propagation pulse V _m1 , FIG. 13C shows the propagation pulse V _m2 , and FIG. _13D shows the output pulse V _out. Voltage V _bias = 3.3 (V), V _r = 1.0 (V), V _pw = 1.33 (V), V _leak = 0.8 (V), V _pl = 1.15 (V) It is.
[0031]
In this way, it can be confirmed that a short delay to a long delay can be realized by connecting delay circuits in multiple stages.
As described above, a delay circuit using a switched current circuit was designed, and an axon circuit used in an asynchronous neural network model was obtained. From the simulation results of this axon circuit, it was confirmed that this axon circuit preserved the timing of each pulse in the pulse train and could realize continuous-time pulse delay transmission.
[0032]
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0033]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
(A) By providing two MOS switches in the switched current circuit, one switch performs current switching, the other switch performs current reset, and the current is determined by the opening and closing timing of the two switches. The pulse width can be adjusted.
[0034]
The pulse delay time is to correspond to the charging time of the capacitor C _m, since the current flowing into the capacitor C _m by the bias voltage V _bias can be analogically controlled, to achieve an analog regulation delay time be able to.
(B) The timing of each pulse in the pulse train can be stored, and continuous-time pulse delay transmission can be realized.
[0035]
In addition, by connecting delay circuits in multiple stages, a short delay to a long delay can be realized.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of ideal axon propagation showing an embodiment of the present invention.
FIG. 2 is a switched current circuit diagram showing an embodiment of the present invention.
FIG. 3 is an operation waveform diagram of a switched current circuit showing an embodiment of the present invention.
FIG. 4 is a refractory neuron circuit diagram showing an embodiment of the present invention.
FIG. 5 is an operation waveform diagram of the refractory neuron circuit showing the embodiment of the present invention.
FIG. 6 is a delay circuit diagram showing an embodiment of the present invention.
FIG. 7 is a first simulation result of the delay circuit according to the embodiment of the present invention.
FIG. 8 is a second simulation result of the delay circuit according to the embodiment of the present invention.
FIG. 9 is a third simulation result of the delay circuit according to the embodiment of the present invention.
FIG. 10 is an axon circuit diagram having a continuous pulse delay function according to an embodiment of the present invention.
FIG. 11 is a simulation result (No. 1) of an axon circuit having a continuous pulse delay function according to the embodiment of the present invention.
FIG. 12 is a simulation result (No. 2) of an axon circuit having a continuous pulse delay function according to the embodiment of the present invention.
FIG. 13 is a simulation result (No. 3) of an axon circuit having a continuous pulse delay function according to the embodiment of the present invention.
[Explanation of symbols]
M1, M2, M3, M4, M6, MP, MC3, MC4, MC5, MRS, MBP, M ref, MB, MC1, MC2, MSW1, MSW2, M15, M16, M17, M18, M19, M20 MOS transistor (MOS switch)
M5, MDM1 dummy transistor (dummy switch)
IN1, IN2 Inverter V _in input voltage (input pulse)
V _reset reset voltage I _out output current V _gs gate-source voltage C _m , C _ref , C _p capacitor V _m voltage across capacitor C _m (delay pulse)
V _pw Voltage applied to gate of MOS transistor MBP V _ref refractory pulse 1, 2,..., N delay circuit 5 waveform shaping circuit V _m1 , V _m2 propagation pulse V _out output pulse

Claims (4)

In an axon circuit having a delay function of pulses propagating on an axon in an asynchronous pulse neural network system,
(A) A switched current circuit that converts an input voltage into a current and outputs the current, and controls the output current with a reset voltage, and a capacitor that is connected to the output unit of the switched current circuit and is charged by the output current. A delay circuit having a refractory neuron circuit having;
(B) The output current flows into the capacitor, the voltage across the capacitor is delayed and raised by the refractory neuron circuit, and the voltage across the capacitor is used as the reset input of the switched current circuit, The capacitor current is cut off to generate a delay pulse, and the delay time of the pulse corresponds to the charge time of the capacitor. Therefore, the current flowing into the capacitor is controlled in an analog manner by the reset input. Axon circuit with continuous pulse delay function. 2. The axon circuit having a continuous pulse delay function according to claim 1, wherein each pulse in a pulse train from a previous neuron is delayed by the delay circuit, and the delayed pulse is waveform-shaped and then transmitted to a subsequent neuron. An axon circuit having a continuous pulse delay function. 3. The axon circuit having a continuous pulse delay function according to claim 2, wherein the pulse timing is stored by setting the maximum delay time of the single delay circuit to be the same as the absolute refractory period of the neuron model. An axon circuit having a pulse delay function. 3. The axon circuit having a continuous pulse delay function according to claim 2, wherein a long delay is obtained by connecting the delay circuits in multiple stages.

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