JP3869180B2 - Pattern formation method - Google Patents

Description

【００１２】
により与えられること。
【００１３】
前記潜像モニタ領域と前記現像モニタ領域が同一の領域であること。
前記潜像モニタ領域或いは現像モニタ領域が、デバイスパターン領域の特定の領域であること。
前記潜像モニタ領域或いは現像モニタ領域が、デバイスパターンの一部を切り出し、そのまま若しくは寸法を一部変更して作成された要素パターンであること。
前記チップ領域とは、デバイスとして動作する領域だけでなく、テストパターンやマークの配置された領域を含むこと。
前記潜像モニタ領域或いは現像モニタ領域が、露光マスク上で特定の透過率を有する領域であること。
【００１４】
前記ウェハ内で代表的な条件で処理されているチップ領域は、潜像モニタ領域の反射光強度の中で最頻値を示したチップ領域であること。
前記ウェハ内で代表的な条件で処理されているチップ領域は、潜像モニタ領域の反射光強度の中で中央値を示したチップ領域であること。
【００１５】
前記ウェハ内で代表的な条件で処理されているチップ領域は、潜像モニタ領域の反射光強度の中で平均値を示したチップ領域であること。
【００２３】
（２）本発明（請求項４）は、被処理基板上のレジストの複数のチップ領域にそれぞれデバイスパターンを露光し、加熱の後、現像によりデバイスパターンを形成するパターン形成方法において、前記デバイスパターンの露光時に、潜像モニタ領域及び現像モニタ領域をデバイスパターンとともに前記被処理基板上のレジストの各チップ領域に露光する工程と、前記露光工程後の加熱工程と現像工程の間で、複数のチップ領域の各潜像モニタ領域に対して特定波長の光を照射し、該潜像モニタ領域からの反射光強度から前記レジストの潜像深さを求める工程と、測定された前記レジストの潜像深さに基づいて前記被処理基板内で代表的な条件で処理されているチップ領域を抽出する工程と、前記デバイスパターンの現像工程の初期に、抽出されたチップ内に配置された前記モニタ領域に複数の波長の光を照射して前記レジストの下地の膜厚を測定する工程と、測定された下地の膜厚から反射光強度しきい値を決定する工程と、前記デバイスパターンの現像中に、抽出されたチップ領域内に配置された前記現像モニタ領域に対して特定波長の光を照射し、該現像モニタ領域からの反射光強度変化と前記決定された反射光強度しきい値に基づいて現像を停止することを特徴とする。
【００２４】
本発明の好ましい実施態様を以下に記す。
現像工程の初期に前記レジストの下地の膜厚構成を測定する工程において、前記下地の膜厚構成は、レジストが全面に形成されている領域とレジスト残膜０の領域との反射光強度比と、前記下地の膜厚との関係より求められること。前記モニタ領域に照射する波長は、膜厚変動に対して前記反射光強度比の変化が大きい波長であることがさらに好ましい。
前記反射光強度しきい値を決定する工程において、前記反射光強度しきい値は、予め求めている下地膜厚に対する反射光強度しきい値と下地膜厚との関係より決定されること。
【００２５】
（３）本発明（請求項７）は、 被処理基板上のレジストの複数のチップ領域にそれぞれデバイスパターンを露光し、加熱の後、現像によりデバイスパターンを形成するパターン形成方法において、前記デバイスパターンの露光時に、潜像モニタ領域及び現像モニタ領域をデバイスパターンとともに前記被処理基板上のレジストの各チップ領域に露光する工程と、前記露光工程後の加熱工程と現像工程の間で、複数のチップ領域の各潜像モニタ領域に対して特定波長の光を照射し、該潜像モニタ領域の反射光強度を測定する工程と、測定された反射強度から前記レジストの潜像深さを求める工程と、測定された前記レジストの潜像深さに基づいて前記被処理基板内で代表的な条件で処理されているチップ領域を抽出する工程と、前記デバイスパターンの現像工程中に、抽出されたチップ領域内の前記現像モニタ領域に特定波長の光を照射し、現像時間と反射光強度との関係の特異点からデバイスパターンが所望寸法に仕上がる現像停止時間を予測する工程と、予測された現像停止時間に現像を停止させる工程とを含むことを特徴とする。
【００２６】
本発明の好ましい実施態様を以下に記す。
前記現像モニタ領域がホール或いはラインパターンで構成される場合、現像時間と反射光強度との関係の特異点はパターンの抜け時間であって、前記現像停止時間は、予め求められているデバイスパターンが所望寸法に仕上がる時間と、前記パターンの抜け時間との関係をもとに予測すること。
【００２７】
前記現像モニタ領域がマスク上で特定の透過率を有するパターンで構成される場合、現像時間と反射光強度との関係の特異点は、レジストの抜け時間であって、前記現像停止時間は、予め求められているデバイスパターンが所望寸法に仕上がる時間と、前記レジストの抜け時間との関係をもとに予測されること。
【００２８】
これらの発明（請求項４，７）の発明の好ましい実施態様を以下に記す。
【００２９】
前記レジストの潜像深さを求める工程において、前記レジストの下地の膜厚が未知の場合、前記特定波長の光が、前記レジストの膜厚と反射強度との関係において、該レジストの初期膜厚付近で前記関係が変曲点を示すと共に、該初期膜厚付近で位相が１８０゜異なる二つの波長の光であり、前記二つの波長の反射光強度からそれぞれ求められた前記レジストの潜像深さを重み付け平均することにより前記レジストの前記潜像深さを求めること。
【００３０】
前記レジストの潜像深さを求める工程において、前記レジストの下地の膜厚が既知の場合、前記潜像モニタ領域に対して、前記レジストの膜厚と反射強度との関係において該レジストの初期膜厚付近で前記関係が変曲点を示す波長の光を照射し、予め求めている下地の膜厚に対する反射光強度とレジスト膜厚の関係をもとに、前記レジストの潜像深さを求めること。
【００３１】
［作用］
本発明は、上記構成によって以下の作用・効果を有する。
【００３２】
ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップ領域を潜像モニタ領域の反射光強度を測定することで抽出し、抽出されたチップ領域の現像モニタ領域を現像中にモニタし、その反射光強度応じて現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができる。
【００３３】
また、反射光強度を測定する際に、光源の照射むら或いは時間的な反射光強度の変化を考慮した反射光強度の規格化を行うことにより、反射光強度の測定精度が向上し、代表的なチップ領域を抽出する精度が向上する。
【００３４】
また、ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップを潜像モニタ領域の潜像深さを測定することで抽出し、そのチップの現像モニタ領域を現像中にモニタし、その反射光強度から最適な現像時間を算出し現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができ、歩留まりが大きく向上する。
【００３５】
また、反射光強度変化の特異点から現像終点を求める手法では、現像モニタ領域の反射光強度変化のなかで下地膜厚に依存しない特異的な点から露光量やフォーカス値を測定し、それにみあった最適な現像を行うことにより、ウェハ間の寸法のばらつきを大きく低減することがきできる。
【００３６】
【発明の実施の形態】
［第１実施形態］
本実施形態は潜像のモニタリングおよび現像中のモニタリングを同じモニタ領域に対して現像装置内で行った場合について説明する。
【００３７】
図１は、本発明の第１実施形態に係わる現像装置の概略構成を示す図である。
【００３８】
現像ユニット１００内に、通常の現像〜リンスを行うのに必要なユニットの他に、モニタを行うためのモニタヘッド１０１が配置されている。モニタヘッド１０１にはプローブ光の光源（条件によって波長選択できるように狭帯域フィルターを複数内蔵）１０２、モニタヘッド１０１に光を導入するファイバ１０３が接続されていて、モニタヘッド１０１中のコリメーションレンズにより、特定の波長に狭帯化したほぼ単色の平行光でウェハ１０４を照明できるようになっている。また、ウェハ１０４からの反射光は、モニタヘッド１０１の中にあるＣＣＤカメラで検出できるようになっている。このモニタヘッド１０１は複数のチップ（チップ領域）１０５内に配置されたモニタ領域１０６をモニタできるように、装置の制御部１０９からの信号でウェハ１０４上を走査可能である。モニタヘッド１０１はマスクのレイアウトおよび露光のショットマップをもとに特定のチップのモニタ領域が検出できる位置に移動し、画像を取得し、解析部１０８に画像を送り、パターンマッチングによりモニタ領域を認識し、モニタ領域の反射光強度を取得できるようになっている。なお、チップ１０５とは、デバイスとして動作する領域だけでなく、テストパターンやマークの配置された領域を含んでいる。
【００３９】
モニタ領域１０６は、図１に示すように、マーク領域１０７が形成されたダイシングラインに配置されている。モニタ領域形成用のマスクパターンとしては、特定の透過率を有するパターンを用いる。特定の透過率を有するマスクパターンは、ウェハ上に０次回折光しか到達しないピッチを有する規則パターンで、かつマスク上での抜きと残しの比率を変えることで作製する。
【００４０】
０次回折光だけがウェハ上に到達するような条件は、露光波長（λ）、パターンのウェハ上のピッチ（ｐ）、ＮＡ、σを用いて、
λ／ｐ≧（１＋σ）ＮＡ （１）
と定められる。
【００４１】
そこで、露光時の照明の条件（ ＮＡ：０．６、σ：０．７５、露光波長：２４８ｎｍ ）から、マスクパターンのピッチとして２２０ｎｍ（ウェハ上の値）を採用する。このようなピッチのパターンを用いることで、特定の透過率を有するマスクパターンを形成することができる。
【００４２】
このようなパターンの透過率Ｔは、パターンピッチをｐ、パターンのスペース幅をｄとすると、
Ｔ＝（ｄ／ｐ）² （２）
と表される。
【００４３】
特定の比率のマスクパターンを用いれば、露光量に応じて、モニタ領域の潜像時の膜減り量、現像時の現像速度が決まる。
【００４４】
図２、図３にモニタ領域形成用のマスクパターンの透過率を４６．９％にした場合の露光量と膜減り量、および、露光量と膜抜け時間の関係を示す。ここでターゲットとするパターンは、２００ｎｍＬ／Ｓパターンとし、ターゲットパターンがほぼ１：１に仕上がる露光量（２０ｍJ／ｃｍ² ）近辺での関係を示している。このときのレジスト膜厚は４００ｎｍ、反射防止膜厚は６０ｎｍである（以下、本実施形態では同条件）。
【００４５】
図２に示すように、ドーズ量と膜減り量とは比例関係にあり、膜減り量からドーズ量が求められることが分かる。従って、潜像モニタ領域をモニタし、膜減り量を測定することで、ドーズ量を求めることができる。
【００４６】
また、図３に示すように、ドーズ量と抜け時間とは比例関係にあり、抜け時間からドーズ量を求めることができる。従って、現像中にモニタし、抜け時間を測定することで露光量を求めることができる。
【００４７】
本実施形態では、潜像のモニタ時にはモニタ領域の膜減り量に相当する量として反射光強度をモニタし、現像のモニタ時には反射光強度変化がなくなる時間（膜抜け時間）をモニタする。
【００４８】
次に、モニタ時にパターンに照射する光の波長の選び方について説明する。潜像のモニタを行う場合には、図２に示すように、十数ｎｍ程度の膜厚が減少するところを精度よくモニタする必要がある。
【００４９】
レジスト上に現像液がない場合の、レジストの膜減り量と反射率の関係を図４に示す。この関係より、膜減り量が十数ｎｍの場合（図中の矢印の範囲）、波長４３０ｎｍでモニタすると反射率変化が膜厚に対して単調に変化しかつ、変化量が大きいため、反射光強度から精度よく膜減り量、即ち露光量をモニタすることが可能である。
【００５０】
このように、レジスト／反射防止膜／下地の構造および、適正露光量付近でのモニタパターンの膜減り量に対して、最も反射率変化が大きくなるようにモニタ時の波長を決めればよい。なお、装置構成として、膜厚計を設置する場所が許される場合には、膜減り量を膜厚計によりモニタしてもよい。
【００５１】
また、現像中にモニタする場合には、図３の縦軸に示す膜抜け時間を精度よく求める必要がある。レジスト上に現像液がある場合の、レジストの膜減り量と反射率の関係を図５に示す。
【００５２】
抜け時間を精度よく求めるためには、レジスト膜厚が０（膜減り量は４００ｎｍ）になる周辺で（図５中の矢印の範囲）反射率変化が大きいほうが望ましいため、波長５５０ｎｍでモニタリングを行う。このように、レジスト／反射防止膜／下地の構造に対して、レジスト膜厚が０になる周辺で反射率変化が大きくなるようにモニタ時の波長を決めればよい。
【００５３】
次に本発明を用いた場合の現像シーケンスを図６のフローチャートを用いて説明する。現像ユニットにウェハを搬送した後（ステップＳ１）、ノッチの位置を検出してウェハの回転方向の位置調整を行う（ステップＳ２）。その後、特定のチップ（i）のモニタ領域にモニタヘッドを移動させ（ステップＳ３）、パターンマッチングによりモニタ領域の位置を検出し、モニタ領域の反射光強度を取得する（ステップＳ４）。モニタ領域の反射光強度を測定したチップの個数を判定し（ステップＳ５）、チップの個数がｎ個になるまで同様のモニタ領域の反射光強度の取得をｎ個のチップに対して行う。そして、ｎ個のチップのモニタ領域の反射光強度を測定した後、得られた反射光強度の最頻値から現像時間を制御するためにモニタするチップ（ｋ）を決定する（ステップＳ６）。
【００５４】
そして、現像を開始し（ステップＳ７）、モニタヘッドをチップ（ｋ）の位置に移動させ、モニタ領域の反射光強度変化を測定する（ステップＳ８）。モニタ領域の反射光強度変化から膜抜け時間を計測し、適正な現像時間を算出し（ステップＳ９）、算出した現像時間で現像を停止させる（ステップＳ１０）。
【００５５】
なお、反射光強度変化から膜抜け時間を計測するのではなく、反射光強度の変化が無くなったところで、現像を停止させても良い。
【００５６】
このシーケンスについて、実際の実験結果をもとに説明する。図７にウェハのショットマップおよび、現像前にモニタする９つのチップの走査順番の一例を示す。図７に示すように、ｃｈｉｐ１，ｃｈｉｐ２，ｃｈｉｐ３，ｃｈｉｐ４，ｃｈｉｐ５，ｃｈｉｐ６，ｃｈｉｐ７，ｃｈｉｐ８，ｃｈｉｐ９と順番にチップをモニタしていく（ステップＳ３）。これらのチップについて、モニタ領域が画像に入るような位置にモニタヘッドを移動させ（ステップＳ４）、パターンマッチングによりモニタ領域の位置を検出し、モニタ領域からの反射光の強度の取得を行う（ステップＳ５）。
【００５７】
観察を行っている光源に全くむらがない、もしくは、モニタヘッドの移動で常に画像の同じ位置にモニタ領域が入ってくれば、ＣＣＤカメラの階調をそのままモニタしていけばよい。ところが、実際には図８に示すように、観察領域での光源の照射むらが存在する。また、モニタ領域は２０μｍ四方（観察領域は１ｍｍ四方）であり、ヘッドの位置精度がそれほどないため、画像の全く同じ位置にはこない。
【００５８】
例えば、同じモニタ領域が図８に示すよう光源の照射むらのなかで暗い部分（位置Ａ）にきた場合と、明るい部分（位置Ｂ）にきた場合では、位置Ａにきた場合（図９）のほうが位置Ｂにきた場合（図１０）よりも暗くなってしまう。そのため、ＣＣＤカメラの階調を測定していっても十分な精度が得られない。
【００５９】
このような場合には各チップのモニタリングを行う前に予め、図８のような光源の照射むらを画像として取得しておき、図９に示すように、モニタ領域が位置Ａにきた場合には、図８の位置Ａの反射光強度で規格化した値をモニタ領域の規格化反射光強度（Ｉ_A／ｉ_A）とし、図１０に示すようにモニタ領域が位置Ｂにきた場合には図８の位置Ｂの反射光強度で規格化した値をモニタ領域の規格化反射光強度（Ｉ_B／ｉ_B）とする。
【００６０】
なお、Ｉ_α（α：Ａ又はＢ）は測定を行ったモニタ領域の反射光強度であり、ｉ_α（α：Ａ又はＢ）は図８に示す前記光源の照射むらが存在する画像中で前記モニタ領域の反射光強度である。
【００６１】
このとき、ＣＣＤの階調にバックグランドがのっている場合には予め測定（Ｉ_bgnd）しておき、バックグランドを引いて規格化反射光強度を求める（例えば位置Ａでは（Ｉ_A−Ｉ_bgnd）／(ｉ_A−Ｉ_bgnd)）。
【００６２】
また、図１１に示すように、光源の照射むらがさほど大きくなく、モニタ領域（位置Ｃ）が常に光源の照射むらのなかで同じところにくる場合には、規格化に用いる反射光強度をモニタ領域の近傍の反射光強度（ｉ_C）として規格化を行ってもよい。
【００６３】
実際に９つのチップについて、規格化反射光強度を取得した結果を図１２に示す。これらから規格化反射光強度の最頻値（モード）を求めると２．０６になり、現像をモニタするチップをｃｈｉｐ４とした。
【００６４】
次に、ｃｈｉｐ４のモニタ領域をモニタすることにより、最適な現像時間を求める方法について説明する。図１３にモニタ領域の現像中の反射光強度変化を示す。この反射光強度変化より、抜け時間が２０秒であることがわかる。予め、モニタ領域の抜け時間と、２００ｎｍＬ／Ｓパターンが１：１に仕上がる時間の関係を図１４のように求めておく。そして、これらの関係をもとに、現像時間（この場合は５５秒）を算出する。そして、算出した現像時間で現像を停止させる。
【００６５】
ここでは、最適な現像時間の算出を図１３および図１４の関係から求めたが、規格化反射光強度と露光量の関係が図１５のように表され、露光量に対する２００ｎｍＬ／Ｓパターンが１：１に仕上がる時間の関係が図１６のように表されるため、現像による揺らぎがウェハごとに同じである場合には、これらの関係から最適な現像時間を求めることも可能である。この場合、規格化反射光強度から露光量を求める場合の測定精度と、抜け時間から露光量を求める場合の測定精度のうち高いほうを採用すればよい。
【００６６】
本実施形態では検出器をＣＣＤとした例を示したが、より測定感度の高いフォトマル等を用いてもよい。この場合は、光源の同じ場所に測定位置がくるので、強度の補正も容易である。
【００６７】
以上説明したように、ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップをモニタ領域の反射光強度を測定することで抽出し、このモニタ領域を現像中にモニタし、その膜抜け時間から最適な現像時間を算出し現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができる。これにより、歩留まりが大きく向上する。また、反射光強度を測定する際に、膜厚変化に対して敏感な波長をプローブ光として用いること、光源の照射むらを考慮した反射光強度の規格化を行うことにより、反射光強度の測定精度が向上し、代表的なチップを抽出する精度が向上する。また現像中にモニタパターンの抜け時間を求める際に、膜厚が０になるときに反射光強度変化が大きくなるような波長の光をプローブ光とすることにより、抜け時間を求める精度が向上し、寸法を制御する精度が大きく向上する。
【００６８】
［第２実施形態］
図１７は、潜像のモニタリングを露光後のベーク（Post Exposure Bake：以下ＰＥＢと記）後の冷却装置で実施し、現像のモニタリングを現像装置内で実施した場合の装置構成図である。本実施形態は、第１実施形態とは異なり、潜像のモニタリングと現像のモニタリングに用いるモニタ領域が異なる場合の実施形態である。
【００６９】
冷却ユニット１７００内には、通常の冷却を行うユニットの他に、モニタを行うためのモニタヘッド１７０１が配置されている。モニタヘッド１７０１は第１実施形態と同様の構成で、プローブ光の光源（条件によって波長選択できるように狭帯域フィルターを複数内蔵）１７０２、モニタヘッド１７０１に光を導入するファイバ１７０３が接続されていて、モニタヘッド１７０１中のコリメーションレンズにより、特定の波長に狭帯化したほぼ単色の平行光でウェハ１７０４を照明できるようになっている。また、ウェハ１７０４からの反射光は、モニタヘッド１７０１の中にあるＣＣＤカメラで検出できるようになっている。このモニタヘッド１７０１は複数のチップ内に配置されたモニタ領域をモニタできるように、装置の制御部１７０９からの信号でウェハ１７０４上を走査可能である。モニタヘッド１７０１はマスクのレイアウトおよび露光のショットマップをもとに特定のチップのモニタ領域が検出できる位置に移動し、画像を取得し、解析部１７０８に画像を送り、パターンマッチングによりモニタ領域を認識し、モニタ領域の強度を取得できるようになっている。また、現像ユニット１００内にも同様のモニタヘッド１０１が通常の現像〜リンスを行うユニットの他に配置されている。
【００７０】
モニタ領域１７０６は、図１８に示すように、デバイスパターン領域１８０１の周囲のマーク領域１７０７が形成されたダイシングラインに配置されている。第１実施形態ではモニタ領域に、特定の透過率を有するマスクパターンを配置し、潜像のモニタリング、現像中のモニタリングに用いたが、本実施形態では図１８に示すように、それぞれのモニタリングに異なるモニタ領域を用いている。
【００７１】
ここでターゲットとするパターンは、１７５ｎｍＬ／Ｓパターンとし、デバイスパターン領域１８０１に配置されている。また、潜像モニタ領域１８０２には第１実施形態で用いた特定の透過率を有するパターン（パターンのピッチは２２０ｎｍ、透過率は４６．９％）を配置し、現像モニタ領域１８０３には、ターゲットパターンと同じ１７５ｎｍＬ／Ｓパターンを配置した。ここではモニタ領域に、特定の透過率を有するマスクパターンを配置やデバイスパターンそのものを用いているが、図１９（ａ）に示すホール系モニタパターンや図１９（ｂ）に示すライン系モニタパターンのように、現像に敏感なパターンを用いることも可能である。なお、図１９（ａ），（ｂ）において、１９０１は遮光膜である。
【００７２】
また、図１９に示した現像に敏感なパターンの他にも、デバイスパターンの一部を切り出し、そのまま若しくは寸法を一部変更して作製された要素領域で構成されているようなパターンも有効である。また、これらのモニタ領域は、潜像モニタ領域と現像モニタ領域のどちらに配置してもよい。また、モニタ領域をマーク領域に形成せずにデバイスパターン領域の中の特定領域をモニタ領域としても良い。それぞれのモニタリングで最も精度が得られるものを用いればよい。例えば、メモリセル部分や周辺回路部分等のライン＆スペースパターンをモニタ領域として用いることができる。
【００７３】
このときのレジスト膜厚は４００ｎｍ、反射防止膜厚は６０ｎｍで、１７５ｎｍＬ／Ｓパターンが１：１に仕上がる露光量が２０．５ｍJ／ｃｍ² であることから、潜像のモニタリングに関しては、第１実施形態と同様に４３０ｎｍの波長の光をプローブ光として用いた。現像のモニタリングに関しては、デバイスパターンが所望寸法に仕上がる近傍で、モニタ領域の強度変化が大きくなるような波長が望ましく、ここでは４７０ｎｍの波長を用いた。このように、デバイスパターンが所望寸法に仕上がる近傍で、レジスト／反射防止膜／下地の構造に対して、反射率変化が大きくなるようにモニタ時の波長を決めればよい。
【００７４】
次に本発明を用いた場合の冷却および現像シーケンスを図２０のフローチャートを用いて説明する。冷却ユニットにウェハが搬送されると（ステップＳ１）、ノッチの位置を検出し、ウェハの回転方向の位置調整を行う（ステップＳ２）。その後、ウェハ温度が特定温度よりも低くなった段階で、特定のチップ（i）の潜像モニタ領域にモニタヘッドが移動し（ステップＳ３）、パターンマッチングにより位置を検出し、モニタ領域の反射光強度を取得する（ステップＳ４）。
【００７５】
モニタ領域の反射光強度を測定したチップの個数を判定し（ステップＳ５）、チップの個数がｎ個になるまで同様のモニタ領域の反射光強度の取得をｎ個のチップに対して行う。そして、ｎ個のチップのモニタ領域の反射光強度を測定した後、得られた反射光強度の最頻値から現像時間を制御するためにモニタするチップ（ｋ）を決定する（ステップＳ６）。
【００７６】
冷却が終了すると（ステップＳ７）、ウェハは現像ユニットに搬送され（ステップＳ８）、ノッチの位置を検出し、ウェハの回転方向の位置調整を行う（ステップＳ９）。そして、現像を開始し（ステップＳ１０）、モニタヘッドはチップ（ｋ）の位置に移動し、現像モニタ領域の反射光強度変化を測定する（ステップＳ１１）。モニタ領域の反射光強度変化から適正な現像時間を算出し（ステップＳ１２）、算出した現像時間で現像を停止させる（ステップＳ１３）。なお、特定温度とは、ＰＥＢの反応がほぼ停止する温度である。
【００７７】
このシーケンスについて、実際の実験結果をもとに説明する。
【００７８】
ウェハのショットマップおよび、冷却ユニットで潜像をモニタする９つのチップの走査順番は第１実施形態と同様に図７のとおりである。これらのチップについて、モニタ領域が画像に入るような位置にモニタヘッドが移動し、パターンマッチングにより位置を検出し、反射光強度の取得を行う。
【００７９】
観察を行っている光源に全くむらがない、もしくは、モニタヘッドの移動で常に画像の同じ位置にモニタ領域が入ってくれば、ＣＣＤカメラの階調をそのままモニタしていけばよいが、実際には図８に示すように観察領域での光源の照射むらが存在する。また、モニタ領域は２０μｍ四方（観察領域は１ｍｍ四方）であり、ヘッドの位置精度がそれほどないため、画像の全く同じ位置にはこない。例えば同じモニタ領域が図８に示すよう光源の照射むらのなかで暗い部分（位置Ａ）にきた場合と、明るい部分（位置Ｂ）にきた場合では、位置Ａにきた場合（図９）のほうが位置Ｂにきた場合（図１０）よりも暗くなってしまう。そのため、ＣＣＤカメラの階調を測定していっても十分な精度が得られない。
【００８０】
このような場合には各チップのモニタリングを行う前に予め、図８のように光源の照射むらを画像として取得しておき、図９のように位置Ａにきた場合には、図８の位置Ａの反射光強度で規格化した値をモニタ領域の規格化反射光強度（Ｉ_A／ｉ_A）とし、図１０に示すようにモニタ領域が位置Ｂにきた場合には図８の位置Ｂの反射光強度で規格化した値をモニタ領域の規格化反射光強度（Ｉ_B／ｉ_B）とする。このとき、ＣＣＤの階調にバックグランドがのっている場合には予め測定（Ｉ_bgnd）しておき、バックグランドを引いて規格化反射光強度を求める（例えば位置Ａでは（Ｉ_A-Ｉ_bgnd）／(ｉ_A-Ｉ_bgnd)）。
【００８１】
なお、Ｉ_α（α：Ａ又はＢ）は測定を行ったモニタ領域の反射光強度であり、ｉ_α（α：Ａ又はＢ）は図８に示す前記光源の照射むらが存在する画像中で前記モニタ領域の反射光強度である。
【００８２】
また、図１１に示すように、光源の照射むらがさほど大きくなく、モニタ領域（位置Ｃ）が常に光源の照射むらのなかで同じところにくる場合には、規格化に用いる反射光強度をモニタ領域の近傍の反射光強度（ｉ_C）として規格化を行ってもよい。
【００８３】
実際に９つのチップについて、規格化反射光強度を取得した結果を図２１に示す。これらから規格化反射光強度の中央値（標本中の中央の値）を求めると２．０８になり、現像をモニタするチップをｃｈｉｐ２とした。代表するチップとしては、チップの反射光強度のばらつき方がランダムである場合には、反射光強度の平均値や中央値から選べばよい。また、ほとんどのチップの反射光強度が同じで特異的なチップがいくつかあるような場合には最頻値から選べばよい。あらかじめ、どのようなばらつきがあるかを調べておいて、最適な方法を選べばよい。
【００８４】
次に、ｃｈｉｐ２の現像モニタ領域をモニタし、最適な現像時間を求める方法について説明する。図２２に現像モニタ領域の反射光強度変化を示す。ここで、縦軸の規格化反射光強度は、第１実施形態で示したように、モニタ領域の反射光強度を予め取得している光源の同じ場所の反射光強度で規格化した値（例えば図９の位置Ａの反射光強度を図８の位置Ａの反射光強度で規格化）である。本実施形態のように現像モニタ領域にパターンが形成されるようなものを用いる場合には、図２２のように現像中の反射光強度変化は単調な変化となる。このような場合には、デバイスパターンが所望寸法に仕上がるときのモニタ領域の反射光強度（所望反射光強度）を予め求めておき、図２２に示すようにモニタ領域の反射光強度が所望値になった時間を現像停止の時間とする。
【００８５】
この実施形態で用いているような現像モニタ領域（パターンが形成される）の反射光強度変化は、第１実施形態で用いたモニタ領域（膜減りが生じる）と比較して小さいため、光源の時間的な変動や現像液面の時間的な変動に起因するノイズの影響が大きくなってくる。そのため、ここでは反射光強度の時間的な変動を考慮した規格化を行う。その説明の図を図２３に示す。図２３（ａ）に示す規格化に用いる画像というのは、予め光源の照射むらを測定するための画像で、レジストの未露光領域の画像を取得したものである。図２３（ｂ）に示す反射光強度の取得に用いる画像というのは、反射光強度変化を取得していくモニタ領域が含まれる画像である。ここまでに示してきた規格化は光源の照射むらを補正するもので、モニタ領域のエリアＡの反射光強度をＩ_A／ｉ_Aとして求めていた。
【００８６】
さらに、時間的な変動を補正するために、モニタ領域の近傍にある未露光領域、エリアＢの反射光強度を求め（Ｉ_B／ ｉ_B）、この反射光強度で規格化を行う。規格化反射光強度I_stを求める式を下記に示す。
【００８７】
【数７】

【００８８】
このように時間的変動を考慮した場合の反射光強度変化を図２４に示す。この図と図２２を比較することにより、時間的変動を考慮することで、ノイズがおさえられていることがわかる。従って、現像中のモニタパターンの反射光強度の取得にはこの規格化の方法を採用した。もし、ＣＣＤの階調にバックグランドがのっている場合には次の式に示すように、バックグランド（Ｉ_bgnd）を差し引いて規格化を行ってもよい。また、第１実施形態では現像中の反射光強度をＣＣＤの階調としているが、下記の式で求めることで、反射光強度変化にノイズが少なくなるので、この方法を用いてもよい。
【００８９】
【数８】

【００９０】
次に、現像を停止させるときのモニタパターンの反射光強度を決めるのに必要なモニタパターンの規格化反射光強度と１７５ｎｍＬ／Ｓのライン寸法との関係を図２５に示す。この関係より、反射光強度しきい値を０．７４６と定めた。従って、実際の現像を行う場合には、図２４の時間変動を考慮した場合の規格化反射光強度を測定していき、反射光強度が０．７４６になった時点で現像を停止させる。
【００９１】
もし、モニタリングを行っている状態から現像を停止（リンス液を供給）させるまでに時間差が生じる場合は、反射光強度変化から時間差分だけ先の反射光強度を予測し、予測反射光強度が所望値となった時点で、現像停止に移ればよい。
【００９２】
ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップを潜像モニタ領域の反射光強度を測定することで抽出し、このチップの現像モニタ領域を現像中にモニタし、その反射光強度変化から最適な現像時間を算出し現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができる。これにより、歩留まりが大きく向上する。また、反射光強度を測定する際に、膜厚変化に対して敏感な波長をプローブ光として用いること、光源の照射むらを考慮した反射光強度の規格化を行うことにより、反射光強度の測定精度が向上し、代表的なチップを抽出する精度が向上する。また現像中に反射光強度変化を測定していく際に、光源の照射むらだけでなく、時間的な変動を考慮した反射光強度の規格化を行うことで、反射光強度の測定精度が向上し、寸法を制御する精度が向上する。
【００９３】
なお、以上説明した発明は、上記実施形態に限定されるものではない。例えば、光源の照射むら、或いは時間的な反射光強度変化を規格化して、反射光強度の補正を行っていたが、前に示した規格化方法は、上述した他のモニタ領域からの反射光強度を規格化する場合も適用することができる。
【００９４】
本実施形態では検出器をＣＣＤとした例を示したが、より測定感度の高いフォトマル等を用いてもよい。この場合は、光源の同じ場所に測定位置がくるので、強度の補正も容易である。
【００９５】
上述した実施形態は、現像前の潜像をモニタして平均的なチップを抽出し、抽出されたチップのモニタパターンからの反射光を現像中にモニタし、反射光の強度変化に基づいて最適な現像時間で現像を終了させるという方法である。しかし、この手法では下地の膜厚が変動する場合、反射光の強度も変動するために、十分な精度が得られないという問題があった。そこで、以下の実施形態では、下地の膜厚変動が変動した場合にも十分な精度が得られる手法について説明する。
【００９６】
［第３実施形態］
本実施形態はウェハの下地膜厚がある範囲で変動していて、その変動がわからない場合に、潜像のモニタリングおよび現像中のモニタリングを異なるモニタ領域に対して行った場合である。
【００９７】
図１は、本発明の現像装置の構成を示す図である。本実施形態は、ウェハの下地膜厚がある範囲で変動していて、その変動量が分からない場合に、潜像のモニタリング及び現像中のモニタリングを異なるモニタ領域に対して行った場合である。
【００９８】
現像ユニット１００内に、通常の現像〜リンスを行うのに必要なユニットの他に、モニタを行うためのモニタヘッド１０１が配置されている。モニタヘッド１０１にはプローブ光の光源（条件によって波長が選択できるように狭帯域フィルタを複数内蔵）１０２、モニタヘッド１０１に光を導入するファイバ１０３が接続されていて、モニタヘッド１０１中のコリメーションレンズにより、特定の波長に狭帯域化したほぼ単色の平行光でウェハ１０４を照明できるようになっている。また、ウェハ１０４からの反射光は、モニタヘッド１０１中にあるＣＣＤカメラとフォトマルで検出できるようになっている。ＣＣＤカメラでは位置検出を行い、フォトマルでは反射光強度を測定する。このモニタヘッド１０１は、複数のチップ１０５内に配置されたモニタ領域１０６をモニタできるように、装置の制御部１０９からの信号でウェハ１０４上を走査可能である。モニタヘッド１０１はマスクのレイアウト及び露光のショットマップを元に特定のチップのモニタ領域が検出できる位置に移動し、フォトマルの検出領域にモニタ領域が含まれるようにヘッドの位置を合わせ、フォトマルで反射強度が測定できるようになっている。
【００９９】
なお、図２６に示すように、本実施形態の場合、ウェハ１７０４に複数形成されたチップ１７０５のモニタ領域１７０７には、潜像モニタ領域１８０２及び現像モニタ領域１８０３の他に、現像直後にレジストが無くなるレジスト残膜０領域が配置１８０４されている。モニタ領域１７０６は、マーク領域１７０７が形成されたダイシングラインに配置されている。
【０１００】
本実施形態では、潜像モニタ領域は特定の透過率を有するパターン、現像モニタ領域にはデバイスパターンである２００ｎｍＬ／Ｓパターンを用いる。特定の透過率を有するパターンの作製方法は第１実施形態に示した通りである。本実施形態でも、潜像モニタパターンとしては透過率を４６．９％にしたパターンを用い、この領域の反射光強度を測定する。
【０１０１】
次に、潜像モニタ領域からの反射光強度の測定時にどのようにしてレジスト膜の膜減り量を求めるかを説明する。ここでは、レジスト、反射防止膜の下層に、下地層として酸化膜が形成され、その酸化膜の膜厚が３１０ｎｍを中心に±５ｎｍの範囲内でばらついている場合を考える。
【０１０２】
先ず、酸化膜厚が３０５，３１０，３１５ｎｍとした場合のレジスト膜減り量と反射光強度の関係を図２７に示す。反射光強度はレジストの初期膜厚（膜減り量０）の反射光強度で規格化している。ここで、潜像モニタ領域に照射するプローブ光の波長は５５０ｎｍとしている。その理由としては、中心膜厚３１０ｎｍのとき、測定したい膜減り量（１０ｎｍ）の付近で反射光の強度変化が大きいためである。
【０１０３】
さらに、図２７において、必要となるレジスト膜減り量１０ｎｍ近傍を拡大した図を図２８に示す。図２８から、例えば潜像モニタ領域からの規格化反射光強度が１．１であった場合、下地の酸化膜厚が３０５〜３１５ｎｍの間で振れていて、レジスト膜厚の測定誤差が３ｎｍ程度となることがわかる。図２に示す露光量と膜減り量との関係を見ると、３ｎｍの測定誤差は余りにも大きすぎて、露光量を正確に求めることは不可能であることがわかる。従って、下地膜厚が変動する場合、一つの波長の反射光強度を測定しても正確にレジスト膜厚を求めることはできない。
【０１０４】
膜厚が変動する下地層上のレジストの膜減り量を正確に求める方法として、潜像モニタ領域に対して複数の波長の光を照射し、それぞれの波長の光の反射率を計測し、予め求めているレジスト・下地が変化した場合の反射率の関係をもとに求めることは可能である。この方法が複数の膜厚を求めるには最も精度が高い。しかし、測定に多大な時間を要する。実際のプロセスでは、複数チップ（１０チップ程度）のモニタ領域の膜厚計測に多く見積もっても３０秒程度しかかけられないため、このような手法はとれない。
【０１０５】
そこで、本実施形態では以下に示すような、潜像モニタ領域からの２つの波長の反射光を用いる方法を説明する。２つの波長としては、図２９に示すように、レジスト膜の初期膜厚付近で変化の変曲点となり、傾きが逆になるような波長を用いる。本実施形態では５５０ｎｍと４２０ｎｍとの二つの波長を用いる。
【０１０６】
ここではレジストの膜減り量１０ｎｍとして、下地の酸化膜厚が変動した場合に同じレジスト膜厚を算出する方法を説明する。図３０は波長が５５０ｎｍの場合、図３１は波長が４２０ｎｍの場合のレジスト膜減り量（潜像深さ）と規格化反射光強度との関係を示す特性図である。ともに、下地の膜厚の中心値（３１０ｎｍ）の関係を用いて、レジスト膜の膜減り量を計測する。
【０１０７】
下地の酸化膜厚が３０５ｎｍに変動していた場合、５５０ｎｍの波長では、図３０の実線の矢印に示すように、レジスト膜の膜減り量を９．２５ｎｍと算出してしまう。また、４２０ｎｍの波長では図３１の実線の矢印に示すようにレジスト膜の膜減り量を１１．５ｎｍと算出する。つまり実際の膜厚からのずれの比率が０．７５：１．５であるため、ずれ比率として１：２としておく。ここで、レジスト膜厚を求める式は、５５０ｎｍの波長を用いて測定されたレジスト膜厚をｄ₅₅₀、４２０ｎｍの波長を用いた測定されたレジスト膜厚をｄ₄₂₀、ずれ比率をｍ：ｎとしたとき真のレジスト膜厚ｄを重み付け平均で求め、下記の式で求めることとする。
【０１０８】
ｄ＝（ｎ×ｄ₅₀₀＋ｍ×ｄ₄₂₀）／（ｍ＋ｎ）
異なる波長の反射光強度の重み付け平均を用いることにより、下地の酸化膜の膜厚が３０５ｎｍ（図３０，３１の実線の矢印）でも膜厚が３１５ｎｍ（図３０，３１の点線の矢印）でも同様に、真のレジスト膜の膜厚を３９０ｎｍ（膜減り量１０ｎｍ）と算出できる。
【０１０９】
次に、現像時のモニタリングでどのように現像終了時間を求めるかを説明する。図３２に本実施形態で現像モニタ領域とした２００ｎｍＬ／Ｓパターンからの現像中における反射光強度変化の一例を示す。ここでは、現像中に反射光強度変化が大きく現れる５５０ｎｍの波長が現像終了時間を決めるためのモニタリング波長である。図３２において、反射光強度は、レジストの未露光部分の反射光強度で規格化されている。つまり、フォトマルでの強度検出領域がレジスト未露光部にくるようにヘッドを移動し、取得した強度で規格化されている。
【０１１０】
なお、図３２に示す現像中における反射光強度の変化は、下地の酸化膜厚が３１０ｎｍ（中心値）の場合のものである。この場合、現像モニタ領域からの規格化反射光強度が０．８８になったときに所望寸法に仕上がることがあらかじめわかっている。従って、図３２に示すような反射光強度変化を示す場合には、規格化反射光強度が０．８８に達した時点（３４秒）で現像を終了させればよい。
【０１１１】
しかし、下地の酸化膜厚が３０５，３１５ｎｍに変化した場合には図３３に示すように、反射光強度が全体的にシフトする。従って、いつも同じしきい値（０．８８）で現像を終了させても同じ寸法に仕上がらない。つまり、現像中に酸化膜の膜厚を測定する必要がある。
【０１１２】
ここではレジスト未露光部の反射光強度で規格化したレジスト残膜０の部分であるレジスト残膜０領域からの反射光強度から下地である酸化膜厚を測定する。この場合、酸化膜厚を精度よく測定するには、レジスト残膜０領域からの規格化反射光強度が膜厚変動に対して大きく変動することが望ましい。図３４に波長４５０ｎｍの光でモニタリングした場合のレジストの膜減り量と規格化反射光強度の関係を示す。図３４より、レジストの膜減り量４００ｎｍ（残膜０）の時の反射光強度が大きく変わることがわかる。
【０１１３】
実際に、酸化膜の膜厚とレジスト残膜０領域からの規格化反射光強度との関係を図３５に示す。この関係をもとに現像中に４５０ｎｍの光でレジスト残膜０領域からの規格化反射光強度を測定することで、下地の酸化膜厚を測定することができる。
【０１１４】
そして、あらかじめ図３６に示すように、下地の酸化膜厚と現像終点の反射光強度しきい値との関係を求めておけば、測定した下地の酸化膜の膜厚から現像終点の反射光強度しきい値を求めることができる。
【０１１５】
次に、本発明を用いた場合の現像シーケンスを図３７に示す。先ず、ウェハを現像ユニットに搬送する（ステップＳ１）。次いで、ウェハが搬送されると、ウェハに設けられているノッチの位置を検出し、ウェハの回転方向の位置調整を行う（ステップＳ２）。その後、特定のチップ（ｉ）のモニタ領域にモニタヘッドを移動させ（ステップＳ３）、フォトマルの検出領域にモニタ領域が含まれるようにヘッドの位置合わせ、フォトマルで反射光強度を測定し、モニタ領域の膜減り量を計測する（ステップＳ４）。
【０１１６】
次いで、モニタ領域のレジストの膜減り量を測定したチップの個数を判定し（ステップＳ５）、チップの個数がｎ個になるまで同様のモニタ領域の膜厚測定をｎ個のチップに対して行う。次いで、得られたレジストの膜減り量の最頻値から現像時間を制御するためにモニタするチップ（ｋ）を決定する（ステップＳ６）。
【０１１７】
そして、現像を開始し（ステップＳ７）、モニタヘッドをチップ（ｋ）の位置に移動させ、現像モニタ領域（２００ｎｍＬ／Ｓパターン）の反射光強度変化を測定する。現像初期では下地の酸化膜厚がわからないため、膜厚の測定のために波長４５０ｎｍの光でレジスト残膜０領域からの規格化反射光強度を測定する。測定された規格化反射強度と図３５とから酸化膜厚を求める（ステップＳ８）。このときの強度測定は、フォトマルの検出領域に、レジスト残膜０の領域、未露光の領域が含まれるようにヘッドを移動し、それぞれの領域の強度を測定し、規格化する。
【０１１８】
求められた酸化膜厚と図３６とから反射光強度しきい値を決定する（ステップＳ９）。次いで、モニタ波長を反射光強度しきい値を求める場合の５５０ｎｍに変更して、更にフォトマルの検出領域に現像モニタ領域が入るようにヘッドを移動し、現像モニタ領域からの規格化反射強度を測定する（ステップＳ１０）。現像モニタ領域からの測定反射光強度が反射光強度しきい値に達したかを判別し（ステップＳ１１）、測定反射光強度が反射光強度しきい値に達した時点で現像を停止させる（ステップＳ１２）。
【０１１９】
このシーケンスについて、実際の実験結果をもとに説明する、図７にウェハのショットマップおよび、現像前にモニタする９つのチップの走査順番の一例を示す。これらのチップについて、潜像モニタ領域が画像に入るような位置にモニタヘッドが移動し、さらにフォトマルの検出領域に未露光領域と潜像モニタ領域が含まれるようにヘッドを移動させて、レジストの膜減り量の計測を行う。実際に９つのチップについて、５５０ｎｍ及び４２０ｎｍの２つ波長を用いてレジストの膜減り量を計測した結果を図３８に示す。これらから膜減り量の最頻値（モード）を求めると１１．５ｎｍになり、現像時にモニタするチップをチップ６と決定した。
【０１２０】
次に、チップ６のモニタ領域をモニタし、最適な現像時間を求める方法について説明する。先ず、現像初期に波長４５０ｎｍ光でレジスト残膜０の領域の規格化反射光強度を測定する。このとき、規格化強度は、フォトマルの検出領域にレジスト残膜０の領域、レジストの未露光部が含まれるようにヘッド位置を合わせ、それぞれの強度から求める。測定の結果、規格化反射光強度は０．９であったので、酸化膜厚が図３５より３１５ｎｍと求められる。
【０１２１】
次いで、図３６より、現像を止める反射光強度しきい値が０．８７と求められる。その後、測定波長を５５０ｎｍとしてフォトマルの検出領域が現像モニタ領域に含まれるようにヘッドの位置を合わせ、２００ｎｍＬ／Ｓパターンの反射光強度変化をモニタすると図３９のようになった。従って２７秒で、被処理基板上に現像停止液を供給して、現像を終了させる。
【０１２２】
本実施形態によれば、ウェハ間の寸法のばらつきを低減させるために、現像時間の制御を行う場合に、ウェハの中で代表的な条件で処理されているチップをモニタ領域の膜厚を測定することで抽出する。現像を開始し、このチップの現像モニタ領域の反射光強度をモニタする前に、下地の膜厚を測定し、反射光強度しきい値を定め、現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができる。これにより、歩留まりが大きく向上する。
【０１２３】
また、レジストの膜減り量を測定する際に、膜厚変化に対して敏感な波長で、測定膜厚付近での位相が１８０度異なる２つの波長をプローブ光として用いることにより短時間での膜厚測定が可能となる。
【０１２４】
また、現像の前半で反射光強度しきい値を決めるためにレジスト残膜０となる領域の反射光強度を計測することで下地膜厚を測定し、現像モニタパターンの反射光強度しきい値を求めることで、現像時間を求める精度が向上し、ウェハ間の寸法のばらつきを大きく低減することができる。また、強度検出器をフォトマルとすることで、測定精度が大きく向上する。
【０１２５】
［第４実施形態］
本実施形態では、ウェハの下地膜厚がある範囲で変動していて、その変動量が現像工程の前までにわかっている場合に、潜像のモニタリングおよび現像中のモニタリングを異なるモニタ領域に対して行った場合について説明する。
【０１２６】
図１は、本発明の現像装置の構成を示す図である。本実施形態は、ウェハの下地膜厚がある範囲で変動して、その変動量が現像工程の前までに分かっている場合に、潜像のモニタリング及び現像中のモニタリングを異なるモニタ領域に対して行った場合である。
【０１２７】
現像ユニット１００内に、通常の現像〜リンスを行うのに必要なユニットの他に、モニタを行うためのモニタヘッド１０１が配置されている。モニタヘッド１０１にはプローブ光の光源１０２、ヘッド１０１に光を導入するファイバ１０３が接続されている。ヘッド１０１内では、光源１０２からファイバ１０３で導入された光をレンズによりハーフミラーに導き、ウェハ上のあるスポットを照明することができる。また、ウェハからの反射光は、現像モニタヘッドの中にあるＣＣＤカメラとフォトマルで検出できるようになっている。ＣＣＤカメラでは位置検出を行い、フォトマルでは反射光強度を測定する。また、フォトマルに光が入射する前には回折格子が設置されていて、フォトマルには特定波長の光が入射できるようになっている。このモニタヘッド１０１は、複数のチップ１０５内に配置されたモニタ領域１０６をモニタできるように、装置の制御部１０９からの信号でウェハ上を走査可能である。モニタヘッド１０１はマスクのレイアウト及び露光のショットマップを元に特定のチップのモニタ領域が検出できる位置に移動し、フォトマルの検出領域にモニタ領域が含まれるようにヘッドの位置を合わせ、フォトマルで反射光強度が測定できるようになっている。
【０１２８】
また、ウェハのチップに形成されたモニタ領域には、第３実施形態と同様に、潜像モニタ領域，現像モニタ領域及びレジスト残膜０領域が形成されている。 本実施形態でも、潜像モニタ領域としては透過率を４６．９％にしたパターンを用い、この領域の膜厚を測定する。
【０１２９】
次に、潜像のモニタ時にどのようにして膜減り量を求めるかを説明する。ここでは、レジスト、反射防止膜の下層に酸化膜が形成され、その酸化膜の膜厚が３１０ｎｍを中心に±５ｎｍの範囲内でばらついている場合を考える。第３実施形態では、下地の酸化膜の膜厚が未知であったが、本実施形態ではすでに現像工程の前まで（例えばＣＭＰ工程）に酸化膜厚が測定済みであり、その膜厚情報は解析部に送られてきている。従って、レジスト膜厚の計測は１つの波長で行う。例えば酸化膜厚が３１０ｎｍと測定されていれば、図２８の実線の関係を用いてレジスト膜厚を計測すればよい。つまり、予め求めている酸化膜厚ごとのレジスト膜減り量と規格化反射光強度の関係をもとに膜厚を計測する。
【０１３０】
次に、現像時のモニタリングでどのように現像終了時間を求めるかを説明する。本実施形態では現像モニタ領域の反射光強度変化の特異的な点に注目し、最適な現像時間を求める。
図４０に現像モニタ領域である２００ｎｍＬ／Ｓパターンからの現像中の反射光強度変化を示す（波長５５０ｎｍ）。この反射光強度変化において、現像時間１５秒の前後で反射光強度変化のモードが変化している。１５秒より以前は、レジストの露光部が現像されてレジスト膜厚が減っていく過程である。１５秒でレジスト膜が抜けきり、その後はパターンの側壁部分が少しずつ現像されていく過程である。
【０１３１】
この反射光強度変化のモード変化は、パターンの現像過程によるものなので、下地の酸化膜の膜厚には全く依存しない。そこで、本実施形態では、この反射光強度変化のモードが変わる点（図４０記載のパターン抜け時間）に基づいて最適な現像時間を算出する。
【０１３２】
図４１に露光量とパターン抜け時間の関係を示す。この関係より、現像モニタ領域でのパターン抜け時間を計測すれば露光量を求められることがわかる。従って、図４２に示すようなあらかじめ露光量と最適な現像時間の関係を求めておけば、現像モニタ領域でのパターン抜け時間から最適な現像時間を求めることができる。
【０１３３】
しかし、フォーカス値が大きくずれてしまった場合には、図４３に示すように、パターン抜け時間から露光量を求めるときにジャストフォーカスのデータを用いてしまうと、正確に露光量を求めることができない。従って、このような場合には、デフォーカスの影響を受けないパターン即ち、特定の透過率を有するパターン（潜像モニタ領域のパターン）からの反射光強度を併せてモニタする。
【０１３４】
現像中において、潜像モニタ領域に用いた透過率４６．９％のパターンからの規格化反射光強度の挙動は、図４４に示すようになる（プローブ光の波長４２０ｎｍ）。このパターンは一定の露光量で露光されているため、時間の経過とともに干渉波形を示しながら膜減りしていき、レジストの膜厚が０になると反射光強度変化を示さなくなる。この反射光強度変化を示さなくなる時間を、抜け時間と呼ぶことにする。図４５に示すように、この抜け時間と露光量の関係は一対一の対応関係にある。従って、潜像モニタ領域でのパターン抜け時間を測定することで正確な露光量が求められる。
【０１３５】
図４４に示した現像中の潜像モニタ領域の規格化反射光強度を測定する際、プローブ光として４２０ｎｍの波長を用いている。この波長を用いた理由は、レジストの膜厚が０になるところで、反射光強度変化の変曲点になるようにしたかったためである。このような波長を設定しておけば、抜け時間が精度よく求められるし、下地膜厚が多少変動してもほとんど影響を受けない。
【０１３６】
このように、特定の透過率を有するパターンの抜け時間から露光量を求め、２００ｎｍＬ／Ｓパターンの抜け時間とあわせて、図４３の関係を用いると、フォーカス値も求めることができる。従って、予め、フォーカス・露光量が与えられたときの最適な現像時間を求めておけば、パターン寸法を所望値に仕上げることができる。もちろん、フォーカスのずれはチップによって異なる場合もあるので、特定の透過率を有するパターンの抜け時間から求めた露光量に応じた現像時間で現像を行ってもよい。
【０１３７】
次に、本発明を用いた場合の現像シーケンスについて説明する。本実施形態の現像シーケンスが、第３実施形態と異なるのは、膜厚の測定方法と現像終了の判断方法である。
【０１３８】
ここでは、現像終了の判断方法について、図４６に示すフローチャートを用いて説明する。図４６は、現像終了の判断方法を示すフローチャートである。
【０１３９】
先ず、現像開始後（ステップＳ１）、波長５５０ｎｍの光で現像モニタ領域からの反射光をモニタし、露光モニタ領域でのパターン抜け時間を測定する（ステップＳ２）。
【０１４０】
次いで、特定の透過率を有するパターン（潜像モニタ領域）からの反射光を波長４２０ｎｍの光でモニタし、潜像モニタ領域でのパターン抜け時間を測定する（ステップＳ３）。
【０１４１】
次いで、測定されたパターン抜け時間と、図４５に示すパターン抜け時間と露光量との関係とから、露光量を算出する（ステップＳ４）。
【０１４２】
ステップＳ３で算出された露光量及び測定されたパターン抜け時間と、図４３に示すフォーカスが変動した場合の露光量とパターン抜け時間との関係とから、フォーカス位置を算出する（ステップＳ５）。
【０１４３】
ステップＳ２，３における反射光強度測定は、フォトマルの検出領域にモニタ領域が含まれるようにヘッドを移動させ、且つモニタ波長が所望の値となるように回折格子の角度を調整して行う。
【０１４４】
次いで、算出された露光量及びフォーカス位置と、予め求められたフォーカス・露光量が与えられたときの最適な現像時間とから、パターン寸法を所望値に仕上げる現像時間を決定する（ステップＳ６）。
【０１４５】
次いで、現像を開始してからの時間が、ステップＳ６で決定された現像時間を経過したか判定する（ステップＳ７）。決定された現像時間が過ぎていたら、ウェハ上に現像停止液を供給し、現像を停止させる（ステップＳ８）。
【０１４６】
本実施形態の現像シーケンスについて、実際の実験結果をもとに説明する。ウェハのショットマップおよび、現像前にモニタする９つのチップの走査順番は第３実施形態と同様、図７の通りである。これらのチップについて、モニタ領域が画像に入るような位置にモニタヘッドを移動させ、フォトマルの検出領域に未露光領域と潜像モニタ領域とが含まれるようにヘッドを移動させ、レジストの膜減り量の計測を行う。
【０１４７】
実際に９つのチップについて、５５０ｎｍの波長を用いて膜厚を計測した結果を図４７に示す。これらから膜減り量の平均値を求めると１１．４ｎｍになり、現像をモニタするチップをチップ１とした。
【０１４８】
次に、チップ１のモニタ領域をモニタし、最適な現像時間を求める方法について説明する。
まず、図４３，４５に示すように、現像中にモニタする２００ｎｍＬ／Ｓパターン（現像モニタ領域）と特定の透過率を有するパターン（潜像モニタ領域）では、抜け時間が前者で１５秒以下、後者で２０〜３０秒であるため、現像開始後１５秒までは波長５５０ｎｍでモニタリングを行ってパターン抜け時間を計測し、１５秒以降は波長４２０ｎｍの光でモニタリングを行って抜け時間を計測する。つまり、１５秒までは、フォトマルの測定領域に２００ｎｍＬ／Ｓパターンが含まれるようにヘッドの位置を合わせ、波長が５５０ｎｍとなるように回折格子の角度を調整してモニタリングを行う。そして、１５秒以降は潜像モニタ領域にヘッドの位置を合わせ、波長が４２０ｎｍとなるように角度を調整してモニタリングを行う。
【０１４９】
実際の計測では、前者が１０秒、後者が２１秒となり、露光量が２０．５ｍＪ／ｃｍ２、フォーカス０μｍと測定され、図４２の関係をもとに、５３秒で現像を終了させた。
【０１５０】
ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップをモニタ領域の膜厚を測定することで抽出する。現像を開始し、このチップの現像モニタ領域の反射光強度変化のなかで下地膜厚に依存しない特異的な点から露光量やフォーカス値を測定し、それにみあった最適な現像を行うことにより、ウェハ間の寸法のばらつきを大きく低減することができる。これにより、歩留まりが大きく向上する。また、強度検出器をフォトマルとすることで測定精度が大きく向上する。
【０１５１】
なお、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で、種々変形して実施することが可能である。
【０１５２】
【発明の効果】
以上説明したように本発明によれば、ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップを潜像モニタ領域の反射光強度を測定することで抽出し、そのチップの現像モニタ領域を現像中にモニタし、その反射光強度から最適な現像時間を算出し現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができる。これにより、歩留まりが大きく向上する。
【０１５３】
また、反射光強度を測定する際に、光源の照射むら或いは時間的な反射光強度の変化を考慮した反射光強度の規格化を行うことにより、反射光強度の測定精度が向上し、代表的なチップを抽出する精度が向上する。
【０１５４】
また、ウェハ間の寸法のばらつきを低減させるために、現像時間制御を行う場合に、ウェハの中で代表的な条件で処理されているチップを潜像モニタ領域の潜像深さを測定することで抽出し、そのチップの現像モニタ領域を現像中にモニタし、その反射光強度から最適な現像時間を算出し現像時間を制御するにより、ウェハ間の寸法のばらつきを大きく低減することができ、歩留まりが大きく向上する。
【０１５５】
また、反射光強度変化の特異点から現像終点を求める手法では、現像モニタ領域の反射光強度変化のなかで下地膜厚に依存しない特異的な点から露光量やフォーカス値を測定し、それにみあった最適な現像を行うことにより、ウェハ間の寸法のばらつきを大きく低減することがきできる。また、強度検出器をフォトマルとすることで測定精度が大きく向上する。
【図面の簡単な説明】
【図１】第１実施形態に係わる現像装置の概略構成を示す図。
【図２】露光量とモニタ領域の潜像の膜減り量の関係を示す図。
【図３】露光量とモニタ領域の抜け時間の関係を示す図。
【図４】レジストの膜減り量と反射率の関係（レジスト上に現像液なし）を示す図。
【図５】レジストの膜減り量と反射率の関係（レジスト上に現像液あり）を示す図。
【図６】モニタチップ決定および現像シーケンスを示すフローチャート。
【図７】現像前にモニタする９つのチップの走査順番の一例を示す図。
【図８】観察領域での光源の照射むらの様子を示す図。
【図９】モニタ領域が位置Ａにきた場合を示す図。
【図１０】現像モニタ領域が位置Ｂにきた場合を示す図。
【図１１】光源の強度むらがそれほど大きくない場合を示す図。
【図１２】モニタ領域の反射光強度を計測した結果の一覧を示す図。
【図１３】現像中のモニタ領域の反射光強度変化を示す図。
【図１４】モニタ領域の抜け時間から現像停止時間を算出する方法を示す図。
【図１５】露光量とモニタ領域の反射光強度との関係を示す図。
【図１６】露光量と２００ｎｍＬ／Ｓが１：１に仕上がる時間の関係を示す図。
【図１７】冷却装置および現像装置の概略構成を示す図。
【図１８】モニタ領域の配置位置を示す図。
【図１９】モニタパターンの例を示す図。
【図２０】モニタチップ決定および現像シーケンスを示すフローチャート。
【図２１】反射光強度を計測した結果の一覧を示す図。
【図２２】現像モニタ領域の反射光強度変化を示す図。
【図２３】反射光強度の時間変動を考慮した規格化の方法を示す図。
【図２４】時間変動を考慮した規格化反射光強度変化を示す図。
【図２５】現像を停止させるときのモニタパターンの反射光強度を決めるのに必要なモニタパターンの規格化反射光強度と１７５ｎｍＬ／Ｓのライン寸法との関係を示す図。
【図２６】第３実施形態に係わるウェハ，チップも及びモニタ領域の概略を示す平面図。
【図２７】複数の酸化膜厚におけるレジスト膜減り量と反射光強度［規格化］との関係を示す特性図。
【図２８】複数の酸化膜厚に対するレジスト膜減り量と反射光強度［規格化］との関係を示す特性図。
【図２９】第３実施形態に係わる潜像モニタ領域のモニタに用いる光の波長に必要な関係を説明する図。
【図３０】波長５５０ｎｍの光の場合、複数の酸化膜厚に対するレジストのレジスト膜減り量と反射光強度［規格化］との関係を示す特性図。
【図３１】波長４２０ｎｍの光の場合、複数の酸化膜厚に対するレジストのレジスト膜減り量と反射光強度［規格化］との関係を示す特性図。
【図３２】波長５５０ｎｍの光の場合、現像モニタ領域からの反射光強度［規格化］の時間変化を示す特性図。
【図３３】波長５５０ｎｍの光の場合、複数の酸化膜厚に対する現像モニタ領域からの反射光強度［規格化］の時間変化を示す特性図。
【図３４】波長４５０ｎｍの光の場合、複数の酸化膜厚に対するレジストの膜減り量と反射光強度［規格化］との関係を示す特性図。
【図３５】波長４５０ｎｍの光の場合に、酸化膜の膜厚とレジスト残膜０領域からの反射光強度［規格化］との関係を示す特性図。
【図３６】波長５５０ｎｍの光の場合に、酸化膜厚と反射光強度［規格化］しきい値との関係を示す特性図。
【図３７】第３実施形態に係わるモニタチップ決定及び現像シーケンスを示すフローチャート。
【図３８】各チップの潜像モニタ領域のレジスト膜減り量を計測した結果を示す図。
【図３９】波長５５０ｎｍの光の場合に、現像中における現像モニタ領域からの反射光強度［規格化］の時間変化を示す特性図。
【図４０】波長５５０ｎｍの光の場合に、現像中における現像モニタ領域からの反射光強度［規格化］の時間変化を示す特性図。
【図４１】露光量とパターン抜け時間の関係を示す特性図。
【図４２】露光量とパターン寸法が所望値に仕上がる現像時間との関係を示す特性図。
【図４３】フォーカス位置が変動した場合の、露光量とパターン寸法が所望値に仕上がる現像時間との関係を示す特性図。
【図４４】現像中における潜像モニタ領域からの反射光強度［規格化］の時間変化を示す特性図。
【図４５】露光量と潜像モニタ領域でのパターン抜け時間との関係を示す特性図。
【図４６】第４実施形態に係わる現像シーケンスを示すフローチャート。
【図４７】各チップの潜像モニタ領域のレジスト膜減り量を計測した結果を示す図。
【符号の説明】
１００…現像ユニット
１０１…モニタヘッド
１０３…ファイバ
１０４…ウェハ
１０５…チップ
１０６…モニタ領域
１０７…マーク領域
１０８…解析部
１０９…制御部
１７００…冷却ユニット
１７０１…モニタヘッド
１７０３…ファイバ
１７０４…ウェハ
１７０６…モニタ領域
１７０７…マーク領域
１７０９…制御部
１８０１…デバイスパターン領域
１８０２…潜像モニタ領域
１８０３…現像モニタ領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a resist pattern for photolithography in manufacturing a semiconductor device.
[0002]
[Prior art]
In photolithography used for manufacturing a semiconductor device, it is important to form a resist pattern with high dimensional accuracy. Therefore, conventionally, a method has been adopted in which a monitor pattern different from the device pattern is provided, the reflected light intensity from the monitor pattern is monitored during development or after development, and development time control and dimension control are performed. For example, Japanese Patent Laid-Open No. 10-300428 discloses a method using a pattern different from a device pattern as a monitor pattern.
[0003]
In the conventional method, since the monitor area arranged on a specific chip on the wafer is monitored, if the chip being monitored has a specific condition for some reason, the size of the chip being monitored is Although it is finished to a desired value, there is a problem that the average dimension of the wafer greatly deviates.
[0004]
As a method of reducing dimensional variation between wafers, a method of controlling the development time from the monitoring result of a monitor area provided separately from the device pattern at the time of development, as in Japanese Patent Application No. 10-40603 and Japanese Patent Application No. 11-74046 There is. In these methods, since the monitor area arranged on a specific chip on the wafer is monitored, if the monitored chip has a specific condition for some reason, the size of the monitored chip is Although finished to a desired value, there was a problem that the average dimension of the wafer greatly deviated. In addition, when the change in the monitor area is viewed with the CCD, there is a problem that a subtle change in reflected light cannot be measured.
[0005]
[Problems to be solved by the invention]
As described above, with the miniaturization of the processing dimensions of LSIs, precise dimensional control is also required for the resist development time. There is a method of using a monitor pattern to control the size of the resist pattern. However, if the condition of the monitored chip is specific for some reason, the size of the monitored chip is finished to a desired value. There is a problem that the average dimension of the wafer is greatly deviated.
[0006]
An object of the present invention is to provide a pattern forming method capable of correcting an average dimensional deviation even when chips formed under specific conditions exist.
[0007]
[Means for Solving the Problems]
[Constitution]
The present invention is configured as follows to achieve the above object.
[0008]
(1) The present invention (Claim 1) is a pattern forming method in which a device pattern is exposed to each of a plurality of chip regions of a resist on a substrate to be processed, and the device pattern is formed by development after heating. A plurality of chips between the step of exposing the latent image monitor area and the development monitor area to each chip area of the resist on the substrate to be processed together with the device pattern, and the heating process and the development process after the exposure process. Irradiating each latent image monitor region of the region with light of a specific wavelength and measuring the reflected light intensity of the latent image monitor region, and based on the measurement results, under typical conditions in the substrate to be processed A process of extracting the chip area being processed, and during development of the device pattern, identified for the development monitor area located within the extracted chip area Irradiating the head of the light, characterized by stopping the development in accordance with the reflected light intensity change from developing monitoring area.
[0009]
Preferred embodiments of the present invention are described below.
After detecting the position of the chip area with a camera such as a CCD, it is preferable to switch the optical system and perform the intensity of the extracted part using a high-sensitivity detector such as photomal, and stop the development of the device pattern Is performed by predicting a development stop time during which a device pattern is finished to a desired dimension based on a change in reflected light intensity from the development monitor region.
[0010]
The reflected light intensity of the latent image monitor area is the reflected light intensity I of the latent image monitor area A where the measurement was performed. _A Normalized reflected light intensity I normalized in consideration of the irradiation unevenness of the light source _s And the reflected light intensity of the monitor region in the image obtained in advance in which there is uneven irradiation of the light source is i. _A , Background reflected light intensity I _bgnd The reflected light intensity I _s Is
[0011]
[Expression 4]

[0012]
To be given by.
[0013]
The latent image monitor area and the development monitor area are the same area.
The latent image monitor area or the development monitor area is a specific area of the device pattern area.
The latent image monitor area or the development monitor area is an element pattern created by cutting out a part of a device pattern and changing the dimensions as it is.
The chip area includes not only an area operating as a device but also an area where test patterns and marks are arranged.
The latent image monitor area or the development monitor area is an area having a specific transmittance on the exposure mask.
[0014]
The chip area processed under typical conditions in the wafer is a chip area showing the mode value in the reflected light intensity of the latent image monitor area.
The chip area processed under typical conditions in the wafer is a chip area showing a median value in the reflected light intensity of the latent image monitor area.
[0015]
The chip area processed under typical conditions in the wafer is a chip area showing an average value in the reflected light intensity of the latent image monitor area.
[0023]
( 2 The present invention (claims) 4 ) Is a pattern forming method in which a device pattern is exposed to each of a plurality of chip regions of a resist on a substrate to be processed, and after heating, a device pattern is formed by development, in the exposure of the device pattern, a latent image monitor region and For each latent image monitor area of a plurality of chip areas between the process of exposing the development monitor area to each chip area of the resist on the substrate to be processed together with the device pattern, and the heating process and the development process after the exposure process. Irradiating light of a specific wavelength, and obtaining the latent image depth of the resist from the intensity of reflected light from the latent image monitor region, and based on the measured latent image depth of the resist, In the initial stage of the process of extracting the chip area processed under typical conditions and the development process of the device pattern, the chip area is arranged in the extracted chip. Irradiating the monitor region with light of a plurality of wavelengths to measure the film thickness of the resist substrate; determining a reflected light intensity threshold from the measured film thickness of the substrate; and During development, the development monitor area arranged in the extracted chip area is irradiated with light of a specific wavelength, and the reflected light intensity change from the development monitor area and the determined reflected light intensity threshold The development is stopped based on the above.
[0024]
Preferred embodiments of the present invention are described below.
In the step of measuring the film thickness configuration of the resist base in the initial stage of the development process, the film thickness configuration of the base includes a reflected light intensity ratio between a region where the resist is formed on the entire surface and a region of the resist residual film 0. It is calculated | required from the relationship with the film thickness of the said foundation | substrate. More preferably, the wavelength irradiated to the monitor region is a wavelength with a large change in the reflected light intensity ratio with respect to the film thickness variation.
In the step of determining the reflected light intensity threshold value, the reflected light intensity threshold value is determined from a relationship between the reflected light intensity threshold value and the underlying film thickness with respect to a previously obtained underlying film thickness.
[0025]
( 3 The present invention (claims) 7 ) In a pattern forming method of exposing a device pattern to each of a plurality of chip regions of a resist on a substrate to be processed, and forming a device pattern by development after heating, in the exposure of the device pattern, For each latent image monitor area of a plurality of chip areas between the process of exposing the development monitor area to each chip area of the resist on the substrate to be processed together with the device pattern, and the heating process and the development process after the exposure process. Irradiating light of a specific wavelength to measure the reflected light intensity of the latent image monitor region, determining the latent image depth of the resist from the measured reflected intensity, and measuring the measured latent image of the resist During the step of extracting the chip region processed under typical conditions in the substrate to be processed based on the depth, and during the development process of the device pattern, Irradiating the development monitor area in the extracted chip area with light of a specific wavelength, and predicting the development stop time when the device pattern is finished to a desired dimension from the singular point of the relationship between the development time and the reflected light intensity, and prediction And a step of stopping development during the development stop time.
[0026]
Preferred embodiments of the present invention are described below.
When the development monitor area is configured with a hole or line pattern, the singular point of the relationship between the development time and the reflected light intensity is a pattern omission time, and the development stop time is determined by a predetermined device pattern. Predicting based on the relationship between the time required to achieve a desired dimension and the pattern omission time.
[0027]
When the development monitor area is configured with a pattern having a specific transmittance on the mask, the singular point of the relationship between the development time and the reflected light intensity is the resist removal time, and the development stop time is determined in advance. Predicted based on the relationship between the time required for a desired device pattern to be finished to a desired dimension and the resist removal time.
[0028]
These inventions (claims) 4,7 Preferred embodiments of the invention are described below.
[0029]
In the step of determining the latent image depth of the resist, if the film thickness of the resist base is unknown, the light of the specific wavelength is the initial film thickness of the resist in the relationship between the film thickness of the resist and the reflection intensity. In the vicinity, the relationship shows an inflection point, and light of two wavelengths having a phase difference of 180 ° near the initial film thickness, and the latent image depth of the resist obtained from the reflected light intensities of the two wavelengths, respectively. The latent image depth of the resist is obtained by weighted averaging.
[0030]
In the step of determining the latent image depth of the resist, when the film thickness of the base of the resist is known, the initial film of the resist in relation to the film thickness of the resist and the reflection intensity with respect to the latent image monitor region Irradiate light having a wavelength at which the relationship indicates an inflection point in the vicinity of the thickness, and obtain the latent image depth of the resist based on the relationship between the reflected light intensity and the resist film thickness with respect to the film thickness of the base that has been obtained in advance. thing.
[0031]
[Action]
The present invention has the following operations and effects by the above configuration.
[0032]
When developing time control is performed to reduce dimensional variation between wafers, chip areas processed under typical conditions in the wafer are extracted by measuring the reflected light intensity of the latent image monitor area. Then, by monitoring the development monitor area of the extracted chip area during development and controlling the development time according to the intensity of the reflected light, the dimensional variation between wafers can be greatly reduced.
[0033]
In addition, when measuring reflected light intensity, standardization of reflected light intensity in consideration of uneven illumination of the light source or changes in reflected light intensity over time improves the measurement accuracy of the reflected light intensity. The accuracy of extracting a simple chip area is improved.
[0034]
In addition, when developing time control is performed in order to reduce the dimensional variation between wafers, the latent image depth of the latent image monitor area of a chip processed under typical conditions in the wafer is measured. , The development monitor area of the chip is monitored during development, the optimum development time is calculated from the reflected light intensity, and the development time is controlled, so that the variation in dimensions between wafers can be greatly reduced. Yield is greatly improved.
[0035]
In addition, in the method of obtaining the development end point from the singular point of the reflected light intensity change, the exposure amount and the focus value are measured from a specific point that does not depend on the underlying film thickness in the reflected light intensity change of the development monitor area. By performing the optimum development, it is possible to greatly reduce the dimensional variation between the wafers.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
In the present exemplary embodiment, a case where monitoring of a latent image and monitoring during development are performed on the same monitor area in the developing device will be described.
[0037]
FIG. 1 is a diagram showing a schematic configuration of a developing device according to the first embodiment of the present invention.
[0038]
In the developing unit 100, a monitor head 101 for performing monitoring is disposed in addition to a unit necessary for performing normal development to rinsing. The monitor head 101 is connected with a probe light source (a plurality of narrow band filters so that the wavelength can be selected depending on conditions) 102 and a fiber 103 for introducing light into the monitor head 101, and is connected by a collimation lens in the monitor head 101. The wafer 104 can be illuminated with substantially monochromatic parallel light narrowed to a specific wavelength. The reflected light from the wafer 104 can be detected by a CCD camera in the monitor head 101. The monitor head 101 can scan the wafer 104 with a signal from the control unit 109 of the apparatus so that the monitor area 106 arranged in a plurality of chips (chip areas) 105 can be monitored. The monitor head 101 moves to a position where the monitor area of a specific chip can be detected based on the mask layout and exposure shot map, acquires an image, sends the image to the analysis unit 108, and recognizes the monitor area by pattern matching In addition, the reflected light intensity of the monitor area can be acquired. Note that the chip 105 includes not only a region operating as a device but also a region where test patterns and marks are arranged.
[0039]
As shown in FIG. 1, the monitor area 106 is arranged on a dicing line in which the mark area 107 is formed. As the mask pattern for forming the monitor region, a pattern having a specific transmittance is used. The mask pattern having a specific transmittance is a regular pattern having a pitch that allows only the 0th-order diffracted light to reach the wafer, and is produced by changing the ratio of extraction and remaining on the mask.
[0040]
The condition that only the 0th-order diffracted light reaches the wafer is as follows: exposure wavelength (λ), pitch of pattern on wafer (p), NA, σ
λ / p ≧ (1 + σ) NA (1)
It is determined.
[0041]
Therefore, 220 nm (value on the wafer) is employed as the mask pattern pitch from the illumination conditions during exposure (NA: 0.6, σ: 0.75, exposure wavelength: 248 nm). By using such a pitch pattern, a mask pattern having a specific transmittance can be formed.
[0042]
The transmittance T of such a pattern is as follows. When the pattern pitch is p and the space width of the pattern is d,
T = (d / p) ² (2)
It is expressed.
[0043]
If a mask pattern with a specific ratio is used, the amount of film reduction during the latent image in the monitor area and the development speed during development are determined according to the exposure amount.
[0044]
FIG. 2 and FIG. 3 show the relationship between the exposure amount and the film reduction amount, and the relationship between the exposure amount and the film removal time when the transmittance of the mask pattern for forming the monitor region is 46.9%. Here, the target pattern is a 200 nm L / S pattern, and the exposure amount (20 mJ / cm) at which the target pattern is finished approximately 1: 1. ² ) Shows the relationship in the vicinity. At this time, the resist film thickness is 400 nm and the antireflection film thickness is 60 nm (hereinafter, the same conditions in this embodiment).
[0045]
As shown in FIG. 2, it can be seen that the dose amount and the film reduction amount are in a proportional relationship, and the dose amount is obtained from the film reduction amount. Accordingly, the dose amount can be obtained by monitoring the latent image monitor region and measuring the film reduction amount.
[0046]
Further, as shown in FIG. 3, the dose amount and the missing time are in a proportional relationship, and the dose amount can be obtained from the missing time. Therefore, the exposure amount can be obtained by monitoring during development and measuring the missing time.
[0047]
In the present embodiment, the reflected light intensity is monitored as an amount corresponding to the amount of film reduction in the monitor area when monitoring a latent image, and the time during which reflected light intensity does not change (film removal time) is monitored during development monitoring.
[0048]
Next, how to select the wavelength of light irradiated to the pattern during monitoring will be described. When monitoring a latent image, as shown in FIG. 2, it is necessary to accurately monitor where the film thickness is reduced by about 10 nm.
[0049]
FIG. 4 shows the relationship between the resist film loss and the reflectance when there is no developer on the resist. From this relationship, when the amount of film loss is more than a dozen nm (the range of the arrow in the figure), when monitoring at a wavelength of 430 nm, the reflectance changes monotonously with the film thickness, and the amount of change is large. It is possible to monitor the film reduction amount, that is, the exposure amount with high accuracy from the intensity.
[0050]
In this way, the wavelength at the time of monitoring may be determined so that the change in reflectance is maximized with respect to the resist / antireflection film / underlying structure and the amount of film loss of the monitor pattern near the appropriate exposure amount. In addition, when the place which installs a film thickness meter is permitted as an apparatus structure, you may monitor the film loss amount with a film thickness meter.
[0051]
Further, when monitoring during development, it is necessary to accurately obtain the film removal time shown on the vertical axis of FIG. FIG. 5 shows the relationship between the amount of film loss of the resist and the reflectance when the developer is present on the resist.
[0052]
In order to obtain the omission time with high accuracy, it is desirable that the change in reflectivity is larger in the vicinity (the range of the arrow in FIG. 5) where the resist film thickness becomes 0 (the film reduction amount is 400 nm). . In this manner, the wavelength at the time of monitoring may be determined so that the change in reflectance increases around the resist film thickness of 0 with respect to the resist / antireflection film / underlying structure.
[0053]
Next, a developing sequence when the present invention is used will be described with reference to the flowchart of FIG. After the wafer is transferred to the developing unit (step S1), the position of the notch is detected and the position of the wafer in the rotational direction is adjusted (step S2). Thereafter, the monitor head is moved to the monitor area of the specific chip (i) (step S3), the position of the monitor area is detected by pattern matching, and the reflected light intensity of the monitor area is acquired (step S4). The number of chips for which the reflected light intensity in the monitor area is measured is determined (step S5), and the reflected light intensity in the same monitor area is obtained for n chips until the number of chips reaches n. Then, after measuring the reflected light intensity in the monitor area of n chips, the chip (k) to be monitored is determined in order to control the development time from the mode value of the obtained reflected light intensity (step S6).
[0054]
Then, development is started (step S7), the monitor head is moved to the position of the chip (k), and the reflected light intensity change in the monitor area is measured (step S8). The film removal time is measured from the reflected light intensity change in the monitor area, an appropriate development time is calculated (step S9), and the development is stopped at the calculated development time (step S10).
[0055]
Note that, instead of measuring the film removal time from the reflected light intensity change, the development may be stopped when the reflected light intensity changes.
[0056]
This sequence will be described based on actual experimental results. FIG. 7 shows an example of a wafer shot map and the scanning order of nine chips to be monitored before development. As shown in FIG. 7, chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8, chip 9 and turn The chip is monitored (step S3). For these chips, the monitor head is moved to a position where the monitor area enters the image (step S4), the position of the monitor area is detected by pattern matching, and the intensity of reflected light from the monitor area is acquired (step S4). S5).
[0057]
If there is no unevenness in the light source being observed, or if the monitor area always enters the same position of the image as the monitor head moves, the gradation of the CCD camera can be monitored as it is. However, actually, as shown in FIG. 8, there is uneven illumination of the light source in the observation region. Further, the monitor area is 20 μm square (the observation area is 1 mm square), and the positional accuracy of the head is not so much, so it does not come to the exact same position of the image.
[0058]
For example, when the same monitor area comes to a dark part (position A) and a bright part (position B) in the uneven illumination of the light source as shown in FIG. 8, when it comes to position A (FIG. 9) It becomes darker than when it comes to position B (FIG. 10). Therefore, sufficient accuracy cannot be obtained even when the gradation of the CCD camera is measured.
[0059]
In such a case, the irradiation unevenness of the light source as shown in FIG. 8 is acquired in advance as an image before monitoring each chip, and when the monitor area comes to the position A as shown in FIG. , The value normalized by the reflected light intensity at position A in FIG. 8 is the normalized reflected light intensity (I _A / I _A 10), when the monitor area comes to the position B as shown in FIG. 10, the value normalized by the reflected light intensity at the position B in FIG. _B / I _B ).
[0060]
I _α (Α: A or B) is the reflected light intensity of the monitor area where the measurement was performed, and i _α (Α: A or B) is the reflected light intensity of the monitor region in the image shown in FIG.
[0061]
At this time, if the background of the CCD gradation is present, measurement (I _bgnd Then, the normalized reflected light intensity is obtained by subtracting the background (for example, at position A, (I _A -I _bgnd ) / (I _A -I _bgnd )).
[0062]
Further, as shown in FIG. 11, when the unevenness of the light source is not so large and the monitor area (position C) is always in the same place in the unevenness of the light source, the reflected light intensity used for normalization is monitored. Reflected light intensity (i _C ) May be standardized.
[0063]
FIG. 12 shows the results of acquiring the normalized reflected light intensity for nine chips. The mode (mode) of the standardized reflected light intensity is obtained from these values to be 2.06, and the chip for monitoring development is chip4.
[0064]
Next, a method for obtaining the optimum development time by monitoring the chip 4 monitor area will be described. FIG. 13 shows changes in reflected light intensity during development of the monitor area. From this reflected light intensity change, it can be seen that the removal time is 20 seconds. The relationship between the missing time of the monitor area and the time required for the 200 nm L / S pattern to finish 1: 1 is obtained in advance as shown in FIG. Based on these relationships, the development time (55 seconds in this case) is calculated. Then, development is stopped at the calculated development time.
[0065]
Here, the optimum development time is calculated from the relationship shown in FIGS. 13 and 14. However, the relationship between the normalized reflected light intensity and the exposure amount is expressed as shown in FIG. 15, and the 200 nm L / S pattern with respect to the exposure amount is 1. Since the relationship of the time of finishing to 1 is expressed as shown in FIG. 16, when the fluctuation due to the development is the same for each wafer, the optimum development time can be obtained from these relationships. In this case, the higher one of the measurement accuracy when obtaining the exposure amount from the normalized reflected light intensity and the measurement accuracy when obtaining the exposure amount from the missing time may be adopted.
[0066]
Although an example in which the detector is a CCD is shown in the present embodiment, a photomultiplier or the like having higher measurement sensitivity may be used. In this case, since the measurement position comes at the same location of the light source, the correction of the intensity is easy.
[0067]
As described above, when developing time control is performed in order to reduce the dimensional variation between wafers, the reflected light intensity of the monitor area is measured for chips processed under typical conditions in the wafer. Thus, by monitoring this monitor area during development, calculating the optimum development time from the film removal time and controlling the development time, the dimensional variation between wafers can be greatly reduced. Thereby, the yield is greatly improved. When measuring the reflected light intensity, use a wavelength that is sensitive to changes in film thickness as the probe light, and normalize the reflected light intensity in consideration of uneven illumination of the light source. The accuracy is improved, and the accuracy of extracting representative chips is improved. Also, when obtaining the monitor pattern omission time during development, the accuracy of obtaining the omission time is improved by using probe light with a wavelength such that the change in reflected light intensity increases when the film thickness becomes zero. The accuracy of controlling the dimensions is greatly improved.
[0068]
[Second Embodiment]
FIG. 17 is an apparatus configuration diagram in the case where the latent image is monitored by a cooling apparatus after post exposure bake (hereinafter referred to as PEB) and the development is monitored in the developing apparatus. Unlike the first embodiment, the present embodiment is an embodiment in which the monitor areas used for the latent image monitoring and the development monitoring are different.
[0069]
In the cooling unit 1700, a monitor head 1701 for monitoring is disposed in addition to a unit for performing normal cooling. The monitor head 1701 has the same configuration as that of the first embodiment, and is connected with a probe light source (a plurality of narrow band filters so that the wavelength can be selected depending on conditions) 1702 and a fiber 1703 for introducing light into the monitor head 1701. The collimation lens in the monitor head 1701 can illuminate the wafer 1704 with substantially monochromatic parallel light narrowed to a specific wavelength. The reflected light from the wafer 1704 can be detected by a CCD camera in the monitor head 1701. The monitor head 1701 can scan the wafer 1704 with a signal from the control unit 1709 of the apparatus so that monitor areas arranged in a plurality of chips can be monitored. The monitor head 1701 moves to a position where the monitor area of a specific chip can be detected based on the mask layout and exposure shot map, acquires an image, sends the image to the analysis unit 1708, and recognizes the monitor area by pattern matching. In addition, the intensity of the monitor area can be acquired. In the developing unit 100, a similar monitor head 101 is disposed in addition to the normal developing and rinsing unit.
[0070]
As shown in FIG. 18, the monitor area 1706 is arranged on a dicing line in which a mark area 1707 around the device pattern area 1801 is formed. In the first embodiment, a mask pattern having a specific transmittance is arranged in the monitor area and used for monitoring a latent image and monitoring during development. However, in this embodiment, as shown in FIG. Different monitor areas are used.
[0071]
Here, the target pattern is a 175 nm L / S pattern and is arranged in the device pattern region 1801. In addition, a pattern having the specific transmittance used in the first embodiment (the pattern pitch is 220 nm and the transmittance is 46.9%) is arranged in the latent image monitor area 1802, and the development monitor area 1803 has a target. The same 175 nm L / S pattern as the pattern was arranged. Here, a mask pattern having a specific transmittance is arranged in the monitor area or the device pattern itself is used. However, the hole-type monitor pattern shown in FIG. 19A or the line-type monitor pattern shown in FIG. Thus, it is also possible to use a pattern sensitive to development. In FIGS. 19A and 19B, reference numeral 1901 denotes a light shielding film.
[0072]
In addition to the pattern sensitive to development shown in FIG. 19, a pattern composed of element regions produced by cutting out a part of a device pattern and changing the dimensions partially is also effective. is there. These monitor areas may be arranged in either the latent image monitor area or the development monitor area. Further, a specific area in the device pattern area may be used as the monitor area without forming the monitor area in the mark area. Whatever gives the most accuracy in each monitoring may be used. For example, a line & space pattern such as a memory cell portion or a peripheral circuit portion can be used as the monitor region.
[0073]
At this time, the resist film thickness is 400 nm, the antireflection film thickness is 60 nm, and the exposure amount at which the 175 nm L / S pattern is finished to 1: 1 is 20.5 mJ / cm. ² Therefore, regarding the monitoring of the latent image, light having a wavelength of 430 nm is used as the probe light as in the first embodiment. Regarding the monitoring of development, a wavelength such that the intensity change in the monitor region becomes large in the vicinity where the device pattern is finished to a desired size is desirable, and a wavelength of 470 nm is used here. In this manner, the wavelength at the time of monitoring may be determined so that the change in reflectance is large with respect to the resist / antireflection film / underlying structure in the vicinity of the device pattern finished to a desired dimension.
[0074]
Next, the cooling and developing sequence when the present invention is used will be described with reference to the flowchart of FIG. When the wafer is transferred to the cooling unit (step S1), the position of the notch is detected and the position of the wafer in the rotational direction is adjusted (step S2). Thereafter, when the wafer temperature becomes lower than the specific temperature, the monitor head moves to the latent image monitor area of the specific chip (i) (step S3), detects the position by pattern matching, and reflects light from the monitor area. The intensity is acquired (step S4).
[0075]
The number of chips for which the reflected light intensity in the monitor area is measured is determined (step S5), and the reflected light intensity in the same monitor area is obtained for n chips until the number of chips reaches n. Then, after measuring the reflected light intensity in the monitor area of n chips, the chip (k) to be monitored is determined in order to control the development time from the mode value of the obtained reflected light intensity (step S6).
[0076]
When the cooling is completed (step S7), the wafer is transferred to the developing unit (step S8), the position of the notch is detected, and the position of the wafer in the rotational direction is adjusted (step S9). Then, development is started (step S10), the monitor head moves to the position of the chip (k), and changes in reflected light intensity in the development monitor region are measured (step S11). An appropriate development time is calculated from the reflected light intensity change in the monitor area (step S12), and the development is stopped at the calculated development time (step S13). The specific temperature is a temperature at which the PEB reaction almost stops.
[0077]
This sequence will be described based on actual experimental results.
[0078]
The wafer shot map and the scanning order of the nine chips whose latent images are monitored by the cooling unit are as shown in FIG. 7 as in the first embodiment. For these chips, the monitor head moves to a position where the monitor region enters the image, detects the position by pattern matching, and acquires the reflected light intensity.
[0079]
If there is no unevenness in the light source being observed, or if the monitor area always enters the same position of the image by moving the monitor head, the gradation of the CCD camera can be monitored as it is. As shown in FIG. 8, there is uneven illumination of the light source in the observation region. Further, the monitor area is 20 μm square (the observation area is 1 mm square), and the positional accuracy of the head is not so much, so it does not come to the exact same position of the image. For example, when the same monitor area comes to a dark part (position A) and a bright part (position B) in the uneven illumination of the light source as shown in FIG. 8, the case where it comes to position A (FIG. 9) is better. When it comes to the position B (FIG. 10), it will be darker. Therefore, sufficient accuracy cannot be obtained even when the gradation of the CCD camera is measured.
[0080]
In such a case, the irradiation unevenness of the light source is acquired as an image in advance as shown in FIG. 8 before monitoring each chip, and when the position A is reached as shown in FIG. 9, the position shown in FIG. The value normalized by the reflected light intensity of A is the normalized reflected light intensity (I _A / I _A 10), when the monitor area comes to the position B as shown in FIG. 10, the value normalized by the reflected light intensity at the position B in FIG. _B / I _B ). At this time, if the background of the CCD gradation is present, measurement (I _bgnd Then, the normalized reflected light intensity is obtained by subtracting the background (for example, at position A, (I _A -I _bgnd ) / (I _A -I _bgnd )).
[0081]
I _α (Α: A or B) is the reflected light intensity of the monitor area where the measurement was performed, and i _α (Α: A or B) is the reflected light intensity of the monitor region in the image shown in FIG.
[0082]
Further, as shown in FIG. 11, when the unevenness of the light source is not so large and the monitor area (position C) is always in the same place in the unevenness of the light source, the reflected light intensity used for normalization is monitored. Reflected light intensity (i _C ) May be standardized.
[0083]
FIG. 21 shows the result of actually obtaining the normalized reflected light intensity for nine chips. From these, the median value of the normalized reflected light intensity (the median value in the sample) was found to be 2.08, and the chip for monitoring development was chip2. A representative chip may be selected from an average value or a median value of reflected light intensity when the variation in reflected light intensity of the chip is random. In addition, when there are some specific chips with the same reflected light intensity of most chips, the mode may be selected. It is sufficient to check in advance what kind of variation there is and select the optimum method.
[0084]
Next, a method for obtaining the optimum development time by monitoring the development monitor area of chip 2 will be described. FIG. 22 shows changes in reflected light intensity in the development monitor area. Here, as shown in the first embodiment, the normalized reflected light intensity on the vertical axis is a value obtained by normalizing the reflected light intensity of the monitor region with the reflected light intensity at the same place of the light source that has been acquired in advance (for example, The reflected light intensity at position A in FIG. 9 is normalized by the reflected light intensity at position A in FIG. When using a pattern in which a pattern is formed in the development monitor area as in this embodiment, the reflected light intensity change during development becomes a monotonous change as shown in FIG. In such a case, the reflected light intensity (desired reflected light intensity) of the monitor area when the device pattern is finished to a desired dimension is obtained in advance, and the reflected light intensity of the monitor area becomes a desired value as shown in FIG. This time is defined as development stop time.
[0085]
Since the change in reflected light intensity in the development monitor region (pattern is formed) as used in this embodiment is smaller than that in the monitor region (film reduction occurs) used in the first embodiment, The influence of noise due to temporal fluctuation and temporal fluctuation of the developer surface becomes large. For this reason, normalization is performed in consideration of temporal variations in reflected light intensity. FIG. 23 shows an explanatory diagram thereof. The image used for normalization shown in FIG. 23A is an image for measuring the irradiation unevenness of the light source in advance, and an image of the unexposed area of the resist is acquired. The image used for acquiring the reflected light intensity shown in FIG. 23B is an image including a monitor region where the reflected light intensity change is acquired. The normalization described so far corrects the uneven illumination of the light source, and the reflected light intensity in the area A of the monitor region is expressed as I. _A / I _A Was asking.
[0086]
Further, in order to correct the temporal variation, the reflected light intensity of the unexposed area and area B in the vicinity of the monitor area is obtained (I _B / I _B ), Normalization is performed with this reflected light intensity. Normalized reflected light intensity I _st The equation for obtaining is shown below.
[0087]
[Expression 7]

[0088]
FIG. 24 shows the reflected light intensity change when the temporal variation is taken into account. By comparing this figure with FIG. 22, it can be seen that noise is suppressed by taking into account temporal variations. Therefore, this standardization method was adopted to obtain the reflected light intensity of the monitor pattern during development. If the background is on the gradation of the CCD, the background (I _bgnd ) May be subtracted for normalization. In the first embodiment, the reflected light intensity during development is the gradation of the CCD. However, this method may be used because noise is reduced in the reflected light intensity change by obtaining the following expression.
[0089]
[Equation 8]

[0090]
Next, FIG. 25 shows the relationship between the normalized reflected light intensity of the monitor pattern necessary for determining the reflected light intensity of the monitor pattern when the development is stopped and the line size of 175 nm L / S. From this relationship, the reflected light intensity threshold was determined to be 0.746. Therefore, when actual development is performed, the normalized reflected light intensity is measured in consideration of the time variation of FIG. 24, and the development is stopped when the reflected light intensity becomes 0.746.
[0091]
If there is a time difference from when monitoring is performed until development is stopped (rinsing solution is supplied), the reflected light intensity ahead is predicted by the time difference from the reflected light intensity change, and the predicted reflected light intensity is desired. When the value is reached, the development can be stopped.
[0092]
When developing time control is performed to reduce dimensional variation between wafers, chips processed under typical conditions in the wafer are extracted by measuring the reflected light intensity in the latent image monitor area. By monitoring the development monitor area of this chip during development, calculating the optimum development time from the change in reflected light intensity, and controlling the development time, the dimensional variation between wafers can be greatly reduced. Thereby, the yield is greatly improved. When measuring the reflected light intensity, use a wavelength that is sensitive to changes in film thickness as the probe light, and normalize the reflected light intensity in consideration of uneven illumination of the light source. The accuracy is improved, and the accuracy of extracting representative chips is improved. When measuring changes in reflected light intensity during development, the reflected light intensity measurement accuracy is improved by standardizing the reflected light intensity in consideration of temporal fluctuations as well as uneven illumination of the light source. In addition, the accuracy of controlling the dimensions is improved.
[0093]
In addition, the invention demonstrated above is not limited to the said embodiment. For example, the illumination unevenness of the light source or the reflected light intensity change with time is standardized to correct the reflected light intensity. However, the normalization method shown above reflects the reflected light from the other monitor areas described above. This can also be applied when the strength is normalized.
[0094]
Although an example in which the detector is a CCD is shown in the present embodiment, a photomultiplier or the like having higher measurement sensitivity may be used. In this case, since the measurement position comes at the same location of the light source, the correction of the intensity is easy.
[0095]
In the above-described embodiment, an average chip is extracted by monitoring a latent image before development, and reflected light from a monitor pattern of the extracted chip is monitored during development, and optimum based on a change in intensity of the reflected light. In this method, development is completed in a short development time. However, this technique has a problem that when the film thickness of the base fluctuates, the intensity of the reflected light also fluctuates, so that sufficient accuracy cannot be obtained. Therefore, in the following embodiment, it is sufficient even when the film thickness fluctuation of the base fluctuates. accuracy A method for obtaining the above will be described.
[0096]
[Third Embodiment]
In the present embodiment, when the underlying film thickness of the wafer varies within a certain range and the variation is not known, the monitoring of the latent image and the monitoring during development are performed on different monitor areas.
[0097]
FIG. 1 is a diagram showing the configuration of the developing device of the present invention. In the present embodiment, when the underlying film thickness of the wafer varies within a certain range and the variation amount is unknown, the latent image monitoring and the monitoring during development are performed on different monitor areas.
[0098]
In the developing unit 100, a monitor head 101 for performing monitoring is disposed in addition to a unit necessary for performing normal development to rinsing. The monitor head 101 is connected to a probe light source (a plurality of narrowband filters so that the wavelength can be selected depending on conditions) 102 and a fiber 103 for introducing light into the monitor head 101. A collimation lens in the monitor head 101 is connected to the monitor head 101. Thus, the wafer 104 can be illuminated with substantially monochromatic parallel light narrowed to a specific wavelength. The reflected light from the wafer 104 can be detected by a CCD camera and a photomultiplier in the monitor head 101. The CCD camera detects the position, and the photomultiplier measures the reflected light intensity. The monitor head 101 can scan the wafer 104 by a signal from the control unit 109 of the apparatus so that the monitor area 106 arranged in the plurality of chips 105 can be monitored. The monitor head 101 moves to a position where the monitor area of a specific chip can be detected based on the mask layout and the exposure shot map, and aligns the head so that the monitor area is included in the photomal detection area. The reflection intensity can be measured.
[0099]
As shown in FIG. 26, in the case of the present embodiment, in the monitor area 1707 of a plurality of chips 1705 formed on the wafer 1704, in addition to the latent image monitor area 1802 and the development monitor area 1803, a resist is formed immediately after development. A resist remaining film 0 region that disappears is arranged 1804. The monitor area 1706 is arranged on the dicing line in which the mark area 1707 is formed.
[0100]
In the present embodiment, a pattern having a specific transmittance is used for the latent image monitor area, and a 200 nm L / S pattern, which is a device pattern, is used for the development monitor area. A method for producing a pattern having a specific transmittance is as described in the first embodiment. Also in this embodiment, a pattern with a transmittance of 46.9% is used as the latent image monitor pattern, and the reflected light intensity in this region is measured.
[0101]
Next, how to determine the amount of reduction in the resist film when measuring the intensity of reflected light from the latent image monitor area will be described. Here, a case is considered in which an oxide film is formed as a base layer under the resist and the antireflection film, and the thickness of the oxide film varies within a range of ± 5 nm centering on 310 nm.
[0102]
First, FIG. 27 shows the relationship between the resist film reduction amount and the reflected light intensity when the oxide film thickness is 305, 310, and 315 nm. The reflected light intensity is standardized by the reflected light intensity of the initial film thickness of the resist (film reduction amount 0). Here, the wavelength of the probe light applied to the latent image monitor region is 550 nm. The reason for this is that when the center film thickness is 310 nm, the intensity change of reflected light is large in the vicinity of the film reduction amount (10 nm) to be measured.
[0103]
Further, in FIG. 27, an enlarged view of the vicinity of the required resist film reduction amount of 10 nm is shown in FIG. From FIG. 28, for example, when the normalized reflected light intensity from the latent image monitor region is 1.1, the underlying oxide film thickness is between 305 and 315 nm. Swinging It can be seen that the measurement error of the resist film thickness is about 3 nm. From the relationship between the exposure amount and the film reduction amount shown in FIG. 2, it can be seen that the measurement error of 3 nm is too large and it is impossible to accurately determine the exposure amount. Therefore, when the base film thickness fluctuates, the resist film thickness cannot be obtained accurately even if the reflected light intensity of one wavelength is measured.
[0104]
As a method of accurately obtaining the amount of film loss of the resist on the underlayer whose thickness varies, the latent image monitor region is irradiated with light of a plurality of wavelengths, and the reflectance of the light of each wavelength is measured in advance. It is possible to obtain it based on the relationship of reflectance when the desired resist / base changes. This method is most accurate for obtaining a plurality of film thicknesses. However, the measurement takes a lot of time. In an actual process, even if a large number of estimates are made for film thickness measurement in a monitor area of a plurality of chips (about 10 chips), such a method cannot be taken.
[0105]
Therefore, in the present embodiment, a method using reflected light having two wavelengths from the latent image monitor area as described below will be described. As the two wavelengths, as shown in FIG. 29, wavelengths that are inflection points of change near the initial film thickness of the resist film and have opposite slopes are used. In this embodiment, two wavelengths of 550 nm and 420 nm are used.
[0106]
Here, a method of calculating the same resist film thickness when the underlying oxide film thickness is changed with the resist film thickness reduced to 10 nm will be described. 30 is a characteristic diagram showing the relationship between the resist film reduction amount (latent image depth) and the normalized reflected light intensity when the wavelength is 550 nm and FIG. 31 is when the wavelength is 420 nm. In both cases, the film thickness reduction amount of the resist film is measured using the relationship of the center value (310 nm) of the film thickness of the base.
[0107]
When the base oxide film thickness has changed to 305 nm, the reduction amount of the resist film is calculated to be 9.25 nm at the wavelength of 550 nm, as indicated by the solid line arrow in FIG. For a wavelength of 420 nm, as shown by the solid line arrow in FIG. 31, the amount of reduction in the resist film is calculated as 11.5 nm. That is, since the ratio of deviation from the actual film thickness is 0.75: 1.5, the deviation ratio is set to 1: 2. Here, the equation for obtaining the resist film thickness is the resist film thickness measured using a wavelength of 550 nm as d ₅₅₀ The measured resist film thickness using a wavelength of 420 nm, d ₄₂₀ When the deviation ratio is m: n, the true resist film thickness d is obtained by weighted average, and is obtained by the following equation.
[0108]
d = (n × d ₅₀₀ + M × d ₄₂₀ ) / (M + n)
By using a weighted average of reflected light intensities at different wavelengths, even if the film thickness of the underlying oxide film is 305 nm (solid arrow in FIGS. 30 and 31) and the film thickness is 315 nm (dotted arrow in FIGS. 30 and 31), the same applies. In addition, the film thickness of the true resist film can be calculated as 390 nm (film loss 10 nm).
[0109]
Next, how to determine the development end time by monitoring during development will be described. FIG. 32 shows an example of a change in reflected light intensity during development from a 200 nm L / S pattern used as a development monitor region in this embodiment. Here, the wavelength of 550 nm at which the reflected light intensity change greatly appears during development is the monitoring wavelength for determining the development end time. In FIG. 32, the reflected light intensity is normalized by the reflected light intensity of the unexposed portion of the resist. That is, the head is moved so that the intensity detection area in the photomultiplier comes to the resist unexposed area, and the intensity is normalized by the acquired intensity.
[0110]
The change in reflected light intensity during development shown in FIG. 32 is for the case where the underlying oxide film thickness is 310 nm (center value). In this case, it is known in advance that when the normalized reflected light intensity from the development monitor region becomes 0.88, the desired size is finished. Therefore, when the reflected light intensity change as shown in FIG. 32 is shown, the development may be terminated when the normalized reflected light intensity reaches 0.88 (34 seconds).
[0111]
However, when the underlying oxide film thickness changes to 305 and 315 nm, the reflected light intensity shifts as a whole as shown in FIG. Therefore, even if the development is always finished with the same threshold value (0.88), the same size is not finished. That is, it is necessary to measure the thickness of the oxide film during development.
[0112]
Here, the oxide film thickness as the base is measured from the reflected light intensity from the resist residual film 0 region, which is the portion of the resist residual film 0 normalized by the reflected light intensity of the resist unexposed portion. In this case, in order to accurately measure the oxide film thickness, it is desirable that the normalized reflected light intensity from the resist residual film 0 region varies greatly with respect to the film thickness variation. FIG. 34 shows the relationship between the resist film loss and the normalized reflected light intensity when monitoring is performed with light having a wavelength of 450 nm. FIG. 34 shows that the reflected light intensity greatly changes when the resist film loss is 400 nm (residual film 0).
[0113]
Actually, the relationship between the thickness of the oxide film and the normalized reflected light intensity from the resist residual film 0 region is shown in FIG. Based on this relationship, by measuring the normalized reflected light intensity from the resist residual film 0 region with 450 nm light during development, the underlying oxide film thickness can be measured.
[0114]
Then, as shown in FIG. 36, if the relationship between the underlying oxide film thickness and the reflected light intensity threshold value at the development end point is obtained in advance, the reflected light intensity at the development end point is determined from the measured underlying oxide film thickness. A threshold can be determined.
[0115]
Next, FIG. 37 shows a developing sequence when the present invention is used. First, the wafer is transferred to the developing unit (step S1). Next, when the wafer is transferred, the position of the notch provided in the wafer is detected, and the position of the wafer in the rotational direction is adjusted (step S2). Thereafter, the monitor head is moved to the monitor area of the specific chip (i) (step S3), the head is aligned so that the monitor area is included in the photomal detection area, and the reflected light intensity is measured with the photomal, The amount of film loss in the monitor area is measured (step S4).
[0116]
Next, the number of chips for which the resist film thickness reduction amount in the monitor region is measured is determined (step S5), and the film thickness measurement in the same monitor region is performed for n chips until the number of chips reaches n. . Next, the chip (k) to be monitored is determined in order to control the development time from the mode value of the obtained resist film reduction amount (step S6).
[0117]
Then, development is started (step S7), the monitor head is moved to the position of the chip (k), and the reflected light intensity change in the development monitor region (200 nm L / S pattern) is measured. Since the underlying oxide film thickness is unknown at the initial stage of development, the normalized reflected light intensity from the resist residual film 0 region is measured with light having a wavelength of 450 nm for the measurement of the film thickness. The oxide film thickness is obtained from the measured normalized reflection intensity and FIG. 35 (step S8). The intensity measurement at this time is performed by moving the head so that the photomal detection area includes the resist residual film 0 area and the unexposed area, and measures and normalizes the intensity of each area.
[0118]
A reflected light intensity threshold value is determined from the obtained oxide film thickness and FIG. 36 (step S9). Next, the monitor wavelength is changed to 550 nm when the reflected light intensity threshold is obtained, and the head is further moved so that the development monitor area enters the photomal detection area, and the normalized reflection intensity from the development monitor area is changed. Measure (Step S10). It is determined whether or not the measured reflected light intensity from the development monitor region has reached the reflected light intensity threshold value (step S11), and development is stopped when the measured reflected light intensity reaches the reflected light intensity threshold value (step S11). S12).
[0119]
This sequence will be described based on actual experimental results. FIG. 7 shows an example of a wafer shot map and an example of the scanning order of nine chips monitored before development. For these chips, the monitor head moves to a position where the latent image monitor area enters the image, and the head is moved so that the unexposed area and latent image monitor area are included in the photomal detection area. Measure the amount of film loss. FIG. 38 shows the results of actually measuring the amount of resist thinning for nine chips using two wavelengths of 550 nm and 420 nm. When the mode value (mode) of the film reduction amount was obtained from these, it was 11.5 nm, and the chip to be monitored during development was determined as the chip 6.
[0120]
Next, a method for monitoring the monitor area of the chip 6 and obtaining the optimum development time will be described. First, the normalized reflected light intensity in the region of the resist residual film 0 is measured with light having a wavelength of 450 nm at the initial stage of development. At this time, the normalized intensity is obtained from the respective intensities by aligning the head position so that the area of the resist remaining film 0 and the unexposed portion of the resist are included in the photomal detection area. As a result of the measurement, the normalized reflected light intensity was 0.9, so that the oxide film thickness is determined to be 315 nm from FIG.
[0121]
Next, from FIG. 36, the reflected light intensity threshold for stopping development is obtained as 0.87. After that, when the measurement wavelength is 550 nm and the head position is adjusted so that the photomal detection region is included in the development monitor region, the change in reflected light intensity of the 200 nm L / S pattern is monitored as shown in FIG. Therefore, in 27 seconds, the development stop solution is supplied onto the substrate to be processed, and the development is completed.
[0122]
According to this embodiment, when developing time is controlled in order to reduce the dimensional variation between wafers, the film thickness of the monitor area is measured for chips processed under typical conditions in the wafer. To extract. Before starting development and monitoring the reflected light intensity in the development monitor area of this chip, measure the film thickness of the substrate, set the reflected light intensity threshold, and control the development time to Variation can be greatly reduced. Thereby, the yield is greatly improved.
[0123]
In addition, when measuring the amount of resist film loss, the film can be formed in a short time by using two wavelengths, which are sensitive to changes in film thickness and have a phase difference of 180 degrees in the vicinity of the measured film thickness, as probe light. Thickness measurement is possible.
[0124]
In addition, in order to determine the reflected light intensity threshold value in the first half of development, the reflected film intensity is measured by measuring the reflected light intensity in the region that becomes the resist residual film 0, and the reflected light intensity threshold value of the development monitor pattern is set. By obtaining, the accuracy for obtaining the development time can be improved, and the variation in dimension between wafers can be greatly reduced. Moreover, the measurement accuracy is greatly improved by using a photomultiplier as the intensity detector.
[0125]
[Fourth Embodiment]
In this embodiment, when the underlying film thickness of the wafer fluctuates within a certain range and the fluctuation amount is known before the development process, the latent image monitoring and the monitoring during development are performed for different monitor areas. Will be described.
[0126]
FIG. 1 is a diagram showing the configuration of the developing device of the present invention. In this embodiment, when the underlying film thickness of the wafer varies within a certain range and the variation amount is known before the development process, monitoring of the latent image and monitoring during development are performed on different monitor areas. This is the case.
[0127]
In the developing unit 100, a monitor head 101 for performing monitoring is disposed in addition to a unit necessary for performing normal development to rinsing. A light source 102 for probe light and a fiber 103 for introducing light into the head 101 are connected to the monitor head 101. In the head 101, light introduced from the light source 102 through the fiber 103 can be guided to a half mirror by a lens to illuminate a spot on the wafer. Reflected light from the wafer can be detected by a CCD camera and a photomultiplier in the development monitor head. The CCD camera detects the position, and the photomultiplier measures the reflected light intensity. In addition, a diffraction grating is installed before light enters the photomultiplier so that light of a specific wavelength can enter the photomultiplier. The monitor head 101 can scan the wafer with a signal from the control unit 109 of the apparatus so that the monitor area 106 arranged in the plurality of chips 105 can be monitored. The monitor head 101 moves to a position where the monitor area of a specific chip can be detected based on the mask layout and the exposure shot map, and aligns the head so that the monitor area is included in the photomal detection area. The reflected light intensity can be measured.
[0128]
Further, in the monitor area formed on the chip of the wafer, a latent image monitor area, a development monitor area, and a resist residual film 0 area are formed as in the third embodiment. Also in this embodiment, a pattern with a transmittance of 46.9% is used as the latent image monitor region, and the film thickness in this region is measured.
[0129]
Next, how the film reduction amount is obtained when monitoring the latent image will be described. Here, a case is considered in which an oxide film is formed under the resist and the antireflection film, and the thickness of the oxide film varies within a range of ± 5 nm centering on 310 nm. In the third embodiment, the thickness of the underlying oxide film is unknown, but in this embodiment, the oxide film thickness has already been measured before the development process (for example, CMP process), and the film thickness information is It has been sent to the analysis department. Accordingly, the resist film thickness is measured at one wavelength. For example, if the oxide film thickness is measured to be 310 nm, the resist film thickness may be measured using the solid line relationship in FIG. That is, the film thickness is measured on the basis of the relationship between the resist film reduction amount and the normalized reflected light intensity for each oxide film thickness obtained in advance.
[0130]
Next, how to determine the development end time by monitoring during development will be described. In this embodiment, paying attention to a specific point of reflected light intensity change in the development monitor region, an optimum development time is obtained.
FIG. 40 shows a change in reflected light intensity during development from a 200 nm L / S pattern which is a development monitor region (wavelength 550 nm). In this reflected light intensity change, the reflected light intensity change mode changes around the developing time of 15 seconds. Prior to 15 seconds, the exposed portion of the resist is developed and the resist film thickness decreases. This is a process in which the resist film is completely removed in 15 seconds, and then the side wall portion of the pattern is developed little by little.
[0131]
The mode change of the reflected light intensity change is due to the pattern development process, and therefore does not depend on the thickness of the underlying oxide film. Therefore, in the present embodiment, the optimum development time is calculated based on the point at which the reflected light intensity change mode changes (pattern omission time shown in FIG. 40).
[0132]
FIG. 41 shows the relationship between the exposure amount and the pattern omission time. From this relationship, it can be seen that the exposure amount can be obtained by measuring the pattern omission time in the development monitor region. Therefore, if the relationship between the exposure amount and the optimum development time is obtained in advance as shown in FIG. 42, the optimum development time can be obtained from the pattern omission time in the development monitor area.
[0133]
However, when the focus value has deviated greatly, as shown in FIG. 43, if the just focus data is used when obtaining the exposure amount from the pattern missing time, the exposure amount cannot be obtained accurately. . Therefore, in such a case, the reflected light intensity from a pattern not affected by defocusing, that is, a pattern having a specific transmittance (pattern of the latent image monitor region) is also monitored.
[0134]
During development, the behavior of the normalized reflected light intensity from the pattern having the transmittance of 46.9% used in the latent image monitor region is as shown in FIG. 44 (wavelength of probe light: 420 nm). Since this pattern is exposed with a constant exposure amount, the film decreases with the passage of time while showing an interference waveform. When the resist film thickness becomes zero, the reflected light intensity does not change. The time during which the reflected light intensity change is not shown is referred to as the omission time. As shown in FIG. 45, there is a one-to-one correspondence between the missing time and the exposure amount. Therefore, an accurate exposure amount can be obtained by measuring the pattern omission time in the latent image monitor area.
[0135]
When measuring the normalized reflected light intensity in the latent image monitor area during development shown in FIG. 44, a wavelength of 420 nm is used as the probe light. The reason why this wavelength is used is that it is desired that the inflection point of the reflected light intensity change be obtained when the resist film thickness becomes zero. If such a wavelength is set, the missing time can be accurately obtained, and even if the underlying film thickness fluctuates slightly, it is hardly affected.
[0136]
As described above, the exposure value is obtained from the missing time of the pattern having a specific transmittance, and the focus value can be obtained by using the relationship of FIG. 43 together with the missing time of the 200 nm L / S pattern. Therefore, if the optimum development time when the focus / exposure amount is given is obtained in advance, the pattern dimension can be finished to a desired value. Of course, since the focus shift may vary depending on the chip, the development may be performed with a development time corresponding to the exposure amount obtained from the missing time of the pattern having a specific transmittance.
[0137]
Next, a development sequence when the present invention is used will be described. The development sequence of this embodiment differs from that of the third embodiment in a film thickness measurement method and a development end determination method.
[0138]
Here, a method for determining the end of development will be described with reference to the flowchart shown in FIG. FIG. 46 is a flowchart showing a method for determining the end of development.
[0139]
First, after development is started (step S1), the reflected light from the development monitor area is monitored with light having a wavelength of 550 nm, and the pattern omission time in the exposure monitor area is measured (step S2).
[0140]
Next, the reflected light from the pattern (latent image monitor region) having a specific transmittance is monitored with light having a wavelength of 420 nm, and the pattern omission time in the latent image monitor region is measured (step S3).
[0141]
Next, the exposure amount is calculated from the measured pattern missing time and the relationship between the pattern missing time and the exposure amount shown in FIG. 45 (step S4).
[0142]
The focus position is calculated from the exposure amount calculated in step S3 and the measured pattern missing time, and the relationship between the exposure amount and the pattern missing time when the focus changes as shown in FIG. 43 (step S5).
[0143]
The reflected light intensity measurement in steps S2 and S3 is performed by moving the head so that the monitor region is included in the photomal detection region and adjusting the angle of the diffraction grating so that the monitor wavelength becomes a desired value.
[0144]
Next, a development time for finishing the pattern dimension to a desired value is determined from the calculated exposure amount and focus position and the optimum development time when a previously determined focus / exposure amount is given (step S6).
[0145]
Next, it is determined whether the development time determined in step S6 has elapsed since the start of development (step S7). If the determined development time has passed, a development stop solution is supplied onto the wafer to stop development (step S8).
[0146]
The development sequence of this embodiment will be described based on actual experimental results. The shot map of the wafer and the scanning order of the nine chips monitored before development are as shown in FIG. 7, as in the third embodiment. For these chips, the monitor head is moved to a position where the monitor area enters the image, and the head is moved so that the unexposed area and the latent image monitor area are included in the photomal detection area. Measure quantity.
[0147]
FIG. 47 shows the result of actually measuring the film thickness of nine chips using a wavelength of 550 nm. From these, the average value of the amount of film loss was found to be 11.4 nm, and the chip for monitoring development was designated as chip 1.
[0148]
Next, a method for monitoring the monitor area of the chip 1 and obtaining the optimum development time will be described.
First, as shown in FIGS. 43 and 45, in the 200 nm L / S pattern (development monitor area) to be monitored during development and the pattern having a specific transmittance (latent image monitor area), the missing time is 15 seconds or less in the former. Since the latter is 20 to 30 seconds, the pattern omission time is measured by monitoring at a wavelength of 550 nm until 15 seconds after the start of development, and the omission time is measured by monitoring with light having a wavelength of 420 nm after 15 seconds. In other words, until 15 seconds, monitoring is performed by adjusting the position of the head so that the 200 nm L / S pattern is included in the photomal measurement region and adjusting the angle of the diffraction grating so that the wavelength becomes 550 nm. After 15 seconds, the position of the head is aligned with the latent image monitor region, and monitoring is performed by adjusting the angle so that the wavelength is 420 nm.
[0149]
In actual measurement, the former was 10 seconds, the latter was 21 seconds, the exposure amount was 20.5 mJ / cm 2, and the focus was 0 μm, and development was completed in 53 seconds based on the relationship shown in FIG.
[0150]
When developing time control is performed in order to reduce dimensional variations between wafers, chips processed under typical conditions in the wafer are extracted by measuring the film thickness of the monitor region. By starting development, measuring the exposure amount and focus value from a specific point that does not depend on the underlying film thickness within the reflected light intensity change in the development monitor area of this chip, and performing the optimum development according to it The variation in dimensions between wafers can be greatly reduced. Thereby, the yield is greatly improved. Moreover, the measurement accuracy is greatly improved by using a photomultiplier as the intensity detector.
[0151]
In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can change and implement variously.
[0152]
【The invention's effect】
As described above, according to the present invention, when developing time control is performed in order to reduce the dimensional variation between wafers, chips processed under typical conditions in the wafer are displayed in the latent image monitor region. By measuring the reflected light intensity of the chip, the development monitor area of the chip is monitored during development, the optimal development time is calculated from the reflected light intensity, and the development time is controlled, so that the dimensional variation between wafers Can be greatly reduced. Thereby, the yield is greatly improved.
[0153]
In addition, when measuring reflected light intensity, standardization of reflected light intensity in consideration of uneven illumination of the light source or changes in reflected light intensity over time improves the measurement accuracy of the reflected light intensity. The accuracy of extracting a simple chip is improved.
[0154]
In addition, when developing time control is performed in order to reduce the dimensional variation between wafers, the latent image depth of the latent image monitor area of a chip processed under typical conditions in the wafer is measured. , The development monitor area of the chip is monitored during development, the optimum development time is calculated from the reflected light intensity, and the development time is controlled, so that the variation in dimensions between wafers can be greatly reduced. Yield is greatly improved.
[0155]
In addition, in the method of obtaining the development end point from the singular point of the reflected light intensity change, the exposure amount and the focus value are measured from a specific point that does not depend on the underlying film thickness in the reflected light intensity change of the development monitor area. By performing the optimum development, it is possible to greatly reduce the dimensional variation between the wafers. Moreover, the measurement accuracy is greatly improved by using a photomultiplier as the intensity detector.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a schematic configuration of a developing device according to a first embodiment.
FIG. 2 is a diagram showing a relationship between an exposure amount and a film reduction amount of a latent image in a monitor area.
FIG. 3 is a diagram showing a relationship between an exposure amount and a monitor area missing time;
FIG. 4 is a diagram showing the relationship between the amount of resist film loss and the reflectance (no developer on the resist);
FIG. 5 is a graph showing the relationship between the amount of resist film reduction and the reflectance (there is a developer on the resist);
FIG. 6 is a flowchart showing a monitor chip determination and development sequence.
FIG. 7 is a diagram showing an example of the scanning order of nine chips monitored before development.
FIG. 8 is a diagram showing uneven illumination of a light source in an observation area.
FIG. 9 is a diagram showing a case where a monitor area comes to a position A.
FIG. 10 is a diagram showing a case where a development monitor area comes to a position B.
FIG. 11 is a diagram showing a case where the intensity unevenness of the light source is not so large.
FIG. 12 is a diagram showing a list of results of measuring reflected light intensity in a monitor area.
FIG. 13 is a diagram showing a change in reflected light intensity in a monitor area during development.
FIG. 14 is a diagram illustrating a method for calculating a development stop time from a monitor region drop time.
FIG. 15 is a diagram showing a relationship between an exposure amount and reflected light intensity of a monitor region.
FIG. 16 is a diagram showing the relationship between the exposure amount and the time required for 200 nm L / S to finish at 1: 1.
FIG. 17 is a diagram showing a schematic configuration of a cooling device and a developing device.
FIG. 18 is a diagram showing the arrangement position of a monitor area.
FIG. 19 is a diagram showing an example of a monitor pattern.
FIG. 20 is a flowchart showing a monitor chip determination and development sequence.
FIG. 21 is a diagram showing a list of results of measuring reflected light intensity.
FIG. 22 is a diagram showing a change in reflected light intensity in a development monitor region.
FIG. 23 is a diagram illustrating a normalization method that takes into account temporal variations in reflected light intensity;
FIG. 24 is a diagram showing a change in normalized reflected light intensity in consideration of time variation.
FIG. 25 is a diagram showing the relationship between the normalized reflected light intensity of a monitor pattern and the line size of 175 nm L / S necessary for determining the reflected light intensity of the monitor pattern when development is stopped.
FIG. 26 is a plan view schematically showing a wafer, chips, and a monitor area according to the third embodiment.
FIG. 27 is a characteristic diagram showing a relationship between a resist film reduction amount and reflected light intensity [standardized] in a plurality of oxide film thicknesses.
FIG. 28 is a characteristic diagram showing a relationship between a resist film reduction amount and reflected light intensity [standardized] with respect to a plurality of oxide film thicknesses.
FIG. 29 is a view for explaining a relationship necessary for the wavelength of light used for monitoring a latent image monitor area according to the third embodiment.
FIG. 30 is a characteristic diagram showing the relationship between the resist film reduction amount and the reflected light intensity [standardized] for a plurality of oxide film thicknesses in the case of light having a wavelength of 550 nm.
FIG. 31 is a characteristic diagram showing the relationship between the resist film reduction amount and the reflected light intensity [standardized] for a plurality of oxide film thicknesses in the case of light having a wavelength of 420 nm.
FIG. 32 is a characteristic diagram showing a change with time of reflected light intensity [standardized] from a development monitor region in the case of light having a wavelength of 550 nm.
FIG. 33 is a characteristic diagram showing a temporal change in reflected light intensity [standardized] from a development monitor region with respect to a plurality of oxide film thicknesses in the case of light having a wavelength of 550 nm.
FIG. 34 is a characteristic diagram showing the relationship between the resist film reduction amount and the reflected light intensity [standardized] for a plurality of oxide film thicknesses in the case of light having a wavelength of 450 nm.
FIG. 35 is a characteristic diagram showing the relationship between the thickness of the oxide film and the intensity of reflected light from the resist residual film 0 region [standardized] in the case of light having a wavelength of 450 nm.
FIG. 36 is a characteristic diagram showing the relationship between the oxide film thickness and the reflected light intensity [standardized] threshold in the case of light having a wavelength of 550 nm.
FIG. 37 is a flowchart showing a monitor chip determination and development sequence according to the third embodiment.
FIG. 38 is a view showing a result of measuring a resist film reduction amount in a latent image monitor region of each chip.
FIG. 39 is a characteristic diagram showing a change over time in reflected light intensity [standardized] from a development monitor region during development in the case of light having a wavelength of 550 nm.
FIG. 40 is a characteristic diagram showing a temporal change in reflected light intensity [standardized] from a development monitor region during development in the case of light having a wavelength of 550 nm.
FIG. 41 is a characteristic diagram showing the relationship between the exposure amount and the pattern omission time.
FIG. 42 is a characteristic diagram showing the relationship between the exposure amount and the development time when the pattern dimension is finished to a desired value.
FIG. 43 is a characteristic diagram showing the relationship between the exposure amount and the development time when the pattern dimension is finished to a desired value when the focus position changes.
FIG. 44 is a characteristic diagram showing a temporal change in reflected light intensity [standardized] from a latent image monitor area during development.
FIG. 45 is a characteristic diagram showing the relationship between the exposure amount and the pattern omission time in the latent image monitor area.
FIG. 46 is a flowchart showing a development sequence according to the fourth embodiment.
47 is a view showing a result of measuring a resist film reduction amount in a latent image monitor area of each chip; FIG.
[Explanation of symbols]
100: Development unit
101 ... Monitor head
103 ... fiber
104 ... wafer
105 ... chip
106: Monitor area
107 ... Mark area
108: Analysis unit
109 ... Control unit
1700 ... Cooling unit
1701 ... Monitor head
1703: Fiber
1704 ... Wafer
1706: Monitor area
1707 ... Mark area
1709: Control unit
1801 ... Device pattern area
1802 ... Latent image monitor area
1803. Development monitor area

Claims (14)

The device pattern is exposed to each of a plurality of chip regions of the resist on the substrate to be processed, and after heating,
In the pattern formation method of forming a device pattern by development, a step of exposing each latent image monitor region and the development monitor region to each chip region of the resist on the substrate to be processed together with the device pattern at the time of exposure of the device pattern;
A step of irradiating each latent image monitor region of the plurality of chip regions with light of a specific wavelength between the heating step and the developing step after the exposure step, and measuring the reflected light intensity of the latent image monitor region; ,
Extracting a chip region processed under typical conditions in the substrate to be processed based on a measurement result;
During development of the device pattern, the development monitor area arranged in the extracted chip area is irradiated with light of a specific wavelength, and development is stopped according to a change in reflected light intensity from the development monitor area. The pattern formation method characterized by the above-mentioned.   2. The development stop process of the device pattern is performed by predicting a development stop time during which the device pattern is finished to a desired dimension based on a change in reflected light intensity from the development monitor area. Pattern forming method. Reflected light intensity of the latent image monitor area is a reflected light intensity I _s normalized taking into account the uneven irradiation of the light source with respect to the reflected light intensity I _A of the latent image monitor area A was measured in advance when acquiring the reflected light intensity of the monitor area in the image in the illumination unevenness is present in the light source are i _a, the background reflected light intensity was I _BGND, the reflected light intensity I _s is

The pattern forming method according to claim 1, wherein the pattern forming method is given by: The device pattern is exposed to each of a plurality of chip regions of the resist on the substrate to be processed, and after heating,
In the pattern formation method of forming a device pattern by development, a step of exposing each latent image monitor region and the development monitor region to each chip region of the resist on the substrate to be processed together with the device pattern at the time of exposure of the device pattern;
Between the heating process and the developing process after the exposure process, each latent image monitor area of the plurality of chip areas is irradiated with light of a specific wavelength, and the latent light of the resist is determined from the reflected light intensity from the latent image monitor area. The step of determining the image depth;
Extracting a chip region processed under typical conditions in the substrate to be processed based on the measured latent image depth of the resist;
Irradiating the monitor region arranged in the extracted chip with light of a plurality of wavelengths to measure the film thickness of the base of the resist at an early stage of the device pattern development step;
Determining a reflected light intensity threshold from the measured film thickness of the substrate;
During development of the device pattern, the development monitor area arranged in the extracted chip area is irradiated with light of a specific wavelength, and the reflected light intensity change from the development monitor area and the determined reflected light A pattern forming method, wherein development is stopped based on an intensity threshold. In the process of measuring the film thickness of the resist base at the beginning of the development process,
Thickness of the underlying, claim 4 where the resist is characterized in that it is determined from the relation between reflected light intensity ratio between the area and the residual resist film 0 of the area being formed on the entire surface, and the thickness of the underlayer The pattern forming method according to 1. In the step of determining the reflected light intensity threshold value, the reflected light intensity threshold value is determined from a relationship between the reflected light intensity threshold value and the underlying film thickness with respect to a previously obtained underlying film thickness. The pattern forming method according to claim 4 . In a pattern forming method of exposing a device pattern to each of a plurality of chip regions of a resist on a substrate to be processed, forming a device pattern by development after heating,
Exposing the latent image monitor area and the development monitor area to each chip area of the resist on the substrate to be processed together with the device pattern at the time of exposure of the device pattern;
Between the heating step and the developing step after the exposure step, irradiating each latent image monitor region of a plurality of chip regions with light of a specific wavelength, and measuring the reflected light intensity of the latent image monitor region;
Obtaining a latent image depth of the resist from the measured reflection intensity;
Extracting a chip region processed under typical conditions in the substrate to be processed based on the measured latent image depth of the resist;
During the development process of the device pattern, the development monitor region in the extracted chip region is irradiated with light of a specific wavelength, and the device pattern is developed to a desired dimension from a singular point of the relationship between development time and reflected light intensity Predicting downtime;
And a step of stopping development at a predicted development stop time. When the development monitor area is configured with a hole or line pattern, the singular point of the relationship between the development time and the reflected light intensity is a pattern omission time, and the development stop time is determined by a predetermined device pattern. The pattern forming method according to claim 7 , wherein prediction is performed based on a relationship between a time for finishing to a desired dimension and a time for missing the pattern. When the development monitor region is configured with a pattern having a specific transmittance on the mask, the singular point of the relationship between the development time and the reflected light intensity is the resist removal time,
The pattern formation method according to claim 7 , wherein the development stop time is predicted based on a relationship between a time required for a device pattern to be obtained in advance to a desired size and the resist removal time. . In the step of determining the latent image depth of the resist,
When the film thickness of the resist base is unknown,
The light of the specific wavelength has an inflection point in the vicinity of the initial film thickness of the resist in the relationship between the film thickness of the resist and the reflection intensity, and the phase differs by 180 ° near the initial film thickness. Two wavelengths of light,
8. The pattern formation according to claim 4 , wherein the latent image depth of the resist is obtained by weighted averaging the latent image depths of the resist obtained from the reflected light intensities of the two wavelengths. Method. In the step of determining the latent image depth of the resist,
When the film thickness of the resist is known,
The latent image monitor region is irradiated with light having a wavelength at which the relationship indicates an inflection point in the vicinity of the initial film thickness of the resist in the relationship between the resist film thickness and the reflection intensity. 8. The pattern forming method according to claim 4 , wherein the latent image depth of the resist is obtained based on the relationship between the reflected light intensity with respect to the film thickness and the resist film thickness. In a pattern forming method of exposing a device pattern to each of a plurality of chip regions of a resist on a substrate to be processed, forming a device pattern by development after heating,
Exposing the latent image monitor area and the development monitor area to each chip area of the resist on the substrate to be processed together with the device pattern at the time of exposure of the device pattern;
Between the heating step and the developing step after the exposure step, irradiating each latent image monitor region of the plurality of chip regions with light of a specific wavelength, and determining the reflected light intensity of the latent image monitor region;
Obtaining a latent image depth of the resist from the measured reflection intensity;
Extracting a chip region processed under typical conditions in the substrate to be processed based on the measured latent image depth of the resist;
Irradiating the development monitor area in the extracted chip area with light of a specific wavelength, and predicting a development stop time when the device pattern is finished to a desired dimension based on reflection intensity;
And a step of performing development based on the development stop time. The step of predicting the development stop time is performed by irradiating the development monitor region arranged in the extracted chip region with light having a specific wavelength between the heating step and the development step. The pattern forming method according to claim 12 , wherein the pattern forming method is performed based on the intensity of reflected light from the light. Claim 1, the pattern forming method according to any of 4,7,12, characterized in that the said latent image monitor area and the development monitor area is the same area.

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