JP3867653B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit in which a plurality of clock drivers for distributing a clock signal are arranged. In particular, in a clock driver, when a phase of a branched clock signal is shifted, a clock signal synchronized with a phase delayed clock signal is generated. The present invention relates to a semiconductor integrated circuit in which clock skew is reduced by outputting.
[0002]
[Prior art]
A conventional semiconductor integrated circuit 111 of this type will be described with reference to the drawings.
[0003]
FIG. 9 is a schematic circuit configuration diagram showing a semiconductor integrated circuit 111 in which a plurality of clock drivers 112 for distributing clock signals are arranged in an H-tree shape, and FIG. 10 is a diagram showing details of the H-tree portion in FIG. is there.
[0004]
9 and 10, a semiconductor integrated circuit 111 includes a plurality of clock drivers 112 arranged in an H-tree, a clock distribution circuit 113, and a logic circuit (not shown) to which an output from the clock driver 112 is input. 2) F / F (flip-flop) circuit 114.
[0005]
Referring to FIG. 10, the clock driver 112a to which the clock signal is input from the clock input point 116 through the clock distribution path 121 and the clock driver 112b to which the clock signal is input through the clock distribution path 122 are manufactured. A delay difference occurs depending on the process and operating conditions, a skew is generated in the clock signal input to the F / F circuit 114, and data transfer between the F / F circuits 114 of the logic circuit is affected.
[0006]
In this case, the clock skew increases due to a shift in the phase of the clock signal after branching depending on the manufacturing process and operating conditions, but there is a problem that the clock skew further increases as the number of stages in the distribution path increases.
[0007]
For this reason, it is necessary to adjust the delay to the phase shift of the clock signal, but there is a delay compensation using a DLL (Delay Locked Loops) circuit (see, for example, Patent Document 1).
[0008]
However, the technique of performing delay compensation by using a DLL circuit has drawbacks such as the accuracy of the comparator, the circuit scale being increased, and the delay cannot be corrected in comparison with every cycle.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-65699 (page 4, FIG. 1)
[0010]
[Problems to be solved by the invention]
As described above, in a semiconductor integrated circuit in which a plurality of H-tree-shaped clock drivers for distributing a clock signal are arranged, a manufacturing process or a process between clock drivers to which a clock signal is input through different clock distribution paths There is a problem that a delay difference occurs depending on operating conditions, and a skew occurs in a clock signal input to the F / F circuit.
[0011]
In addition, the delay compensation technique using the DLL circuit to correct the skew has a problem of the accuracy of the comparator, the circuit scale becomes large, and the delay cannot be corrected by comparing the phases every cycle. There are drawbacks.
[0012]
In a semiconductor integrated circuit in which a plurality of clock drivers for distributing a clock signal are arranged, when the phase of the clock signal branched from the clock driver is shifted, the object of the present invention is to adjust the phase shift to the clock signal delayed in phase. An object of the present invention is to provide a semiconductor integrated circuit in which clock skew is reduced by outputting a signal.
[0013]
[Means for Solving the Problems]
A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit in which a plurality of clock drivers for distributing a clock signal are arranged on the same substrate, and has a phase correction clock driver to which a plurality of clock signals are inputted from the clock driver. The phase correction clock driver is configured to detect a phase difference of a clock signal with respect to a plurality of clock signal inputs having a phase difference, a negative product circuit and a logical sum circuit, and a negative product circuit and a logical sum circuit to And a flip-flop circuit to which each pulse signal is generated and the pulse signal is input. The flip-flop circuit outputs a clock signal synchronized with a clock signal having a phase delay among a plurality of clock signal inputs. And
[0014]
The negative product circuit detects the phase delay of the rising edge of the clock signal, and the logical sum circuit detects the phase delay of the falling edge of the clock signal.
[0015]
The flip-flop circuit outputs a clock signal synchronized with a clock signal having a maximum phase delay among a plurality of clock signal inputs.
[0016]
The phase correction clock driver has two or four clock signal inputs.
[0017]
The phase correction clock driver is arranged at the end of a clock signal distribution path and is connected to a flip-flop circuit of a logic circuit.
[0018]
The phase correction clock driver is provided in the middle of the branch of the clock signal distribution path.
[0019]
The clock drivers are arranged in an H-tree shape.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a diagram showing details of an H-tree portion in FIG.
[0022]
Referring to FIGS. 1 and 2, the semiconductor integrated circuit 11 receives a clock signal from a plurality of clock drivers 12 arranged in an H-tree shape, a clock distribution circuit 13, and a clock driver 12 in the adjacent previous stage. The phase correction clock driver 31 is arranged at the end of the distribution paths 21 and 22 and connected to the F / F circuit 14 of a logic circuit (not shown).
[0023]
Referring to FIG. 3 showing the circuit configuration of the phase correction clock driver 31, the phase correction clock driver 31 calculates the phase difference between the clock signals 1 and 2 with respect to the input of the clock signal 1 and the clock signal 2 having a phase difference. It comprises a negative product circuit 5 and a logical sum circuit 6 to be detected, and an F / F (flip-flop) circuit 7 to which pulse signals 53 and 54 respectively output from the negative product circuit 5 and the logical sum circuit 6 are inputted. .
[0024]
Next, the operation of the semiconductor integrated circuit 11 configured as described above will be described with reference to the drawings.
[0025]
FIG. 4 is a timing chart of the phase correction clock driver 31 shown in FIG.
[0026]
Referring to FIG. 3 and FIG. 4, the negative product circuit (NAND circuit) 5 is such that when both the input signal 51 of the clock signal 1 and the input signal 52 of the clock signal 2 become high level, the pulse signal 53 becomes low level. In the OR circuit (OR circuit) 6, when both the input signal 51 and the input signal 52 are at low level, the pulse signal 54 is at low level.
[0027]
The pulse signal 53 generates a pulse with the edge of the rising waveform of the input signal 51 and the input signal 52 being delayed, and the output pulse 54 is the phase of the falling waveform of the input signal 51 and the input signal 52. A pulse is generated at the edge that is delayed.
[0028]
The output pulse 55 from the F / F circuit 7 becomes a high level when the pulse signal 53 falls and becomes a low level when the pulse signal 54 falls. That is, the clock signal 2 having the phase lag among the input signals 51 and 52 of the clock signals 1 and 2 is output.
[0029]
Referring to FIG. 2 showing the details of the H-tree portion of the semiconductor integrated circuit 11, the phase correction clock driver 31 connected to the F / F circuit 14 of the logic circuit receives clock signals from the adjacent clock drivers 12a and 12b in the preceding stage. The output clock signal is generated based on the phase of the input clock signal. The clock signal output from the clock input point 16 passes through the clock distribution path 21 and the clock driver 12b passes through the clock distribution path 22. The clock skew can be reduced by generating an output clock signal in which the phase of the clock signal from is synchronized with the clock signal of whichever phase is later.
[0030]
In FIG. 2, the phase correction clock driver 31 is arranged at a location connected to the F / F circuit 14 of the logic circuit. However, as shown in FIG. As a result of the insertion, the effect of reducing the clock skew is obtained in the same manner as the arrangement of the phase correction clock driver 31 shown in FIG. 2, and the clock skew is also obtained by the combination of the arrangement of the phase correction clock driver 31 shown in FIGS. Needless to say, there is a reduction effect.
[0031]
Next, a case where the path of the clock driver through which the clock signal is distributed to the phase correction clock driver is from four directions will be described with reference to the drawings.
[0032]
6 is a diagram showing details of the H-tree portion in which four clock signals are input to the phase correction clock driver 71 (however, the F / F circuit of the logic circuit subsequent to the phase correction clock driver 71 is omitted), FIG. FIG. 8 is a circuit configuration diagram of the phase correction clock driver 71, and FIG. 8 is a timing chart of the phase correction clock driver 71.
[0033]
6 to 8, the phase correction clock driver 71 receives a clock signal having a phase difference from the clock driver 12c, the clock driver 12d, the clock driver 12e, and the clock driver 12f in four directions, and a clock having a phase difference. A negative product circuit 40 for detecting a phase difference between the clock signals 1 to 4 with respect to the signal 1, the clock signal 2, the clock signal 3, the input signal 71 of the clock signal 4, the input signal 72, the input signal 73, and the input signal 74, and The logical sum circuit 41, the negative product circuit 40, and the F / F circuit 42 to which the pulse signals 75 and 76 output from the logical sum circuit 41 are input.
[0034]
In the negative product circuit (NAND circuit) 40, when the input signals 71 to 74 of the clock signals 1 to 4 all become high level, the output pulse signal 75 becomes low level, and the OR circuit (OR circuit) 41 When the input signals 71 to 74 are all at the low level, the output pulse signal 76 is at the low level.
[0035]
The pulse signal 75 generates a pulse at the edge of the input signal 74 whose rising waveform phase is most delayed among the input signals 71 to 74, and the pulse signal 76 has a falling waveform among the input signals 71 to 74. A pulse is generated with the input signal 74 having the most delayed phase as an edge.
[0036]
The output pulse 77 from the F / F circuit 42 becomes a high level when the pulse signal 75 falls and becomes a low level when the pulse signal 76 falls. That is, among the input signals 71 to 74 of the clock signals 1 to 4, the clock signal 4 having the largest phase delay becomes the output pulse 77.
[0037]
The clock signal 4 having the largest phase lag can be detected with respect to the input signals 71 to 74 of the four clock signals 1 to 4, and the output pulse 77 synchronized with the detected clock signal 4 can be generated. There is an effect that can be reduced.
[0038]
【The invention's effect】
As described above, the semiconductor integrated circuit according to the present invention includes a phase correction clock driver that outputs a clock signal that is input from a plurality of clock drivers and that is synchronized with the clock signal having the largest phase lag. By providing, there is an effect that the delay variation of the clock signal can be suppressed and the clock skew can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a diagram illustrating details of an H-tree portion in FIG. 1;
FIG. 3 is a circuit configuration diagram of a phase correction clock driver.
FIG. 4 is a timing chart of a phase correction clock driver.
FIG. 5 is a diagram showing details of an H-tree portion when a phase correction clock driver is arranged in the middle of a branch of clock signal distribution.
FIG. 6 is a diagram illustrating details of an H-tree unit in which four clock signals are input to the phase correction clock driver 7;
7 is a circuit configuration diagram of the phase correction clock driver in FIG. 6. FIG.
FIG. 8 is a timing chart of the phase correction clock driver of FIG.
FIG. 9 is a schematic circuit diagram showing a conventional semiconductor integrated circuit.
FIG. 10 is a diagram showing details of the H-tree part in FIG. 9;
[Explanation of symbols]
5, 40 Negative product circuit 6, 41 OR circuit 7, 42 F / F circuit 11, 111 Semiconductor integrated circuit 12, 112 Clock driver 12a, 12b Clock driver 12c, 12d Clock driver 12e, 12f Clock driver 112a, 112b Clock driver 13, 113 Clock distribution circuit 14, 114 F / F circuit 16, 116 Clock input point 21, 22 Clock distribution path 121, 122 Clock distribution path 31, 71 Phase correction clock driver 51, 52 Input signal 71, 72 Input signal 73, 74 Input signal 53, 54 Pulse signal 75, 76 Pulse signal 55, 77 Output pulse

Claims (7)

A semiconductor integrated circuit in which a plurality of clock drivers for distributing a clock signal on the same substrate are arranged, and includes a phase correction clock driver to which a plurality of the clock signals are input from the clock driver, and the phase correction clock driver Is a negative product circuit and a logical sum circuit for detecting a phase difference of the clock signal with respect to a plurality of clock signal inputs having a phase difference, and a pulse for the clock signal input by the negative product circuit and the logical sum circuit. A flip-flop circuit to which each of the signals is generated and the pulse signal is input. The flip-flop circuit outputs the clock signal synchronized with the clock signal having a phase lag among the plurality of clock signal inputs. A semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the negative product circuit detects a phase delay of the rising edge of the clock signal, and the OR circuit detects a phase delay of the falling edge of the clock signal. 2. The semiconductor integrated circuit according to claim 1, wherein the flip-flop circuit outputs a clock signal synchronized with the clock signal having a maximum phase delay among the plurality of clock signal inputs. 2. The semiconductor integrated circuit according to claim 1, wherein the phase correction clock driver has two or four clock signal inputs. 2. The semiconductor integrated circuit according to claim 1, wherein the phase correction clock driver is disposed at an end of the clock signal distribution path and is connected to a flip-flop circuit of a logic circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the phase correction clock driver is provided in the middle of a branch of the clock signal distribution path. 2. The semiconductor integrated circuit according to claim 1, wherein the clock drivers are arranged in an H-tree shape.

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