JP3866336B2 - Pen input display device - Google Patents

Description

但し、ＶPG3S6 （ｔ２）はｔ＝ｔ２時のＧ３Ｓ６の電位である。また、ＴＦＴがオフしているので
ＱG3S6(t1)= ＱG3S6(t2) …（３）となり、（１）、（２）、（３）式を計算すると、

となり、（４）式で表されるＶPG3S6 （ｔ２）が得られる。ここで具体的数値として、ＶON＝２５Ｖ、ＶOFF ＝−１０Ｖ、Ｃｓ＝０．５ＰＦ、Ｃｇｓ＝０．０２ＰＦ、ＣＬＣ＝０．３ＰＦとすると、
ＶPG3S6(t2) ＝ 21.34Ｖ …（５）
となる。但し、小数点３桁以下は四捨五入した。
【０１３３】
よって、ＶPG3S6 が０Ｖ〜２１．３４Ｖに変化することが示された（ＶPG3S4 は５Ｖ〜２６．３４Ｖ、ＶPG3S5 は−５〜１６．３４Ｖに変化）。このＶPG3S6 の変化分を、突き上げ電圧と呼び（ここではＣｓ線による突き上げ電圧である）、ここではＣ３がＶOFF 〜ＶONに変化した際生じる突き上げ電圧は２１．３４Ｖとなる。
【０１３４】
図４４に、本実施例にかかわるバックライト１１の相対出力及び各着色層３０の透過率特性及びフォトダイオードアレイ１７のフォトダイオード（ＤFA、ＤFB、ＤFC、ＤFD、ＤFE、ＤFF）の受光感度特性を示す。
【０１３５】
図４４（ａ）はバックライト１１の相対出力を示しており横軸は波長を縦軸は最大出力を１００％と正規化した相対出力を示しており、波長４３０ｎｍ〜４４０ｎｍ、５４０ｎｍ〜５５０ｎｍ、６１０ｎｍ〜６２０ｎｍに於いて同等に最大相対出力１００％が出力されているが他の帯域では、相対出力０％で出力されていない。
【０１３６】
図４４（ｂ）は各着色層の透過率特性を示しており、横軸に波長を縦軸に最大透過率を１００％と正規化した相対透過率を示している。Ｂ着色層では波長４００ｎｍ〜５００ｎｍに於いて透過率１００％で他の帯域では０％である。Ｇ着色層では波長５００ｎｍ〜６００ｎｍに於いて透過率１００％で他の帯域では０％である。Ｒ着色層では波長６００ｎｍ〜７００ｎｍに於いて透過率１００％で他の帯域では０％である。
【０１３７】
図４４（ｃ）はフォトダイオードの受光感度特性を示しており、横軸には波長を縦軸には最高感度波長での感度を１００％と正規化した相対感度（％）を示している。この様にフォトダイオードの受光感度特性は波長に対して均一ではない。従って、放射束が同じでも波長成分が著しく異なっていると得られるフォトダイオードの出力電流も異なってしまうのである。
【０１３８】
図４５にフォトダイオードＤFBの受光面に入射する入射光の様子を示す。図４５（ａ）はｔ＝ｔ１に於ける受光成分を示しており、ｔ＝ｔ１時図４１で示されている通りＶPG3S5 ＝ＶCC、ＶPG3S6 ＝ＧＮＤ、ＶPG3S4 ＝ＶDDであるため図４２より、Ｇ３Ｓ５とＧ３Ｓ６とＧ３Ｓ４を合わせ青色が表示されている。図４５（ｂ）はｔ＝ｔ２に於けるフォトダイオードＤFBの受光成分を示しており、前述の通りの電圧設定になっているため図４２より、Ｇ３Ｓ５とＧ３Ｓ６とＧ３Ｓ４を合わせ黒色が表示されている。なお、図４５（ａ）、（ｂ）の横軸は波長を、縦軸は最大入力を１００％と正規化したフォトダイオードＤFBの受光面に入射する放射束の相対入力を示す。
【０１３９】
なお、液晶層２４には電圧が印加されてから光学特性が変化するまでの時間が存在する。これを一般に応答速度（参考文献：工業調査会「液晶ディスプレイのすべて」佐々木／苗村著、講談社サイエンティフィク「液晶材料」くさ林編）と呼び、ＴＮ液晶で２０ｍｓｅｃ程である。図３６に示したＣｓ線駆動部の出力電圧（ＶＣ１、ＶＣ２、…、ＶＣｌ）のパルス幅（ＶONを出力している時間）は２ＣＰＶ分であるが、このパルス幅は液晶層の応答速度に応じて変えるのが望ましく、ＶＧＡクラスでは１ＣＰＶ期間（１走査期間）約４０μｓｅｃであるので、ＴＮ液晶では２ＣＰＶ分以上とるのが望ましく（より望ましくは５ＣＰＶ〜４００ＣＰＶの間で、もっとより望ましくは１０ＣＰＶ〜３００ＣＰＶの間である）、応答速度が２００μｓｅｃ程の反強誘電性液晶や強誘電性液晶では１ＣＰＶ分以上とるのが望ましい（より望ましくは１ＣＰＶ〜２００ＣＰＶの間で、もっとより望ましくは２ＣＰＶ〜１００ＣＰＶの間である）。また、ＳＶＧＡクラスでは、１ＣＰＶ期間が約３２μｓｅｃであるので、それぞれの液晶材料に於いて、ＶＧＡクラスの１．２５倍のパルス幅をとるのが望ましく、ＸＧＡクラスでは１ＣＰＶ期間が約２５μｓｅｃであるので、それぞれの液晶材料に於いて、ＶＧＡクラスの１．６倍のパルス幅をとるのが望ましい。つまり、ＴＮ液晶ではパルス幅を８０μｓｅｃ以上とるのが望ましく（より望ましくは２００μｓｅｃ〜１６０００μｓｅｃの間で、もっとより望ましくは４００μｓｅｃ〜１２０００μｓｅｃの間である）、応答速度が２００μｓｅｃ程の反強誘電性液晶や強誘電性液晶ではパルス幅を４０μｓｅｃ以上とるのが望ましい（より望ましくは４０μｓｅｃ〜８０００μｓｅｃの間で、もっとより望ましくは８０μｓｅｃ〜４０００μｓｅｃの間である）。
【０１４０】
なぜなら、図４６（ａ）〜（ｃ）に示した様に各液晶材料によって、応答速度は著しくことなり、Ｃｓ線駆動部の出力電圧（ＶＣ１、ＶＣ２、…、ＶＣｌ）のパルス幅が十分長くないと、液晶相２４の透過率変化が十分生じず、光信号変換部３４のフォトダイオードで表示装置１０の光透過率変化を正確に検出できず、初期座標検出の誤検出が生じてしまう。例えば応答速度が２０ｍｓｅｃのＴＮ液晶で１ＣＰＶが２０μｓｅｃで表示装置１０の最大輝度が１００［ｃｄ／ｍｍ2 ］の場合、Ｃｓ線駆動部の出力電圧（ＶＣ１、ＶＣ２、…、ＶＣｌ）のパルス幅が１ＣＰＶ期間であれば、表示装置１０の光透過率変化として約０．１％程しか生じず（輝度変化としては約０．１［ｃｄ／ｍｍ2 ］である）、これを高性能なフォトダイオードで検出できたとしてもこの程度の変化は外部光及びバックライトの輝度変化として生じる可能性があり、その都度誤動作してしまう。Ｃｓ線駆動部の出力電圧（ＶＣ１、ＶＣ２、…、ＶＣｌ）のパルス幅を２ＣＰＶ期間とすれば、表示装置１０の光透過率変化として約０．２％程生じ（輝度変化としては約０．２［ｃｄ／ｍｍ2 ］である）、雑音に対して強くなるため、誤動作を少なくすることが可能である。なお、図４６の（ａ）〜（ｃ）に於いて、縦軸は液晶印加電圧及び透過率を示し、横軸は時間を示す。
【０１４１】
説明をもとに戻すと、図４５の（ａ）と（ｂ）に示されるフォトダイオードＤFBの受光面に入射する放射束変化及びフォトダイオードＤFBの受光感度特性のため（表示が青色から緑色に変化した場合等）、フォトダイオードＤFBに出力変化が生じる。図４５の（ｃ）と（ｄ）はそれぞれフォトダイオードの受光感度特性を考慮した場合の受光成分を示しており横軸に波長を、縦軸にフォトダイオードの受光感度特性を考慮した場合の最大入力を１．０と正規化したフォトダイオードの受光面に入射する放射束の相対入力を示す。（ｃ）と（ｄ）からｔ＝ｔ１〜ｔ＝ｔ２に於いてフォトダイオードの受光感度特性を考慮した場合フォトダイオードの受光面に入射する放射束の相対入力が変化し、結果として図１３からフォトダイオードの出力電流が変化する。
【０１４２】
以上を考慮し、本実施例に関わる初期座標検出方法を具体的に説明する。
【０１４３】
以下に、表示装置１０上に於けるペン先１５のＹ方向初期座標検出の詳細を説明する。
【０１４４】
使用者がペン先１５を図４０に示す表示装置の位置に配置したとするとＶPSR がＨｉｇｈになり、ゲート線駆動部３の出力が全てＶOFF になり、Ｃｓ駆動部９が動作し始め、図２７のＳＷ１２、ＳＷ１３がオフし、その時バックライト１１からＧ３Ｓ４、Ｇ３Ｓ６、Ｇ３Ｓ５を通してくる放射束に応じた出力電流がＤFBに流れ、図１２の光信号変換部３４によって図１２のようにＤFBの出力電流に応じたＶＢが得られ、コンデンサ８４と９２にＶＢが保持される（但し、ＳＷ１２、ＳＷ１３はコンデンサ８４、９２にＶＢが書き込まれた後オフする）。その後図４１に示すタイミングで突き上げ電圧が生じ、液晶層２４の光学的変化によりフォトダイオードの出力電流が減少しＶＢが上昇すると図２７のコンデンサ９２、９３、ダイオード９４の動作から明らかな様に図４７に示す様にオペアンプ９５の出力も上昇し、オペアンプ９５の出力がＶREF3以上になるとコンパレータ９６はＶOFF を出力し、ＯＲ回路１００の出力はＨｉｇｈになる。ペン先１５が表示装置として接触しているのでＶPSR ＝Ｈｉｇｈであり、結果として図４７に示すタイミングでＶYSTOP ＝Ｈｉｇｈになる。
【０１４５】
ＶYSTOP ＝Ｈｉｇｈになるタイミングは、ペン先１５が表示装置のＹ方向のどの位置にあるかによって左右される。なぜなら、生じる突き上げ電圧はＣｓ線電圧が立ち上がることによって生じ、各Ｃｓ線のＶONが立ち上がるタイミングは図３６で明らかな様にＳＴＶ、ＣＰＶのタイミングによって決まっており、Ｃ１ならばＳＴＶがＨｉｇｈになった後１ＣＰＶでＶONが立ち上がり、Ｃ２ならば２ＣＰＶでＶONが立ち上がり、Ｃ３ならば３ＣＰＶでＶONが立ち上がり、ＣｍならばｍＣＰＶ（ここではＣＰＶの立ち上がりエッジをＳＴＶの立ち上がりから数えｍ個目にＶＣｍ＝ＶONになるが、その時間を意味する）でＶONが立ち上がる。
【０１４６】
図２７に示したＹ方向初期座標検出部８３は、図２８に示す通り、ｔcount 期間カウントされたＣＰＶの値を検出保持することができるので、ここでは１０４によって３ＣＰＶ（ＱＡ＝Ｈｉｇｈ、ＱＢ＝Ｈｉｇｈ、ＱＣ＝Ｌｏｗ、ＱＤ＝Ｌｏｗ）がカウントされ、補正値をＤYa3 ＝Ｌｏｗ、ＤYa2 ＝Ｌｏｗ、ＤYa1 ＝Ｌｏｗ、ＤYa0 ＝Ｌｏｗとすれば、ＤY03 ＝Ｌｏｗ、ＤY0２＝Ｌｏｗ、ＤY0１＝Ｈｉｇｈ、ＤY0０＝Ｈｉｇｈ（十進数では３を意味する）となり、ペン先１５の表示装置１０上のＹ方向の座標が検出された。なお、本実施例で使用した液晶層２４の応答速度は約５０μｓｅｃ程度と十分速いものであるとしている。
【０１４７】
仮に液晶層２４の応答速度が遅く１０４によって１０ＣＰＶ（ＱＡ＝Ｌｏｗ、ＱＢ＝Ｈｉｇｈ、ＱＣ＝Ｌｏｗ、ＱＤ＝Ｈｉｇｈ）がカウントされても補正値をＤYa3 ＝Ｈｉｇｈ、ＤYa2 ＝Ｌｏｗ、ＤYa1 ＝Ｌｏｗ、ＤYa0 ＝Ｈｉｇｈ（Ｃｓ線数を１５本としている）とすればＤY03 ＝Ｌｏｗ、ＤY02 ＝Ｌｏｗ、ＤY01 ＝Ｈｉｇｈ、ＤY00 ＝Ｈｉｇｈ（十進数では３を意味する）となり、液晶層２４の応答速度を補正する事が可能である。
【０１４８】
以上によって、Ｙ方向の初期座標（ＤY03 ＝Ｌｏｗ、ＤY02 ＝Ｌｏｗ、ＤY01 ＝Ｈｉｇｈ、ＤY00 ＝Ｈｉｇｈ）が検出された。なお、本実施例ではＴＦＴがオフした後、Ｃｓ線駆動部９により突き上げ電圧が生じるため画素電極に信号線電圧を書き込む際生じる表示装置１０の輝度変化によって初期座標検出部が誤動作することなく、突き上げ電圧によって生じる表示装置１０上の輝度変化のみを初期座標検出部が検出するので高精度な初期座標検出が実現されている。ＴＦＴがオフしてからＣｓ線駆動部９が動作するまでの期間は、ＴＮ液晶で１００μｓｅｃ以上（より望ましくは１ｍｓｅｃ以上）、強誘電液晶や反強誘電液晶では５μｓｅｃ以上（より望ましくは２０μｓｅｃ以上）とるのが望ましい。
【０１４９】
ＤY3、ＤY2、ＤY1、ＤY0の値はペン先１５がアレイ基板８の上から何番目のＣｓ線で制御される画素電極（ＴＦＴを介して、アレイ基板８の上から何番目のゲート線で制御される画素電極）上にあるのかを示しており、ここではアレイ基板８の上から３番目（Ｃ３）のＣｓ線で制御される画素電極上に位置していることを示している。ＤY3、ＤY2、ＤY1、ＤY0の値はペン先１５がアレイ基板８の上から何番目のＣｓ線で制御される画素電極上にあるのかを２進数で示しており、（ＤY3＝Ｌｏｗ、ＤY2＝Ｌｏｗ、ＤY1＝Ｌｏｗ、ＤY0＝Ｈｉｇｈ）はペン先１５がアレイ基板８の上から１番目のＣｓ線で制御される画素電極上に位置していることを示し、（ＤX3＝Ｌｏｗ、ＤX2＝Ｌｏｗ、ＤX1＝Ｈｉｇｈ、ＤX0＝Ｌｏｗ）はペン先１５がアレイ基板８の上から２番目のＣｓ線で制御される画素電極上に位置していることを示し、（ＤX3＝Ｌｏｗ、ＤX2＝Ｌｏｗ、ＤX1＝Ｈｉｇｈ、ＤX0＝Ｈｉｇｈ）はペン先１５がアレイ基板８の上から３番目のＣｓ線で制御される画素電極上に位置していることを示している。
【０１５０】
この様にＣｓ駆動部９の動作とＹ方向初期座標検出部８３の検出のタイミング（図４７）からＹ方向の初期座標を検出することが可能である。
【０１５１】
液晶層２４の光学特性変化によって初期座標を検出する際（本実施例では突き上げ電圧によって液晶層２４の光学特性変化を生じさせている）、正極性の信号線によって書き込まれ画素電極電圧がＶDDである画素電極に突き上げ電圧が生じても図４２に示す様な液晶層２４の光学特性のため、初期座標検出用光センサーの受光面がその画素電極上からの光を支配的に受光したのでは、その画素電極上の光学特性変化が生じないため、初期座標検出が行えない。
【０１５２】
本実施例では、初期座標検出用光センサーの受光面をＸ方向が最も長くなる様に配置した場合の受光面のＸ方向の長さが、図４０に示した様に、１画素電極のＸ方向の長さよりも長く、画素電極図３９に示した様に信号線駆動部２が隣合う信号線が常に逆極性になる様動作するため、Ｘ方向の隣合う画素電極も同様に常に逆極性であり、初期座標検出用光センサーの受光面が、隣合う２つ以上の画素電極からの光を受光し、１つの画素電極からの光を支配的に受光することがないので（１つの画素電極からの光成分は９９％以下で、最高でも８０％以下が望ましい）、図４１〜４９に示した様に初期座標検出用光センサーの受光状態に変化が生じ、安定した初期座標が可能である。
【０１５３】
また、信号線駆動部２が液晶層２４を駆動する電圧をＶDD＝４Ｖ〜−４Ｖとし（図４２で分かる通り透過率特性が飽和しない状態を維持する）、液晶層２４の実力以下の低コントラスト状態で動作させていれば、画素電極電圧が何Ｖであっても突き上げ電圧より画素電極上の光学特性変化が生じる。
【０１５４】
次に、表示装置１０上に於けるペン先１５のＸ方向初期座標検出について説明する。
【０１５５】
ＶPSR ＝Ｈｉｇｈ、ＶYSTOP ＝Ｈｉｇｈになり、Ｙ方向の初期座標（ＤY03 ＝Ｌｏｗ、ＤY02 ＝Ｌｏｗ、ＤY01 ＝Ｈｉｇｈ、ＤY00 ＝Ｈｉｇｈ）が検出されると、図３６に示される様にＣｓ線駆動部９の出力は一端ＶOFF になりその後ハイインピーダンス状態になり、Ｃｓ線には直接電圧が供給されず図４３に示す各画素容量（Ｃｓｉｇ，ｃｓ、Ｃｓ等）によって電位が保たれる。
【０１５６】
また、図１の排他的論理和回路１２０の出力はＨｉｇｈになり、ＳＷ１〜ＳＷｎは全てオフする。さらに、図３０に示すＸ駆動部４の動作から明らかな様に図３１に示される様な信号線電圧がＳ１〜Ｓｎに書き込まれていく。
【０１５７】
ここで、以上の場合の画素電極電圧ＶPG3S6 の変化を説明する。図４８はＣｓ線駆動部９の出力がハイインピーダンス状態で、ＴＦＴが全てオフしている時の画素容量モデルを示しており（但し、Ｃｇ，ｃｏｍの影響は少ないと考えられるので以下では無視する）、図４８のＧ３Ｓ６とＳ６間の容量（ＣG3S6−Ｓ６）を計算すると以下の様になる。
【０１５８】

従って、Ｓ６の電圧変化ΔＶＳ６によって生じるＶPG3S6 の電圧変化ΔＶPG3S6 は以下の様になる。
【０１５９】
ΔＶPG3S6 ＝ＣG3S6- Ｓ６／（ＣG3S6- Ｓ６＋ＣLC）＊ΔＶS6
となる。具体的数値として、Ｃｐ，ｓｉｇ＝０．０１ＰＦ、Ｃｇｓ＝０．０２ＰＦ、Ｃｓｉｇ，ｇ＝０．０５ＰＦ、Ｃｓ＝０．５ＰＦ、ＣＬＣ＝０．４ＰＦ、ΔＶＳ６＝２５Ｖ、Ｃｓｉｇ，ｃｓ＝０．２ＰＦとすると、
ＣG3S6−Ｓ６＝０．１ＰＦ
ΔＶPG3S6 ＝５．０Ｖ
となる。
【０１６０】
以上の結果より、図４９（図４９に於ける、Ｓ６は信号線Ｓ６に印加される信号線電圧を示している）に示すＶPG3S6 が得られるのは明らかであり（ＶPG3S6 のｔ＝ｔ４〜ｔ＝ｔ６の電圧変化分をＸ駆動部による突き上げ電圧と呼ぶ）、図４１〜図４５で説明したフォトダイオードの出力電流変化が生じ、図３２のＸ方向初期座標検出部８２の動作から明らかなように、図４９に示すオペアンプ１２７の出力及びＶXSTOP が得られる（但し、ｔ＝ｔ４時のＶPG3S4 、ＶPG3S6 、ＶPG3S5 及びフォトダイオードの受光面に入射する入射光の受光成分はｔ＝ｔ１時のそれと同等であり、ｔ＝ｔ６時のフォトダイオードの受光面に入射する入射光の受光成分はｔ＝ｔ２時のそれと同等である）。また、カウンタ１４１の動作から図４９に示す１４１の出力ＱＡ＝Ｈｉｇｈ、ＱＢ＝Ｌｏｗ、ＱＣ＝Ｌｏｗ、ＱＤ＝Ｌｏｗが得られ、補正ＤXa3 ＝Ｌｏｗ、ＤXa2 ＝Ｌｏｗ、ＤXa1 ＝Ｌｏｗ、ＤXa0 ＝Ｌｏｗ（この補正値もＹ方向初期座標検出部８３のそれと同様な使い方が可能である）とすれば、ＤX03 ＝Ｌｏｗ、ＤX02 ＝Ｌｏｗ、ＤX01 ＝Ｌｏｗ、ＤX ００＝Ｈｉｇｈが得られる。
【０１６１】
但し、本実施例では、Ｘ駆動部４によって突き上げ電圧を発生させる前に図３６のようにＣｓ線をＣｓ線駆動部から切り放しているため、突き上げ電圧が画素電極に生じ、生じた突き上げ電圧を維持しておくことが可能である。仮にＣｓ線がＣｓ線駆動部から切り放されていなければ、Ｃｓ線電位はＣｓ線駆動部から供給される電位を維持しているため突き上げ電圧は画素電極に生じない。仮にＣｓのシート抵抗が高く、突き上げ電圧が生じてもＣｓ線電位はいずれＣｓ線駆動部から供給される電位に変化するため、生じた突き上げ電圧もその後Ｃｓ線電位に引っ張られてしまい所望する突き上げ電圧は生じない。
【０１６２】
以上によって、Ｘ方向の初期座標（ＤX03 ＝Ｌｏｗ、ＤX02 ＝Ｌｏｗ、ＤX01 ＝Ｌｏｗ、ＤX00 ＝Ｈｉｇｈ）が検出された。
【０１６３】
ＤX3、ＤX2、ＤX1、ＤX0の値はペン先１５がアレイ基板８の左から何番目の信号線で制御される画素電極（ＴＦＴを介して制御される）上にあるのかを示しており、本実施例に於ける図４０から図４９ではアレイ基板８の左から４〜６番目（Ｓ４〜Ｓ６）の信号線で制御される画素電極上に位置していることを示している。
【０１６４】
ＤX3、ＤX2、ＤX1、ＤX0の値はペン先１５がアレイ基板８の左から何番目の信号線で制御される画素電極（ＴＦＴを介して制御される）上にあるのかを２進数で示しており、図３０に示すＸ駆動部４の動作から明かな様にＳ１〜Ｓ３、Ｓ４〜Ｓ６…を同時に駆動しているので、（ＤX3＝Ｌｏｗ、ＤX2＝Ｌｏｗ、ＤX1＝Ｌｏｗ、ＤX0＝Ｌｏｗ）はペン先１５がアレイ基板８の左から１〜３番目の信号線で制御される画素電極（ＴＦＴを介して制御される）上に位置していることを示し、（ＤX3＝Ｌｏｗ、ＤX2＝Ｌｏｗ、ＤX1＝Ｌｏｗ、ＤX0＝Ｈｉｇｈ）はペン先１５がアレイ基板８の左から４〜６番目の信号線で制御される画素電極（ＴＦＴを介して制御される）上に位置していることを示し、（ＤX3＝Ｌｏｗ、ＤX2＝Ｌｏｗ、ＤX1＝Ｈｉｇｈ、ＤX0＝Ｌｏｗ）はペン先１５がアレイ基板８の左から７〜９番目の信号線で制御される画素電極（ＴＦＴを介して制御される）上に位置していることを示している。
【０１６５】
この様にＸ駆動部４の動作とＸ方向初期座標検出部８２の検出のタイミング（図４９）からＸ方向の初期座標を検出することが可能である。
【０１６６】
Ｘ駆動部による突き上げ電圧は、Ｃｓ線電圧による突き上げ電圧と比較すると低く４分の１程度である。液晶層２４の応答速度は印加電圧が高い方が早い。従って、本実施例の様にＸ駆動部で信号線にＶONを順次供給する際ＶONを信号線に一端書き込むとＶXSTOP ＝ＨｉｇｈになるまでＶONを信号線に印加するのが望ましくこれによって液晶層２４の応答速度が遅くとも確実に液晶層２４は応答する。
【０１６７】
本実施例では、以上説明した様に表示装置のスイッチング素子（アレイ基板８のＴＦＴ）を全てオフした状態に於いて、Ｃｓ線と画素電極間のカップリング容量及び信号線と画素電極間のカップリング容量によって画素電極に生じる突き上げ電圧を利用し、その突き上げ電圧によって生じる表示装置の光学特性変化（輝度変化）を検出することによって、表示装置上のペンの座標を検出する。よって、ＴＦＴを介して画素電極に電圧を印加しその印加電圧によって生じる表示装置の光学特性変化を検出しないので、ペンの座標検出精度がＴＦＴの製造ばらつきやＴＦＴのオン抵抗ばらつき（温度や製造や設計ルール等によるばらつきをさす）に影響されず高精度な座標検出が可能であると同時に、ＴＦＴのオン抵抗による書き込み時間に影響されないのでより高速な座標検出も可能である。
【０１６８】
ＴＦＴにはオン抵抗（Ｒオン）が存在し、そのため画素電極にＴＦＴを介して電圧を印加する場合、
τ＝Ｒオン＊Ｃ画素
の時定数が存在し、一般にこれを書き込み時間と呼ぶ。但し、Ｃ画素は画素電極に存在する容量である。ＲオンはＴＦＴのサイズに影響されるため当然製造ばらつきにも影響される（参考文献：辻他、ＩＤY ９３−６５「ａ−Ｓｉ ＴＦＴ−ＬＣＤにおける書き込み時の簡易設計法の検討」、Ａｎａｌｙｓｉｓ ａｎｄＤｅｓｉｇｎ ｏｆ Ａｎａｌｏｇ Ｉｎｔｅｒａｔｅｄ ＣｉｒｃｕｉｔｓＳｅｃｏｎｄ Ｅｄｉｔｉｏｎ、Ｐａｕｌ Ｒ．Ｇｒａｙ、Ｒｏｂｅｒｔ Ｇ．Ｍｅｙｅｒ）。当然、Ｃ画素の大きさにも製造ばらつきが存在しており、結果として、τには大きなばらつきが存在してしまう。
【０１６９】
本実施例では、表示装置１０に存在する容量間の電荷再結合によって生じる突き上げ電圧によって、液晶層２４に電圧を印加し、その際生じる液晶層２４の光学特性変化からペン先１５の表示装置１０上の座標を検出することで、液晶層２４に電圧を印加する際抵抗成分が限りなくゼロになるので、電圧をＣ画素に書き込む際、印加電圧の時定数を考慮する必要がなく、高速で高精度な座標検出が可能である。
【０１７０】
また、本実施例では、ＶREF2、ＶREF3、ＶREF4、ＶREF5を任意に設定することが出来るため、突き上げ電圧によって生じる表示装置１０の各画素電極上の輝度変化が白（透過率１００％）から黒（透過率０％）又は黒から白に変化しなくても、ＶREF2、ＶREF3、ＶREF4、ＶREF5を適宜設定することで、表示装置１０の各画素電極上の僅かな輝度変化が透過率１００％から透過率９８％の場合や透過率０％から透過率２％の様な場合で十分座標検出可能である。本実施例では、透過率が約１０％変化すると座標検出できる様ＶREF2、ＶREF3、ＶREF4、ＶREF5を設定しているので、初期座標を検出する際、表示装置１０の画質劣化が生じない。
また、本実施例ではＸ駆動部４及びＣｓ線駆動部９及びＳＷ１−ｎをアレイ基板８と同一基板上に形成しているため（参考文献：井上他、ＥＩＤ９１−１２５ｐ５９−ｐ６４、大島他、電子情報通信学会論文誌、Ｃ− Ｖｏｌ．Ｊ７６−Ｃ− Ｎｏ．５ ｐｐ２７−ｐｐ２３４）、ペン入力一体型表示装置のより狭額縁化を実現している。
【０１７１】
以上によって、ペン先１５が表示装置１０に接触した時のペン先１５の１０上での座標（Ｙ方向初期座標とＸ方向初期座標）が検出された。
【０１７２】
表示装置１０が表示しているアイコンの座標を検出する場合など上述した座標検出方法のみで十分であるが、ペン入力装置には手書き文字入力（かたかな、ひらがな、漢字、ローマ字等）などを検出する要求なども強い。が、手書き文字入力の検出にはアイコンの座標を検出する場合と違って、ペン先１５が表示装置１０上で高速に移動するため、ペン入力装置がペン先１５の座標を１秒間に検出する回数（検出周波数）を多く（高く）する必要がある。また、手書き文字入力の座標検出をする場合、検出される座標の画素電極上ではほとんどの場合、白が表示されている（本実施例の１０は加法混色を使っているので、厳密には画素電極上では赤または青または緑が表示されている）（参考文献：日経ＢＰ社、フラットパネルディスプレイ１９９０〜１９９５、日経ＢＰ社、日経マイクロデバイス１９９２年６月号）。これは、ノートに鉛筆で字を書くときや、印刷物を考えるとわかるが、通常、白字に黒の文字を書き込んでいる。
【０１７３】
図５０にブラックマトリックス２９の透過率特性とブラックマトリックス２９上のフォトダイオードの受光感度特性を考慮した受光成分を示す。
【０１７４】
図５０（ａ）はブラックマトリックス２９の透過率特性を示しており、横軸に波長を縦軸に最大透過率を１００％と正規化した相対透過率を示している。図５０（ａ）に示される様にブラックマトリックスは可視光線にたいし透過率０％である（参考文献：日経ＢＰ社、フラットパネルディスプレイ１９９０〜１９９５、日経ＢＰ社、日経マイクロデバイス１９９０年１月号〜１９９５年９月号）。したがって、図５０（ｂ）が示す様にブラックマトリックス２９上にフォトダイオードがある場合相対入力は０である。なお、図５０（ｂ）の横軸は波長を縦軸にフォトダイオードの受光感度特性を考慮した場合の最大入力を１００％と正規化したフォトダイオードの受光面に入射する放射束の相対入力を示す。
【０１７５】
本実施例では図５０に示したブラックマトリックス２９の透過率特性と各着色層３０の透過率特性（図４４）の違いをフォトダイオードで検出することで、ペン先１５が表示装置１０上で移動した移動量を検出する。が、実際移動量を検出するだけでは不十分で、それがＸ方向の移動量なのかＹ方向の移動量なのかを識別できなければならない。より、厳密に言うなら、Ｘｕｐ方向の移動量なのかＸｄｏｗｎ方向の移動量なのか、Ｙｕｐ方向の移動量なのかＹｄｏｗｎ方向の移動量なのかを識別できなければならない。本実施例では、移動量及び移動方向を同時に検出する方式を発明したので以下に説明する。
【０１７６】
図５１は、本実施例に於いて、フォトダイオードが表示装置１０から受光する様子とペン先１５の移動量及び移動方向を同時に検出できる方式の基本概念を示すための図で、最初フォトダイオードアレイ１７が図５１（ａ）の様に配置しており、その後図５１（ｂ）の様にペン先１５が移動したものとし、各着色層からは光が液晶層２４の光透過率１００％で光がくるものとする（つまり、表示装置１０はラスター白を表示している）。
【０１７７】
また、図５１に於いてブラックマトリックス下（上）には図示していないが、信号線、Ｃｓ線、ゲート線が配置されている。
【０１７８】
図５２（ａ）〜（ｆ）に、図５１（ａ）に於ける各受光面の受光状態を示しており、横軸は各受光面の左端を０μｍとし左端から右方向への距離を示し縦軸は最大照度を１００％と正規化しブラックマトリックス２９の照度を０％とし各着色層の最大照度を等しいとした場合の単位長さ当たりの相対照度を示している。
図５２（ａ）はＡ受光面の受光状態を示しており、ブラックマトリックス２９上の相対照度が０％で各着色層上の相対照度が１００％である。図５２（ｂ）、（ｃ）はそれぞれＢ受光面の受光状態とＣ受光面の受光状態を示しており、受光状態は図５２（ａ）と同様である。
【０１７９】
図５２（ｄ）はＤ受光面の受光状態を示しており、Ｄ受光面がＹ方向（Ｃｓ線方向）に細長い形であるため、Ｄ受光面はブラックマトリックス２９の相対照度の影響より各着色層３０の相対照度の影響の方を強く受けており、よって、相対照度は１００％付近である。Ｄ受光面をよりＣｓ線方向に細長くすれば相対照度はより１００％に近ずく。図５２（ｅ）（ｆ）はそれぞれ受光面Ｅの受光状態とＦ受光面の受光状態を示しており、図５２（ｄ）と同様である。
【０１８０】
図５３（ａ）〜（ｆ）は、図５１（ｂ）に於ける各受光面の受光状態を示しており、横軸は各受光面の左端を０μｍとし左端から右方向への距離を示し縦軸は最大照度を１００％と正規化しブラックマトリックス２９の照度を０％（実際ブラックマトリックス２９から各受光面が受ける照度は０％である）とし各着色層の最大照度を等しいとした場合の単位長さ当たりの相対照度を示している。
【０１８１】
この様に、表示装置１０の表面には、表示装置１０が本来持っている空間光学特性差が存在している。
【０１８２】
図５３（ａ）はＡ受光面の受光状態を示しており、図５１（ｂ）から明かな様にＡ受光面がＸ方向（信号線方向）に細長い形であるためＸ方向のブラックマトリックス２９（信号線上のブラックマトリックス２９）の相対照度の影響を受け安くなっているため、Ａ受光面の相対照度はブラックマトリックス２９の相対照度０％付近になっている。
【０１８３】
Ｂ受光面及びＣ受光面が受ける相対照度は図５１から明かな様に図５２のそれとほぼ等しくなっている。
【０１８４】
図５３（Ｄ）はＤ受光面の受光状態を示しており、図５１（ｂ）から明かな様にＤ受光面がＹ方向（Ｃｓ線方向）に細長い形であるためＹ方向のブラックマトリックス２９（Ｃｓ線上のブラックマトリックス２９）の相対照度の影響を受け安くなっているため、Ｄ受光面の相対照度はブラックマトリックス２９の相対照度０％付近になっている。Ｅ受光面及びＦ受光面は完全に着色層上に配置されているのでこれらの相対照度は１００％である。
【０１８５】
以上のことから次の結論が得られる。Ａ受光面を有するフォトダイオード、Ｂ受光面を有するフォトダイオード、Ｃ受光面を有するフォトダイオードはＸ方向に細長い構造であるためＹ方向（Ｃｓ線方向）のブラックマトリックス２９の影響は受けにくいがＸ方向（信号線方向）のブラックマトリックス２９の影響は受け易い。Ｄ受光面を有するフォトダイオード、Ｅ受光面を有するフォトダイオード、Ｆ受光面を有するフォトダイオードはＹ方向に細長い構造であるためＹ方向（Ｃｓ線方向）のブラックマトリックス２９の影響は受け易いがＸ方向（信号線方向）のブラックマトリックス２９の影響は受け難い。よって、各フォトダイオードはＸ方向のブラックマトリックス２９とＹ方向のブラックマトリックス２９を区別することが可能である。
【０１８６】
また、Ｘ方向検出用の光センサーの受光面は、各受光面を各受光面のＹ方向が最も長くなる様に配置した時の各受光面のＸ方向の長さが図５に示す２９のＸ方向長（２９Ｘ）の２倍以下の長さになる様設計するのが望ましくより望ましくは２９Ｘ以下の長さにするのが望ましい。
【０１８７】
なぜなら、本実施例で使用したフォトダイオードや他のＣＣＤなどの光センサーは受光面に入射する光エネルギーに応じて出力信号を発生する。したがって、受光面の面積に応じた出力信号が得られるため、検出しようとするブラックマトリックス２９の２９Ｘが上述したＸ方向の長さよりも短すぎると、マトリクスを横切るときの出力変化が少なく光センサーがブラックマトリックス２９を検出出来なくなってしまう。本実施例では上述したＸ方向の長さが２９Ｘの長さと同等以下になる様設計し、正常動作を確認した。
【０１８８】
また、Ｙ方向検出用の光センサーの受光面も同様に、各受光面を各受光面のＸ方向が最も長くなる様に配置した時の各受光面のＹ方向の長さが図５に示す２９のＹ方向長（２９Ｙ）の２倍以下の長さになる様設計するのが望ましくより望ましくは２９Ｙ以下の長さにするのが望ましい。本実施例では上述したＹ方向の長さが２９Ｙの長さと同等以下になる様設計し、正常動作を確認した。
【０１８９】
図５４（ａ）に本発明に於けるアレイ基板８の構造とブラックマトリックス２９の配置を示す。
【０１９０】
図５４（ａ）、（ｂ）、（ｃ）に於いて点線はブラックマトリックス２９を示している。ここで重要なことは図５４（ａ）、（ｃ）の様に、Ｃｓ線と画素電極の重なり部分をゲート線近傍に配置することである。なぜなら、Ｃｓ線はブラックマトリックス２９と同様に一般に光を透過しないので、例えば図５４（ｂ）の様にＣｓ線と画素電極の重なり部分とゲート線を離して配置したのではフォトダイオードがゲート線上にあるブラックマトリックス２９によってその出力電流が変化したのか、Ｃｓ線によってその出力電流が変化したのか判別できず、ペン入力表示装置の誤動作を引き起こしてしまう。また、フォトダイオードの受光面はブラックマトリックス２９より著しく大きくすることはできない。なぜなら、フォトダイオードの受光面はブラックマトリックス２９に大きく影響されなければならないからである。したがって、図５４（ｂ）においてフォトダイオードの受光面の大きさはゲート線幅上のブラックマトリックス２９の幅（又は、ゲート線幅）によって制限されることになり、つまりはゲート線幅によって制限されることになる。フォトダイオードの受光面を広くするためゲート線上のブラックマトリックス２９の幅をただ大きくしたのでは、表示装置１０の開口率低下を生じ消費電力増大を招く。本発明の様に図５４（ａ）、（ｃ）のアレイ基板構造にすることで、ゲート線及びＣｓ線上のブラックマトリックス２９の幅を広くすることが出来てしかも表示装置１０の開口率を損なわず（なぜなら、Ｃｓ線の位置がただ単に画素電極上でずれただけである）、フォトダイオードの受光面を広くすることが可能である。フォトダイオードの出力電流はその受光面の面積に比例しており、受光面積が大きいほどより多くの出力電流を流すことが出来るため、その出力電流変化を電圧変化に変換する図１２の光信号変換部３４がオペアンプ４４のオフセット電流の影響及びバイアス電流の影響を受け誤動作しにくくなる。しかも４２、４５の抵抗値をより小さくすることが出来るため（オームの法則より、小さい抵抗値でもより大きい電流を流すことでより大きい電圧を得る）、光信号変換部３４をより高速に動作させることが可能になり、より、高速なペン入力が可能になる。
【０１９１】
以上まとめると、本実施例に於いて、図５４（ａ）、（ｃ）に示す様にゲート線近傍にＣｓ線を配置してゲート線とＣｓ線間に表示装置１０の開口部がない（つまり、あるＣｓ線とそのＣｓ線に最も近いゲート線との間に開口部がない）様にブラックマトリックス２９をゲート線及びＣｓ線上に配置する様なアレイ構造にすることで、表示装置１０の開口率を損なわず、ゲート線及びＣｓ線上のブラックマトリックス２９の幅を広くすることが出来るとともに、フォトダイオードがゲート線上にあるブラックマトリックス２９によってその出力電流が変化したのか、Ｃｓ線によってその出力電流が変化したのか判別する必要もないので、より高精度でより低消費電力なペン入力装置を提供することが出来る。
【０１９２】
以上のことを考慮し、本実施例に於いて、ペン先１５が図５５、図５６、図５７に示す様に移動した場合のその移動量の検出方法（移動量検出方法）を説明する。
【０１９３】
ｔ＝ｔ８に於いて、ペン先は図５５に示される様に配置している。その後ｔ＝ｔ９になり、図５６に示される様な位置に移動し、その後ｔ＝ｔ１０になり、図５７に示される様な位置に移動する（ただし、その間の移動は最短距離で移動したものとする）。
【０１９４】
図５８に、上述した様にペン先が移動した時の各受光面が受ける相対照度を示す。
【０１９５】
図５８（ａ）〜（ｆ）の横軸は時間軸で、縦軸は表示装置の光透過率が１００％で（図４２参考）各フォトダイオードの受光面が図５５の様に配置している時の各受光面が受ける照度を１００％と正規化し各受光面全面がブラックマトリックス２９上にある時の照度を０％とした相対照度である。
【０１９６】
図５５に於ける各フォトダイオードの配置から、全てのフォトダイオード受光面に最大照度（１００％）が入射されているのが解る。
【０１９７】
その後ペン先１５は、図５６に示される位置に移動するため各フォトダイオード受光面はゲート線Ｇ４上（厳密にはＧ４及びＣ４上）のブラックマトリックス２９を横切る。その際Ａ、Ｂ、Ｃ各受光面はＸ方向に細長い構造をしているため、ゲート線Ｇ４上のブラックマトリックス２９の影響を大きく受けるため図５８に示す様に、ｔ＝ｔ８〜ｔ＝ｔ９に於いて各相対照度が大きく低下している。一方、Ｄ、Ｅ、Ｆ各受光面はＹ方向に細長い構造をしているため、ゲート線Ｇ４上のブラックマトリックス２９の影響を受けにくく図５８に示す様に、ｔ＝ｔ８〜ｔ＝ｔ９に於いて各相対照度が僅かに低下している。
【０１９８】
その後ペン先１５は図５７に示される位置に移動するため各フォトダイオード受光面は信号線Ｓ４、Ｓ３、Ｓ２上のブラックマトリックス２９を横切る。その際Ｄ、Ｅ、Ｆ各受光面はＹ方向に細長い構造をしているため、信号線Ｓ４、Ｓ３、Ｓ２上のブラックマトリックス２９の影響を大きく受けるため図５８に示す様に、ｔ＝ｔ９〜ｔ＝ｔ１０に於いて各相対照度が大きく低下している。一方、Ａ、Ｂ、Ｃ各受光面はＸ方向に細長い構造をしているため、信号線Ｓ４、Ｓ３、Ｓ２上のブラックマトリックス２９の影響を受けにくく図５８に示す様に、ｔ＝ｔ９〜ｔ＝ｔ１０に於いて各相対照度が僅かに低下している。図５５と図５６と図５７から図５８が得られるのは明らかである。
【０１９９】
また、ｔ＝ｔ８〜ｔ＝ｔ９に於ける相対照度の変化において、Ｂ受光面の相対照度変化の次にＡ受光面、Ｃ受光面どちらの相対照度が変化するかは、ペン先１５が表示装置１０上でＹｕｐ方向に移動しているかＹｄｏｗｎ方向に移動しているかによる。なぜなら図５５に於いて、ゲート線Ｇ４上のブラックマトリックス２９からＣ受光面が最も近くその次にＢ受光面が近くその次にＡ受光面が近いからであり、ゲート線Ｇ３上のブラックマトリックス２９からＡ受光面が最も近くその次にＢ受光面が近くその次にＣ受光面が近いからである。よって、Ｂ受光面の相対照度変化の次にＡ受光面の相対照度が変化する場合は、ペン先１５がＹｄｏｗｎ方向に移動している時であり、Ｂ受光面の相対照度変化の次にＣ受光面の相対照度が変化する場合は、ペン先１５がＹｕｐ方向に移動している時である。一方、ｔ＝ｔ９〜ｔ＝ｔ１０に於ける相対照度の変化において、Ｅ受光面の相対照度変化の次にＤ受光面、Ｆ受光面どちらの相対照度が変化するかは、ペン先１５が表示装置１０上でＸｕｐ方向に移動しているかＸｄｏｗｎ方向に移動しているかによる。なぜなら図５６に於いて、ペン先１５がＸｄｏｗｎ方向に移動する場合、Ｄ、Ｅ、Ｆ各受光面とＤ、Ｅ、Ｆ各受光面からＸｄｏｗｎ方向の最も近い各信号線までの距離は、各受光面毎に異なっており、Ｆ受光面が最も近く次にＥ受光面であり次にＤ受光面である。また同様に、ペン先１５がＸｕｐ方向に移動する場合、Ｄ、Ｅ、Ｆ各受光面とＤ、Ｅ、Ｆ各受光面からＸｕｐ方向の最も近い各信号線までの距離は、各受光面毎に異なっており、Ｄ受光面が最も近く次にＥ受光面であり次にＦ受光面である。従って、図５６に於いて、ペン先がＸｄｏｗｎ方向に移動する場合まずＦ受光面の相対照度変化が起こり次にＥ受光面の相対照度変化が起こり次にＤ受光面の相対照度変化が起こるのである。同様に、ペン先がＸｕｐ方向に移動する場合まずＤ受光面の相対照度変化が起こり次にＥ受光面の相対照度変化が起こり次にＦ受光面の相対照度変化が起こるのである。
【０２００】
この様に本実施例では、各フォトダイオードが表示装置１０上に配置された時の各受光面の位置関係を次の様にしている。
【０２０１】
上下方向（Ｙｕｐ、Ｙｄｏｗｎ方向）を検出する各フォトダイオードの各受光面の位置関係を、各受光面と各受光面からＹｄｏｗｎ方向の最も近い各ゲート線までの距離を、各受光面毎に異なる様に配置し、同様に各受光面と各受光面からＹｕｐ方向の最も近い各ゲート線までの距離を、各受光面毎に異なる様に配置する。
【０２０２】
よって、本実施例では、各フォトダイオードからの電気信号のみでペン先１５がＸｕｐ方向とＸｄｏｗｎ方向（Ｙｕｐ方向とＹｄｏｗｎ方向）のどちらに移動しているかを検出することが出来るとともに、同一のフォトダイオード構成及び同一回路構成で（図１８と図１９参考）ペン先１５がＸｕｐ方向とＸｄｏｗｎ方向（Ｙｕｐ方向とＹｄｏｗｎ方向）のどちらに移動しているかを検出することが出来る。よって、本実施例により、ペン入力表示装置の部品点数削減が可能になり、ペン入力表示装置の軽薄短小化が実現出来る。
【０２０３】
図５９（ａ）〜（ｆ）に、図５８に示される様な各受光面の相対照度時間変化が生じた時の光信号変換部３４の出力（ＶＡ〜ＶＦ）の時間変化を示す。なお、図５９（ａ）〜（ｆ）の横軸は時間軸であり縦軸は出力の最大値を１００％、最小値を０％とした時の相対出力を示している。また、図５９（ａ）〜（ｆ）に示される様にＶREF1を設定すると、レベルシフト部４９の動作から明らかな様に図６０（ａ）〜（ｆ）に示すＶＡ０、ＶＢ０、ＶＣ０、ＶＤ０、ＶＥ０、ＶＦ０が得られる。図６０（ａ）〜（ｆ）に於いて横軸は時間軸であり、縦軸は電圧を示す。
【０２０４】
図６１に図６０に示される様なＶＡ０、ＶＢ０、ＶＣ０、ＶＤ０、ＶＥ０、ＶＦ０が得られた場合のシリアル信号発生部５０（図１８）の動作結果から得られる信号（ＶＹｄｏｗｎ、ＶＹｕｐ）を示す。図１８から明らかな様に図６１の結果が得られる。
【０２０５】
図６２に図６１に示される様な信号（ＶＹｄｏｗｎ、ＶＹｕｐ）が得られた時に、図２２のパラレル信号発生部５１から得られる信号（ＤY13 、ＤY12 、ＤY11 、ＤY10 ）と図３４のＹ座標検出部３９から得られる信号（ＤY3、ＤY2、ＤY1、ＤY0）を示す。
【０２０６】
図６３に図６０に示される様なＶＡ０、ＶＢ０、ＶＣ０、ＶＤ０、ＶＥ０、ＶＦ０が得られた場合のシリアル信号発生部（図１９参考）の動作結果から得られる信号（ＶＸｄｏｗｎ、ＶＸｕｐ、ＶＸｄｏｗｎ３、ＶＸｕｐ３）を示す。図１９から明らかな様に図６３の結果が得られる。
【０２０７】
図６４に図６３に示される様な信号（ＶＸｄｏｗｎ、ＶＸｕｐ、ＶＸｄｏｗｎ３、ＶＸｕｐ３）が得られた時に、パラレル信号発生部（図２３）から得られる信号（ＤX13 、ＤX12 、ＤX11 、ＤX10 ）とＸ座標検出部３８から得られる信号（ＤX3、ＤX ２、ＤX １、ＤX0）を示す。
【０２０８】
なお、本実施例の図５８及び図５９に於いて、各受光面の相対照度変化が生じてからＶＡ〜ＶＦの相対出力が変化するまでの時間は、ペン入力デバイス１が有する光センサーの応答速度に依存し、光センサーとしてフォトダイオードを使用した場合は約１０μｓｅｃであり、フォトトランジスターを使用した場合は約３０μｓｅｃである。従って、図５に於いて２９のＹ方向長及び２９のＸ方向長を３０μｍ、１画素に於ける各着色層のＹ方向の長さを２７０μｍ、Ｘ方向の長さを７０μｍとし、ペン先１５が表示装置１０上でＸ方向に１秒間にＺ画素分（信号線上のブラックマトリックスＺ本分）移動したものとする。このとき移動した距離は、
１００μｍ＊Ｚ
となり、３０μｍを移動するのに要した時間ｔ（３０）は、
ｔ（３０）＝０．３／Ｚ［秒］
となる。従って、本実施例に於いて画素数で表された１秒間に検出可能な移動量Ｚは、光センサーがブラックマトリックス２９を検出出来るか否かによるので、Ｚは以下の様になる。
【０２０９】
ｔ（３０）＞３０μｍ
Ｚ ＜ １００００
（但し、フォトトランジスターを使用した）
よって、本発明に係わるペン入力一体型表示装置を使用者が正常な目的で使っている限り、移動量の検出に於いて、時間分解能が足りないというような不具合は生じず、本発明によって、高時間分解能を備えたペン入力一体型表示装置が提供できる。
【０２１０】
以上によって、ペン先１５が表示装置１０上に配置され移動した場合のペン先１５の座標が以下の様に検出された。
【０２１１】
ｔ＝ｔ１・ペン先が図４０の様に配置される。
【０２１２】
ｔ＝ｔ２・Ｙ方向の初期座標を検出。
【０２１３】
ＤY03 ＝Low 、ＤY02 ＝Low 、ＤY01 ＝High、ＤY00 ＝High
移動量が無いので、初期座標がＹ座標となる。
【０２１４】
ｔ＝ｔ６・Ｘ方向の初期座標を検出。
【０２１５】
ＤX03 ＝Low 、ＤX02 ＝Low 、ＤX01 ＝Low 、ＤX00 ＝High
移動量が無いので、初期座標がＸ座標となる。
【０２１６】

が検出され、コントロール部７は、ＤX 、ＤY を受けそれに応じたＶＤを出力。検出された座標が表示装置に出力（黒表示となる）される。
【０２１７】
ｔ＝ｔ９・Ｙ方向の移動量を検出。
【０２１８】
Ｙ座標は、ＤY3 ＝Low 、ＤY2 ＝High、ＤY1 ＝Low 、ＤY0 ＝Low
Ｘ方向の移動量は無し。
【０２１９】

が検出され、コントロール部７は、ＤX 、ＤY を受けそれに応じたＶＤを出力。検出された座標が表示装置に出力（黒表示となる）される。
【０２２０】
ｔ＝ｔ10・Ｘ方向の移動量を検出。
【０２２１】
Ｘ座標は、ＤX3 ＝Low 、ＤX2 ＝Low 、ＤX1 ＝Low 、ＤX0 ＝Low
Ｙ方向の移動量は無し。
【０２２２】

が検出され、コントロール部７は、ＤX 、ＤY を受けそれに応じたＶＤを出力。検出された座標が表示装置に出力（黒表示となる）される。
【０２２３】
以上説明したように、本発明の第１実施例によれば、表示装置１０上に於いてペン先１５が移動した移動量を、表示装置１０の着色層３０とブラックマトリックス２９の透過率差によって生じる表示装置表面の光学特性差によって検出し、ペン先１５が表示装置１０に配置された際の初期座標を、アレイ基板８の信号線及びＣｓ線を駆動した時に表示装置１０の画素電極に生じる突き上げ電圧によって検出できるので、表示装置１０の背後もしくは前面にペン先１５の座標検出用タブレットを設ける必要が無いとともに、ペン先１５の移動量をペン入力デバイス１が有する光センサーによって瞬時に検出でき、初期座標をＴＦＴの製造ばらつきに影響されることなく検出できる。
【０２２４】
この結果、高精度及び高時間分解能なペン入力機能を備えた小型・軽量なペン入力一体型表示装置を実現できる。
【０２２５】
なお、本発明のペン入力一体方表示装置は上述した実施例に限定されるものではない。ペン入力デバイス１、信号線駆動部２、Ｃｓ線駆動部９、Ｘ駆動部４、アレイ基板８、ゲート線駆動部３、表示装置１０、フォトダイオードアレイ１７、光信号変換部３４、初期座標検出部３６、移動量検出部３７、Ｘ座標検出部３８、Ｙ座標検出部３９、ペンシステムリセット部３５の構成も適宜変更可能である。
【０２２６】
なお、本実施例に於ける移動量検出手段は、本実施例で表示装置１０として使用したＴＦＴ−ＬＣＤ以外で、表示部と遮光部を有する表示装置例えば単純マトリクスＬＣＤやプラズマディスプレイやＣＲＴ（参考文献：日経ＢＰ社、フラットパネルディスプレイ１９９０〜１９９５、日経ＢＰ社、日経マイクロデバイス１９９１年４月号−１９９４年７月号）などにも適用可能でその具体的構成も適宜変更可能である。
【０２２７】
次に本発明に係わる第２の実施例を以下に示す。
【０２２８】
ペン入力装置に於けるペンと表示装置の傾きが大きく変化すると、受光面に入射する光エネルギーが変化し、光センサーの誤動作を招くことがある。第２実施例はこの問題を解決するもので、ペンと表示装置の傾きが変化してもペンの光センサーの受光面の表示装置に対する傾きを所定角度以下に保つ。
【０２２９】
図６５は、本発明の実施例２に係わるペン入力デバイスの構造を示しており、第１実施例１と同一のものについては同一符号を付し、詳細な説明は省略する。
図６５に於ける傾き制御部１５６は、フォトダイオードアレイ１７の受光面と表示装置１０の表示面の傾きが０度〜４５度（望ましくは０度〜２０度でより望ましくは０度つまり平行である）になるよう制御しており、これによって、図６５（ａ）〜図６５（ｃ）の様にペン入力デバイス１の傾き（ペンの傾き角）が変化しても、フォトダイオードアレイ１７の受光面と表示装置１０の表示面の傾きが０度〜４５度に制御される。
【０２３０】
ＣＲＴ、プラズマディスプレイ、液晶ディスプレイ等の表示装置では、表示装置の表面をどの角度から見るかによって表示装置表面の輝度が異なっている。この特性は液晶ディスプレイに於いてより顕著に見られ、一般には視野角（参考文献：日経ＢＰ社，フラットパネルディスプレイ１９９０〜１９９５、日経ＢＰ社，日経マイクロデバイス１９９０年１月号〜１９９５年９月号）と呼ばれている。したがって、光学的に座標検出を行う場合、この視野角のためペン入力デバイス１の傾き角（ペンの傾き角）により光信号変換部３４の出力ＶＡ〜ＶＦが変化してしまい結果として座標検出の誤動作が生じていた。しかし、本実施例２によって、ペンの傾き角による誤動作を抑えることが出来、安定した座標検出が可能となった。
【０２３１】
図６６及び図６８は、本発明の第２実施例に係わるペン入力デバイスの構造をより詳細に示しており、第１実施例と同一のものについては同一符号を付し、詳細な説明は省略する。
【０２３２】
図６６〜図６８に於いて、１５７はバネ１５８を支えている支持台であり、１５９は１６に加わる力によって移動するスライダーを示している。ペンの傾きが図６６〜図６８の様に変化しても（本実施例では１５度〜９５度の場合を示している）、バネ１５８の復元力によって、スライダー１５９が移動し、光センサーであるフォトダイオードアレイ１７の受光面が表示装置１０の表示面と常に平行になるように制御されるので、バックライト１１からフォトダイオードアレイ１７の受光面に入射する光の入射角がペンの傾き角が何度であっても常に一定に制御されるため、ペンの傾き角変化によって、フォトダイオードアレイ１７の受光面に入射する放射照度が変化せず、より安定した座標検出が実現されている。また、本実施例の様に傾き制御部１５６を支持台１５７とバネ１５８とスライダー１５９で構成することで、ペン入力デバイス１に要求される小型化及び軽量化が同時に実現されている（これらを合わせても１グラム以下である）。また、傾き制御部１５６の構成は適宜変更可能であり、ゴムやジャイロスコープセンサの様に角度変化を検出するセンサーを使用してもよく、その使用方法も適宜変更可能である。
【０２３３】
以上説明したように、本発明の第２実施例によれば、ペン入力デバイス１の傾きが変化しても、傾き制御部１５６がフォトダイオードアレイ１７の受光面と表示装置１０の表示面の傾きが０度〜４５度になるよう制御するので、ペン入力デバイス１の傾き角変化による光信号変換部３４の出力ＶＡ〜ＶＦが変化を抑えることができるため、誤動作の無い安定した座標検出を行うことが出来る。
【０２３４】
この結果、小型軽量なペン入力デバイス１を備えたペン入力一体型表示装置に於いて、安定した座標検出が可能となる。
【０２３５】
次に本発明による第３の実施例を説明する。
【０２３６】
高精細な表示装置を使ったペン入力表示装置では使用者がペン入力を行う際に生じる手振れやペン入力を行う入力面が紙と違い滑りやすいために生じる誤入力がより顕著に表れるため、表示装置が持っている高精細な表示ができず手振れによる誤入力などが目立ちみすぼらしい筆跡となってしまう。本実施例はこの問題を解決するためのもので、画素サイズの比較的小さい表示装置を有するペン入力装置で、手書き入力速度が比較的速い場合にも十分にペンの軌跡に対して補正を行うことができる。
【０２３７】
図６９は本実施例の全体的な構成を示す。１１００はペン入力表示装置であり、第１実施例で説明したペン入力表示装置１０００（図１参照）と基本的に同一の構成であるが、第１実施例のＸ及びＹ座標が各々４ビットで構成されたのに対し、この第３の実施例で用いられるペン入力表示装置のＸ及びＹ座標はより実際的な６ビットで各々構成されている。図６９のＤＸ及びＤＹはペン入力表示装置１１００のＸ及びＹ座標出力である。
【０２３８】
図６９に於いて、１７０はＤＸ，ＤＹ信号から、検出ペンがペン入力状態に於いて表示装置上で移動した速度（移動速度）を検出するペンスピード検出部であり、ＤＳは検出ペンの移動速度を示す。１７１はＤＸ，ＤＹから、検出ペンがペン入力状態に於いて表示装置上で移動した移動ベクトルとその変化であるベクトル変化を検出するベクトル変化検出部であり、ＤＸＶはＸ方向の移動ベクトルを示しＤＹＶはＹ方向の移動ベクトルを示し、ＤＸＶとＤＹＶで検出ペンの表示装置１０’上での移動ベクトル（単にベクトルとも呼ぶ）を示す。また、ＶＶは移動ベクトルのベクトル変化を示す。１７２は１７０及び１７１からの信号に基づいてペン入力示表装置１１００からの信号を補正して、検出ペンの表示装置上での位置を示す補正された信号ＤＹＣ，ＤＸＣをペン入力示表装置１１００に出力する補正部である。これらの詳細も後程説明する。
【０２３９】
図７０に表示装置１０’の各画素を示すデジタル信号ＤＸ（ＤX6，ＤX5，ＤX4，ＤX3，ＤX2，ＤX1），ＤＹ（ＤY6，ＤY5，ＤY4，ＤY3，ＤY2，ＤY1）を示す。図７０に於いて、１番左上の画素の座標をＤＸ，ＤＹで示すとＤＸ＝（０，０，０，０，０，１），ＤＹ＝（０，０，０，０，０，１）となる。一番右上の座標をＤＸ，ＤＹで示すとＤＸ＝（１，１，１，１，１，１），ＤＹ＝（０，０，０，０，０，１）となる。一番左下の画素の座標をＤＸ，ＤＹで示すとＤＸ＝（０，０，０，０，０，１），ＤＹ＝（１，１，１，１，１，１）となる。一番右下の座標をＤＸ，ＤＹで示すとＤＸ＝（１，１，１，１，１，１），ＤＹ＝（１，１，１，１，１，１）となる。他の画素についても同様な順序でデジタル信号が対応してある。なお、本実施例ではＸ方向Ｙ方向とも６４画素の表示装置であるので、前述したようにＤＸ及びＤＹとも図７０に示される６ビットのデジタル信号で表現される。なお、表示装置１０’の画素サイズは３００μｍ×３００μｍである。
【０２４０】
以上の構成のペン入力表示装置に於いて、図７１に示す様に「１」を手書き入力する。図７２に示すように、一般に（本実施例を含む）ペン入力表示装置の表面は紙などと異なり滑らかで滑りやすく、その上、ペン入力表示装置の表面は何度も手書き入力しなくてはならないため、ペン入力表示装置に使用する検出ペンのペン先を尖らすことができず、より滑りやすくなっている。従って手書きで文字を入力するような場合、ぎこちない書体となることがある。これは、表示装置１０’が高精細になる程より大きな問題になる。よって、本実施例におけるペンスピード検出部１７０、ベクトル変化検出部１７１、補正部１７２が無い場合、「１」を入力したつもりでも、図７３に示す様な「１」が入力され表示される。図７３に於いて、各格子は表示装置１０’の１画素を示しており、黒色で表示された画素はペン入力によって選択された画素を示しており、各画素とデジタル信号ＤＸ，ＤＹの関係は図７０で示した通りである。ここで、図７３のように得られた座標デジタル信号ＤＸ，ＤＹを分析する。
【０２４１】
図７４に、図７３の場合に得られたデジタル信号ＤＸ，ＤＹと時間との関係を示す。図７４における検出時間とは、手書き入力開始からどれほど時間が経過したかを示し、０ｍｓｅｃは手書き入力が開始された時を示しており、図７４で示された検出時間間隔（１ｍｓｅｃ）は、ペン入力表示装置の座標検出における時間分解能（参考文献：情報処理学会論文誌Ｍａｒ．１９２０４Ｖｏｌ．２９Ｎｏ．３「手書き編集記号を用いたオンライン文字図形編集法」児島他）を示している。なお、本実施例において検出時間間隔は表示装置の精細度にもよるが、１画素のペン座標データ（ＤＸ，ＤＹ）を２回以上検出できる程短いことが望ましく、より望ましくは３回上であり、その値は適宜変更可能である。
【０２４２】
図７５にペンスピード検出部１７０の構成を示す。図７５の１７３，１７４，１７６，１７７，１８６，１８７はＤタイプフリップフロップであり本実施例ではＴＣ７４ＨＣ５７４を使用した。１８１はブッファーであり１８２，１８３，１９２はインバーターであり、１７５，１７８はコンパレーターであり本実施例ではＴＣ７４ＨＣ６２０４を使用した。１７９は非論理和回路であり、１８０は論理積回路であり、１８４，１８５はカウンターであり本実施例ではＴＣ７４ＨＣ１６１を使用した。１８８は２チャンネルマルチプレクサーであり例えばＴＣ７４ＨＣ４０５３で構成してもよい。１８９は乗算回路であり、例えば参考文献「デジタルシステムの設計 ＣＱ出版社 猪飼／本多共著」に示される回路構成で良い。なお、インバータ１９２はバッファ１８１に比べ動作速度が速い。
【０２４３】
図７６にベクトル変化検出部１７１の構成を示す。１９０はベクトル検出部であり、デジタルデータＤＸ，ＤＹから検出ペンの移動ベクトルを検出しアナログ信号であるＤＸＶ，ＤＹＶを出力する回路であり、１９１はベクトル比較部でありＤＸＶ，ＤＹＶから移動ベクトル変化を示すデジタル信号ＶＶを出力する回路であり、ＶＶがＨｉｇｈの時移動ベクトルが変化したことを示し、Ｌｏｗの時移動ベクトルの変化は無い。
【０２４４】
図７７に図７３に対応した検出ペンの移動ベクトル方向の定義を示す。図７７におけるＶ１〜Ｖ８の矢印は検出ペンのペン先が図７３上でその矢印方向の移動ベクトル方向に移動していることを示すための矢印であり、Ｖ９はペン先が静止していることを示したものである。
【０２４５】
図７８はＤＸＶ，ＤＹＶ信号と移動ベクトル方向の関係を示した図である。なお、ＤＸＶ，ＤＹＶ信号は３レベル（Ｈｉｇｈ，Ｍｉｄｄｌｅ，Ｌｏｗ）のアナログ信号である。
【０２４６】
ペンスピード検出部１７０の動作から図７９に示される結果が得られる。Ｄフリップフロップ１７３及び１７６によって半クロック遅れたＤＸ，ＤＹが得られ、Ｄフリップフロップ１７４，１７７によって１クロック遅れたＤＸ，ＤＹが得られる。コンパレータ１７５及び１７８によってＤフリップフロップ１７３と１７４の出力及びＤフリップフロップ１７６と１７７の出力が比較され、同じ値であればＬｏｗが異なった値であればＨｉｇｈが出力される。１８４，１８５ではコンパレータ１７５及び１７８からＨｉｇｈが出力された後次ぎのＨｉｇｈが出力されるまでの期間のＣＬＫ１のクロック数をカウントし出力する。１８６，１８７は１８４，１８５の出力を１９２の出力をクロックとして取り込み保持する。図７９に１８６，１８７の出力を１０進数で示す。実際に得られる値は複数ビットによる２進数で示されるのだが、説明が複雑になるため以下では１０進数を使って示す。１８６，１８７の出力は検出ペンの移動速度を示しており、１８６，１８７の出力が４であれば１画素をペン先が横切るのに４クロック要したことになる。よって、本実施例に於いて１画素サイズが３００μｍ＊３００μｍであるので、移動速度は３００μｍ／（４Ｔ）となる。なお、ＴはＣＬＫ１の周期を示す。１画素は長方形や正方形の形をしているため１画素をペン先がどの様に横切るかで１画素を横切る距離が異なる。本実施例では１画素は正方形であるため、Ｖ１，Ｖ３，Ｖ５，Ｖ７方向に移動する場合１画素を横切る距離は３００μｍであり、Ｖ２，Ｖ４，Ｖ６，Ｖ８方向に移動する場合１画素を横切る距離は１４０μｍである。よって、本実施例では１８８を使ってペン先がどの方向に移動したかによって、１８６，１８７に重みずけする値を変えている。１８８は１８０の出力がＨｉｇｈの時ｃｈ１を選択し、１８０の出力がＬｏｗの時ｃｈ２を選択する。１８０がＨｉｇｈになる時ペン先はＶ２，Ｖ４，Ｖ６，Ｖ８方向に移動している。本実施例ではｃｈ１とｃｈ２の比をｃｈ１／ｃｈ２＝１．４（１０進数で示している）に近くなる様設定しており、１８９の乗算回路で１８６，１８７の出力に重みずけしている。乗算回路１８９の出力を図７９に示す。本実施例では以上の方式で移動速度を検出しているので画素の形状に依存しない正確な移動速度を検出できるとともに図７５に示す様に簡単な回路構成で移動速度を検出可能である。なお、１画素のサイズが１００μｍ＊３３μｍの様に長方形の場合も本実施例と同様に１画素の形状に応じて得られた検出ペンの移動速度に重みずけすることでより正確な移動速度が得られる。
【０２４７】
ベクトル検出部１９０から図７９に示す移動ベクトル方向が得られ、ベクトル比較部１９１によって図７９に示すＶＶが得られる。ベクトル比較部１９１はＤＸＶ，ＤＹＶを受け、ベクトルが変化した際にＨｉｇｈを出力する。なお、ベクトルがＶ９の時は前ベクトルでペン先が移動しているものとし、ベクトル比較部１９１ではＶ９を前ベクトルに置き換え処理を行う。ベクトル比較部１９１は検出時間４ｍｓｅｃで検出されたベクトルをＶ５として扱い検出時間５ｍｓｅｃ〜９ｍｓｅｃで検出されたベクトルをＶ５として扱い検出時間１０ｍｓｅｃで検出されたベクトルをＶ３として取り扱い、ベクトル変化が生じた時図７９に示される様にＨｉｇｈを出力する。他も同様である。
【０２４８】
図８０に補正部１７２の構成を示す。図８０の位相調整部１９２は、入力された信号を処理しやすくするため図８１の様に位相調整する。なお、Ｄｓ′，ＶＶ′，ＤＸＶ′，ＤＹＶ′，ＤＸ′，ＤＹ′は１９２によって位相調整されたＤｓ，ＶＶ，ＤＸＶ，ＤＹＶ，ＤＸ，ＤＹである。変換部１９３は、ＤＸ′，ＤＹ′から削除するデータを選択する方法は以下の通りである。
【０２４９】
（１）Ｄｓ′から得られる移動速度が増加しているにも係らず移動ベクトルに変化が生じた場合（ＶＶ′＝Ｈｉｇｈ）、そのＤＸ′，ＤＹ′データを無効とし削除する。”
（２）削除する直前の移動速度及び移動ベクトル（ＤＸＶ′，ＤＹＶ′）と削除後の移動速度及び移動ベクトルを比較し、削除後の移動ベクトルと削除直前の移動ベクトルが同じであるかもしくは削除後の移動速度が削除直前の移動速度よりも遅ければそのＤＸ′，ＤＹ′データを有効と判断し取り込む。
【０２５０】
以上によって得られたＤＸＣ′，ＤＹＣ′を図８１に示す。
【０２５１】
よって、誤入力データであるＤＸ＝（０，１，０，０，０，０），ＤＹ＝（０，０，１，１，０，１）が削除されたが、正常入力データであるＤＸ＝（０，０，１，１，１，１），ＤＹ＝（０，０，１，１，１，０）も削除されてしまった。本実施例ではこの様な問題を解決するため補間部１９４でこの表示上の不具合を解消するため、ＤＸ＝（０，０，１，１，１，１），ＤＹ＝（０，０，１，１，０，１）とＤＸ＝（０，０，１，１，１，１），ＤＹ＝（０，０，１，１，１，１）間を線形補間するデータを作成しこれをＤＸＣ′，ＤＹＣ′に重ねあわせる。これによって得られるＤＸＣ，ＤＹＣデータを図８１に示す。Ｄｘｍ，ＤＹｍは線形補間されたデータであり、Ｄｘｍ＝（０，０，１，１，１，１），ＤＹｍ＝（０，０，１，１，１，０）である。なお、線形補間とは図８２に示す通り、線のぬけた部分を最少距離でつなぎ不具合を修正するものである。
【０２５２】
次に本発明による第４実施例を説明する。図８３は第４実施例に係るペン入力表示装置の構成を示す。本実施例と前述の第３実施例で異なる点は、ペン入力表示装置に抵抗皮膜タブレットを使用していることである。
【０２５３】
図８３に於いて、１９５は抵抗膜を示し、１９６は抵抗膜を示し、１９７は抵抗膜１９５上に配置された導電層を示し、１９８は抵抗膜１９５上に配置された導電層を示し、５は抵抗膜１９６上に配置された導電層を示し、２００は抵抗膜１９６上に配置された導電層を示し、ＳＷ１及びＳＷ２はＣＮＴ１で制御されるスイッチであり、ＳＷ３及びＳＷ４はＣＮＴ２で制御されるスイッチであり、２０４は一定電圧を各抵抗膜に供給する電圧源であり５Ｖを供給している。インピーダンス変換部２０２は導電層１９８及び導電層６からアナログの電気信号で検出ペン２０５の表示装置１０’上での位置を示しているＸ方向信号とＹ方向信号を、インピーダンス変換した後Ｘ′，Ｙ′として出力するインピーダンス変換部であり、２０３はアナログ信号であるＸ′，Ｙ′をそれぞれＤＸ，ＤＹのデジタル信号に変換するＡ／Ｄ変換部である。以上説明した各構成要素の動作は後程詳細に説明するが、これらの参考文献として「東芝レビュー１９９４Ｖｏｌ．４９Ｎｏ．１２」などがある。なお、移動ベクトル方向（Ｘ方向、Ｙ方向）の定義は図８３に示す通りである。
【０２５４】
図８４に本実施例におけるペン座標検出の原理を示す。図８４（ａ）は１９５と１９６の抵抗膜で形成されるタブレットの断面図を示しており、１３は非ペン入力状態時に抵抗膜１９５と１９６を非接触させておくためのスペーサである。この様に、抵抗膜１９５と１９６に検出ペンが圧力を加えてないと抵抗膜１９５と１９６は非接触状態を保っている。
【０２５５】
図８４（ｂ）は、抵抗膜１９５と１９６に検出ペン２０５が圧力を加えている状態を示す図であり、この様に検出ペン２０５からの圧力が加えられると抵抗膜１９５と１９６は接触状態になる。また、検出ペン２０５から圧力が加えられている箇所を対抗電極２０７とし、図８４（ｃ）に示す様に導電層１９７と対抗電極２０７との間の抵抗をＲ１５とし、導電層１９８と対抗電極２０７の間の抵抗をＲ１６とし、導電層１９９と対抗電極２０７の間の抵抗をＲ１９とし、２００と検出ペン２０５の間の抵抗をＲ２０とする。なお、１９５と１９６の抵抗膜にはある一定のシート抵抗が存在するが導電層１９７，１９８，１９９，２００ではこのシート抵抗が無視できる程小さい。
【０２５６】
図８５にインピーダンス変換部２０２の構成を示す。図８５の２０８及び２０９はオペアンプであり、いわゆるボルテージフォロワーとして使われており、入力信号をインピーダンス変換し出力する。図８６にＳＷ１〜ＳＷ４の制御を示す。ＣＮＴ１がＨｉｇｈレベル時ＳＷ１，ＳＷ２はオン状態であり、ＣＮＴ１がＬｏｗレベル時ＳＷ１，ＳＷ２はオフ状態である。ＣＮＴ２がＨｉｇｈレベル時ＳＷ３，ＳＷ４はオン状態であり、ＣＮＴ２がＬｏｗレベル時ＳＷ３，ＳＷ４はオフ状態である。ＣＮＴ１及びＣＮＴ２は常に両方が逆位相で駆動されている。
【０２５７】
図８７に、図８４（ｃ）の場合の等価回路を示す。図８７（ａ）はＣＮＴ１＝Ｈｉｇｈ，ＣＮＴ２＝Ｌｏｗの場合の等価回路を示しており、導電層１９９及び６に電圧が印加されておらず導電層１９７に０Ｖが１９８に５Ｖが印加されている。従って、６の電圧は５＊Ｒ１５／（Ｒ１５＋Ｒ１６）となるためＸ′＝５＊Ｒ１５／（Ｒ１５＋Ｒ１６）である。つまり、検出ペンのＸ方向の位置１４がアナログ信号Ｘ′として検出された。
【０２５８】
図８７（ｂ）はＣＮＴ１＝Ｌｏｗ，ＣＮＴ２＝Ｈｉｇｈの場合の等価回路を示しており、導電層１９７及び１９８に電圧が印加されておらず導電層１９９に０Ｖが６に５Ｖが印加されている。従って、２００の電圧は５ＶとなるためＸ′＝５Ｖである。本実施例では、Ｘ′＝５Ｖの場合これをペンのＸ方向の位置を示すアナログ信号として取り扱わない。
【０２５９】
図８８に、図８４（ｃ）の場合の等価回路を示す。図８８（ａ）はＣＮＴ１＝Ｈｉｇｈ，ＣＮＴ２＝Ｌｏｗの場合の等価回路を示しており、導電層１９９及び６に電圧が印加されておらず導電層１９７に０Ｖが１９８に５Ｖが印加されている。従って、１９８の電圧は５Ｖであり、Ｙ′＝５Ｖとなる。本実施例では、Ｙ′＝５Ｖの場合これをペンのＹ方向の位置を示すアナログ信号として取り扱わない。
【０２６０】
図８８（ｂ）はＣＮＴ１＝Ｌｏｗ，ＣＮＴ２＝Ｈｉｇｈの場合の等価回路を示しており、導電層１９７及び１９８に電圧が印加されておらず導電層１９９に０Ｖが２００に５Ｖが印加されている。従って、６の電圧は５ＶとなるためＹ′＝５＊Ｒ１９／（Ｒ１９＋Ｒ２０）である。つまり、検出ペンのＹ方向の位置１４がアナログ信号Ｙ′として検出された。
【０２６１】
以上の様に、本実施例では以下に示す通りペンの位置を検出し、
ＣＮＴ１＝Ｈｉｇｈ，ＣＮＴ２＝Ｌｏｗの場合
検出ペンのＸ方向の位置をアナログ信号として検出する
ＣＮＴ１９６＝Ｈｉｇｈ，ＣＮＴ１＝Ｌｏｗの場合
検出ペンのＹ方向の位置をアナログ信号として検出する
得られたアナログ信号をＡ／Ｄ変換部２０３によってデジタル信号ＤＸ，ＤＹに変換する。デジタル信号ＤＸ，ＤＹは図８３のペンスピード検出部１７０、ベクトル変化検出部１７１及び補正部１７２に出力され、前述したように補正される。
【０２６２】
以上の通り、本実施例によって、人間工学上誤入力であるデータを削除した使用者の意図にそったペン入力が実現可能であるペン入力表示装置が実現された。また、本実施例では１画素移動毎に移動速度及び移動ベクトルを検出しているのでよりすばらしい筆跡の手書き入力が可能となった。なお、本実施例は抵抗薄膜タブレットを利用したペン入力表示装置以外の例えば、電磁誘導タブレットを利用したペン入力表示装置（参考文献：東芝レビュー１９９４Ｖｏｌ．４９Ｎｏ．１２、日経ＢＰ社フラットパネルディスプレイ '９３、日経ＢＰ社ＭＡＴＥＲＩＡＬＳ＆ＴＥＣＨＮＯＬＯＧＹ９３．８）や静電結合タブレットを利用したペン入力表示装置（参考文献：東芝レビュー１９９４Ｖｏｌ．４９Ｎｏ．１２、日経ＢＰ社フラットパネルディスプレイ '９３、日経ＢＰ社ＭＡＴＥＲＩＡＬＳ＆ＴＥＣＨＮＯＬＯＧＹ９３．８）や、その他のペン入力表示装置（特開平４−２８３８１９、特開平４−２９９７２７、特開平５−１２７８２３、特開平５−１５２０４８０、特開平４−３４３３８７、特開平５−１８９１２６、特開平５−１９７４８７、特開昭６２−９２０２１、特開昭６３−２９３６２３）などに利用でき、それ以外のペン入力表示装置にも利用できる。
【０２６３】
次に本発明による第５の実施例を説明する。
【０２６４】
上記従来のアクティブマトリックス型表示装置を使ったペン入力表示装置ではアクティブ素子に電圧を供給する信号線やゲート線が開口率向上及び高精細化のため近年ますます微細加工されるようになっており（参考文献：日経ＢＰ社 フラットパネルディスプレイ１９９１〜１９９５）、このため、検出ペンと各電極線間の結合容量が小さくなり結果として検出電圧が小さくなり正確な座標検出が困難になっている。図１００にそのことを示す。
【０２６５】
図１００の４００はアレイ基板であり、４０１は４００上に配置されたシリコン酸化膜であり、４０２は４００上に配置されたＣｓ線であり、４０３は４００上に配置されたゲート線であり、４０４は４００上に配置された信号線であり、４０５は４００上に配置された画素電極であり、４０９は４００の対向に配置された対向基板であり、４０６は４００と対抗基板４０９の間に注入された液晶層であり、４０８は対抗基板４０９上に配置された着色層であり、４０７は対抗基板４０９上に配置された対向電極である。４００〜４０９でアクティブマトリックス型表示装置を構成している。３１０は検出ペンのペン先を示し、Ｃｐｇはペン先３１０とゲート線４０３の結合容量を示し、Ｃｐｓはペン先３１０と信号線４０４の結合容量を示し、ＣＬはペン先３１０とＧＮＤ間（ここではＡＣグラウンドを意味する）の容量を示し、Ｖｐはペン先に生じる検出電圧を示す。ゲート線に生じる電圧変化をΔＶｇ、信号線に生じる電圧変化をΔＶｓとし検出電圧Ｖｐの初期条件を０Ｖとすると、ペン先に生じる検出電圧Ｖｐは近似的に以下の式で示される。
【０２６６】
Ｖｐ＝ΔＶｇ＊Ｃｐｇ／（Ｃｐｇ＋ＣＬ）
Ｖｐ＝ΔＶｓ＊Ｃｐｓ／（Ｃｐｓ＋ＣＬ）
よって、Ｃｐｇ（Ｃｐｓ）又はΔＶｇ（ΔＶｓ）を大きくすることで検出電圧Ｖｐを大きくすることが可能であるが、ΔＶｇ（ΔＶｓ）はアクティブ素子の耐圧のため極端に大きくすることが出来ず、酸化膜４０１の膜厚が３５００オングストローム程度であれば４５Ｖ程度が信頼性上望ましい。Ｃｐｇ（Ｃｐｓ）の値は最も単純な式で以下のように示される。
【０２６７】
Ｃｐｇ ∝ ε０＊εｇ＊Ｇｈａｂａ／ｄｇ
Ｃｐｇ ∝ ε０＊εｇ＊Ｓｈａｂａ／ｄｇ
ε０：真空の誘電率
εｇ：ガラスの非誘電率
Ｇｈａｂａ：ゲート線幅
Ｓｈａｂａ：信号線幅
ｄｇ：ガラスの厚み
Ｃｐｇ（Ｃｐｓ）を大きくするには、εｇ，Ｇｈａｂａ，Ｓｈａｂａを大きくするかｄｇを小さくしなくてはならない。が、εｇは材料の基本的性質であるため極端に大きくすることなど望めず、ｄｇを小さくしすぎてはガラス破損やたわみが生じてアクティブ素子をアレイ基板４００上に均一に作れなくなってしまうため、ｄｇとしては０．３ｍｍ〜１．１ｍｍが望ましい。唯一変更可能な要素なのがＧｈａｂａ，Ｓｈａｂａであるが、これは上述した通り近年ますます微細化されている。なお、ここで述べているゲート線幅及び信号線幅を図１０１に示す。図１０１はアクティブマトリックス型表示装置を真上から見た図である。
【０２６８】
したがって、信号線又はゲート線と検出ペンの結合容量が小さくなり検出ペンで検出する検出電圧が小さくなり、高精細で高開口率なアクティブマトリックス型表示装置ではバックライトや他からのノイズのため正確な座標検出が不可能である。
【０２６９】
本実施例は、上記事情を考慮してなされたものであり、ペン入力表示装置のより正確でしかも細かい筆跡でかつすばやい手書き入力でも見栄えの良い手書き入力ができることを目的とする。以下、本発明による第５実施例を詳細に説明する。
【０２７０】
図８９に本発明の実施例１に係るペン入力表示装置を示す。図８９に於いて、３０１はＴＦＴ基板（アレイ基板）でありこれに信号線（Ｓ１〜Ｓ５）、ゲート線（Ｇ１〜Ｇ４）、Ｃｓ線（Ｃｓ１〜Ｃｓ４）、ＴＦＴ、画素電極が配置されている。３０２は対向基板であり、３０３は対向基板に配置された対向電極であり、３０４はＴＦＴ基板３０１に配置された信号線に信号線電圧を印加する信号線駆動回路であり、３０５はＴＦＴ基板３０１に配置されたゲート線にゲート線電圧を印加するゲート線駆動回路である。３０１〜３０９でＴＦＴ−ＬＣＤ（以下では単に表示装置と呼ぶ）を構成しておりこれらの参考文献として例えば「日経ＢＰ社フラットパネルディスプレイ１９９１〜１９９５」などがある。３０６はＸ駆動回路であり、３０７はＣｓ線にＣｓ線駆動電圧を供給するＣｓ駆動回路であり、これらの具体的構成例は後程示す。３０８は電源部であり、各回路部に必要な電圧を供給している。３０９９は制御部であり、各駆動部を正常に動作させるための各種信号を各駆動部に供給しており、信号線駆動回路３０４にはＥＳをゲート線駆動回路３０５にはＥＧをＸ駆動回路３０６にはＥＸをＣｓ駆動回路３０７にはＥＣを、スイッチｓｗｓ１〜ｓｗｓ５にはＣＮＴＳを、スイッチｓｗｇ１〜ｓｗｇ４にはＣＮＴｇを、スイッチｓｗｘ１〜ｓｗｘ５にはＣＮＴｘを、スイッチｓｗｃ１〜ｓｗｃ４にはＣＮＴＣを供給している。また、制御部３０９は検出ペン３１０に必要な信号を供給するとともに、３１０から検出ペンの座標検出に必要な信号を供給されている。ＥＧ，ＥＳ，ＥＣ，ＥＸはそれぞれデータバスラインを示しており、各種制御信号がこれらにそれぞれ含まれている。また、スイッチｓｗｓ１〜ｓｗｓ５はＣＮＴＳでオンオフ制御されるスイッチであり、スイッチｓｗｇ１〜ｓｗｇ４はＣＮＴｇでオンオフ制御されるスイッチであり、スイッチｓｗｘ１〜ｓｗｘ５はＣＮＴｘでオンオフ制御されるスイッチであり、スイッチｓｗｃ１〜ｓｗｃ４はＣＮＴＣでオンオフ制御されるスイッチである。ｓｗｃｏｍはＣＮＴｃｏｍでオンオフ制御されるスイッチであり、このスイッチを通し電圧Ｖcom が２に供給される。５０００は対抗電極３０３に対向電極電圧Ｖcom を供給する対向電極駆動回路である。３１０はＴＦＴ基板３０１から供給される検出電圧（図１００のＶｐにあたる）を検出するもので、第５実施例に係るペン入力表示装置では検出電圧の発生タイミングによって３１０のＴＦＴ基板３０１上での位置（ペン座標）を検出する。なお、Ｘ方向とＹ方向を図８９に示す通り定義する。
【０２７１】
図９０に各スイッチの動作タイミングを示す。本実施例に係るペン入力表示装置では１フレーム中の垂直ブランキング期間中にペン座標検出を行う。表示期間中はｓｗｇ１〜ｓｗｇ４，ｓｗｓ１〜ｓｗｓ５，ｓｗｃ１〜ｓｗｃ４，ｓｗｃｏｍはオンし、ｓｗｘ１〜ｓｗｘ５はオフしている。よって、画像信号に応じた信号線電圧が信号線駆動回路３０４から画素電極にＴＦＴを通し供給される。この時Ｘ駆動回路３０６からの電圧はｓｗｘ１〜ｓｗｘ５がオフしているので表示装置の画像に影響しない。表示装置が表示期間から垂直ブランキング期間に移りＸ方向ペン座標検出期間になるとｓｗｘ１〜ｓｗｘ５はオフからオン状態になり、他のスイッチはオフ状態になる。Ｙ方向ペン座標検出期間に入るとｓｗｃ１〜ｓｗｃ４はオン状態になり他はオフ状態になる。
【０２７２】
図９１にＸ駆動回路６の構成を示す。Ｘ駆動回路３０６は３１１〜３１５のＤフリップフロップから成り、３１１〜１５はＣＬＫをクロック、ＳＴＨＸをスタートパルスとしいわゆるシフトレジスタを構成している。
【０２７３】
図９２にＣｓ駆動回路３０７の構成を示す。Ｃｓ駆動回路３０７は３１６〜３１９のＤフリップフロップから成り、３１６〜３１９はＣＬＫをクロック、ＳＴＨＣＳをスタートパルスとするいわゆるシフトレジスタを構成している。
【０２７４】
図９３にＸ駆動回路３０６，Ｃｓ駆動回路３０７の動作を示す。ＳＴＨＸは表示装置がＸ方向ペン座標検出期間になると１ＣＬＫ分ＶＨになり、ＶＸ１〜ＶＸ５が順次ＶＨになる。ただし、ＶＸ１〜ＶＸ５はそれぞれＸ１〜Ｘ５の印加電圧を示し、ＶＣ１〜ＶＣ４はそれぞれＣ１〜Ｃ４の印加電圧を示す。ＳＴＨＣＳは表示装置がＹ方向ペン座標検出期間になると１ＣＬＫ分ＶＨになり、ＶＣ１〜ＶＣ５が順次ＶＨになる。また、ＶＸＴ，ＶＹＴは制御部９の内部信号で、ＶＸＴはＸ方向ペン座標検出期間時にＨｉｇｈレベルで他の期間はＬｏｗレベルである。ＶＹＴはＹ方向ペン座標検出期間時にＨｉｇｈレベルで他の期間はＬｏｗレベルである。以上の動作は図９１及び図９２から明らかである。
【０２７５】
図９４（ａ）に検出ペン３１０が表示装置のＳ１４及びＣＳ１３上近傍に配置されている図を示す。また、この時の断面図を図９４（ｂ）、図９４（ｃ）に示す。図９４（ｂ）、図９４（ｃ）に示す通り、ペン先３１０と表示装置の各電極間及び各電極間には結合容量が存在しており、ｃｐｇはゲート線とペン先３１０との結合容量を、ｃｐｓは信号線とペン先３１０との結合容量を、ｃｓｇは信号線とゲート線との結合容量を、ｃｓｃは信号線とＣｓ線との結合容量を、ｃｓは画素電極とＣｓ線との結合容量を、ｃｐｃはＣｓ線とペン先３１０との結合容量を、ｃｐｌｃは画素電極とペン先３１０との結合容量を、ｃｇｓはゲート線と画素電極との結合容量を、ｃｌｃは着色層４０７と画素電極との結合容量を、ｃｓｃｏｍは信号線と着色層４０７との結合容量をそれぞれ示している。但し、図９４（ｂ）、図９４（ｃ）に示している各結合容量は結合容量を形成する電極間から直接結合されている結合容量を示し、他の電極を通して生じる結合容量は含まれない。例えばペン先３１０と信号線４０４の電極のみ考慮した場合、ペン先３１０と信号線４０４の結合容量は図９４（ｂ）に示すｃｐｓであるが、実際はＣｓ線等の他の電極が表示装置には存在しており、これらに一定のバイアス電圧が印加されず電荷の出し入れが出来ない場合これらの電極を通した結合容量がペン先３１０と信号線４０４間に生じる。なお、図９４（ｂ），（ｃ）に示す各結合容量は、信号線一本とペン先３１０との結合容量を、Ｃｓ線一本とペン先３１０との結合容量を、ゲート線一本とペン先３１０との結合容量を、１画素電極とペン先３１０との結合容量を、信号線一本と対向電極との結合容量を、Ｃｓ線一本と対向電極との結合容量を、ゲート線一本と対向電極との結合容量を、１画素電極と対向電極との結合容量をそれぞれ示している。
【０２７６】
また、本実施例に於いて、表示装置が表示期間から垂直ブランキング期間になった際でＸ１がＶＬからＶＨになる直前に於いて、信号線駆動回路３０４及びゲート線駆動回路３０５，Ｃｓ駆動回路３０７は全信号線及び全ゲート線、全Ｃｓ線にＶＬを供給する。この様にしたことで表示期間から垂直ブランキング期間に移った際、ＴＦＴは確実にすべてオフし信号線に信号線電圧を供給する供給源が信号線駆動回路３０４からＸ駆動回路３０６に変わっても信号線電圧がＶＬ一定に保たれているので、信号線、ゲート線、Ｃｓ線、画素電極等に電圧変動が生じないため検出ペン３１０に誤差電圧が生じずより正確な座標検出が可能となった。
【０２７７】
本実施例におけるペン先３１０と信号線４０４との結合容量Ｃpstotal （ペン先３１０，信号線４０４以外の電極を通して生じる結合容量を含む）及びペン先３１０とＣｓ線４０２との結合容量Ｃpctotal （ペン先３１０，Ｃｓ線４０２以外の電極を通して生じる結合容量を含む）を求めると以下の様になる。なお、アレイ基板４００の厚さは酸化膜４０１，液晶層４０６の厚さに比べ圧倒的に厚い。
【０２７８】
Ｃpstotal ＝Ｃpctotal ＝Ｃｐｓ＋Ｃｐｃ＋Ｃｐｌｃ＋Ｃｐｇ
よって、信号線及びＣｓ線の電圧変化（ΔＶｓ，ΔＶｃｓ）により生じる検出電圧は以下の通りである。
【０２７９】
Ｖｐ＝ΔＶｓ＊Ｃpstotal ／（Ｃpstotal ＋ＣＬ） …（５）
Ｖｐ＝ΔＶｃｓ＊Ｃpctotal ／（Ｃpctotal ＋ＣＬ） …（６）
Ｘ駆動回路３０６及びＣｓ駆動回路３０７を駆動することによって生じる検出電圧は図９５の通りである。検出ペン３１０のペン先が位置している画素電極に係っている信号線及びＣｓ線に電圧変化が生じると図９５に示される通り検出電圧にも電圧変化が生じる。
【０２８０】
図９６に検出電圧に生じる電圧変化のタイミングから検出ペンの位置座標を求める制御部９の内部機能を示す。図９６の３２０はＶｐを扱い易いデジタルパルス信号に変換する波形補正回路であり、３２１，３２２はクリアー機能付きカウンターであり例えば７４ＨＣ１６３等で良い。３２３，３２４はフリップフロップでありカウンタ３２１，３２２の出力を記憶保持する。図９６に示す制御部３０９の動作を図９７に示す。なお、図９７では３２１〜３２４の出力を１０進数で示しているが実際は複数ビットで表わされる２進数である。ＶＰは波形補正回路３２０により１ＣＬＫのデジタルパルスに変換され、カウンタ３２１及び３２２はクリアーされた後のＣＬＫをカウントしフリップフロップ３２３及び３２４に出力する。フリップフロップ３２３はＸ方向ペン座標検出期間でかつＶｐｐがＨｉｇｈレベルの時カウンタ３２１の出力を取り込み保持する。フリップフロップ３２４はＹ方向ペン座標検出期間でかつＶｐｐがＨｉｇｈレベルの時カウンタ３２２の出力を取り込み保持する。従って、フリップフロップ３２３及び３２４に保持される値はペン先がどの画素電極上に配置されるかによって異なり、フリップフロップ３２３はＸ方向のペン座標を示すデータを保持しフリップフロップ３２４はＹ方向のペン座標を示すデータを保持する。本実施例ではＦ１＝３、Ｆ２＝２が保持されるが、ペン先がｓ３とｃｓ２に係る画素電極上に配置されている場合Ｆ１＝２、Ｆ２＝１が保持される。つまり、ペン先の位置に応じたＦ１，Ｆ２の値が得られる。図示しないが制御部３０９では内部データであるＦ１，Ｆ２の値からペン先の位置を決定し、その位置を表示するためのデータを信号線駆動回路３０４及びゲート線駆動回路３０５に送っている。本発明に係るペン入力表示装置では上述により正確な座標検出が可能である。
【０２８１】
図９８に本実施例に係る表示装置をＴＦＴ基板側から見た図を示す。図９８ではペン先３１０が表示装置上に配置されてる時の様子を示しており、図９８の点線はペン先と表示装置との接触面を示している。本実施例に於いて画素電極、信号線、ゲート線、Ｃｓ線のサイズは図９８に示す通り、画素電極３００μｍ＊１００μｍ、ゲート線幅１０μｍ、信号線幅１０μｍ、Ｃｓ線幅１０μｍである。表示装置の各電極とペン先との結合容量は図９８に示すペン先と表示装置との接触面と各電極がどの程度オーバーラップしているかによる。なぜなら平行平板タイプの容量は一般に以下の式で表わされ、
Ｃ＝ε0 εx Ｓ／ｄ
ε0 ＝真空の誘電率
εx ＝コンデンサーの電極間に挟まれた絶縁体の比誘導率
Ｓ＝上記電極の面積
ｄ＝上記絶縁体の厚さ
コンデンサーを形成する電極の面積を大きくすることで容量値を大きくすることが可能である。
【０２８２】
従って、Ｃｐｓ，Ｃｐｃ，Ｃｐｌｃ，Ｃｐｇをそれぞれ比較した場合図９８から明らかな様に、ペン先と表示装置との接触面と画素電極の重なり面積は他の電極の重なり面積に比べ圧倒的に広いため、
Ｃｐｌｃ≒１０Ｃｐｓ≒３０Ｃｐｃ≒６０Ｃｐｇ
Ｃｐｓ＝０．１ｆＦ
である。（５），（６）式より本実施例において検出電圧に生じる電圧変化ΔＶｐは

である。ちなみに実測値はＶｐ＝３８ｍＶであった。実測値が理論値よりも低くなったのは、表示装置には図示していないが１上に保護用シートを被せておりその分絶縁体の厚みがましたためだと考えられる。
【０２８３】
図９４（ｂ）、図９４（ｃ）に於ける検出ペンと表示装置の各電極間等価回路は図９９の通りである。ここで、ＶＸ４をＶＬ〜ＶＨに駆動（信号線電圧変化ΔＶｓ＝ＶＨ−ＶＬ）する際他の電極をフローティング状態にしなければ、Ｃpstotal は以下の様になる。
【０２８４】
Ｃpstotal ＝Ｃｐｓ＝０．１ｆＦ
Ｖｃｓ３をＶＬ〜ＶＨに駆動（Ｃｓ線電圧変化ΔＶｃｓ＝ＶＨ−ＶＬ）する際他の電極をフローティング状態にしなければ、Ｃpctotal は以下の様になる。
【０２８５】
Ｃpctotal ＝Ｃｐｃ＝０．０３ｆＦ
また、この時のＶｐに生じる電圧変化（ΔＶｐ）は、それぞれ以下の通りである。
【０２８６】

となり、実測ではバックライト（図示せず）や３０８などの電源ノイズが原因でこれらは検出不可能であり座標検出を正常に行うことができなかった。
【０２８７】
よって、本実施例による効果が確認できた。
【０２８８】
【発明の効果】
本発明の第１実施例によれば、表示装置と独立して座標検出用タブレットを、表示装置の表又は裏に設ける必要が無く、表示装置と座標検出用タブレットを同一面に形成できるので、ペン入力一体型表示装置の軽量薄型化及び高画質化可能であり、表示装置が数インチ以上の大画面であればあるほど、ペン入力に必要とする部品点数が基本的に変わらないので、本発明による軽量薄型化の効果は大きい。
【０２８９】
例えば、表示装置が対角１２．１インチＸＧＡで画素ピッチが２１０μｍ＊７０μｍのものや、表示装置が対角４０インチで画素ピッチが６３０μｍ＊２１０μｍのものなどに有効であり、表示装置としては透過型でサイズが対角５．５インチ以上のものに特に有効である（対角１０インチ以上にはより有効で、対角２０インチ以上には更に有効である）。
【０２９０】
また、表示装置上のペンの移動量を、ペンが有する光センサーによって表示装置から直接瞬間的に検出するので、高時間分解能な座標検出が可能である。よって、手書き入力に於いて表示装置に対して小さい字を早く書く様な場合（表示装置の大きさを１とした場合に於いて、大きさ１０分の１以下の字を書く場合などに本発明は有効であり、また、８０ドット／秒以上の速度で手書き入力する場合に本発明は有効である）、本発明は非常に有効である。
【０２９１】
また、表示装置上のペンのＸ方向の移動量と表示装置上のペンのＹ方向の移動量を、表示装置表面の表示装置本来ある異なる空間光学特性差によって検出することが可能であるため、ペンＸ方向に移動したのかＹ方向に移動したのかより正確に検出することが可能である。
【０２９２】
また、ペンが有する光センサーの受光面が表示装置上のＸ方向とＹ方向とで異なった長さであるため、光センサーが表示装置のどちらか一方向の空間光学特性差の影響を受けやすくなるので、ペンがＸ方向に移動したのかＹ方向に移動したのかより正確に検出することができる。
【０２９３】
また、ペンが表示装置上に配置された座標を、表示装置のＣｓ線及び信号線を順次選択駆動する際に画素電極に生じる突き上げ電圧による表示装置の輝度変化を利用して検出するので、表示装置に於けるアレイ基板と独立して座標検出用アレイ基板を設ける必要が無く、表示装置と座標検出用タブレットを同一面に形成できるので、ペン入力一体型表示装置の軽量薄型化が可能であり、容量結合による表示装置の輝度変化を利用して、座標を検出するので、画素電極に瞬時に所望する電圧を印加することが出来、画素電極を駆動するスイッチング素子のばらつきが影響されず、高精度な座標検出が可能である。
【０２９４】
また、検出した座標を調整することが可能なため、表示装置の応答速度の温度特性のため発生した検出誤差を調整し、より高精度な座標検出が可能である。
【０２９５】
また、表示装置の画素電極毎に配置されたスイッチング素子をオフした後、Ｃｓ線によって突き上げ電圧を発生させるので、座標検出時に画素電極への信号線電圧書き込みによって生じる表示装置の輝度変化の影響を受けないのでより高精度な座標検出が可能である。
【０２９６】
また、Ｃｓ線をＣｓ線駆動手段から切り離した後、信号線によって突き上げ電圧を発生させるので、生じた突き上げ電圧がＣｓ線駆動手段の影響を受けず突き上げ電圧を維持することが出来る。
【０２９７】
よって、高画質、軽量薄型で高時間分解能、高精度座標検出を実現したペン入力一体型表示装置を得ることが出来る。
【０２９８】
本発明の第２の実施例によれば、ペン入力装置に於けるペンと表示装置の傾きが変化してもペンの光センサーの受光面の表示装置に対する傾きが０度から４５度に保たれるので、受光面に入射する光エネルギーが大きく変化せず、結果として、ペンと表示装置の傾きによって生じる光センサーの誤動作を抑え、より高精度な座標検出が可能である。
【０２９９】
本発明の第３及び４の実施例によれば、補正手段が移動速度と移動速度の変化と移動ベクトルと移動ベクトルの変化にもとずいてペン座標を補正し、移動速度が増加したにもかかわらず移動ベクトルが変化するペン座標を削除し、削除する直前の移動速度及び移動ベクトルと削除後の移動速度及び移動ベクトルを比較し、削除後の移動ベクトルと削除する直前の移動ベクトルが同じかもしくは削除後の移動速度が削除する直前の移動速度よりも遅いかもしくはほぼ等しければ削除後のペン座標を削除しないので、ペン座標の人間工学にもとずいた補正ができる。
【０３００】
本発明の第５の実施例によれば、信号線を駆動してペン座標を検出する際ゲート線およびＣｓ線および対向電極のうち少なくとも一つをフローティング状態にし、ゲート線を駆動してペン座標を検出する際信号線およびＣｓ線および対向電極のうち少なくとも一つをフローティング状態にし、Ｃｓ線を駆動してペン座標を検出する際信号線およびゲート線および対向電極のうち少なくとも一つをフローティング状態にするので、検出ペンが表示装置の各電極とより大きな結合容量を有することができる。
【０３０１】
このため、第５実施例によれば、細かい筆跡でかつすばやい手書き入力でも見栄えの良い手書き入力ができるとともに信号線、ゲート線、Ｃｓ線が細くなっても正確な手書き入力ができる。
【図面の簡単な説明】
【図１】本発明の第一の実施例に係わるペン入力一体型表示装置の構成を示す図。
【図２】同第１実施例に係わるペン入力一体型表示装置の外形図を示す図。
【図３】同第１実施例に係わるペン入力デバイスの断面図。
【図４】同第１実施例に於けるペン入力デバイスの受光の様子を示す図。
【図５】同第１実施例に係わる対向基板の構造を示す図。
【図６】同第１実施例に係わるフォトダイオードアレイ構造を示す図。
【図７】同第１実施例に係わるフォトダイオードアレイ構造を示す図。
【図８】同第１実施例に係わるフォトダイオードアレイ構造を示す図。
【図９】同第１実施例に係わるフォトダイオードアレイの等価回路を示す図。
【図１０】同第１実施例に係わるペン入力デバイスの構成を示す図。
【図１１】同第１実施例に係わるペンシステムリセット部の構成と出力波形を示す図。
【図１２】同第１実施例に係わる光信号変換基本回路の構成を示す図。
【図１３】同第１実施例に係わるフォトダイオードの特性を示す図。
【図１４】同第１実施例に係わる移動量検出部の構成図。
【図１５】同第１実施例に係わるＹ方向移動量検出部の構成図。
【図１６】同第１実施例に係わるレベルシフト部の構成図。
【図１７】同第１実施例に係わるレベルシフト部の動作例を示した図。
【図１８】同第１実施例に係わるシリアル信号発生部の構成図。
【図１９】同第１実施例に係わるシリアル信号発生部の構成図。
【図２０】同第１実施例に係わるパルス３分の一回路の動作を示した図。
【図２１】同第１実施例に係わるシリアル信号発生部の動作を示した図。
【図２２】同第１実施例に係わるパラレル信号発生部の構成を示した図。
【図２３】同第１実施例に係わるパラレル信号発生部の構成を示した図。
【図２４】同第１実施例に係わるフルアダーの回路構成例を示した図。
【図２５】同第１実施例に係わるパラレル信号発生部の動作例を示した図。
【図２６】同第１実施例に係わる初期座標検出部の構成を示した図。
【図２７】同第１実施例に係わるＹ方向初期座標検出部の構成を示した図。
【図２８】同第１実施例に係わるＹ方向初期座標検出部の動作を示した図。
【図２９】同第１実施例に係わる立ち上がりエッジ検出回路の動作を示した図。
【図３０】同第１実施例に係わるＸ駆動部の構成を示した図。
【図３１】同第１実施例に係わるＸ駆動部の動作例を示した図。
【図３２】同第１実施例に係わるＸ方向初期座標検出部の構成を示した図。
【図３３】同第１実施例に係わるＸ方向初期座標検出部の動作を示した図。
【図３４】同第１実施例に係わるＹ座標検出部の構成を示した図。
【図３５】同第１実施例に係わるＣｓ線駆動部の構成を示した図。
【図３６】同第１実施例に係わるＣｓ線駆動部の動作を示した図。
【図３７】同第１実施例に係わるパルス幅変調回路の動作を示した図。
【図３８】同第１実施例に係わるゲート線駆動部３の動作を示した図。
【図３９】同第１実施例に係わる信号線駆動部の動作を示した図。
【図４０】同第１実施例に係わる表示装置上に於けるペン先の位置を示した図。
【図４１】同第１実施例に係わる画素電極電圧のタイミングを示した図。
【図４２】同第１実施例に係わる表示装置のＶ−Ｔ特性を示す図。
【図４３】同第１実施例に係わる画素容量モデルを示す図。
【図４４】同第１実施例に係わるパックライトの相対出力及び各着色層の透過率特性及びフォトダイオードの受光感度特性を示す図。
【図４５】同第１実施例に係わるフォトダイオードの受光変化を示す図。
【図４６】ＴＮ液晶、強誘電液晶、反強誘電液晶の応答速度を示す図。
【図４７】同第１実施例に係わるＹ方向初期座標検出部の動作を示す図。
【図４８】同第１実施例に係わるＣｓ線駆動部の出力がハイインピーダンスでアレイ基板のＴＦＴが全てオフしている時の画素容量モデルを示す図。
【図４９】同第１実施例に係わるＸ方向初期座標検出部の動作を示す図。
【図５０】同第１実施例に係わるブラックマトリクスの透過率特性とブラックマトリクス上のフォトダイオードの受光感度特性を考慮した受光成分を示した図。
【図５１】同第１実施例に係わるフォトダイオードの配置状態を示した図。
【図５２】同第１実施例に係わる図５１（ａ）に於ける各受光面の受光状態を示した図。
【図５３】同第１実施例に係わる図５１（ｂ）に於ける各受光面の受光状態を示した図。
【図５４】同第１実施例に係わるアレイ基板８の構造とブラックマトリクスの配置を示した図。
【図５５】同第１実施例に係わる表示装置上に於けるペン先の位置を示した図。
【図５６】同第１実施例に係わる表示装置上に於けるペン先の位置を示した図。
【図５７】同第１実施例に係わる表示装置上に於けるペン先の位置を示した図。
【図５８】同第１実施例に係わる各受光面の相対照度の時間変化を示した図。
【図５９】同第１実施例に係わる光信号変換部の相対出力の時間変化を示した図。
【図６０】同第１実施例に係わる各レベルシフト部の出力の時間変化を示した図。
【図６１】同第１実施例に係わるシリアル信号発生部の動作を示した図。
【図６２】同第１実施例に係わるパラレル信号発生部の動作及びＹ座標検出部の動作を示した図。
【図６３】同第１実施例に係わるシリアル信号発生部の動作を示した図。
【図６４】同第１実施例に係わるパラレル信号発生部の動作及びＸ座標検出部の動作を示した図。
【図６５】本発明の第２の実施例に係わるペン入力デバイスを示す図。
【図６６】同第２実施例に係わるペン入力デバイスを示す図。
【図６７】同第２実施例に係わるペン入力デバイスを示す図。
【図６８】同第２実施例に係わるペン入力デバイスを示す図。
【図６９】本発明の第３の実施例に係わるペン入力デバイスを示す図。
【図７０】同第３実施例に係る表示装置１０’とＤＸ，ＤＹ信号の関係を示す図。
【図７１】同第３実施例に係る手書き入力の様子を示す図。
【図７２】同第３実施例に係る手書き入力の様子を示す図。
【図７３】同第３実施例に係る本発明の効果が無い場合の手書き入力結果を示す図。
【図７４】同第３実施例に係るペン入力座標データＤＸ，ＤＹと時間関係を示す図。
【図７５】同第３実施例に係るペンスピード検出部の構成を示す図。
【図７６】同第３実施例に係るベクトル変化検出部の構成を示す図。
【図７７】同第３実施例に係る図７３に対応した移動ベクトル方向の定義を示す図。
【図７８】同第３実施例に係るベクトル変化検出部の動作を示す図。
【図７９】同第３実施例に係るペンスピード検出部、ベクトル変化検出部、補正部の動作を示す図。
【図８０】同第３実施例に係る補正部１７２の構成を示す図。
【図８１】同第３実施例に係る補正部１７２の構成を示す図。
【図８２】同第３実施例に係る本発明の効果を示す図。
【図８３】本発明の第４実施例に係るペン入力装置の構成図
【図８４】同第４実施例に係るペン座標検出の原理を示す図。
【図８５】同第４実施例に係るインピーダンス変換部８の構成を示す図。
【図８６】同第４実施例に係るｓｗ１〜ｓｗ４の制御を示す図。
【図８７】同第４実施例に係る図８４（ｃ）の等価回路を示す図。
【図８８】同第４実施例に係る図８４（ｃ）の等価回路を示す図。
【図８９】本発明の第５実施例に係るペン入力装置の構成図。
【図９０】同第５実施例に係るペン入力装置の駆動シーケンスを示す図。
【図９１】同第５実施例に係るＸ駆動回路の構成を示す図。
【図９２】同第５実施例に係るＣｓ駆動回路の構成を示す図。
【図９３】同第５実施例１に係るＸ駆動回路とＣｓ駆動回路の動作を示す図。
【図９４】同第５実施例に於いて検出ペンが表示装置上に配置されている様子を示す図。
【図９５】同第５実施例におけるペン座標検出方法を示す図。
【図９６】同第５実施例におけるペン座標検出方法を示す図。
【図９７】同第５実施例におけるペン座標検出結果を示す図。
【図９８】同第５実施例におけるアレイ基板の構造を示す図。
【図９９】同第５実施例における結合容量の等価回路を示す図。
【図１００】従来例を示すための図。
【図１０１】従来例を示すための図。
【符号の説明】
３０…着色層
３３…フォトダイオードアレイ基板
４４…オペアンプ
６６、１９３…クリアー機能付Ｄフリップフロップ
６７、６８、１８４，１８５、２３１、２３２…カウンター
７３〜７３、２３７〜２４０…フルアダー
８８、９６、１７５，１７８…コンパレータ
８７、９５…オペアンプ
ＤFA〜ＤFF…フォトダイオード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device having a pen input function, and more particularly to a pen input display device in which pen input means is improved.
[0002]
[Prior art]
With the development of an advanced information society in recent years, there has been a strong demand for higher performance, lighter and shorter size, and lower power consumption of devices (information devices) that input, store and display the information. Under such circumstances, many types of information devices are currently proposed and put into practical use. Among them, a pen input display device equipped with a pen input function is attracting attention as an information device that satisfies the above requirements.
[0003]
As a means for inputting handwritten characters and figures into a computer, a word processor, a portable information terminal device, etc., for example, a pen input display device using a resistive thin film tablet (reference: Toshiba review 1994 Vol. 49 No. 12, Nikkei BP flat panel display '93, Nikkei BP MATERIALS & TECHNOLOGY 93.8) and pen input display devices using electromagnetic induction tablets (reference: Toshiba review 1994 Vol. 49 No. 12, Nikkei BP flat panel display '93, Nikkei BP MATERIALS & TECHNOLOGY 93.8) Pen input display device using electrostatic coupling tablet (Reference: Toshiba review 1994 Vol. 49 No. 12, Nikkei BP flat panel display '93, Nikkei BP M TERIALS & TECHNOLOGY 93.8), and other pen input display devices such as reference documents (Japanese Patent Laid-Open Nos. 4-283819, 4-299727, 5-127823, 5-158880, and 4-343387). Kaihei 5-189126, JP-A-5-197487, JP-A 62-92021, JP-A 63-293623, Nikkei Computer '93 / 6, IPSJ Journal 1988 Vol. 29 No. 3 “Online using handwritten editing symbols” Text and graphic editing method ").
[0004]
With the development of the information society in recent years, the definition of a display device in a pen input display device has been increasing, and at the same time the pixel size has been reduced. In addition, the pen input display device is required to have more accurate and quick performance for inputting a large amount of information.
[0005]
Recently, pen input display devices in which a display device and a pen input device (tablet) are integrated have been proposed (Japanese Patent Laid-Open Nos. 54-24538, 6-295219, 6-314165, and 4-337824). ) The pen input method is becoming the mainstream because pen input can be performed without impairing the display capability of the display device, and active elements such as transistors and diodes are used as these display devices for higher quality display. An active matrix type display device is used.
[0006]
[Problems to be solved by the invention]
The conventional capacitance method can integrate a pen input device and a display device, which is advantageous for reducing the thickness, cost, and cost of information equipment. However, the detection error is caused by electromagnetic noise from the display device. When the electrode in the display device is miniaturized (as in the TFT-LCD, the gate line and the nib electrode are basically utilized. When the signal line is thin or when the electrode is miniaturized for high definition of the display device, the detection error becomes large.
[0007]
The resistive film method is advantageous for reducing the weight and cost of information equipment, but the pen coordinate detection accuracy is not so good.
[0008]
Although the electromagnetic induction method is advantageous for highly accurate pen input, a detection tablet must be provided behind the display device, and it is difficult to reduce the size and weight. In addition, an information device having a large screen display device ( (40 inches or more), it is difficult to improve detection accuracy due to the problem of alignment accuracy between the display device and the detection tablet.
[0009]
In addition, in a pen input display device using a high-definition display device, hand shake that occurs when a user performs pen input and erroneous input that occurs because the input surface for performing pen input is slippery unlike paper are more prominent. The high-definition display that the display device has cannot be performed, and erroneous input due to camera shake or the like becomes noticeable handwriting. As a technique for correcting these, there are, for example, a reference (JP-A-6-295219, JP-A-5-274081) and a method of thinning the pen tip of the detection pen in accordance with the definition of the display device, but the pixel size is relatively small. When the handwriting input speed is relatively fast in a pen input display device having a display device, the above method is not sufficient.
[0010]
In addition, since the pen input display device performs handwritten input many times on the same surface, it is basically desirable that the pen tip of the detection pen be round so as not to damage the input surface. The input surface of the input display device is damaged, and the protective sheet must be replaced several times. If the pixel size is 300 μm × 300 μm or less (especially 150 μm × 150 μm or less), more advanced correction is required. Basically, the above-described method cannot perform advanced correction for each pixel, and the handwriting is fine. More accurate correction cannot be performed during quick handwriting input.
[0011]
Accordingly, an object of the present invention is to provide a highly accurate detection coordinate (high space) for a pen input integrated display device having a large-screen display device or a high-definition display device and having the same pen input surface and display surface. The present invention is to provide a pen input device having both resolution), lightness, smallness, and high time resolution.
[0012]
It is another object of the present invention to provide a pen input device that can perform handwriting input that is more accurate and finer than a pen input display device and that can be performed with good-looking handwriting.
[0013]
A further object of the present invention is to provide a capacitive pen input display device that is resistant to electromagnetic noise and has a small detection error.
[0015]
[Means for Solving the Problems]
A pen input device and a display device according to the present invention are provided. 1 In the pen input integrated display device, the pen in the pen input device includes an optical sensor, and the amount of movement of the pen on the display device changes in accordance with the position change on the display device surface. It is characterized by comprising a movement amount detecting means for detecting the light transmittance of the surface by detecting it with the optical sensor. Therefore, the amount of movement of the pen in the pen input device on the display device can be detected based on the light transmittance of the surface that changes in response to a change in position on the surface of the display device.
[0016]
A pen input device and a display device according to the present invention are provided. 2 In the pen input integrated display device, the pen in the input device includes an optical sensor, and the amount of movement of the pen on the display device is determined by the light shielding unit disposed in the display device and the light of the opening. It is characterized by comprising a movement amount detecting means for detecting a transmittance difference by detecting it with an optical sensor. Therefore, the amount of movement of the pen in the pen input device on the display device can be detected based on the difference in light transmittance between the light shielding unit and the opening arranged in the display device.
[0017]
According to the first to third pen input integrated display devices of the present invention, there is no need to provide a coordinate detection tablet on the front or the back of the display device independently of the display device, and the display device and the coordinate detection device. Since the tablet can be formed on the same surface, the pen input integrated display device can be made lighter and thinner and the image quality can be improved. The larger the display device is a few inches or more, the more parts required for pen input. Therefore, the effect of reducing the weight and thickness according to the present invention is great.
[0018]
For example, the display device is effective when the diagonal is 12.1 inches XGA and the pixel pitch is 210 μm * 70 μm, or the display device is diagonal 40 inches and the pixel pitch is 630 μm * 210 μm. It is particularly effective for molds that are 5.5 inches diagonal or larger (more effective for diagonals 10 inches or more and even more effective for diagonals 20 inches or more).
[0019]
Further, since the movement amount of the pen on the display device is instantaneously detected directly from the display device by the optical sensor of the pen, coordinate detection with high time resolution is possible. Therefore, when writing small characters on the display device quickly in handwriting input (when the size of the display device is 1 and writing characters less than 1/10 in size, etc.) The present invention is effective, and the present invention is effective when handwritten input is performed at a speed of 80 dots / second or more). The present invention is very effective.
[0020]
In addition, the amount of movement of the pen on the display device in the X direction and the amount of movement of the pen on the display device in the Y direction can be detected based on different spatial optical characteristic differences inherent in the display device on the display device surface. It is possible to more accurately detect whether the pen has moved in the X direction or the Y direction.
[0021]
In addition, since the light receiving surface of the light sensor of the pen has different lengths in the X direction and the Y direction on the display device, the light sensor is easily affected by the spatial optical characteristic difference in one direction of the display device. Therefore, it is possible to more accurately detect whether the pen has moved in the X direction or the Y direction.
[0022]
In addition, since the coordinates where the pen is arranged on the display device are detected by using the change in luminance of the display device due to the push-up voltage generated in the pixel electrode when the Cs line and the signal line of the display device are sequentially selected and driven, the display is displayed. Since there is no need to provide an array substrate for coordinate detection independently of the array substrate in the device, the display device and the coordinate detection tablet can be formed on the same surface, making it possible to reduce the weight and thickness of the pen input integrated display device. Because the coordinates are detected by using the luminance change of the display device due to capacitive coupling, the desired voltage can be instantaneously applied to the pixel electrode, and the variation of the switching element that drives the pixel electrode is not affected, Accurate coordinate detection is possible.
[0023]
Further, since the detected coordinates can be adjusted, the detection error generated due to the temperature characteristic of the response speed of the display device can be adjusted, and more accurate coordinate detection can be performed.
[0024]
In addition, since the push-up voltage is generated by the Cs line after the switching element arranged for each pixel electrode of the display device is turned off, the influence of the luminance change of the display device caused by writing the signal line voltage to the pixel electrode at the time of coordinate detection is affected. Since it is not received, more accurate coordinate detection is possible.
[0025]
Further, since the push-up voltage is generated by the signal line after the Cs line is disconnected from the Cs line drive means, the push-up voltage generated can be maintained without being influenced by the Cs line drive means.
[0026]
Therefore, it is possible to obtain a pen input integrated display device that realizes high image quality, light weight, thin shape, high time resolution, and high accuracy coordinate detection.
[0027]
Furthermore, said 1st provided with the pen input device and display apparatus concerning this invention. Or second The pen input integrated display device includes a pen housing in which the pen in the pen input device is coupled to the housing via a buffer mechanism, and a light receiving surface of the light receiving portion. Is controlled to be parallel to the surface of the display device.
[0028]
A pen input device and a display device according to the present invention are also provided. 3 In the pen input integrated display device, the buffer mechanism is provided with a spring.
[0029]
A pen input device and a display device according to the present invention are also provided. 3 In the pen input integrated display device, the buffer mechanism includes a rubber.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Embodiments according to the present invention will be described below with reference to the drawings.
[0035]
FIG. 1 shows the configuration of a pen input display device according to the first embodiment. Reference numeral 1 shows drive signals VON, VOFF, VDD, control signals STV, CPV and outputs output signals VPSR, DX, DY, VYSTOP. It is a pen input device.
[0036]
8 is a signal line (S1 to Sn), gate line (G1 to Gm), Cs line (C1 to Cl), Cs capacity, and controlled by the gate line to write the signal line voltage to the Cs capacity and pixel capacity (not shown). This is an array substrate composed of TFTs, etc., and is a reference document (The Institute of Electronics, Information and Communication Engineers Journal C-II Vol. J76-C-II No5 pp. 177-183 “Technical Trends of a-Si TFT / LCD” Nikkei BP, flat panel displays 1994-1995, Nikkei BP, Nikkei Microdevices April 1991-July 1994). A counter electrode (not shown) is disposed opposite the array substrate 8, and a liquid crystal (not shown) is sandwiched between the counter electrode and the array substrate 8 to provide a pixel capacitance (not shown). Forming. As these references, there are (Nikkei BP: Flat panel display 1994-1995, Nikkei BP: Nikkei Microdevices April 1991-July 1994).
[0037]
Reference numeral 2 denotes a signal line drive unit that receives the drive voltages VDD and VCC, the control signals CPH and SHT, the digital data VD, and the reference voltage VR, and writes the signal line voltage to the signal line, which is described in References (H. Okada, et al., SID93 Digest, pp.11-pp.14, T. Furuhashi, et al., SID94 Digest, pp.359-pp.362, Toshiba Integrated Circuit Technical Document “Toshiba LCD Driver Controller LSI 1992-1995”).
[0038]
Reference numeral 3 denotes a gate line driving unit which receives the driving voltages VON and VOFF and the control signals CPV, STV and VYSTOP and writes the gate voltage to the gate line, which is described in Reference Document (K. Hyugaji, et al., SID91 Digest, pp. 543). pp. 546, Toshiba Integrated Circuit Technical Document “Toshiba LCD Driver Controller LSI 1992-1995”).
[0039]
A Cs line drive unit 9 receives the drive voltages VON and VOFF and the control signals CPV, STV, VYSTOP and VPSR and writes the Cs voltage to the Cs line.
[0040]
Reference numeral 4 denotes an X drive unit that receives the drive voltage VON, the control signals VYSTOP, VXSTOP, and CPV and writes the signal line voltage to the signal line.
[0041]
A control unit 7 receives the driving voltage VDD, the control signals VPSR and ICPH, the digital source data SVD, and the coordinate data DX and DY related to pen input, and outputs CPV, STV, CPH, STH, and VD. The control unit 7 receives coordinate data DX and DY indicating the coordinates of the pen input device from the pen input device 1, and the coordinates detected by the signal line driving unit 2 and the gate line driving unit 3 with the pen input device are stored on the array substrate 8. After processing the data so that it can be displayed, the output signal is sent to the signal line driver 2 and the gate line driver 3.
[0042]
SW1 to SWn are switches controlled by the exclusive OR circuit 120, and are turned off when the output of 120 is high level and turned on when low level.
[0043]
Here, the horizontal direction of the array substrate 8 is the X direction (Xup is the right direction as shown in FIG. 1 and Xdown is the left direction), and the Y direction is the top direction (shown in FIG. 1). The direction is Yup, and the downward direction is Ydown).
[0044]
FIG. 2 shows the outer shape of the pen input display device, where 1 is a pen input device, 10 is a display device, 11 is a backlight, and 12 is a connection cord. In this embodiment, an active matrix type liquid crystal display device, so-called TFT-LCD (reference document: Nikkei BP, flat panel display 1990-1995, Nikkei BP, Nikkei Microdevice, April 1991 issue) 1994 July).
[0045]
A cross-sectional view of the pen input device 1 is shown in FIG. In FIG. 3, 13 indicates a metal A, 14 indicates a metal B, and 15 indicates a pen tip. The pen tip 15 can be moved by a force applied to the pen tip 15. By adding, metal A13 and metal B14 contact. The nib 15 is composed of 16 glasses, 17 photodiode arrays, 18 carrier tapes, etc., and the glass prevents a strong force from being directly applied to the 17. The incoming light is converted into an electrical signal, and the carrier tape 18 sends the electrical signal obtained by the photodiode array 17 to 20 circuit boards via 19 connectors. Various electronic components 21 for detecting the position of the pen tip 15 on the display device are mounted on the circuit board 20. Reference numeral 22 denotes a body of a pen input device, which uses a light and durable plastic. The drive voltage (VON, VOFF, VDD), control signals (STV, CPV, SSTH, CCPH) and output signals (VPSR, DX, DY, VYSTOP) shown in FIG.
[0046]
In this embodiment, the coordinate detection is performed using the photodiode array 17, but in actuality, the 17 may be configured by a discrete photodiode, or may be configured by a discrete or array-like phototransistor. . A charge coupled device such as a CCD may be used.
[0047]
FIG. 4 shows how light is received by the pen input device. The prism sheet 23 collects light emitted from the backlight 11 (27 indicates a light path) in the vertical direction of the backlight 11. The brightness of the display device is highest when the display device is viewed vertically, and the light emitted from the backlight 11 passes through the 26 polarizing plates and the array substrate 8 to the 24 liquid crystal layers. The light is modulated into light having an intensity corresponding to the applied voltage value, and is received by the photodiode array 17 through 25 counter substrates.
[0048]
FIG. 5 shows the structure of the counter substrate 25. FIG. Is a cross-sectional view, FIG. Shows a top view. In addition, The cross-sectional view of FIG. 5A is the AA cross-sectional view of FIG. 28 is glass, 29 is a light shielding layer (black matrix), 30 is a colored layer colored red (R), blue (B), and green (G), 31 is an overcoat layer, 32 is The counter electrode is shown. References for the counter substrate 25 include (Nikkei BP "Flat Panel Displays 91-95").
[0049]
Further, the light shielding layer may be simply referred to as a light shielding portion, and the colored layer may be simply referred to as a display portion or an opening portion.
[0050]
FIG. 6 shows the structure of the photodiode array 17, which has A light receiving surface, B light receiving surface, C light receiving surface, D light receiving surface, E light receiving surface, and F light receiving surface on 33 photodiode array substrates. Light energy incident on the light receiving surface is converted into electrical energy between the terminals (Ak-Aa to Fk-Fa) and output. The subscript k indicates the cathode and a indicates the anode.
[0051]
7 and 8 show other structures of the photodiode array 17, and at the same time, the colored layer 30 of the counter substrate 25 is overlapped with a dotted line to show the size and the positional relationship between the light receiving surfaces.
[0052]
FIG. 9 shows an equivalent circuit of the photodiode array 17, and DFA to DFF are photodiodes corresponding to the light receiving surfaces A to F, respectively.
[0053]
FIG. 10 shows the configuration of the pen input device. Reference numeral 34 denotes an optical signal converter that converts the optical energy from the display device 10 into electrical signals VA to VF and outputs the drive voltages VON, VOFF, and VDD. is there. Therefore, an electrical signal corresponding to the intensity of the light energy incident on the optical signal converter 34 (more precisely, the light energy incident on the light receiving surface of each photodiode in the optical signal converter) is output. The optical signal conversion unit 34 includes optical signal conversion basic circuits (not shown, which will be described in detail later) corresponding to the outputs VA to VF.
[0054]
A pen system reset unit 35 determines whether or not the pen input display device is in a pen input state, and indicates a pen input state when VPSR = High level, and a non-pen input state when VPSR = Low level. Since the system of the pen input display device is reset by the pen system reset unit 35, it is possible to enter the pen input state only when the user desires, so that malfunction (eg, malfunction due to light energy other than the display device) ) Can be prevented.
[0055]
Reference numeral 36 denotes an initial coordinate detection unit which receives drive voltages VON, VOFF, VDD and control signals STV, CPV, VPSR, VB, and outputs initial coordinate data DX03 to DX00 (X direction), DY03 to DY00 (Y direction). . The initial coordinate data is the coordinate data of the pen tip 15 on the display device 10 when VPSR changes from the Low level to the High level. Further, in FIG. 10, the X direction and the Y direction are simple for 4-bit data. However, for example, in the case of a VGA display device, the initial coordinate data is 9 bits for the Y direction and 10 bits for the X direction.
[0056]
Reference numeral 37 denotes a movement amount detection unit for detecting the movement amount of the pen tip 15 on the display device 10, which receives the driving voltages VON, VOFF, VDD, control signals VPSR, VA to VF, and movement amount data DX13 to DX10, DY13 to DY10 is output. The number of bits of the movement amount data is as described in the initial coordinate data.
[0057]
Reference numeral 38 denotes an X coordinate detection unit which outputs coordinate data (X coordinate data) DX3 to DX0 in the X direction from the data obtained by 36 and the movement amount detection unit 37.
[0058]
Reference numeral 39 denotes a Y coordinate detection unit which outputs coordinate data (Y coordinate data) DY3 to DY0 in the Y direction from the data obtained by 36 and the movement amount detection unit 37. Note that the number of bits in the coordinate data is as described in the initial coordinate data.
[0059]
FIG. 11 shows the configuration and output waveform of the pen system reset unit. FIG. 11A shows the configuration of the pen system reset unit, which consists of 41 inverters using metal A13, metal B14, 40 resistors, and VDD as the drive voltage. FIG. 11B shows the VPSR output waveform obtained. When the metal A13 and the metal B14 are in contact, VPSR = VDD, and when the metal A13 and the metal B14 are not in contact, VPSR = GND.
[0060]
FIG. 12 shows a specific example of the optical signal conversion basic circuit 46 in the optical signal converter 34. Reference numeral 42 denotes a resistor, 43 denotes a capacitor, 44 denotes an operational amplifier, and 45 denotes a resistor. 46 converts the optical signal incident on the A light receiving surface of the photodiode DFA into an electrical signal VA and outputs the electrical signal. The actual optical signal conversion unit 34 has an optical signal conversion basic circuit having the same configuration as that shown in 46 for each photodiode (DFA to DFF) of the photodiode array 17, and the electric signals VA to VF are respectively received. Output.
[0061]
FIG. 13 shows the relationship between the characteristics of the photodiode and the basic optical signal conversion circuit. FIG. 13A shows the general characteristics of the photodiode, and FIG. 13B shows the photodiode having such characteristics. The operation of the optical signal conversion basic circuit 46 is shown (reference: Hamamatsu Photoelectronics Co., Ltd. “Photodiode Catalog”). The operational amplifier 44 preferably has rail-to-rail characteristics and can output up to VOFF.
[0062]
As is clear from FIG. 13A, when a light with high illuminance is incident on the light receiving surface of the photodiode (here, for the sake of simplicity, the spectral wavelength characteristic of the photodiode is ignored), a larger output current is obtained. As apparent from the operation of the optical signal conversion basic circuit 46 shown in FIG. 12, most of the current flowing through the photodiode flows through the resistor 45 because of the low bias current characteristic and virtual short characteristic of the operational amplifier 44. Also, because of the virtual short characteristic of the operational amplifier 44, the inverting input terminal of the operational amplifier 44 is 0v, the output voltage is R44 as the resistance value of the resistor 45, and the current flowing through the photodiode is ID.
-R44 * ID [v]
It becomes. Therefore, the characteristics shown in FIG. 13B are obtained.
[0063]
FIG. 14 shows a configuration of the movement amount detection unit 37. The movement amount detection unit 37 includes a Y direction movement amount detection unit 47 and an X direction movement amount detection unit 48. The Y direction movement amount detection unit 47 determines the Y direction movement amount of the pen tip 15 on the display device 10 as VA and VB. , VC, and VPSR and output as DY13 to DY10 parallel signals (in this example, 4 bits, but the number of bits is as described in the initial coordinate data).
[0064]
48 detects the amount of movement of the pen tip 15 on the display device 10 in the X direction from VD, VE, VF, and VPSR, and DX13 to DX10 parallel signals (in this example, 4 bits are used, but the number of bits is the initial coordinate data. Output as described). For example, when the pen tip 15 moves by three gate lines, (DY13, DY12, DY11, DY10) = (0, 0, 1, 1) is output, and when the pen tip 15 moves by nine signal lines, DX13, DX12, DX11, DX10) = (0, 0, 1, 1) is output (in this embodiment, each RGB, R, G, B colored layer forms one RGB pixel, so the output is 0, 0, 1, 1).
[0065]
Further, in the TFT-LCD, each colored layer shown in FIG. 5 is usually called 1 dot, and each continuous RGB is made up of 3 dots for a total of 3 dots, but in this embodiment, 1 dot is called 1 pixel, One pixel is called an RGB pixel.
[0066]
FIG. 15 shows a configuration of the Y-direction movement amount detection unit 47, and the Y-direction movement amount detection unit 47 includes a level shift unit 49, a serial signal generation unit 50, and a parallel signal generation unit 51. 49 converts VA, VB, VC into digital data VAO, VBO, VCO at a level that is easy to handle. The serial signal generator 50 receives VAO, VBO, VCO and receives a VYup signal indicating the amount of movement in the Yup direction and a Ydown direction. The parallel signal generator 51 receives the VYup and VYdown signals and outputs parallel signals DY13, DY12, DY11, and DY10 indicating the amount of movement in the Y direction. Note that DY13, DY12, DY11, and DY10 are shown in complement.
[0067]
The configuration of the X-direction movement amount detection unit 48 is the same as that of the Y-direction movement amount detection unit 47 (however, VA, VB, VC, VAO, VBO, VCO, VYup, VYdown, DY13, DY12, DY11, DY10 are each VD. , VE, VF, VDO, VOEO, VFO, VXup, VXdown, DX13, DX12, DX11, DX10).
[0068]
FIG. 16 shows the configuration of the level shift unit 49, 52, 53 and 54 are comparators, 55 is a variable resistor and VON and VOFF are made from VREF1, and 56, 57 and 58 are N channel MOS transistors. Yes, 59, 60 and 61 are resistors, and 62 is an inverter.
[0069]
FIG. 17 shows an operation example of the level shift unit 49. VA, VB, and VC are analog signals corresponding to light energy incident on DFA, DFB, and DFC, and have amplitudes of VOFF to GND. The comparators 52, 53, 54 compare VA, VB, VC and VREF1, and output VON when VA, VB, VC> VREF1, and VOFF when VA, VB, VC <VREF1. Therefore, when VA, VB, and VC in FIG. 17 are input, the outputs of the comparators 52, 53, and 54 shown in FIG. 17 are obtained, and the MOS transistors 56, 57, and 58 operate as source followers. 17 VAO, VBO and VCO are obtained.
[0070]
The level shift unit in the X-direction movement amount detection unit 48 has the same configuration as that of the level shift unit 49 shown in FIG. 16 (however, VA, VB, VC, VAO, VBO, VCO are VD, VE, VF, VDO, VEO, VFO).
[0071]
FIG. 18 shows the configuration of the serial signal generation unit 50 in the Y-direction movement amount detection unit. SW01 and SW02 are switches controlled by the output signal Q of 66, and both SW01 and SW02 are off when Q = High level. When Q = Low level, SW01 and SW02 are both on. 63 and 64 are resistors, 65 is an OR circuit, and 66 is a D flip-flop with a clear function. Specific examples of the D flip-flop 66 include TC74HC74AP.
[0072]
FIG. 19 shows the configuration of the serial signal generation unit in the X-direction movement amount detection unit. SW03 and SW04 are switches controlled by the output signal Q of 193. When Q = High level, both SW03 and SW04 are off. When Q = Low level, both SW03 and SW04 are on. Reference numerals 190 and 191 denote resistors, 192 denotes an OR circuit, and 193 denotes a D flip-flop with a clear function. Specific examples of 193 include TC74HC74AP.
[0073]
Reference numeral 194 denotes a circuit of a pulse third, which is a circuit that operates as shown in FIG. The configuration and operation of the serial signal generation unit in the X-direction movement amount detection unit is the same as that of the serial signal generation unit 50 in the Y-direction movement amount detection unit, but the serial signal generation in the X-direction movement amount detection unit. There is a 1/3 pulse circuit 194 in the part.
[0074]
FIG. 20 shows an operation example of the pulse 1/3 circuit 194. The pulse one-third circuit 194 receives the input signals VXup and VXdown and outputs the output signals VXup3 and VXdown3, and outputs VXup3 for every three VXup pulses as shown in FIG. 20 (however, VXup pulse If a VXdown pulse is input before 3 pulses, subtract the number of VXdown pulses from the number of VXup pulses). Also, VXdown3 is output as one pulse every three VXdown pulses as shown in FIG. 20 (however, if the VXup pulse is input before the VXdown pulse becomes 3 pulses, the number of VXup pulses is subtracted from the number of VXdown pulses). . However, in the pulse 1/3 circuit 194, the pulse count method of VXup and VXdown is reset when the number of pulses is 3, and the count of the number of pulses is 0.
[0075]
FIG. 21 shows an operation example of the serial signal generation circuit unit 50. Note that tdelay 1 is a time until the output of the OR circuit 65 becomes High level, the output Q of the D flip-flop becomes High level, the SW01 and SW02 are turned off, and VYdown (or VYup) becomes Low level. .
[0076]
When the output Q of the D flip-flop 66 is High, SW01 and SW02 are off, so that GND (in this case, Low level) is supplied to VYup and VYdown through resistors 63 and 64. When VBO becomes Low, the D flip-flop 66 is cleared (Reference: Toshiba Integrated Circuit Technical Document “High Speed C2MOS TC74HC Series 1992”) Q becomes Low and SW01 and SW02 are turned on. Next, when High is input to either VAO or VCO, the output of the OR circuit 65 also becomes High, and the output Q of the D flip-flop 66 also becomes High. As a result, SW01 and SW02 are turned off, so that VYup and VYdown are Become Low.
[0077]
FIG. 22 shows the configuration of the parallel signal generation unit 51 in the Y direction movement amount detection unit, 67 and 68 are counters (for example, TC74HC161AP), 69, 70, 71 and 72 are inverters, and 220 is an AND circuit. 73, 74, 75, and 76 are full adder circuits (reference: CQ publisher, Kunio Ukai / Chuo Honda), digital system design), and FIG. 24 shows a configuration example and a Carnot diagram of the full adder circuit.
[0078]
In FIG. 24, 77 is an exclusive OR circuit, 78, 79 and 80 are NAND circuits, and 81 is a negative logic input OR circuit.
[0079]
FIG. 22 shows a configuration of a subtracting circuit that subtracts the number of VYup pulses from the number of VYdown pulses using a complement.
[0080]
FIG. 25 shows an operation example of the parallel signal generator 51 of FIG. In the parallel signal generator 51, if both VPSR and VXSTOP (described later) are not at a high level, the output of 220 is at a low level, and therefore the outputs of the counters 67 and 68 are all at a low level. Therefore, DY13, DY12, DY11, and DY10 are all “Low” regardless of how VYup and VYdown change.
[0081]
In this embodiment, as described above, the movement amount is detected only when both VPSR and VXSTOP are at the High level (that is, the movement amount can be detected only when the pen input state and the initial coordinate data are detected). Therefore, it is possible to prevent a malfunction of the pen input device (unintended information is input, or the initial coordinate data cannot be detected, and only the movement amount is output to an unintended location).
[0082]
When both VPSR and VXSTOP are at a high level, counters 67 and 68 output counts corresponding to the number of pulses of VYup and VYdown, respectively, and values calculated using complements are output from full adders 73, 74, 75, and 76. (DY13, DY12, DY11, DY10).
[0083]
FIG. 23 shows the configuration of the parallel signal generation unit in the X direction movement amount detection unit, 231 and 232 are counters (for example, TC74HC161AP), 233, 234, 235 and 236 are inverters, and 230 is an AND circuit. Reference numerals 237, 238, 239, and 240 denote full adder circuits (reference: CQ Publishing Co., Kunio Ukai / Takaji Honda), digital system design).
[0084]
The parallel signal generation unit in the X-direction movement amount detection unit in FIG. 23 has a configuration of a subtracting circuit that subtracts the number of VXdown3 pulses from the number of VXup3 pulses using a complement. This is the same as the parallel signal generator 51 in the detector.
[0085]
FIG. 26 shows the configuration of the initial coordinate detector 36 of FIG. The initial coordinate detection unit 36 includes an X-direction initial coordinate detection unit 82 that detects initial coordinates in the X direction and a Y-direction initial coordinate detection unit 83 that detects initial coordinates in the Y direction.
[0086]
FIG. 27 shows the configuration of the Y-direction initial coordinate detection unit 83.
[0087]
In FIG. 27, 84, 92, 85, and 93 are capacitors, and SW12 and SW13 are switches controlled by VPSR, which are turned off when VPSR is High and turned on when VPSR is Low. 86 and 94 are diodes, 87 and 95 are operational amplifiers, 88 and 96 are comparators, 89 and 97 are variable resistors that create VREF2 and VREF3 from VON and VOFF, respectively, 90 and 98 are P-channel MOS transistors, 91, 99 is an N-channel MOS transistor, 100 is an OR circuit, and 114 is a D flip-flop with a clear function (example: TC74HC74AP). 101 is an inverter, 102 is an OR circuit, 103 is an inverter, 104 is a counter (example: TC74HC161), and 105, 106, 107, and 108 are full adder circuits shown in FIG.
[0088]
The operation of the components shown in FIG. 27 will be briefly described. Capacitors 84 and 85 and a diode 86 form a clip circuit that cuts the voltage change on the high voltage side of VB. The forward voltage of the diode 86 is a Schottky barrier diode. If the voltage is low (ideally 0V in this case), the operation is performed so that a voltage change of 0V or more is not input to the operational amplifier 87, and VB- is generated from VB (and the capacitance value of 84 capacitors is 85 capacitors) Desirably larger than the capacity value). Reference numeral 87 denotes a voltage follower that impedance-converts an input signal and outputs it. 88 operates as a comparator and outputs VON when VB-> VREF2 and VOFF when VB- <VREF2. Reference numerals 90 and 91 operate as a level shift circuit, and convert the output of the comparator 88 into a signal of 0V to VDD.
[0089]
A clip circuit that cuts the voltage change on the low voltage side of VB is formed by the capacitors 92 and 93 and the diode 94. If the forward voltage of the diode 94 is as low as a Schottky barrier diode (in this case, ideally 0V) A voltage change of 0 V or less is not input to the operational amplifier 95 to create VB + from VB (and the capacitance value of 92 capacitors is preferably sufficiently larger than the capacitance value of 93 capacitors). Reference numeral 95 is a voltage follower that impedance-converts the input signal and outputs it. 96 operates as a comparator and outputs VOFF when VB +> VREF3 and VON when VB + <VREF3. 98 and 99 operate as a level shift circuit, and convert the output of the comparator 96 into a signal of 0V to VDD.
[0090]
The D flip-flop 114 outputs High at the rising edge of CLK, and then maintains VYSTOP = High until VPSR becomes Low.
[0091]
104 operates as a counter. When ENP = Low, the counter operation is stopped, and when Low is input to the clear terminal, the output is set to Low. For the operation of the counter 104, there is a reference document (Toshiba Integrated Circuit Technical Document “High Speed C2MOS TC74HC Series 1992”).
[0092]
105, 106, 107, and 108 operate as full adder circuits (a specific circuit configuration and a Carnot diagram are shown in FIG. 24. Reference: CQ Publishing Co., Ltd., Kunio Ukai / Chuo Honda), Digital System Design) DYa3, DYa2, DYa1, DYa0 are added to the output of the counter 104. DYa3, DYa2, DYa1, and DYa0 are for determining the initial state of DY03, DY02, DY01, and DY00. The temperature characteristics of the array substrate 8, pen input device 1, display device 10, and liquid crystal layer 24 are shown in FIG. 1 is a signal for the user who uses the pen input device of FIG. 1 to arbitrarily set and adjust when there is an error in the Y-direction initial coordinate detection by 83, and a High / Low signal by a switch (not shown) or the like. Enter. In addition, this signal may be adjusted, input and fixed when the product is completed, which basically improves the coordinate detection accuracy of the pen input device. In practice, this causes errors due to individual differences and temperature characteristics of the pen input device. Can be suppressed.
[0093]
Reference numeral 270 denotes a rising edge detection circuit. As shown in FIG. 29, the output becomes High immediately after the rising edge of STV, but then becomes Low immediately. Note that STV is a line synchronization signal, and CPV is a pixel synchronization signal.
[0094]
The operation of the Y-direction initial coordinate detection unit 83 is shown in FIG.
[0095]
When the system reset VPSR = High in FIG. 11, SW12 and SW13 are off, and when VPSR = Low, SW12 and SW13 are on. When SW12 and SW13 are on, VB + and VB- are GND (the forward voltages of 86 and 93 are ideally set to 0 V). When VREF2 and VREF3 are set as shown in FIG. Becomes VON, and the output of the OR circuit 100 becomes Low. Since VPSR = Low, VYSOTP is Low. At this time, since ENP = High, the counter 104 counts. Thereafter, VPSR = High, SW12 and SW13 are turned off, and when the voltage change occurs in VB and the outputs of the operational amplifiers 87 and 95 as shown in FIG. 28 are obtained, the output of the OR circuit 100 becomes VB− <VREF2. Is changed from Low to High, so VYSTOP = High and ENP = Low, so the count operation of the counter 104 is stopped and the count number counted at the tcount time is held and output to the full adders 105, 106, 107 and 108. . The full adders 105, 106, 107 and 108 add DYa3, DYa2, DYa1 and DYa0 to the output of the counter 104 and output the result as DY03, DY02, DY01 and DY00.
[0096]
As apparent from the operation of the counter 104, when STV = High when VYSTOP = Low, the output of the counter 104 is cleared and all become Low.
[0097]
1 CPV period corresponds to a time difference until VON is applied to the Cs line in the adjacent Cs line when the Cs line driving unit 9 of FIG. 1 is operating (VPSR = High, VYSTOP = Low). 27, when the STV 104 is reset, the circuit shown in FIG. 27 indicates which Cs line was scanned by the counter 104 when the Cs line driving unit 9 became VYSTOP = High. Detect by counting. That is, when VYSTOP = High (DY03, DY02, DY01, DY00) = (0, 0, 1, 1), when VYSTOP = High, the gate line driving unit 3 sets the third gate line. This means that they have been driven (however, DYa 3, DYa 2, DYa 1, DYa 0 are low level “0”).
[0098]
FIG. 30 shows the configuration of the X drive unit 4 of FIG. 1. SWX1, SWX2, and SWX3 are switches controlled by an AND circuit 350. When the output of 350 is high, the switch is on. When the output of 350 is low, the switch is off. is there.
[0099]
SWX4, SWX5, and SWX6 are switches controlled by a D flip-flop with a clear function (for example, TC74HC74AP) 115, which is on when the output Q of the D flip-flop 115 is High and off when the output Q of the D flip-flop 115 is Low. is there.
[0100]
SWX7, SWX8 (not shown), SWX9 (not shown) are switches controlled by a D flip-flop with a clear function (eg, TC74HC74AP) 116. When the output Q of 116 is High, the output Q of 116 is Low. Is off.
SWXn-2, SWXn-1, and SWXn are switches controlled by a D flip-flop with a clear function (for example, TC74HC74AP) 117. The switch is turned on when the output Q of 117 is High, and is turned off when the output Q of D flip-flop 117 is Low. It is.
[0101]
Switches SWX8 to SWXn-3 (not shown) controlled by a D flip-flop with a clear function (not shown) similar to the D flip-flop 115 are provided between SWX7 and SWXn-2. Control is performed in the same manner as the switch shown in FIG. That is, the three switches are controlled by the same D flip-flop with a clear function. Therefore, there are D flip-flops with a clear function, which is the number of switches SWX8 to SWXn-3 divided by three. 118 and an AND circuit 350 are AND circuits, and 119 is an inverter circuit.
[0102]
FIG. 31 shows an operation example of the X drive unit 4. As is apparent from the operations of the exclusive OR circuit 120 (see FIG. 1), the AND circuit 118, the inverter 119, and the AND circuit 350, when VYSOTP = VXSTOP, the output of the exclusive OR circuit 120 is Low and SW1 to SWn are on. However, when VYSOTP ≠ VXSTOP, the output of the exclusive OR circuit 120 is High and SW1 to SWn are turned off.
[0103]
SWX1 to SWXn are selectively turned on when VYSOTP = High and VXSTOP = Low and VPSR = High, but are all turned off when VXSTOP = High or VPSR = Low. Therefore, when SW1 to SWn are turned on and SWX1 to SWXn are turned off, the signal line voltage corresponding to the output of 2 is written to the signal line (S1-Sn).
[0104]
When SW1 to SWn are turned off and SWX1 to SWXn are selectively turned on, VON is written to the selected signal line (S1-Sn) according to the CPV timing. Further, as shown in FIG. 31, VON is written to the three signal lines at the same timing. (Example: VON is written to S1, S2 and S3 at the same timing) In FIG. 31, Sn means a signal line voltage applied to the signal line Sn.
[0105]
FIG. 32 shows the configuration of the X-direction initial coordinate detection unit 82 of FIG. In FIG. 32, 121, 122, 123, and 124 are capacitors, and SW14 and SW15 are switches controlled by VYSTOP, which are turned off when VYSTOP = High and turned on when VYSTOP = Low. 125 and 126 are diodes, 127 and 128 are operational amplifiers, 129, 130 are comparators, 131 and 132 are variable resistors that create VREF4 and VREF5 from VON and VOFF, respectively, 133 and 135 are 134 P-channel MOS transistors, 136 is an N channel MOS transistor, 137 is an OR circuit, and 138 is a D flip-flop with a clear function (example: TC74HC74AP). 140 is an inverter, 139 is an OR circuit, 141 is a counter (example: TC74HC161), and 142, 143, 144, and 145 are full adder circuits shown in FIG.
[0106]
32 briefly describes the operation of each of the components shown in FIG. 32. Capacitors 121 and 123 and a diode 125 form a clip circuit that cuts the voltage change on the high voltage side of VB. The forward voltage of the diode 125 is a Schottky barrier diode. If it is low (ideally 0V in this case), the operation is performed so that a voltage change of 0V or more is not input to the operational amplifier 127, and VBX- is generated from VB (and the capacitance value of the capacitor of 121 is that of the capacitor of 123 Desirably larger than the capacity value). The operational amplifier 127 is a voltage follower, and impedance-converts the input signal and outputs it.
[0107]
129 operates as a comparator and outputs VON when VBX-> VREF4 and VOFF when VBX- <VREF4. Reference numerals 133 and 134 operate as level shift circuits, and convert the output of the comparator 129 into a signal of 0V to VDD.
[0108]
A clip circuit that cuts the voltage change on the low voltage side of VB is formed by the capacitors 122 and 124 and the diode 126. If the forward voltage of the diode 126 is as low as a Schottky barrier diode (in this case, ideally 0V) A voltage change of 0 V or less is not input to the operational amplifier 128 to create VBX + from VB (and the capacitance value of the 122 capacitor is preferably sufficiently larger than the capacitance value of the 124 capacitor). Reference numeral 128 denotes a voltage follower that impedance-converts an input signal and outputs it.
[0109]
130 operates as a comparator and outputs VOFF when VBX +> VREF5 and VON when VBX + <VREF5. Reference numerals 135 and 136 operate as level shift circuits, and convert the output of the comparator 130 into a signal of 0V to VDD. The D flip-flop 138 outputs High at the rising edge of CLK, and then maintains VXSTOP = High until VPSR becomes Low.
[0110]
141 operates as a counter (for example, 74HC161). When ENP = Low, the counter operation is stopped. When Low is input to the clear terminal, the output is set to Low. For the operation of the counter 141, there is a reference document (Toshiba Integrated Circuit Technical Document “High Speed C2MOS TC74HC Series 1992”). Reference numerals 142, 143, 144, and 145 operate as full adder circuits (adder circuits) (see FIG. 24, reference: CQ publisher, Kunio Hikai / Chuo Honda), digital system design). DXa3, DXa2, DXa1, and DXa0 are added to the output. DXa3, DXa2, DXa1, and DXa0 are used to determine the initial state of DX03, DX02, DX01, and DX00, and are initially in the X direction because of the temperature characteristics of the array substrate 8, pen input device 1, display device 10, and liquid crystal layer 24. This is a signal for the user who uses the pen input device of FIG. 1 to arbitrarily set and adjust when an error occurs in the X-direction initial coordinate detection by the coordinate detection unit 82, and is set to High by a switch (not shown) or the like. A Low signal is input. In addition, this signal may be adjusted, input and fixed when the product is completed, and basically improves the coordinate detection accuracy of the pen input device. In practice, this can suppress errors due to individual differences and temperature characteristics. .
[0111]
FIG. 33 shows the operation of the X-direction initial coordinate detector 82. The output of the operational amplifier 127 <VREF4, the comparator 129 outputs VOFF, the output of the OR circuit 137 changes from 0V to VDD, and the output VXSTOP of the D flip-flop 138. Becomes High. Then, ENP of the counter 141 becomes Low, and the counting operation of the counter 141 is stopped. Accordingly, the counter 141 counts until VYSTOP = High and VXSTOP = High, and then maintains that value until VPSR = Low. The basic operation and basic configuration of the X direction initial coordinate detection unit are the same as those of the Y direction initial coordinate detection unit.
[0112]
FIG. 34 shows the configuration of the Y coordinate detection unit 39 of FIG. In FIG. 34, reference numerals 109, 110, 111, and 112 denote full adder circuits as shown in FIG. 24, which constitute an adder circuit, add DY13-DY10 to DY03-DY00, and DY3, DY2, DY1, DY0 is output.
[0113]
DY3, DY2, DY1, and DY0 indicate the positions of the pen tip 15 on the display device 10, and if (DY3, DY2, DY1, DY0) = (0, 0, 1, 1), they are controlled by the Cs line C3. The pen tip 15 is arranged on the pixel electrode (on the pixel electrode controlled by the TFT controlled by the gate line G3), and (DY3, DY2, DY1, DY0) = (0, 1, 1, 1) Then, it shows that the pen tip 15 is arranged on the pixel electrode controlled by the Cs line C7 (on the pixel electrode controlled by the TFT controlled by the gate line G7).
[0114]
The configuration of the X coordinate detection unit is the same as the configuration of the Y coordinate detection unit shown in FIG. 34 (however, DY03-DY00, DY13-DY10, DY3, DY2, DY1, DY0 are replaced with DX03-DX00, DX13-DX10). , DX3, DX2, DX2, DX0).
[0115]
FIG. 35 shows the configuration of the Cs line drive unit 9 of FIG. 146 in FIG. 35 is a delay circuit that delays and outputs the VYSTOP signal by tcs. SWZ1 to SWZl are switches controlled by VYSTOP, which are turned on when VYSTOP = Low and turned off when VYSTOP = High, but the delay circuit 146 is turned on. Therefore, even if VYSTOP changes from Low to High, it does not turn off immediately but turns off after tcs.
[0116]
Reference numeral 147 denotes an exclusive OR circuit, and reference numeral 148 denotes a pulse width modulation circuit. The pulse width of the STV is modulated to an arbitrary width as shown in FIG. 37, and the pulse width can be arbitrarily set. . Reference numerals 149, 150, 151, and 152 are D flip-flops with a clear function (for example, operate like TC74HC74AP), but not all are shown, but in reality, this is the number of Cs lines. The level shift circuit outputs VON when High is input from each flip-flop with a clear function, and outputs VOFF when Low is input.
[0117]
FIG. 36 shows an operation of the Cs line driving unit shown in FIG. When VYSTOP = Low and VPSR = High, the output of the exclusive OR 147 becomes High. Therefore, 149, 150, 151, and 152 are the same as the other D flip-flops with clear function (not shown). The input data is output in synchronization with and the output is held until the rising edge of CPV is input again. Therefore, when CPV and STV in FIG. 36 are input, VC1, VC2 and VC3 in FIG. 36 are output (VC1 is the same for other VC2 to VCl which means a voltage output from the Cs drive unit and applied to C1. is there). Note that 148 modulates the pulse width twice, and when VYSTOP = High when VPSR = High, the output of the exclusive OR 147 becomes Low, so the output of the Cs drive unit (VC1 to VCl) is completely at one end. After that, VZ is turned off, and SWZ1 to SWZl are turned off with a delay of tcs, and the output is set to a high impedance state. Therefore, no voltage is directly supplied to the Cs lines (Cs1 to Csl). Note that the pulse width modulation by 148 is changed according to the response speed of the liquid crystal layer 24 (the time from the application of voltage to the change in optical characteristics indicates the time from 10% to 90% of the normal luminance change). It is desirable to increase the pulse width when the response time is long, and shorten the pulse width when the response time is short.
[0118]
FIG. 38 shows the operation of the gate line driving unit 3 of FIG. When VPSR = High and VXSTOP = Low, the gate line driver 3 once writes VOFF to the gate lines (G1-Gm) so that all TFTs on the array substrate 8 are turned off. During other periods, normal operation is performed, and G1, G2, G3... (Here, meaning voltages written to the gate lines G1, G2, G3...) Are output at the timings of CPV and STV as shown in FIG.
[0119]
FIG. 39 shows an example of the operation of the signal line driver 2 shown in FIG. In this embodiment, the counter electrode voltage applied to the counter electrode 32 is GND (which can be adjusted according to display characteristics, but a DC voltage is applied to the counter electrode 32), and the signal line voltage of the signal line is When the potential is higher than GND, the polarity is positive, and when the signal line voltage of the signal line is lower than GND, the polarity is negative. 2 is for n-1 frame and n + 1 frame (or n-1 line and n + 1 line). ), A negative signal line voltage is written to odd-numbered signal lines (S1, S3, S5,... Sn-1), and a positive signal is applied to even-numbered signal lines (S2, S4, S6,... Sn). Write the line voltage. Further, the positive signal line voltage is written to the odd-numbered signal lines (S1, S3, S5,... Sn-1) at the time of n frames (or at the n-line), and the even-numbered signal lines (S2, S4, S6). ,... Sn is written with a negative signal line voltage.
[0120]
When the polarity switching described above is performed for each frame, it is called signal line inversion drive or power supply level shift drive (reference: Tsuchida et al., ITE '94 "Realization of signal line inversion drive by 5V driver IC"). Is called dot inversion driving. As a reference for these driving methods (Nikkei BP, flat panel display 1994-1995, Nikkei BP, Nikkei Microdevice June 1992, Ikeda, N et al., 1992, Society For Information Display 1992 International Symposium, lecture number 5.6, May 1992).
[0121]
The actual operation of the pen input display device according to the present invention will be described below. In the following description, VDD = 5V and VCC = -5V unless otherwise specified.
[0122]
FIG. 40 shows the position of the pen tip 15 on the display device 10 at t = t1.
[0123]
In FIG. 40, A, B, C, D, E, and F are the A light receiving surface, B light receiving surface, C light receiving surface, D light receiving surface, E light receiving surface, and F light receiving surface of the photodiode array 17, respectively. S1, S2, S3... Are signal lines, and G1, G2, G3. The black matrix 29 of FIG. 5 is arranged on the signal line and the gate line (in FIG. 40, the black matrix 29 and the signal line or gate line are shown as the same line in order to avoid complicating the drawing. When the gate line functions as a black matrix (reference: T. Ueda et al. SID93Digest 739-742) or when the black matrix 29 is present on the array substrate 8 (reference: Nikkei BP, flat panel display) 1990-1995, Nikkei BP, Nikkei Microdevices April 1991-July 1994) can be handled in the same way.For details of the black matrix 29, reference literature (Nikkei BP, flat panel) Display 1994-1995, Nikkei BP, Nikkei Lee black device 1991 April - July 1994), and the like.
[0124]
G1S1 in FIG. 40 indicates a pixel electrode surface (pixel electrode) connected to the TFT controlled by G1 and S1, and the liquid crystal layer 24 and the colored layer are formed on the pixel electrode as shown in FIGS. 30 (reference documents: Nikkei BP, flat panel displays 1994-1995, Nikkei BP, Nikkei Microdevices April 1991-July 1994). G1S2 and G2S1 are the same as G1S1, and the other pixel electrode surfaces are also the same (for example, G3S4 below D).
[0125]
Further, the colored layer 30 has three types of an R colored layer, a G colored layer, and a B colored layer, and the R colored layer is formed on the pixel electrode surface connected to the TFT controlled by S1, S4, S7,. A G colored layer is formed on the surface of the pixel electrode connected to the TFT controlled by S2, S5, S8..., And a B colored layer is formed on the pixel electrode surface connected to the TFT controlled by S3, S6, S9. Are arranged, and the colored layers are also arranged in this order on the other pixel electrode surfaces.
[0126]
FIG. 41 shows the timing of the pixel electrode voltage when VPSR is High, all the outputs of the gate line driving unit 3 are VOFF, and the Cs line driving unit 9 is operating. The timing of CPV and VC3 is as shown in FIG.
[0127]
VPG3S4 is a voltage written in G3S4, VPG3S6 is a voltage written in G3S6, and VPG3S5 is a voltage written in G3S5.
[0128]
At t = t1, VDD is applied to G3S4, GND is applied to G3S6, GND is applied to G3S5, and VCC is applied to G3S5. Since the counter electrode voltage is GND, the VT characteristics of the display characteristics shown in FIG. BP, flat panel display 1990-1995, Nikkei BP, Nikkei Microdevice June 1992 issue), G3S4 displays black in G3S5 and black in G3S6 (display device is normally white) ). A push-up voltage is generated in each pixel voltage at t = t2, which will be described below.
[0129]
43 shows a pixel capacity model on the array substrate 8 in this embodiment (reference: Suzuki et al., Television Society Journal, Vol. 47, No. 5, pp 649-655, Tomita et al., EID 91-120 pp29). -Pp34, Nikkei BP, flat panel display 1990-1995).
[0130]
43, G3 is the gate line of FIG. 40, S6 is the signal line of FIG. 40, C3 is the Cs line of FIG. 40, Csig, g is the coupling capacitance of the signal line and gate line in one pixel, Cgs is the coupling capacitance between the TFT gate and the pixel electrode, CLC is the liquid crystal capacitance between the counter electrode 25 and the pixel electrode in one pixel, Cs is the coupling capacitance (auxiliary capacitance) between the pixel electrode and the Cs line, and Cg , Com are the coupling capacitance between the gate line and the counter electrode 25 in one pixel, Cp and sig are the coupling capacitance between the signal line and the pixel electrode G3S6 in one pixel, and Csig and cs are the signal line and the Cs line in one pixel. Each coupling capacity is shown.
[0131]
The pixel capacity of the display device 10 according to the present embodiment can be expressed by the pixel capacity model shown in FIG.
[0132]
In such a pixel capacity model, if G3 = VOFF, VPG3S6 = 0V, S6 = 0V, and C3 = VOFF at t = t1, the charge QG3S6 (t1) stored in G3S6 ignores the effects of Cp and sig. Then
QG3S6 (t1) = − VOFF * (Cs + Cgs) [C] (1). When t = t2, G3 = VOFF, C3 = VON, VPG3S6 = VPG3S6 (t2), and S6 = 0V. The charge QG3S6 (t2) stored in G3S6 is

However, VPG3S6 (t2) is the potential of G3S6 at t = t2. Also, because the TFT is off
QG3S6 (t1) = QG3S6 (t2) (3), and calculating equations (1), (2) and (3),

Thus, VPG3S6 (t2) expressed by the equation (4) is obtained. As specific numerical values, when VON = 25V, VOFF = −10V, Cs = 0.5PF, Cgs = 0.02PF, CLC = 0.3PF,
VPG3S6 (t2) = 21.34V (5)
It becomes. However, the numbers after the decimal point are rounded off.
[0133]
Therefore, it was shown that VPG3S6 changes from 0V to 21.34V (VPG3S4 changes from 5V to 26.34V, VPG3S5 changes from -5 to 16.34V). This change in VPG3S6 is called a push-up voltage (here, it is a push-up voltage by the Cs line). Here, the push-up voltage generated when C3 changes from VOFF to VON is 21.34V.
[0134]
FIG. 44 shows the relative output of the backlight 11 and the transmittance characteristics of each colored layer 30 and the light receiving sensitivity characteristics of the photodiodes (DFA, DFB, DFC, DFD, DFE, DFF) of the photodiode array 17 according to this embodiment. Show.
[0135]
44A shows the relative output of the backlight 11, the horizontal axis indicates the wavelength, the vertical axis indicates the relative output normalized to 100% of the maximum output, and the wavelengths 430 nm to 440 nm, 540 nm to 550 nm, and 610 nm. The maximum relative output of 100% is output equally at ˜620 nm, but the relative output is not output at 0% in other bands.
[0136]
FIG. 44B shows the transmittance characteristics of each colored layer, with the horizontal axis indicating the wavelength and the vertical axis indicating the relative transmittance normalized to 100% of the maximum transmittance. In the B colored layer, the transmittance is 100% at a wavelength of 400 nm to 500 nm, and 0% in other bands. The G colored layer has a transmittance of 100% at a wavelength of 500 nm to 600 nm and 0% in other bands. In the R colored layer, the transmittance is 100% at a wavelength of 600 nm to 700 nm, and 0% in other bands.
[0137]
FIG. 44 (c) shows the light receiving sensitivity characteristics of the photodiode. The horizontal axis represents the wavelength, and the vertical axis represents the relative sensitivity (%) normalized to 100% of the sensitivity at the highest sensitivity wavelength. Thus, the light receiving sensitivity characteristic of the photodiode is not uniform with respect to the wavelength. Therefore, even if the radiant flux is the same, if the wavelength components are significantly different, the resulting output current of the photodiode will also be different.
[0138]
FIG. 45 shows the incident light incident on the light receiving surface of the photodiode DFB. FIG. 45A shows the light receiving component at t = t1, and when t = t1, VPG3S5 = VCC, VPG3S6 = GND, and VPG3S4 = VDD as shown in FIG. , G3S6 and G3S4 are displayed in blue. FIG. 45 (b) shows the light receiving component of the photodiode DFB at t = t2. Since the voltage is set as described above, G3S5, G3S6 and G3S4 are combined and black is displayed from FIG. Yes. 45 (a) and 45 (b), the horizontal axis represents the wavelength, and the vertical axis represents the relative input of the radiant flux incident on the light receiving surface of the photodiode DFB with the maximum input normalized to 100%.
[0139]
The liquid crystal layer 24 has a time from when a voltage is applied until the optical characteristics change. This is generally referred to as response speed (reference: Industrial Research Committee “All about Liquid Crystal Display” by Sasaki / Naemura, Kodansha Scientific “Liquid Crystal Materials” edited by Kusabayashi), which is about 20 msec for TN liquid crystal. The pulse width (time during which VON is output) of the output voltage (VC1, VC2,..., VCl) of the Cs line driver shown in FIG. 36 is 2 CPV, but this pulse width depends on the response speed of the liquid crystal layer. In the VGA class, 1 CPV period (one scanning period) is about 40 μsec. Therefore, it is preferable to take 2 CPV minutes or more in TN liquid crystal (more preferably between 5 CPV to 400 CPV, and even more preferably 10 CPV to It is desirable to take at least 1 CPV for an antiferroelectric liquid crystal or a ferroelectric liquid crystal having a response speed of about 200 μsec (more preferably between 1 CPV and 200 CPV, and even more preferably between 2 CPV and 100 CPV). Between). In the SVGA class, the 1 CPV period is about 32 μsec. Therefore, it is desirable that each liquid crystal material has a pulse width 1.25 times that of the VGA class. In the XGA class, the 1 CPV period is about 25 μsec. In each liquid crystal material, it is desirable to take a pulse width 1.6 times that of the VGA class. In other words, it is desirable that the TN liquid crystal has a pulse width of 80 μsec or more (more desirably between 200 μsec and 16000 μsec, and even more desirably between 400 μsec and 12000 μsec), and an antiferroelectric liquid crystal having a response speed of approximately 200 μsec. In a ferroelectric liquid crystal, it is desirable to take a pulse width of 40 μsec or more (more desirably between 40 μsec and 8000 μsec, and even more desirably between 80 μsec and 4000 μsec).
[0140]
This is because, as shown in FIGS. 46A to 46C, the response speed is remarkably different depending on each liquid crystal material, and the pulse width of the output voltage (VC1, VC2,..., VCl) of the Cs line driver is sufficiently long. Otherwise, the change in the transmittance of the liquid crystal phase 24 does not occur sufficiently, and the change in the light transmittance of the display device 10 cannot be accurately detected by the photodiode of the optical signal converter 34, resulting in erroneous detection of initial coordinate detection. For example, when the response speed is 20 msec, 1 CPV is 20 μsec, and the maximum brightness of the display device 10 is 100 [cd / mm 2], the pulse width of the output voltage (VC1, VC2,..., VCl) of the Cs line driving unit is 1 CPV. In the period, only about 0.1% of the light transmittance change of the display device 10 occurs (the brightness change is about 0.1 [cd / mm 2]), which is detected by a high-performance photodiode. Even if it is possible, such a change may occur as a change in luminance of the external light and the backlight, and each time a malfunction occurs. If the pulse width of the output voltage (VC1, VC2,..., VCl) of the Cs line driving unit is set to 2 CPV period, about 0.2% of the light transmittance change of the display device 10 occurs (the brightness change is about 0.1%). 2 [cd / mm <2>]), and it is strong against noise, so that malfunctions can be reduced. In FIGS. 46A to 46C, the vertical axis represents liquid crystal applied voltage and transmittance, and the horizontal axis represents time.
[0141]
Returning to the description, because of the change in the radiant flux incident on the light receiving surface of the photodiode DFB and the light receiving sensitivity characteristic of the photodiode DFB shown in FIGS. 45A and 45B, the display changes from blue to green. In the case of a change, the output changes in the photodiode DFB. 45 (c) and 45 (d) each show a light receiving component when the light receiving sensitivity characteristic of the photodiode is taken into consideration. The horizontal axis indicates the wavelength, and the vertical axis indicates the maximum when the light receiving sensitivity characteristic of the photodiode is taken into consideration. The relative input of the radiant flux incident on the light receiving surface of the photodiode normalized with 1.0 is shown. From (c) and (d), when the light receiving sensitivity characteristic of the photodiode is taken into consideration at t = t1 to t = t2, the relative input of the radiant flux incident on the light receiving surface of the photodiode changes, and as a result, from FIG. The output current of the photodiode changes.
[0142]
In consideration of the above, the initial coordinate detection method according to the present embodiment will be specifically described.
[0143]
The details of detecting the initial coordinate in the Y direction of the pen tip 15 on the display device 10 will be described below.
[0144]
If the user places the pen tip 15 at the position of the display device shown in FIG. 40, VPSR becomes High, all the outputs of the gate line driving unit 3 become VOFF, and the Cs driving unit 9 starts to operate. SW12 and SW13 are turned off, and at that time, an output current corresponding to the radiant flux coming from the backlight 11 through G3S4, G3S6, and G3S5 flows to DFB, and the optical signal converter 34 in FIG. VB corresponding to is obtained, and VB is held in the capacitors 84 and 92 (however, SW12 and SW13 are turned off after VB is written in the capacitors 84 and 92). Thereafter, when a push-up voltage is generated at the timing shown in FIG. 41, and the output current of the photodiode decreases and VB increases due to the optical change of the liquid crystal layer 24, the operation of the capacitors 92 and 93 and the diode 94 in FIG. 47, the output of the operational amplifier 95 also rises. When the output of the operational amplifier 95 becomes VREF3 or more, the comparator 96 outputs VOFF, and the output of the OR circuit 100 becomes High. Since the pen tip 15 is in contact as a display device, VPSR = High, and as a result, VYSTOP = High at the timing shown in FIG.
[0145]
The timing at which VYSTOP = High depends on the position of the pen tip 15 in the Y direction of the display device. This is because the generated push-up voltage is generated by the rise of the Cs line voltage, and the timing at which VON of each Cs line rises is determined by the timing of STV and CPV, as shown in FIG. 36, and if C1, STV becomes High. Later, VON rises at 1 CPV, VON rises at 2 CPV if C2, VON rises at 3 CPV if C3, and mCPV if Cm (here, the rising edge of CPV is counted from the rising edge of STV to VCm = VON VON rises at that time.
[0146]
The Y-direction initial coordinate detection unit 83 shown in FIG. 27 can detect and hold the value of CPV counted for the tcount period as shown in FIG. 28, and here, 3CPV (QA = High, QB = High) by 104 , QC = Low, QD = Low), and if the correction values are set as DYa3 = Low, DYa2 = Low, DYa1 = Low, DYa0 = Low, DY03 = Low, DY02 = Low, DY011 = High, DY00 = High (Decimal number means 3), and the coordinates of the pen tip 15 in the Y direction on the display device 10 were detected. It should be noted that the response speed of the liquid crystal layer 24 used in this embodiment is sufficiently fast, about 50 μsec.
[0147]
Even if the response speed of the liquid crystal layer 24 is slow and 10 CPV (QA = Low, QB = High, QC = Low, QD = High) is counted by 104, the correction values are expressed as Dya3 = High, Dya2 = Low, Dya1 = Low, Dya0. = High (with 15 Cs lines), DY03 = Low, DY02 = Low, DY01 = High, DY00 = High (decimal number means 3), and the response speed of the liquid crystal layer 24 is corrected. Things are possible.
[0148]
Thus, initial coordinates in the Y direction (DY03 = Low, DY02 = Low, DY01 = High, DY00 = High) are detected. In this embodiment, after the TFT is turned off, a push-up voltage is generated by the Cs line driving unit 9, so that the initial coordinate detection unit does not malfunction due to the luminance change of the display device 10 that occurs when the signal line voltage is written to the pixel electrode. Since the initial coordinate detection unit detects only the luminance change on the display device 10 caused by the push-up voltage, highly accurate initial coordinate detection is realized. The period from when the TFT is turned off until the Cs line driving unit 9 operates is 100 μsec or more (more desirably 1 msec or more) for TN liquid crystal, and 5 μsec or more (more desirably 20 μsec or more) for ferroelectric liquid crystal or antiferroelectric liquid crystal. It is desirable to take.
[0149]
The values of DY3, DY2, DY1, and DY0 are controlled by the pixel electrode at which the pen tip 15 is controlled by the Cs line from the top of the array substrate 8 (controlled by the gate line from the top of the array substrate 8 via the TFT). In this case, the pixel electrode is positioned on the pixel electrode controlled by the third (C3) Cs line from the top of the array substrate 8. The values of DY3, DY2, DY1, and DY0 indicate in binary notation the pen tip 15 is on the pixel electrode controlled by the Cs line from the top of the array substrate 8, and (DY3 = Low, DY2 = Low, DY1 = Low, DY0 = High) indicates that the pen tip 15 is located on the pixel electrode controlled by the first Cs line from the top of the array substrate 8, and (DX3 = Low, DX2 = Low) , DX1 = High, DX0 = Low) indicates that the pen tip 15 is located on the pixel electrode controlled by the second Cs line from the top of the array substrate 8, and (DX3 = Low, DX2 = Low, DX1 = High, DX0 = High) indicates that the pen tip 15 is located on the pixel electrode controlled by the third Cs line from the top of the array substrate 8.
[0150]
Thus, it is possible to detect the initial coordinate in the Y direction from the operation of the Cs drive unit 9 and the detection timing of the Y-direction initial coordinate detection unit 83 (FIG. 47).
[0151]
When the initial coordinates are detected by the change in the optical characteristics of the liquid crystal layer 24 (in this embodiment, the change in the optical characteristics of the liquid crystal layer 24 is caused by the push-up voltage), the pixel electrode voltage is written by the positive signal line. Even if a push-up voltage is generated in a certain pixel electrode, the light receiving surface of the photosensor for initial coordinate detection does not receive light from the pixel electrode predominantly because of the optical characteristics of the liquid crystal layer 24 as shown in FIG. Since the optical characteristics on the pixel electrode do not change, initial coordinate detection cannot be performed.
[0152]
In the present embodiment, the length of the light receiving surface in the X direction when the light receiving surface of the photosensor for initial coordinate detection is arranged so that the X direction is the longest is the X length of one pixel electrode as shown in FIG. The pixel electrode is longer than the length in the direction, and the signal line driving unit 2 operates so that the adjacent signal line always has the reverse polarity as shown in FIG. 39. Therefore, the adjacent pixel electrode in the X direction always has the reverse polarity as well. The light receiving surface of the photosensor for initial coordinate detection receives light from two or more adjacent pixel electrodes and does not dominantly receive light from one pixel electrode (one pixel The light component from the electrode is 99% or less, preferably 80% or less at the maximum). As shown in FIGS. 41 to 49, the light receiving state of the photosensor for initial coordinate detection changes, and stable initial coordinates are possible. is there.
[0153]
Further, the voltage at which the signal line driving unit 2 drives the liquid crystal layer 24 is set to VDD = 4V to −4V (maintaining the state where the transmittance characteristic is not saturated as can be seen in FIG. 42), and the low contrast below the capability of the liquid crystal layer 24 If the operation is performed in a state, the optical characteristics on the pixel electrode are changed by the push-up voltage regardless of the voltage of the pixel electrode.
[0154]
Next, detection of the initial coordinate in the X direction of the pen tip 15 on the display device 10 will be described.
[0155]
When VPSR = High and VYSTOP = High and the initial coordinates in the Y direction (DY03 = Low, DY02 = Low, DY01 = High, DY00 = High) are detected, the Cs line driving unit 9 is shown in FIG. The output of V is at one end VOFF and then enters a high impedance state, and no voltage is directly supplied to the Cs line, and the potential is maintained by each pixel capacitance (Csig, cs, Cs, etc.) shown in FIG.
[0156]
Further, the output of the exclusive OR circuit 120 in FIG. 1 becomes High, and all of SW1 to SWn are turned off. Further, as apparent from the operation of the X drive unit 4 shown in FIG. 30, the signal line voltage as shown in FIG. 31 is written into S1 to Sn.
[0157]
Here, a change in the pixel electrode voltage VPG3S6 in the above case will be described. FIG. 48 shows a pixel capacitance model when the output of the Cs line driving unit 9 is in a high impedance state and all the TFTs are turned off (however, the influence of Cg and com is considered to be small and will be ignored below). ), The capacity (CG3S6-S6) between G3S6 and S6 in FIG. 48 is calculated as follows.
[0158]

Accordingly, the voltage change ΔVPG3S6 of VPG3S6 caused by the voltage change ΔVS6 of S6 is as follows.
[0159]
ΔVPG3S6 = CG3S6-S6 / (CG3S6-S6 + CLC) * ΔVS6
It becomes. As specific numerical values, Cp, sig = 0.01PF, Cgs = 0.02PF, Csig, g = 0.05PF, Cs = 0.5PF, CLC = 0.4PF, ΔVS6 = 25V, Csig, cs = 0.2PF Then,
CG3S6-S6 = 0.1PF
ΔVPG3S6 = 5.0V
It becomes.
[0160]
From the above results, it is clear that VPG3S6 shown in FIG. 49 (in FIG. 49, S6 indicates the signal line voltage applied to the signal line S6) is obtained (VPG3S6 t = t4 to t4). = T6 voltage change is referred to as a push-up voltage by the X drive unit), the change in the output current of the photodiode described in FIGS. 41 to 45 occurs, and is apparent from the operation of the X-direction initial coordinate detection unit 82 in FIG. 49, the output of the operational amplifier 127 and VXSTOP shown in FIG. 49 are obtained (however, the light receiving components of VPG3S4, VPG3S6, VPG3S5 and the incident light incident on the photodiode at t = t4 are equivalent to those at t = t1. And the light receiving component of the incident light incident on the light receiving surface of the photodiode at t = t6 is equivalent to that at t = t2.) 49, the outputs QA = High, QB = Low, QC = Low, QD = Low shown in FIG. 49 are obtained, and correction DXa3 = Low, DXa2 = Low, DXa1 = Low, DXa0 = Low ( If this correction value can be used in the same way as that of the Y-direction initial coordinate detection unit 83), then DX03 = Low, DX02 = Low, DX01 = Low, and DX00 = High are obtained.
[0161]
However, in this embodiment, since the Cs line is disconnected from the Cs line drive unit as shown in FIG. 36 before the push-up voltage is generated by the X drive unit 4, the push-up voltage is generated in the pixel electrode, and the generated push-up voltage is It is possible to keep it. If the Cs line is not cut off from the Cs line driving unit, the Cs line potential is maintained at the potential supplied from the Cs line driving unit, so that no push-up voltage is generated in the pixel electrode. Even if the sheet resistance of Cs is high and a push-up voltage is generated, the Cs line potential will eventually change to a potential supplied from the Cs line drive unit, so that the generated push-up voltage is then pulled to the Cs line potential and the desired push-up is performed. No voltage is generated.
[0162]
Thus, initial coordinates in the X direction (DX03 = Low, DX02 = Low, DX01 = Low, DX00 = High) are detected.
[0163]
The values of DX3, DX2, DX1, and DX0 indicate the number of signal lines from the left of the array substrate 8 on the pixel electrode (controlled through the TFT) that is controlled by the pen tip 15. In FIGS. 40 to 49 in the embodiment, the array substrate 8 is positioned on the pixel electrode controlled by the fourth to sixth (S4 to S6) signal lines from the left.
[0164]
The values of DX3, DX2, DX1, and DX0 indicate the number of signal lines from the left of the array substrate 8 on the pixel electrode (controlled by the TFT) that is controlled by the binary number. Since S1 to S3, S4 to S6,... Are simultaneously driven as apparent from the operation of the X drive section 4 shown in FIG. 30, (DX3 = Low, DX2 = Low, DX1 = Low, DX0 = Low). Indicates that the pen tip 15 is located on the pixel electrode (controlled through the TFT) controlled by the first to third signal lines from the left of the array substrate 8, and (DX3 = Low, DX2 = Low, DX1 = Low, DX0 = High) is that the pen tip 15 is positioned on the pixel electrode (controlled via TFT) controlled by the fourth to sixth signal lines from the left of the array substrate 8 (DX3 = Low, DX2 = Low, DX1 = High, DX0 = L w) indicates that it is located on the pixel electrode nib 15 is controlled by 7-9 th signal line from the left of the array substrate 8 (controlled via the TFT).
[0165]
In this way, it is possible to detect the initial coordinate in the X direction from the operation of the X drive unit 4 and the detection timing of the X direction initial coordinate detection unit 82 (FIG. 49).
[0166]
The push-up voltage by the X drive unit is lower than the push-up voltage by the Cs line voltage and is about a quarter. The response speed of the liquid crystal layer 24 is higher when the applied voltage is higher. Therefore, when VON is sequentially supplied to the signal line by the X driving unit as in this embodiment, it is desirable to apply VON to the signal line until VXSTOP = High when VON is written to the signal line. Even if the response speed is slow, the liquid crystal layer 24 responds reliably.
[0167]
In the present embodiment, as described above, the coupling capacitance between the Cs line and the pixel electrode and the coupling between the signal line and the pixel electrode in a state where all the switching elements (TFTs of the array substrate 8) of the display device are turned off. By utilizing the push-up voltage generated in the pixel electrode by the ring capacitance and detecting the change in the optical characteristic (luminance change) of the display device caused by the push-up voltage, the coordinates of the pen on the display device are detected. Therefore, since a voltage is applied to the pixel electrode via the TFT and a change in the optical characteristics of the display device caused by the applied voltage is not detected, the pen coordinate detection accuracy is affected by variations in TFT manufacturing and TFT on-resistance (temperature, manufacturing, Highly accurate coordinate detection is possible without being affected by variations due to design rules and the like, and at the same time, faster coordinate detection is possible because it is not affected by the writing time due to the on-resistance of the TFT.
[0168]
An on-resistance (R-on) exists in the TFT, so when applying a voltage to the pixel electrode via the TFT,
τ = R on * C pixel
There is a time constant of, and this is generally called a write time. However, the C pixel is a capacitance existing in the pixel electrode. Since R-on is affected by the size of the TFT, it is naturally affected by manufacturing variations (Reference: Tsuji et al., IDY 93-65 “Study of Simple Design Method for Writing in a-Si TFT-LCD”, Analysis and Design. of Analog Interacted Circuits Second Edition, Paul R. Gray, Robert G. Meyer). Naturally, there is a manufacturing variation in the size of the C pixel, and as a result, there is a large variation in τ.
[0169]
In the present embodiment, a voltage is applied to the liquid crystal layer 24 by a push-up voltage generated by charge recombination between the capacities existing in the display device 10, and the display device 10 of the pen tip 15 is changed from the optical characteristic change of the liquid crystal layer 24 that occurs at that time. By detecting the upper coordinate, the resistance component becomes zero as much as possible when a voltage is applied to the liquid crystal layer 24. Therefore, when writing the voltage to the C pixel, it is not necessary to consider the time constant of the applied voltage, and at high speed. High-precision coordinate detection is possible.
[0170]
In this embodiment, VREF2, VREF3, VREF4, and VREF5 can be arbitrarily set. Therefore, the luminance change on each pixel electrode of the display device 10 caused by the push-up voltage changes from white (transmittance 100%) to black (transmittance 100%). Even if the transmittance does not change from black to white, by setting VREF2, VREF3, VREF4, and VREF5 as appropriate, slight luminance changes on each pixel electrode of the display device 10 can be transmitted from the transmittance of 100%. Coordinates can be sufficiently detected when the rate is 98% or when the transmittance is 0% to 2%. In this embodiment, VREF2, VREF3, VREF4, and VREF5 are set so that the coordinates can be detected when the transmittance changes by about 10%, so that the image quality of the display device 10 does not deteriorate when the initial coordinates are detected.
Further, in this embodiment, the X driving unit 4, the Cs line driving unit 9, and the SW1-n are formed on the same substrate as the array substrate 8 (reference: Inoue et al., EID91-125p59-p64, Oshima et al. IEICE Transactions, C-Vol. J76-C- No. 5 pp27-pp234), a pen input integrated display device is realized with a narrower frame.
[0171]
As described above, the coordinates (Y direction initial coordinates and X direction initial coordinates) on the pen tip 15 when the pen tip 15 contacts the display device 10 are detected.
[0172]
Only the above-described coordinate detection method is sufficient, for example, when detecting the coordinates of the icon displayed on the display device 10, but handwritten character input (such as katakana, hiragana, kanji, romaji, etc.) is used for the pen input device. The demand to detect is also strong. However, unlike the case of detecting the coordinates of the icon for detecting handwritten character input, the pen input device detects the coordinates of the pen tip 15 in one second because the pen tip 15 moves at high speed on the display device 10. The number of times (detection frequency) needs to be increased (higher). In addition, when detecting coordinates of handwritten character input, white is displayed on the pixel electrode of the detected coordinates in most cases (10 in the present embodiment uses additive color mixture, so strictly speaking, pixels Red, blue, or green is displayed on the electrode) (reference: Nikkei BP, flat panel display 1990-1995, Nikkei BP, Nikkei Microdevice June 1992 issue). This can be seen when writing in a notebook with a pencil or considering printed matter, but usually black characters are written in white characters.
[0173]
FIG. 50 shows a light receiving component considering the transmittance characteristics of the black matrix 29 and the light receiving sensitivity characteristics of the photodiodes on the black matrix 29.
[0174]
FIG. 50 (a) shows the transmittance characteristics of the black matrix 29. The horizontal axis represents the wavelength and the vertical axis represents the relative transmittance normalized to 100% of the maximum transmittance. As shown in FIG. 50 (a), the black matrix has a transmittance of 0% for visible light (reference: Nikkei BP, flat panel displays 1990-1995, Nikkei BP, Nikkei Microdevice January 1990. Issue-September 1995 issue). Therefore, as shown in FIG. 50B, when the photodiode is on the black matrix 29, the relative input is zero. In FIG. 50B, the horizontal axis represents the relative input of the radiant flux incident on the light receiving surface of the photodiode normalized with the wavelength as the vertical axis and the maximum input when the light receiving sensitivity characteristic of the photodiode is considered as 100%. Show.
[0175]
In this embodiment, the pen tip 15 moves on the display device 10 by detecting the difference between the transmittance characteristic of the black matrix 29 shown in FIG. 50 and the transmittance characteristic of each colored layer 30 (FIG. 44). The amount of movement is detected. However, it is not sufficient to detect the actual movement amount, and it must be possible to identify whether the movement amount is in the X direction or the Y direction. Strictly speaking, it must be possible to identify whether the movement amount is in the Xup direction, the Xdown direction, the movement in the Yup direction, or the movement amount in the Ydown direction. In this embodiment, a method of detecting the movement amount and the movement direction at the same time has been invented, and will be described below.
[0176]
FIG. 51 is a diagram for showing a basic concept of a system capable of simultaneously detecting the manner in which the photodiode receives light from the display device 10 and the amount and direction of movement of the pen tip 15 in this embodiment. 17 is arranged as shown in FIG. 51 (a), and then the pen tip 15 is moved as shown in FIG. 51 (b). The light from each colored layer is 100% light transmittance of the liquid crystal layer 24. It is assumed that light comes (that is, the display device 10 displays raster white).
[0177]
In FIG. 51, although not shown below (upper) the black matrix, signal lines, Cs lines, and gate lines are arranged.
[0178]
52A to 52F show the light receiving state of each light receiving surface in FIG. 51A, and the horizontal axis shows the distance from the left end to the right direction with the left end of each light receiving surface being 0 μm. The vertical axis represents the relative illuminance per unit length when the maximum illuminance is normalized to 100%, the illuminance of the black matrix 29 is 0%, and the maximum illuminance of each colored layer is equal.
FIG. 52A shows the light receiving state of the A light receiving surface, where the relative illuminance on the black matrix 29 is 0% and the relative illuminance on each colored layer is 100%. 52B and 52C respectively show the light receiving state of the B light receiving surface and the light receiving state of the C light receiving surface, and the light receiving state is the same as that in FIG. 52A.
[0179]
FIG. 52D shows the light receiving state of the D light receiving surface. Since the D light receiving surface is elongated in the Y direction (Cs line direction), the D light receiving surface is colored by the influence of the relative illuminance of the black matrix 29. The influence of the relative illuminance of the layer 30 is strongly influenced, and thus the relative illuminance is around 100%. If the D light receiving surface is further elongated in the Cs line direction, the relative illuminance becomes closer to 100%. 52 (e) and 52 (f) show the light receiving state of the light receiving surface E and the light receiving state of the F light receiving surface, respectively, which are the same as FIG. 52 (d).
[0180]
53A to 53F show the light receiving state of each light receiving surface in FIG. 51B, and the horizontal axis shows the distance from the left end to the right direction with the left end of each light receiving surface being 0 μm. The vertical axis is normalized when the maximum illuminance is 100%, the illuminance of the black matrix 29 is 0% (actually the illuminance received by each light receiving surface from the black matrix 29 is 0%), and the maximum illuminance of each colored layer is equal. The relative illuminance per unit length is shown.
[0181]
As described above, the surface optical characteristic difference inherent to the display device 10 exists on the surface of the display device 10.
[0182]
FIG. 53 (a) shows the light receiving state of the A light receiving surface. As apparent from FIG. 51 (b), the A light receiving surface is elongated in the X direction (signal line direction). Since it is less affected by the relative illuminance of the (black matrix 29 on the signal line), the relative illuminance of the A light receiving surface is close to 0% of the relative illuminance of the black matrix 29.
[0183]
As is clear from FIG. 51, the relative illuminance received by the B light receiving surface and the C light receiving surface is substantially equal to that in FIG.
[0184]
FIG. 53 (D) shows the light receiving state of the D light receiving surface. As apparent from FIG. 51 (b), the D light receiving surface is elongated in the Y direction (Cs line direction), so that the black matrix 29 in the Y direction is shown. Since it is less affected by the relative illuminance of the (black matrix 29 on the Cs line), the relative illuminance of the D light receiving surface is around 0% of the relative illuminance of the black matrix 29. Since the E light-receiving surface and the F light-receiving surface are completely disposed on the colored layer, their relative illuminance is 100%.
[0185]
From the above, the following conclusion can be obtained. A photodiode having an A light-receiving surface, a photodiode having a B light-receiving surface, and a photodiode having a C light-receiving surface have a structure elongated in the X direction and are not easily influenced by the black matrix 29 in the Y direction (Cs line direction). The direction (signal line direction) is easily affected by the black matrix 29. A photodiode having a D light-receiving surface, a photodiode having an E light-receiving surface, and a photodiode having an F light-receiving surface are elongated in the Y direction, and thus are easily affected by the black matrix 29 in the Y direction (Cs line direction). The direction (signal line direction) of the black matrix 29 is hardly affected. Therefore, each photodiode can distinguish between the black matrix 29 in the X direction and the black matrix 29 in the Y direction.
[0186]
In addition, the light receiving surface of the photosensor for detecting the X direction has the length in the X direction of each light receiving surface when the light receiving surfaces are arranged so that the Y direction of each light receiving surface is the longest as shown in FIG. It is desirable to design the length to be not more than twice the length in the X direction (29X), more desirably it is not more than 29X.
[0187]
This is because an optical sensor such as a photodiode or another CCD used in this embodiment generates an output signal in accordance with the light energy incident on the light receiving surface. Accordingly, since an output signal corresponding to the area of the light receiving surface is obtained, if the 29X of the black matrix 29 to be detected is too shorter than the length in the X direction described above, the output of the optical sensor is small when the matrix crosses the matrix. The black matrix 29 cannot be detected. In this embodiment, the length in the X direction described above was designed to be equal to or less than the length of 29X, and normal operation was confirmed.
[0188]
Similarly, for the light receiving surface of the photosensor for detecting the Y direction, the length in the Y direction of each light receiving surface when each light receiving surface is arranged so that the X direction of each light receiving surface is the longest is shown in FIG. It is desirable to design the length to be not more than twice the length of 29 in the Y direction (29Y), more desirably it is not more than 29Y. In this embodiment, the length in the Y direction was designed to be equal to or less than the length of 29Y, and normal operation was confirmed.
[0189]
FIG. 54A shows the structure of the array substrate 8 and the arrangement of the black matrix 29 in the present invention.
[0190]
54 (a), (b), and (c), the dotted line indicates the black matrix 29. What is important here is that the overlapping portion of the Cs line and the pixel electrode is arranged in the vicinity of the gate line as shown in FIGS. 54 (a) and 54 (c). This is because the Cs line generally does not transmit light like the black matrix 29. For example, if the Cs line and the overlapping portion of the pixel electrode are separated from the gate line as shown in FIG. It is impossible to determine whether the output current has changed due to the black matrix 29 or whether the output current has changed due to the Cs line, causing a malfunction of the pen input display device. Further, the light receiving surface of the photodiode cannot be made significantly larger than the black matrix 29. This is because the light receiving surface of the photodiode must be greatly influenced by the black matrix 29. Therefore, in FIG. 54B, the size of the light receiving surface of the photodiode is limited by the width (or gate line width) of the black matrix 29 on the gate line width, that is, limited by the gate line width. Will be. If the width of the black matrix 29 on the gate line is simply increased in order to widen the light receiving surface of the photodiode, the aperture ratio of the display device 10 is reduced and the power consumption is increased. 54A and 54C as in the present invention, the width of the black matrix 29 on the gate lines and Cs lines can be widened, and the aperture ratio of the display device 10 is impaired. (Because the position of the Cs line is simply shifted on the pixel electrode), it is possible to widen the light receiving surface of the photodiode. The output current of the photodiode is proportional to the area of the light receiving surface, and the larger the light receiving area, the more output current can flow. Therefore, the optical signal conversion in FIG. The unit 34 is less likely to malfunction due to the influence of the offset current and bias current of the operational amplifier 44. In addition, since the resistance values of 42 and 45 can be made smaller (according to Ohm's law, a larger voltage is obtained by flowing a larger current even with a smaller resistance value), the optical signal conversion unit 34 is operated at a higher speed. This makes it possible to perform faster pen input.
[0191]
In summary, in this embodiment, as shown in FIGS. 54A and 54C, the Cs line is arranged in the vicinity of the gate line, and there is no opening of the display device 10 between the gate line and the Cs line ( In other words, the black matrix 29 is arranged on the gate line and the Cs line so that there is no opening between a certain Cs line and the gate line closest to the Cs line. The width of the black matrix 29 on the gate line and the Cs line can be increased without impairing the aperture ratio, and whether the output current of the photodiode is changed by the black matrix 29 on the gate line or the output current by the Cs line. Therefore, it is not necessary to determine whether or not the change has occurred, so that a pen input device with higher accuracy and lower power consumption can be provided.
[0192]
Considering the above, a detection method (movement amount detection method) of the movement amount when the pen tip 15 moves as shown in FIGS. 55, 56, and 57 in this embodiment will be described.
[0193]
At t = t8, the pen tip is arranged as shown in FIG. After that, t = t9 and moves to the position as shown in FIG. 56, and then t = t10 and moves to the position as shown in FIG. 57 (however, the movement between them is the shortest distance) And).
[0194]
FIG. 58 shows the relative illuminance received by each light receiving surface when the pen tip moves as described above.
[0195]
58A to 58F, the horizontal axis is the time axis, and the vertical axis is the light transmittance of the display device 100% (see FIG. 42). The light receiving surface of each photodiode is arranged as shown in FIG. The relative illuminance is obtained by normalizing the illuminance received by each light receiving surface as 100% and setting the illuminance when the entire surface of each light receiving surface is on the black matrix 29 to 0%.
[0196]
It can be seen from the arrangement of the photodiodes in FIG. 55 that the maximum illuminance (100%) is incident on all the photodiode light receiving surfaces.
[0197]
Thereafter, the nib 15 moves to the position shown in FIG. 56, so that each photodiode light-receiving surface crosses the black matrix 29 on the gate line G4 (strictly on G4 and C4). At this time, since each of the light receiving surfaces A, B, and C has a long and narrow structure in the X direction, it is greatly affected by the black matrix 29 on the gate line G4, so that t = t8 to t = t9 as shown in FIG. However, each relative illuminance is greatly reduced. On the other hand, since each of the light receiving surfaces D, E, and F has an elongated structure in the Y direction, it is not easily influenced by the black matrix 29 on the gate line G4, and as shown in FIG. 58, t = t8 to t = t9. However, each relative illuminance is slightly decreased.
[0198]
Thereafter, the pen tip 15 moves to the position shown in FIG. 57, so that each photodiode light-receiving surface crosses the black matrix 29 on the signal lines S4, S3, and S2. At this time, since each of the light receiving surfaces D, E, and F has a long and narrow structure in the Y direction, it is greatly affected by the black matrix 29 on the signal lines S4, S3, and S2, so that t = t9 as shown in FIG. Each relative illuminance is greatly reduced at t = t10. On the other hand, since each of the light receiving surfaces A, B, and C has an elongated structure in the X direction, it is not easily influenced by the black matrix 29 on the signal lines S4, S3, and S2, and as shown in FIG. Each relative illuminance slightly decreases at t = t10. It is clear that FIG. 58 is obtained from FIG. 55, FIG. 56, and FIG.
[0199]
The pen tip 15 displays whether the relative illuminance on the A light receiving surface or the C light receiving surface changes after the relative illuminance change on the B light receiving surface in the change in relative illuminance from t = t8 to t = t9. It depends on whether the device 10 is moving in the Yup direction or the Ydown direction. This is because, in FIG. 55, the C light receiving surface is closest to the black matrix 29 on the gate line G4, the B light receiving surface is next, and the A light receiving surface is next, so that the black matrix 29 on the gate line G3. This is because the A light-receiving surface is the closest, the B-light-receiving surface is next, and the C-light-receiving surface is next. Therefore, when the relative illuminance of the A light receiving surface changes after the change of the relative illuminance of the B light receiving surface, the pen tip 15 is moving in the Ydown direction. The case where the relative illuminance on the light receiving surface changes is when the pen tip 15 is moving in the Yup direction. On the other hand, when the relative illuminance changes from t = t9 to t = t10, the pen tip 15 displays which of the D light receiving surface and the F light receiving surface changes after the relative illuminance change of the E light receiving surface. It depends on whether the device 10 is moving in the Xup direction or the Xdown direction. 56, when the pen tip 15 moves in the Xdown direction, the distances from the D, E, and F light receiving surfaces to the closest signal lines in the Xdown direction from the D, E, and F light receiving surfaces are as follows. The light receiving surface is different, and the F light receiving surface is the closest, the E light receiving surface, and then the D light receiving surface. Similarly, when the pen tip 15 moves in the Xup direction, the distances from the D, E, and F light receiving surfaces to the closest signal lines in the Xup direction from the D, E, and F light receiving surfaces are the same for each light receiving surface. The D light receiving surface is the closest, the E light receiving surface next, and then the F light receiving surface. Therefore, in FIG. 56, when the pen tip moves in the Xdown direction, first, the relative illuminance change of the F light receiving surface occurs, then the relative illuminance change of the E light receiving surface occurs, and then the relative illuminance change of the D light receiving surface occurs. is there. Similarly, when the pen tip moves in the Xup direction, first, the relative illuminance change of the D light receiving surface occurs, then the relative illuminance change of the E light receiving surface occurs, and then the relative illuminance change of the F light receiving surface occurs.
[0200]
As described above, in this embodiment, the positional relationship between the light receiving surfaces when the photodiodes are arranged on the display device 10 is as follows.
[0201]
The positional relationship of each light receiving surface of each photodiode that detects the vertical direction (Yup, Ydown direction), and the distance from each light receiving surface and each light receiving surface to the nearest gate line in the Ydown direction differ for each light receiving surface. Similarly, the distance between each light receiving surface and each light receiving surface to each gate line closest in the Yup direction is different for each light receiving surface.
[0202]
Therefore, in this embodiment, it is possible to detect whether the pen tip 15 is moving in the Xup direction or the Xdown direction (Yup direction or Ydown direction) only by an electric signal from each photodiode, and the same photo With the diode configuration and the same circuit configuration (see FIGS. 18 and 19), it is possible to detect whether the pen tip 15 is moving in the Xup direction or the Xdown direction (Yup direction or Ydown direction). So book Example Accordingly, the number of parts of the pen input display device can be reduced, and the lightness, thinness, and size of the pen input display device can be realized.
[0203]
FIGS. 59A to 59F show temporal changes in the outputs (VA to VF) of the optical signal conversion unit 34 when the relative illuminance time changes of the respective light receiving surfaces as shown in FIG. 58 occur. In FIGS. 59A to 59F, the horizontal axis is the time axis, and the vertical axis represents the relative output when the maximum value of the output is 100% and the minimum value is 0%. When VREF1 is set as shown in FIGS. 59A to 59F, VA0, VB0, VC0, and VD0 shown in FIGS. 60A to 60F are apparent from the operation of the level shift unit 49. , VE0, VF0 are obtained. In FIGS. 60A to 60F, the horizontal axis is the time axis, and the vertical axis indicates the voltage.
[0204]
FIG. 61 shows signals (VYdown, VYup) obtained from the operation result of the serial signal generator 50 (FIG. 18) when VA0, VB0, VC0, VD0, VE0, VF0 as shown in FIG. 60 are obtained. . As is apparent from FIG. 18, the result of FIG. 61 is obtained.
[0205]
When signals (VYdown, VYup) as shown in FIG. 61 are obtained in FIG. 62, signals (DY13, DY12, DY11, DY10) obtained from parallel signal generator 51 in FIG. 22 and Y coordinate detection in FIG. Signals (DY3, DY2, DY1, DY0) obtained from the unit 39 are shown.
[0206]
FIG. 63 shows signals (VXdown, VXup, VXdown3, VXdown3, VXdown3, VA0, VB0, VC0, VD0, VE0, VF0 obtained from the operation result of the serial signal generator (see FIG. 19). VXup3). As is clear from FIG. 19, the result of FIG. 63 is obtained.
[0207]
When signals (VXdown, VXup, VXdown3, VXup3) as shown in FIG. 63 are obtained in FIG. 64, signals (DX13, DX12, DX11, DX10) and X coordinates obtained from the parallel signal generator (FIG. 23) are obtained. Signals (DX3, DX2, DX1, DX0) obtained from the detector 38 are shown.
[0208]
In FIGS. 58 and 59 of this embodiment, the time from when the relative illuminance change of each light receiving surface occurs until the relative output of VA to VF changes is the response of the optical sensor of the pen input device 1. Depending on the speed, it is about 10 μsec when a photodiode is used as an optical sensor, and about 30 μsec when a phototransistor is used. Accordingly, in FIG. 5, the Y direction length of 29 and the X direction length of 29 are 30 μm, the Y direction length of each colored layer in one pixel is 270 μm, the X direction length is 70 μm, and the pen tip 15 Is moved on the display device 10 in the X direction by Z pixels (for Z black matrices on the signal line) in one second. The distance moved at this time is
100μm * Z
The time t (30) required to move 30 μm is
t (30) = 0.3 / Z [seconds]
It becomes. Accordingly, in the present embodiment, the amount of movement Z that can be detected in one second expressed by the number of pixels depends on whether or not the optical sensor can detect the black matrix 29, and therefore Z is as follows.
[0209]
t (30)> 30 μm
Z <10000
(However, phototransistors were used)
Therefore, as long as the user uses the pen input integrated display device according to the present invention for a normal purpose, there is no problem that the time resolution is insufficient in the detection of the movement amount. A pen input integrated display device having high time resolution can be provided.
[0210]
As described above, the coordinates of the pen tip 15 when the pen tip 15 is arranged and moved on the display device 10 are detected as follows.
[0211]
t = t1 · The nib is arranged as shown in FIG.
[0212]
t = t2 · Detects the initial coordinate in the Y direction.
[0213]
DY03 = Low, DY02 = Low, DY01 = High, DY00 = High
Since there is no movement amount, the initial coordinate is the Y coordinate.
[0214]
t = t6 · Detects the initial coordinate in the X direction.
[0215]
DX03 = Low, DX02 = Low, DX01 = Low, DX00 = High
Since there is no movement amount, the initial coordinate is the X coordinate.
[0216]

Is detected, and the control unit 7 receives DX and DY and outputs VD corresponding thereto. The detected coordinates are output (displayed in black) on the display device.
[0217]
t = t9 · The amount of movement in the Y direction is detected.
[0218]
Y coordinate is DY3 = Low, DY2 = High, DY1 = Low, DY0 = Low
No movement in the X direction.
[0219]

Is detected, and the control unit 7 receives DX and DY and outputs VD corresponding thereto. The detected coordinates are output (displayed in black) on the display device.
[0220]
t = t10 · The amount of movement in the X direction is detected.
[0221]
X coordinate is DX3 = Low, DX2 = Low, DX1 = Low, DX0 = Low
No movement in the Y direction.
[0222]

Is detected, and the control unit 7 receives DX and DY and outputs VD corresponding thereto. The detected coordinates are output (displayed in black) on the display device.
[0223]
As described above, according to the first embodiment of the present invention, the amount of movement of the pen tip 15 on the display device 10 is determined by the transmittance difference between the colored layer 30 and the black matrix 29 of the display device 10. The initial coordinates when the pen tip 15 is arranged on the display device 10 are detected by the generated optical characteristic difference on the surface of the display device, and are generated in the pixel electrodes of the display device 10 when the signal lines and Cs lines of the array substrate 8 are driven. Since it can be detected by the push-up voltage, there is no need to provide a coordinate detection tablet for the pen tip 15 behind or in front of the display device 10 and the amount of movement of the pen tip 15 can be instantaneously detected by the optical sensor of the pen input device 1. The initial coordinates can be detected without being affected by TFT manufacturing variations.
[0224]
As a result, a small and lightweight pen input integrated display device having a pen input function with high accuracy and high time resolution can be realized.
[0225]
The pen input integrated display device of the present invention is not limited to the above-described embodiments. Pen input device 1, signal line drive unit 2, Cs line drive unit 9, X drive unit 4, array substrate 8, gate line drive unit 3, display device 10, photodiode array 17, optical signal conversion unit 34, initial coordinate detection The configurations of the unit 36, the movement amount detection unit 37, the X coordinate detection unit 38, the Y coordinate detection unit 39, and the pen system reset unit 35 can be changed as appropriate.
[0226]
The moving amount detection means in this embodiment is a display device having a display portion and a light shielding portion other than the TFT-LCD used as the display device 10 in this embodiment, for example, a simple matrix LCD, a plasma display, a CRT (reference Literature: Nikkei BP, flat panel display 1990-1995, Nikkei BP, Nikkei Microdevice April 1991-July 1994), and the specific configuration can be changed as appropriate.
[0227]
Next, a second embodiment according to the present invention will be described below.
[0228]
When the tilt of the pen and the display device in the pen input device changes greatly, the light energy incident on the light receiving surface changes, which may cause the optical sensor to malfunction. The second embodiment solves this problem. Even if the tilt of the pen and the display device changes, the tilt of the light receiving surface of the pen photosensor with respect to the display device is kept below a predetermined angle.
[0229]
FIG. 65 shows the structure of a pen input device according to the second embodiment of the present invention. The same components as those in the first embodiment 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
65, the inclination control unit 156 has an inclination between the light receiving surface of the photodiode array 17 and the display surface of the display device 10 of 0 ° to 45 ° (preferably 0 ° to 20 °, more preferably 0 ° or parallel). As a result, even if the inclination of the pen input device 1 (the inclination angle of the pen) changes as shown in FIGS. 65 (a) to 65 (c), the photodiode array 17 The inclination of the light receiving surface and the display surface of the display device 10 is controlled to 0 degree to 45 degrees.
[0230]
In display devices such as CRTs, plasma displays, and liquid crystal displays, the brightness of the display device surface varies depending on the angle at which the surface of the display device is viewed. This characteristic is more prominent in liquid crystal displays. In general, the viewing angle (reference: Nikkei BP, flat panel displays 1990-1995, Nikkei BP, Nikkei Microdevices, January 1990-September 1995) No.). Accordingly, when coordinate detection is performed optically, the outputs VA to VF of the optical signal conversion unit 34 are changed depending on the tilt angle of the pen input device 1 (the tilt angle of the pen) due to this viewing angle. A malfunction occurred. However, according to the second embodiment, malfunction due to the tilt angle of the pen can be suppressed, and stable coordinate detection is possible.
[0231]
66 and 68 show the structure of the pen input device according to the second embodiment of the present invention in more detail. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. To do.
[0232]
66 to 68, reference numeral 157 denotes a support base for supporting the spring 158, and reference numeral 159 denotes a slider which is moved by a force applied to 16. Even if the tilt of the pen changes as shown in FIGS. 66 to 68 (in this embodiment, the case of 15 degrees to 95 degrees is shown), the slider 159 moves by the restoring force of the spring 158, and the optical sensor Since the light receiving surface of a certain photodiode array 17 is controlled so as to be always parallel to the display surface of the display device 10, the incident angle of light incident on the light receiving surface of the photodiode array 17 from the backlight 11 is the tilt angle of the pen. Since the irradiance incident on the light receiving surface of the photodiode array 17 does not change due to the change in the tilt angle of the pen, more stable coordinate detection is realized. Further, as in the present embodiment, the tilt control unit 156 is configured by the support base 157, the spring 158, and the slider 159, so that the miniaturization and weight reduction required for the pen input device 1 are realized at the same time. The total is 1 gram or less). In addition, the configuration of the tilt control unit 156 can be changed as appropriate, and a sensor that detects an angle change such as rubber or a gyroscope sensor may be used, and the method of using the sensor can also be changed as appropriate.
[0233]
As described above, according to the second embodiment of the present invention, even if the tilt of the pen input device 1 changes, the tilt controller 156 tilts the light receiving surface of the photodiode array 17 and the display surface of the display device 10. Since the output VA to VF of the optical signal conversion unit 34 due to the change in the tilt angle of the pen input device 1 can be suppressed, a stable coordinate detection without malfunction is performed. I can do it.
[0234]
As a result, in the pen input integrated display device including the small and light pen input device 1, stable coordinate detection is possible.
[0235]
Next, a third embodiment according to the present invention will be described.
[0236]
In pen input display devices using high-definition display devices, hand-shake that occurs when a user performs pen input and erroneous input that occurs because the input surface for pen input is slippery, unlike paper, are more noticeable. The high-definition display that the device has cannot be made, and erroneous input due to camera shake becomes a noticeable handwriting. The present embodiment is for solving this problem, and is a pen input device having a display device having a relatively small pixel size, and sufficiently corrects the pen trajectory even when the handwriting input speed is relatively fast. be able to.
[0237]
FIG. 69 shows the overall configuration of this embodiment. Reference numeral 1100 denotes a pen input display device which has basically the same configuration as the pen input display device 1000 (see FIG. 1) described in the first embodiment, but each of the X and Y coordinates in the first embodiment is 4 bits. In contrast, the X and Y coordinates of the pen input display device used in the third embodiment are each composed of more practical 6 bits. 69 and 69 are the X and Y coordinate outputs of the pen input display device 1100.
[0238]
In FIG. 69, 170 is a pen speed detector for detecting the speed (movement speed) of the detection pen moving on the display device in the pen input state from the DX and DY signals, and DS is the movement of the detection pen. Indicates speed. Reference numeral 171 denotes a vector change detection unit that detects a movement vector moved from the DX and DY on the display device in the pen input state and a vector change that is a change thereof. DXV indicates a movement vector in the X direction. DYV indicates a movement vector in the Y direction, and DXV and DYV indicate movement vectors (also simply referred to as vectors) of the detection pen on the display device 10 ′. VV represents a vector change of the movement vector. Reference numeral 172 corrects a signal from the pen input display device 1100 based on signals from 170 and 171, and corrects signals DYC and DXC indicating the position of the detection pen on the display device to the pen input display device 1100. It is the correction | amendment part which outputs to. These details will also be described later.
[0239]
FIG. 70 shows digital signals DX (DX6, DX5, DX4, DX3, DX2, DX1) and DY (DY6, DY5, DY4, DY3, DY2, DY1) indicating the respective pixels of the display device 10 ′. In FIG. 70, when the coordinates of the upper left pixel are denoted by DX and DY, DX = (0,0,0,0,0,1), DY = (0,0,0,0,0,1) ) When the upper right coordinates are represented by DX and DY, DX = (1, 1, 1, 1, 1, 1) and DY = (0, 0, 0, 0, 0, 1). When the coordinates of the lower left pixel are represented by DX and DY, DX = (0, 0, 0, 0, 0, 1) and DY = (1, 1, 1, 1, 1, 1). When the lower right coordinates are represented by DX and DY, DX = (1,1,1,1,1,1) and DY = (1,1,1,1,1,1). Digital signals correspond to other pixels in the same order. In this embodiment, since the display device has 64 pixels in both the X and Y directions, both DX and DY are expressed by 6-bit digital signals shown in FIG. 70 as described above. The pixel size of the display device 10 ′ is 300 μm × 300 μm.
[0240]
In the pen input display device having the above configuration, “1” is input by handwriting as shown in FIG. As shown in FIG. 72, in general, the surface of the pen input display device (including this embodiment) is smooth and slippery unlike paper and the like, and the surface of the pen input display device has to be handwritten many times. Therefore, the pen tip of the detection pen used in the pen input display device cannot be pointed and is more slippery. Therefore, when inputting characters by handwriting, the font may be awkward. This becomes a larger problem as the display device 10 ′ becomes higher definition. Therefore, when there is no pen speed detection unit 170, vector change detection unit 171 and correction unit 172 in the present embodiment, even if “1” is intended to be input, “1” as shown in FIG. 73 is input and displayed. In FIG. 73, each grid indicates one pixel of the display device 10 ′, and a pixel displayed in black indicates a pixel selected by pen input, and the relationship between each pixel and the digital signals DX and DY. Is as shown in FIG. Here, the coordinate digital signals DX and DY obtained as shown in FIG. 73 are analyzed.
[0241]
FIG. 74 shows the relationship between the digital signals DX and DY obtained in the case of FIG. 73 and time. The detection time in FIG. 74 indicates how much time has passed since the start of handwriting input, 0 msec indicates the time when handwriting input is started, and the detection time interval (1 msec) shown in FIG. The time resolution in the coordinate detection of the input display device (reference document: Journal of Information Processing Society of Japan, Mar. 19204 Vol. 29 No. 3 “Online Character Graphic Editing Method Using Handwritten Editing Symbols” Kojima et al.) Is shown. In this embodiment, although the detection time interval depends on the definition of the display device, it is desirable that the detection time interval is short enough to detect pen coordinate data (DX, DY) of one pixel twice or more, and more desirably three times above. Yes, and the value can be changed as appropriate.
[0242]
FIG. 75 shows the configuration of the pen speed detection unit 170. 75, 173, 174, 176, 177, 186 and 187 are D-type flip-flops, and TC74HC574 is used in this embodiment. 181 is a buffer, 182, 183 and 192 are inverters, 175 and 178 are comparators, and TC74HC6204 is used in this embodiment. 179 is a non-OR circuit, 180 is an AND circuit, 184 and 185 are counters, and TC74HC161 is used in this embodiment. Reference numeral 188 denotes a two-channel multiplexer, which may be composed of, for example, TC74HC4053. Reference numeral 189 denotes a multiplication circuit, which may have a circuit configuration shown in, for example, a reference document “Digital System Design CQ Publishing Co., Ltd., Ukai / Honda”. Note that the inverter 192 operates faster than the buffer 181.
[0243]
FIG. 76 shows the configuration of the vector change detection unit 171. Reference numeral 190 denotes a vector detection unit, which detects a movement vector of the detection pen from the digital data DX and DY, and outputs analog signals DXV and DYV. Reference numeral 191 denotes a vector comparison unit that changes the movement vector from DXV and DYV. Is a circuit that outputs a digital signal VV indicating that the movement vector has changed when VV is High, and there is no change in the movement vector when Low.
[0244]
FIG. 77 shows the definition of the movement vector direction of the detection pen corresponding to FIG. The arrows V1 to V8 in FIG. 77 are arrows for indicating that the pen tip of the detection pen is moving in the direction of the movement vector in the direction of the arrow on FIG. 73, and V9 is that the pen tip is stationary. Is shown.
[0245]
FIG. 78 is a diagram showing the relationship between the DXV and DYV signals and the movement vector direction. The DXV and DYV signals are three-level (High, Middle, Low) analog signals.
[0246]
The result shown in FIG. 79 is obtained from the operation of the pen speed detector 170. DX and DY delayed by a half clock are obtained by the D flip-flops 173 and 176, and DX and DY delayed by one clock are obtained by the D flip-flops 174 and 177. The outputs of the D flip-flops 173 and 174 and the outputs of the D flip-flops 176 and 177 are compared by the comparators 175 and 178. If the values are the same, Low is output if the values are different. In 184 and 185, the number of clocks of CLK1 in a period from when High is output from the comparators 175 and 178 to when the next High is output is counted and output. 186 and 187 fetch and hold the outputs of 184 and 185 using the output of 192 as a clock. FIG. 79 shows the outputs of 186 and 187 in decimal numbers. Actually obtained values are indicated by binary numbers of a plurality of bits, but since the explanation is complicated, the following will be shown using decimal numbers. Outputs 186 and 187 indicate the moving speed of the detection pen. If the output of 186 and 187 is 4, it means that 4 clocks are required for the pen tip to cross one pixel. Therefore, in this embodiment, since the size of one pixel is 300 μm * 300 μm, the moving speed is 300 μm / (4T). T represents the period of CLK1. Since one pixel has a rectangular or square shape, the distance across one pixel differs depending on how the pen tip crosses one pixel. In this embodiment, since one pixel is a square, the distance across one pixel is 300 μm when moving in the directions of V1, V3, V5, and V7, and one pixel is crossed when moving in the directions of V2, V4, V6, and V8. The distance is 140 μm. Therefore, in this embodiment, the value weighted to 186 and 187 is changed depending on in which direction the pen tip has moved using 188. 188 selects ch1 when the output of 180 is high, and selects ch2 when the output of 180 is low. When 180 becomes High, the pen tip moves in the directions of V2, V4, V6 and V8. In this embodiment, the ratio of ch1 and ch2 is set to be close to ch1 / ch2 = 1.4 (shown in decimal number), and the outputs of 186 and 187 are weighted by 189 multiplier circuits. . The output of the multiplication circuit 189 is shown in FIG. In this embodiment, since the moving speed is detected by the above method, it is possible to detect an accurate moving speed that does not depend on the pixel shape, and it is possible to detect the moving speed with a simple circuit configuration as shown in FIG. Even when the size of one pixel is a rectangle such as 100 μm * 33 μm, the moving speed of the detection pen obtained in accordance with the shape of one pixel is weighted in the same manner as in the present embodiment, so that the moving speed is more accurate. Is obtained.
[0247]
79 is obtained from the vector detection unit 190, and VV shown in FIG. 79 is obtained by the vector comparison unit 191. The vector comparison unit 191 receives DXV and DYV and outputs High when the vector changes. When the vector is V9, it is assumed that the pen tip has moved with the previous vector, and the vector comparison unit 191 performs processing to replace V9 with the previous vector. When the vector comparison unit 191 treats the vector detected at the detection time of 4 msec as V5, treats the vector detected at the detection time of 5 msec to 9 msec as V5, treats the vector detected at the detection time of 10 msec as V3, and a vector change occurs As shown in FIG. 79, High is output. Others are the same.
[0248]
FIG. 80 shows the configuration of the correction unit 172. The phase adjustment unit 192 in FIG. 80 adjusts the phase as shown in FIG. 81 in order to facilitate processing of the input signal. Ds ′, VV ′, DXV ′, DYV ′, DX ′, and DY ′ are Ds, VV, DXV, DYV, DX, and DY phase-adjusted by 192. The conversion unit 193 selects the data to be deleted from DX ′ and DY ′ as follows.
[0249]
(1) If the movement vector changes despite the increase in the movement speed obtained from Ds ′ (VV ′ = High), the DX ′ and DY ′ data are invalidated and deleted. ”
(2) The movement speed and movement vector (DXV ′, DYV ′) immediately before deletion are compared with the movement speed and movement vector after deletion, and the movement vector after deletion and the movement vector immediately before deletion are the same or deleted. If the subsequent movement speed is slower than the movement speed immediately before the deletion, the DX ′ and DY ′ data are determined to be valid and are captured.
[0250]
FIG. 81 shows DXC ′ and DYC ′ obtained as described above.
[0251]
Therefore, DX = (0, 1, 0, 0, 0, 0) and DY = (0, 0, 1, 1, 0, 1) that are erroneous input data are deleted, but DX that is normal input data is deleted. = (0,0,1,1,1,1) and DY = (0,0,1,1,1,0) have also been deleted. In this embodiment, in order to solve such a problem, the interpolation unit 194 eliminates this display problem, so that DX = (0,0,1,1,1,1), DY = (0,0,1). , 1, 0, 1) and DX = (0, 0, 1, 1, 1, 1), DY = (0, 0, 1, 1, 1, 1) are created and data is created. Overlay on DXC 'and DYC'. FIG. 81 shows DXC and DYC data obtained as a result. Dxm and DYm are linearly interpolated data, and Dxm = (0,0,1,1,1,1) and DYm = (0,0,1,1,1,0). Note that the linear interpolation is to correct a defect by connecting the missing part of the line with the minimum distance as shown in FIG.
[0252]
Next, a fourth embodiment according to the present invention will be described. FIG. 83 shows the configuration of the pen input display device according to the fourth embodiment. The difference between the present embodiment and the third embodiment described above is that a resistive film tablet is used for the pen input display device.
[0253]
83, reference numeral 195 denotes a resistance film, reference numeral 196 denotes a resistance film, reference numeral 197 denotes a conductive layer arranged on the resistance film 195, reference numeral 198 denotes a conductive layer arranged on the resistance film 195, 5 indicates a conductive layer disposed on the resistance film 196, 200 indicates a conductive layer disposed on the resistance film 196, SW1 and SW2 are switches controlled by CNT1, and SW3 and SW4 are controlled by CNT2. The switch 204 is a voltage source for supplying a constant voltage to each resistance film and supplying 5V. The impedance conversion unit 202 converts the X-direction signal and the Y-direction signal indicating the position of the detection pen 205 on the display device 10 ′ from the conductive layer 198 and the conductive layer 6 with analog electrical signals, and then converts the impedance to X ′, Reference numeral 203 denotes an impedance converter that outputs as Y '. Reference numeral 203 denotes an A / D converter that converts analog signals X' and Y 'into digital signals DX and DY, respectively. The operation of each component described above will be described in detail later, but there are “Toshiba Review 1994 Vol. The definition of the movement vector direction (X direction, Y direction) is as shown in FIG.
[0254]
FIG. 84 shows the principle of pen coordinate detection in this embodiment. FIG. 84A shows a cross-sectional view of a tablet formed of resistance films 195 and 196, and reference numeral 13 denotes a spacer for keeping the resistance films 195 and 196 in non-contact in a non-pen input state. As described above, the resistance films 195 and 196 are kept in a non-contact state unless the detection pen applies pressure to the resistance films 195 and 196.
[0255]
FIG. 84 (b) is a diagram showing a state in which the detection pen 205 applies pressure to the resistance films 195 and 196. When the pressure from the detection pen 205 is applied in this way, the resistance films 195 and 196 are in contact with each other. become. Further, a portion where pressure is applied from the detection pen 205 is a counter electrode 207, and as shown in FIG. 84C, a resistance between the conductive layer 197 and the counter electrode 207 is R15, and the conductive layer 198 and the counter electrode are The resistance between 207 is R16, the resistance between the conductive layer 199 and the counter electrode 207 is R19, and the resistance between 200 and the detection pen 205 is R20. Note that a certain sheet resistance exists in the resistance films of 195 and 196, but in the conductive layers 197, 198, 199, and 200, this sheet resistance is negligibly small.
[0256]
FIG. 85 shows the configuration of the impedance converter 202. 85 and 209 in FIG. 85 are operational amplifiers, which are used as so-called voltage followers, and impedance-convert input signals and output them. FIG. 86 shows the control of SW1 to SW4. When CNT1 is at high level, SW1 and SW2 are in the on state, and when CNT1 is at low level, SW1 and SW2 are in the off state. When CNT2 is at high level, SW3 and SW4 are in the on state, and when CNT2 is at low level, SW3 and SW4 are in the off state. Both CNT1 and CNT2 are always driven in opposite phases.
[0257]
FIG. 87 shows an equivalent circuit in the case of FIG. FIG. 87 (a) shows an equivalent circuit when CNT1 = High and CNT2 = Low, and no voltage is applied to the conductive layers 199 and 6, and 0V is applied to the conductive layer 197 and 5V is applied to 198. . Accordingly, since the voltage of 6 is 5 * R15 / (R15 + R16), X ′ = 5 * R15 / (R15 + R16). That is, the position 14 in the X direction of the detection pen is detected as the analog signal X ′.
[0258]
FIG. 87B shows an equivalent circuit in the case of CNT1 = Low and CNT2 = High, where no voltage is applied to the conductive layers 197 and 198, and 0V is applied to the conductive layer 199 and 5V is applied to 6. . Therefore, since the voltage of 200 is 5V, X ′ = 5V. In this embodiment, when X ′ = 5 V, this is not handled as an analog signal indicating the position of the pen in the X direction.
[0259]
FIG. 88 shows an equivalent circuit in the case of FIG. FIG. 88A shows an equivalent circuit in the case of CNT1 = High and CNT2 = Low, in which no voltage is applied to the conductive layers 199 and 6 and 0V is applied to the conductive layer 197 and 5V is applied to 198. . Therefore, the voltage of 198 is 5V, and Y ′ = 5V. In this embodiment, when Y ′ = 5V, this is not handled as an analog signal indicating the position of the pen in the Y direction.
[0260]
FIG. 88 (b) shows an equivalent circuit when CNT1 = Low and CNT2 = High, and no voltage is applied to the conductive layers 197 and 198, and 0V is applied to the conductive layer 199 and 5V is applied to 200. . Accordingly, since the voltage of 6 becomes 5V, Y ′ = 5 * R19 / (R19 + R20). That is, the position 14 in the Y direction of the detection pen is detected as the analog signal Y ′.
[0261]
As described above, in this embodiment, the position of the pen is detected as shown below,
When CNT1 = High and CNT2 = Low
The position of the detection pen in the X direction is detected as an analog signal.
When CNT196 = High and CNT1 = Low
The position of the detection pen in the Y direction is detected as an analog signal.
The obtained analog signal is converted into digital signals DX and DY by the A / D converter 203. The digital signals DX and DY are output to the pen speed detection unit 170, vector change detection unit 171 and correction unit 172 shown in FIG. 83, and are corrected as described above.
[0262]
As above Example Thus, a pen input display device capable of realizing pen input according to the intention of the user who has deleted data that is erroneously input due to ergonomics has been realized. Further, in this embodiment, since the moving speed and the moving vector are detected for each pixel movement, a more excellent handwriting input of handwriting becomes possible. Book Example Is a pen input display device using an electromagnetic induction tablet other than a pen input display device using a resistance thin film tablet (reference: Toshiba review 1994 Vol. 49 No. 12, Nikkei BP flat panel display '93, Nikkei BP MATERIALS & TECHNOLOGY 93 .8) and pen input display devices using electrostatic coupling tablets (reference: Toshiba review 1994 Vol. 49 No. 12, Nikkei BP flat panel display '93, Nikkei BP MATERIALS & TECHNOLOGY 93.8) and other pen input displays (Japanese Patent Laid-Open Nos. 4-283819, 4-299727, 5-127823, 5-515480, 4-343387, 5-189126, 5-197487) , JP-A-62-292021, JP-A-63-293623), and other pen input display devices.
[0263]
Next, a fifth embodiment according to the present invention will be described.
[0264]
In the conventional pen input display device using the active matrix display device described above, signal lines and gate lines for supplying voltage to the active elements have been increasingly finely processed in recent years in order to improve the aperture ratio and increase the definition. (Reference document: Nikkei Business Publications, Inc., flat panel display 1991-1995) For this reason, the coupling capacity between the detection pen and each electrode line is reduced, resulting in a lower detection voltage, making accurate coordinate detection difficult. This is shown in FIG.
[0265]
In FIG. 100, 400 is an array substrate, 401 is a silicon oxide film disposed on 400, 402 is a Cs line disposed on 400, 403 is a gate line disposed on 400, 404 is a signal line disposed on 400, 405 is a pixel electrode disposed on 400, 409 is a counter substrate disposed opposite to 400, and 406 is between 400 and the counter substrate 409. An injected liquid crystal layer, 408 is a colored layer disposed on the counter substrate 409, and 407 is a counter electrode disposed on the counter substrate 409. 400 to 409 constitute an active matrix display device. 310 indicates the pen tip of the detection pen, Cpg indicates the coupling capacitance between the pen tip 310 and the gate line 403, Cps indicates the coupling capacitance between the pen tip 310 and the signal line 404, and CL indicates between the pen tip 310 and GND (here. Represents the AC ground), and Vp represents the detection voltage generated at the pen tip. If the voltage change occurring on the gate line is ΔVg, the voltage change occurring on the signal line is ΔVs, and the initial condition of the detection voltage Vp is 0 V, the detection voltage Vp generated at the pen tip is approximately expressed by the following equation.
[0266]
Vp = ΔVg * Cpg / (Cpg + CL)
Vp = ΔVs * Cps / (Cps + CL)
Therefore, the detection voltage Vp can be increased by increasing Cpg (Cps) or ΔVg (ΔVs). However, ΔVg (ΔVs) cannot be extremely increased due to the breakdown voltage of the active element, and the oxidation voltage is reduced. If the thickness of the film 401 is about 3500 angstroms, about 45 V is desirable for reliability. The value of Cpg (Cps) is the simplest expression and is expressed as follows.
[0267]
Cpg ∝ ε0 * εg * Ghaba / dg
Cpg ∝ ε0 * εg * Shaba / dg
ε0: Dielectric constant of vacuum
εg: non-dielectric constant of glass
Ghaba: Gate line width
Shaba: signal line width
dg: Glass thickness
In order to increase Cpg (Cps), εg, Ghaba, Shaba must be increased or dg must be decreased. However, since εg is a fundamental property of the material, it cannot be expected to be extremely large, and if dg is too small, glass breakage or deflection occurs, and active elements cannot be uniformly formed on the array substrate 400. , Dg is preferably 0.3 mm to 1.1 mm. The only elements that can be changed are Ghaba and Shaba, which have been increasingly miniaturized in recent years as described above. Note that FIG. 101 shows the gate line width and the signal line width described here. FIG. 101 is a diagram of an active matrix display device viewed from directly above.
[0268]
Therefore, the coupling capacity between the signal line or gate line and the detection pen is reduced, the detection voltage detected by the detection pen is reduced, and the active matrix display device with high definition and high aperture ratio is accurate due to noise from the backlight and others. Coordinate detection is impossible.
[0269]
The present embodiment has been made in consideration of the above-described circumstances, and an object thereof is to enable a good-looking handwriting input with a more accurate and fine handwriting and a quick handwriting input of the pen input display device. Hereinafter, a fifth embodiment of the present invention will be described in detail.
[0270]
FIG. 89 shows a pen input display device according to Embodiment 1 of the present invention. In FIG. 89, reference numeral 301 denotes a TFT substrate (array substrate) on which signal lines (S1 to S5), gate lines (G1 to G4), Cs lines (Cs1 to Cs4), TFTs, and pixel electrodes are arranged. Yes. Reference numeral 302 denotes a counter substrate, 303 denotes a counter electrode arranged on the counter substrate, 304 denotes a signal line driving circuit for applying a signal line voltage to a signal line arranged on the TFT substrate 301, and 305 denotes a TFT substrate 301. 2 is a gate line driving circuit for applying a gate line voltage to the gate lines arranged in the gate line. Reference numerals 301 to 309 constitute a TFT-LCD (hereinafter simply referred to as a display device). References to these include, for example, “Nikkei BP flat panel display 1991-1995”. Reference numeral 306 denotes an X drive circuit, and reference numeral 307 denotes a Cs drive circuit for supplying a Cs line drive voltage to the Cs line. Specific examples of these configurations will be described later. A power supply unit 308 supplies a necessary voltage to each circuit unit. A control unit 3099 supplies various signals for operating each driving unit to each driving unit. The signal line driving circuit 304 has ES and the gate line driving circuit 305 has EG and X driving circuit. EX is supplied to Cs drive circuit 307, CNTS is supplied to switches sws1 to sws5, CNTg is supplied to switches swg1 to swg4, CNTx is supplied to switches swx1 to swx5, and CNTC is supplied to switches swc1 to swc4. is doing. The control unit 309 supplies a signal necessary for the detection pen 310 and a signal necessary for detecting the coordinates of the detection pen from 310. EG, ES, EC, and EX indicate data bus lines, and various control signals are included therein. Further, the switches sws1 to sws5 are switches that are on / off controlled by CNTS, the switches swg1 to swg4 are switches that are on / off controlled by CNTg, the switches swx1 to swx5 are switches that are on / off controlled by CNTx, and the switches swc1 to swc1 swc4 is a switch that is ON / OFF controlled by CNTC. swcom is a switch that is ON / OFF controlled by CNTcom, and the voltage Vcom is supplied to 2 through this switch. Reference numeral 5000 denotes a counter electrode driving circuit that supplies a counter electrode voltage Vcom to the counter electrode 303. Reference numeral 310 denotes a detection voltage (corresponding to Vp in FIG. 100) supplied from the TFT substrate 301. In the pen input display device according to the fifth embodiment, the position of 310 on the TFT substrate 301 is determined according to the detection voltage generation timing. (Pen coordinates) is detected. The X direction and the Y direction are defined as shown in FIG.
[0271]
FIG. 90 shows the operation timing of each switch. In the pen input display device according to the present embodiment, pen coordinate detection is performed during a vertical blanking period in one frame. During the display period, swg1 to swg4, sws1 to sws5, swc1 to swc4, swcom are on, and swx1 to swx5 are off. Therefore, a signal line voltage corresponding to the image signal is supplied from the signal line driver circuit 304 to the pixel electrode through the TFT. At this time, the voltage from the X drive circuit 306 does not affect the image of the display device because swx1 to swx5 are off. When the display device moves from the display period to the vertical blanking period and enters the X-direction pen coordinate detection period, swx1 to swx5 are turned off to on, and the other switches are turned off. In the Y-direction pen coordinate detection period, swc1 to swc4 are turned on and the others are turned off.
[0272]
FIG. 91 shows the configuration of the X drive circuit 6. The X drive circuit 306 is composed of D flip-flops 311 to 315, and 311 to 15 constitute a so-called shift register with CLK as a clock and STHX as a start pulse.
[0273]
FIG. 92 shows the configuration of the Cs drive circuit 307. The Cs driving circuit 307 is composed of D flip-flops 316 to 319, and 316 to 319 constitute a so-called shift register having CLK as a clock and STHCS as a start pulse.
[0274]
FIG. 93 shows operations of the X drive circuit 306 and the Cs drive circuit 307. STHX becomes VH for 1 CLK when the display device enters the X-direction pen coordinate detection period, and VX1 to VX5 sequentially become VH. However, VX1 to VX5 indicate applied voltages X1 to X5, respectively, and VC1 to VC4 indicate applied voltages C1 to C4, respectively. STHCS becomes VH for 1 CLK when the display device enters the Y-direction pen coordinate detection period, and VC1 to VC5 sequentially become VH. Further, VXT and VYT are internal signals of the control unit 9, and VXT is at a high level during the X-direction pen coordinate detection period and is at a low level during the other periods. VYT is at a high level during the Y-direction pen coordinate detection period and is at a low level during the other periods. The above operation is apparent from FIGS. 91 and 92.
[0275]
FIG. 94A shows a diagram in which the detection pen 310 is arranged in the vicinity of the display device S14 and CS13. Further, cross-sectional views at this time are shown in FIGS. 94 (b) and 94 (c). 94 (b) and 94 (c), there is a coupling capacitance between the pen tip 310 and each electrode of the display device and between each electrode, and cpg is a coupling between the gate line and the pen tip 310. Cps is the coupling capacitance between the signal line and the pen tip 310, csg is the coupling capacitance between the signal line and the gate line, csc is the coupling capacitance between the signal line and the Cs line, and cs is the pixel electrode and the Cs line. , Cpc is the coupling capacitance between the Cs line and the pen tip 310, cpc is the coupling capacitance between the pixel electrode and the pen tip 310, cgs is the coupling capacitance between the gate line and the pixel electrode, and clc is colored. The coupling capacitance between the layer 407 and the pixel electrode is indicated by cscom, and the coupling capacitance between the signal line and the coloring layer 407 is indicated. However, each coupling capacity shown in FIGS. 94B and 94C indicates a coupling capacity directly coupled from between the electrodes forming the coupling capacity, and does not include coupling capacity generated through other electrodes. . For example, when only the electrodes of the pen tip 310 and the signal line 404 are considered, the coupling capacitance between the pen tip 310 and the signal line 404 is cps shown in FIG. 94B, but in reality, other electrodes such as Cs lines are used in the display device. When a constant bias voltage is not applied to them and charges cannot be taken in and out, a coupling capacitance through these electrodes is generated between the nib 310 and the signal line 404. 94 (b) and 94 (c), the coupling capacitance between one signal line and the pen tip 310, the coupling capacitance between one Cs line and the pen tip 310, and one gate line. The coupling capacitance between one pixel electrode and the pen tip 310, the coupling capacitance between one signal line and the counter electrode, and the coupling capacitance between one Cs line and the counter electrode. The coupling capacitance between one line and the counter electrode is shown, and the coupling capacitance between one pixel electrode and the counter electrode is shown.
[0276]
In this embodiment, the signal line driving circuit 304, the gate line driving circuit 305, and the Cs driving are performed immediately before X1 changes from VL to VH when the display device changes from the display period to the vertical blanking period. The circuit 307 supplies VL to all signal lines, all gate lines, and all Cs lines. As a result, when the display period shifts to the vertical blanking period, all the TFTs are surely turned off, and the supply source for supplying the signal line voltage to the signal line is changed from the signal line driving circuit 304 to the X driving circuit 306. Since the signal line voltage is kept constant at VL, no voltage fluctuation occurs in the signal line, gate line, Cs line, pixel electrode, etc., and no error voltage is generated in the detection pen 310, and more accurate coordinate detection is possible. became.
[0277]
In this embodiment, the coupling capacitance Cpstotal (including the coupling capacitance generated through the electrodes other than the pen tip 310 and the signal line 404) and the coupling capacitance Cpctotal between the pen tip 310 and the Cs line 402 (the pen tip). 310 and the coupling capacitance generated through the electrodes other than the Cs line 402 are obtained as follows. The array substrate 400 is overwhelmingly thicker than the oxide film 401 and the liquid crystal layer 406.
[0278]
Cpstotal = Cpctotal = Cps + Cpc + Cplc + Cpg
Therefore, the detection voltage generated by the voltage change (ΔVs, ΔVcs) of the signal line and the Cs line is as follows.
[0279]
Vp = ΔVs * Cpstotal / (Cpstotal + CL) (5)
Vp = ΔVcs * Cpctotal / (Cpctotal + CL) (6)
The detection voltages generated by driving the X drive circuit 306 and the Cs drive circuit 307 are as shown in FIG. When a voltage change occurs in the signal line and the Cs line related to the pixel electrode where the pen tip of the detection pen 310 is located, a voltage change also occurs in the detection voltage as shown in FIG.
[0280]
FIG. 96 shows the internal function of the control unit 9 for obtaining the position coordinates of the detection pen from the timing of voltage change occurring in the detection voltage. 96 in FIG. 96 is a waveform correction circuit for converting Vp into an easy-to-handle digital pulse signal, and 321 and 322 are counters with a clear function, such as 74HC163. Reference numerals 323 and 324 denote flip-flops that store and hold the outputs of the counters 321 and 322. The operation of the control unit 309 shown in FIG. 96 is shown in FIG. In FIG. 97, the outputs 321 to 324 are represented by decimal numbers, but in reality, they are binary numbers represented by a plurality of bits. The VP is converted to a 1 CLK digital pulse by the waveform correction circuit 320, and the counters 321 and 322 count the CLK after being cleared and output it to the flip-flops 323 and 324. The flip-flop 323 captures and holds the output of the counter 321 during the X-direction pen coordinate detection period and when Vpp is at a high level. The flip-flop 324 captures and holds the output of the counter 322 during the Y-direction pen coordinate detection period and when the Vpp is at a high level. Therefore, the values held in the flip-flops 323 and 324 vary depending on which pixel electrode the pen tip is placed on, and the flip-flop 323 holds data indicating pen coordinates in the X direction, and the flip-flop 324 holds in the Y direction. Holds data indicating pen coordinates. In this embodiment, F1 = 3 and F2 = 2 are held. However, when the pen tip is arranged on the pixel electrode related to s3 and cs2, F1 = 2 and F2 = 1 are held. That is, the values of F1 and F2 corresponding to the pen tip position are obtained. Although not shown, the control unit 309 determines the position of the pen tip from the values of F1 and F2, which are internal data, and sends data for displaying the position to the signal line driving circuit 304 and the gate line driving circuit 305. With the pen input display device according to the present invention, accurate coordinate detection is possible as described above.
[0281]
FIG. 98 is a view of the display device according to this example as viewed from the TFT substrate side. 98 shows a state when the pen tip 310 is arranged on the display device, and the dotted line in FIG. 98 shows the contact surface between the pen tip and the display device. In this embodiment, the sizes of the pixel electrode, signal line, gate line, and Cs line are 300 μm * 100 μm, gate line width 10 μm, signal line width 10 μm, and Cs line width 10 μm, as shown in FIG. The coupling capacity between each electrode and the pen tip of the display device depends on how much each electrode overlaps the contact surface between the pen tip and the display device shown in FIG. Because the capacity of the parallel plate type is generally expressed by the following equation:
C = ε0 εx S / d
ε0 = dielectric constant of vacuum
εx = Specific induction rate of insulator sandwiched between capacitor electrodes
S = area of the electrode
d = thickness of the insulator
The capacitance value can be increased by increasing the area of the electrode forming the capacitor.
[0282]
Therefore, when Cps, Cpc, Cplc, and Cpg are compared with each other, as apparent from FIG. 98, the overlapping area of the contact surface between the pen tip and the display device and the pixel electrode is overwhelmingly larger than the overlapping area of the other electrodes. For,
Cplc≈10 Cps≈30 Cpc≈60 Cpg
Cps = 0.1fF
It is. From the equations (5) and (6), the voltage change ΔVp generated in the detected voltage in this embodiment is

It is. Incidentally, the measured value was Vp = 38 mV. Although the measured value was lower than the theoretical value, although not shown in the figure, it is thought that the protective sheet was put on 1 and the thickness of the insulator was increased accordingly.
[0283]
The equivalent circuit between the electrodes of the detection pen and the display device in FIGS. 94 (b) and 94 (c) is as shown in FIG. Here, when VX4 is driven from VL to VH (signal line voltage change ΔVs = VH−VL), if the other electrodes are not in a floating state, Cpstotal is as follows.
[0284]
Cpstotal = Cps = 0.1fF
If Vcs3 is driven from VL to VH (Cs line voltage change ΔVcs = VH−VL) and the other electrodes are not in a floating state, Cpctotal is as follows.
[0285]
Cpctotal = Cpc = 0.03fF
Further, the voltage change (ΔVp) generated in Vp at this time is as follows.
[0286]

In actual measurement, these could not be detected due to power source noise such as a backlight (not shown) and 308, and coordinate detection could not be performed normally.
[0287]
So book Example The effect by can be confirmed.
[0288]
【The invention's effect】
According to the first embodiment of the present invention, it is not necessary to provide the coordinate detection tablet on the front or back of the display device independently of the display device, and the display device and the coordinate detection tablet can be formed on the same surface. The pen input integrated display device can be made lighter, thinner, and higher in image quality. The larger the display device is a few inches or larger, the more the number of parts required for pen input does not change. The effect of reducing the weight and thickness according to the invention is great.
[0289]
For example, the display device is effective when the diagonal is 12.1 inches XGA and the pixel pitch is 210 μm * 70 μm, or the display device is diagonal 40 inches and the pixel pitch is 630 μm * 210 μm. Particularly effective for molds with a size of 5.5 inches diagonal or larger (more effective for diagonals of 10 inches or larger, and more effective for diagonals of 20 inches or larger).
[0290]
Further, since the movement amount of the pen on the display device is instantaneously detected directly from the display device by the optical sensor of the pen, coordinate detection with high time resolution is possible. Therefore, when writing small characters on the display device quickly in handwriting input (when the size of the display device is 1 and writing characters less than 1/10 in size, etc.) The present invention is effective, and the present invention is effective when handwritten input is performed at a speed of 80 dots / second or more). The present invention is very effective.
[0291]
In addition, since it is possible to detect the amount of movement of the pen on the display device in the X direction and the amount of movement of the pen on the display device in the Y direction based on different spatial optical characteristics inherent in the display device surface, It is possible to more accurately detect whether the pen has moved in the X direction or the Y direction.
[0292]
In addition, since the light receiving surface of the light sensor of the pen has different lengths in the X direction and the Y direction on the display device, the light sensor is easily affected by the spatial optical characteristic difference in one direction of the display device. Therefore, it is possible to more accurately detect whether the pen has moved in the X direction or the Y direction.
[0293]
In addition, since the coordinates where the pen is arranged on the display device are detected by using the change in luminance of the display device due to the push-up voltage generated in the pixel electrode when the Cs line and the signal line of the display device are sequentially selected and driven, the display is displayed. Since there is no need to provide an array substrate for coordinate detection independently of the array substrate in the device, the display device and the coordinate detection tablet can be formed on the same surface, making it possible to reduce the weight and thickness of the pen input integrated display device. Because the coordinates are detected by using the luminance change of the display device due to capacitive coupling, the desired voltage can be instantaneously applied to the pixel electrode, and the variation of the switching element that drives the pixel electrode is not affected, Accurate coordinate detection is possible.
[0294]
Further, since the detected coordinates can be adjusted, the detection error generated due to the temperature characteristic of the response speed of the display device can be adjusted, and more accurate coordinate detection can be performed.
[0295]
In addition, since the push-up voltage is generated by the Cs line after the switching element arranged for each pixel electrode of the display device is turned off, the influence of the luminance change of the display device caused by writing the signal line voltage to the pixel electrode at the time of coordinate detection is affected. Since it is not received, more accurate coordinate detection is possible.
[0296]
Further, since the push-up voltage is generated by the signal line after the Cs line is disconnected from the Cs line drive means, the push-up voltage generated can be maintained without being influenced by the Cs line drive means.
[0297]
Therefore, it is possible to obtain a pen input integrated display device that realizes high image quality, light weight, thin shape, high time resolution, and high accuracy coordinate detection.
[0298]
According to the second embodiment of the present invention, even if the tilt of the pen and the display device in the pen input device changes, the tilt of the light receiving surface of the pen photosensor with respect to the display device is kept from 0 to 45 degrees. Therefore, the light energy incident on the light receiving surface does not change greatly, and as a result, the malfunction of the optical sensor caused by the tilt of the pen and the display device can be suppressed, and more accurate coordinate detection is possible.
[0299]
According to the third and fourth embodiments of the present invention, the correction means corrects the pen coordinates based on the movement speed, the change in the movement speed, the movement vector, and the change in the movement vector, and the movement speed increases. Regardless of whether the pen coordinate where the movement vector changes is deleted, the movement speed and movement vector immediately before deletion are compared with the movement speed and movement vector after deletion, and the movement vector after deletion and the movement vector immediately before deletion are the same. Alternatively, if the movement speed after the deletion is slower or almost equal to the movement speed immediately before the deletion, the pen coordinates after the deletion are not deleted, so that the correction based on the ergonomics of the pen coordinates can be performed.
[0300]
According to the fifth embodiment of the present invention, when the pen coordinate is detected by driving the signal line, at least one of the gate line, the Cs line and the counter electrode is brought into a floating state, and the pen line is driven by driving the gate line. At least one of the signal line, the Cs line and the counter electrode is in a floating state when detecting the signal, and at least one of the signal line, the gate line and the counter electrode is in a floating state when detecting the pen coordinates by driving the Cs line Therefore, the detection pen can have a larger coupling capacity with each electrode of the display device.
[0301]
For this reason, according to the fifth embodiment, good-looking handwriting input can be performed with fine handwriting and quick handwriting input, and accurate handwriting input can be performed even if the signal line, gate line, and Cs line become thin.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a pen input integrated display device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an outline view of a pen input integrated display device according to the first embodiment;
FIG. 3 is a cross-sectional view of the pen input device according to the first embodiment.
FIG. 4 is a view showing a state of light reception of a pen input device in the first embodiment.
FIG. 5 is a view showing a structure of a counter substrate according to the first embodiment.
FIG. 6 is a view showing a photodiode array structure according to the first embodiment;
FIG. 7 is a view showing a photodiode array structure according to the first embodiment;
FIG. 8 is a view showing a photodiode array structure according to the first embodiment;
FIG. 9 is a view showing an equivalent circuit of the photodiode array according to the first embodiment;
FIG. 10 is a diagram showing a configuration of a pen input device according to the first embodiment.
FIG. 11 is a diagram showing a configuration and output waveform of a pen system reset unit according to the first embodiment;
FIG. 12 is a diagram showing a configuration of an optical signal conversion basic circuit according to the first embodiment.
FIG. 13 is a graph showing the characteristics of the photodiode according to the first embodiment.
FIG. 14 is a configuration diagram of a movement amount detection unit according to the first embodiment.
FIG. 15 is a configuration diagram of a Y-direction movement amount detection unit according to the first embodiment.
FIG. 16 is a configuration diagram of a level shift unit according to the first embodiment;
FIG. 17 is a view showing an operation example of a level shift unit according to the first embodiment;
FIG. 18 is a configuration diagram of a serial signal generator according to the first embodiment.
FIG. 19 is a configuration diagram of a serial signal generator according to the first embodiment.
FIG. 20 is a view showing the operation of a one-third pulse circuit according to the first embodiment;
FIG. 21 is a view showing the operation of the serial signal generator according to the first embodiment.
FIG. 22 is a diagram showing a configuration of a parallel signal generator according to the first embodiment.
FIG. 23 is a diagram showing a configuration of a parallel signal generator according to the first embodiment.
FIG. 24 is a diagram showing a circuit configuration example of a full adder according to the first embodiment;
FIG. 25 is a view showing an operation example of a parallel signal generator according to the first embodiment;
FIG. 26 is a diagram showing a configuration of an initial coordinate detection unit according to the first embodiment.
FIG. 27 is a diagram showing a configuration of a Y-direction initial coordinate detection unit according to the first embodiment.
FIG. 28 is a view showing the operation of the Y-direction initial coordinate detection unit according to the first embodiment.
FIG. 29 is a view showing the operation of a rising edge detection circuit according to the first embodiment;
FIG. 30 is a diagram showing a configuration of an X drive unit according to the first embodiment.
FIG. 31 is a view showing an operation example of an X drive unit according to the first embodiment;
FIG. 32 is a diagram showing a configuration of an X-direction initial coordinate detection unit according to the first embodiment.
FIG. 33 is a view showing the operation of the X-direction initial coordinate detection unit according to the first embodiment.
FIG. 34 is a diagram showing a configuration of a Y-coordinate detection unit according to the first embodiment.
FIG. 35 is a diagram showing a configuration of a Cs line driving unit according to the first embodiment;
FIG. 36 is a view showing the operation of the Cs line driving unit according to the first embodiment;
FIG. 37 is a view showing the operation of the pulse width modulation circuit according to the first embodiment;
FIG. 38 is a view showing the operation of the gate line driving section 3 according to the first embodiment;
FIG. 39 is a view showing the operation of the signal line driver according to the first embodiment.
FIG. 40 is a view showing a position of a pen tip on the display device according to the first embodiment.
FIG. 41 is a view showing pixel electrode voltage timing according to the first embodiment;
FIG. 42 is a diagram showing VT characteristics of the display device according to the first example.
FIG. 43 is a view showing a pixel capacity model according to the first embodiment;
44 is a diagram showing the relative output of the pack light, the transmittance characteristics of each colored layer, and the light receiving sensitivity characteristics of the photodiode according to the first embodiment. FIG.
FIG. 45 is a view showing a change in received light of the photodiode according to the first embodiment.
FIG. 46 is a graph showing the response speed of TN liquid crystal, ferroelectric liquid crystal, and antiferroelectric liquid crystal.
47 is a view showing the operation of the Y-direction initial coordinate detection unit according to the first embodiment. FIG.
FIG. 48 is a view showing a pixel capacitance model when the output of the Cs line driving unit according to the first embodiment is high impedance and all TFTs of the array substrate are turned off.
49 is a view showing the operation of the X-direction initial coordinate detection unit according to the first embodiment. FIG.
FIG. 50 is a view showing a light receiving component in consideration of a transmittance characteristic of a black matrix and a light receiving sensitivity characteristic of a photodiode on the black matrix according to the first embodiment.
FIG. 51 is a view showing the arrangement state of photodiodes according to the first embodiment;
FIG. 52 is a view showing a light receiving state of each light receiving surface in FIG. 51A according to the first embodiment;
FIG. 53 is a view showing a light receiving state of each light receiving surface in FIG. 51B according to the first embodiment;
54 is a view showing the structure of the array substrate 8 and the arrangement of the black matrix according to the first embodiment. FIG.
FIG. 55 is a view showing the position of a pen tip on the display device according to the first embodiment;
FIG. 56 is a view showing the position of a pen tip on the display device according to the first embodiment;
FIG. 57 is a view showing the position of a pen tip on the display device according to the first embodiment;
FIG. 58 is a view showing a change over time in relative illuminance of each light receiving surface according to the first embodiment;
FIG. 59 is a diagram showing a change over time in the relative output of the optical signal converter according to the first embodiment;
FIG. 60 is a view showing a change over time in the output of each level shift unit according to the first embodiment;
61 is a view showing the operation of the serial signal generating unit according to the first embodiment; FIG.
FIG. 62 is a view showing the operation of the parallel signal generator and the operation of the Y coordinate detector according to the first embodiment.
63 is a view showing the operation of the serial signal generation unit according to the first embodiment; FIG.
FIG. 64 is a view showing the operation of the parallel signal generation unit and the operation of the X coordinate detection unit according to the first embodiment;
FIG. 65 is a diagram showing a pen input device according to a second embodiment of the present invention.
66 is a view showing a pen input device according to the second embodiment; FIG.
67 is a diagram showing a pen input device according to the second embodiment; FIG.
FIG. 68 is a diagram showing a pen input device according to the second embodiment;
FIG. 69 is a diagram showing a pen input device according to a third embodiment of the present invention.
FIG. 70 is a view showing the relationship between the display device 10 ′ and the DX and DY signals according to the third embodiment;
71 is a diagram showing a state of handwriting input according to the third embodiment; FIG.
FIG. 72 is a view showing a state of handwriting input according to the third embodiment;
FIG. 73 is a view showing a handwritten input result when there is no effect of the present invention according to the third embodiment;
FIG. 74 is a diagram showing a time relationship with pen input coordinate data DX, DY according to the third embodiment;
FIG. 75 is a diagram showing a configuration of a pen speed detection unit according to the third embodiment;
FIG. 76 is a diagram showing a configuration of a vector change detection unit according to the third embodiment;
77 is a diagram showing a definition of a movement vector direction corresponding to FIG. 73 according to the third embodiment; FIG.
78 is a view showing the operation of the vector change detecting unit according to the third embodiment; FIG.
FIG. 79 is a diagram showing operations of a pen speed detection unit, a vector change detection unit, and a correction unit according to the third embodiment.
FIG. 80 is a diagram showing a configuration of a correction unit 172 according to the third embodiment.
FIG. 81 is a diagram showing a configuration of a correction unit 172 according to the third embodiment.
FIG. 82 is a view showing the effect of the present invention according to the third embodiment.
FIG. 83 is a block diagram of a pen input device according to a fourth embodiment of the present invention.
FIG. 84 is a view showing the principle of pen coordinate detection according to the fourth embodiment;
FIG. 85 is a diagram showing a configuration of an impedance converter 8 according to the fourth embodiment;
86 is a view showing control of sw1 to sw4 according to the fourth embodiment. FIG.
87 is a view showing an equivalent circuit of FIG. 84 (c) according to the fourth embodiment.
FIG. 88 is a view showing an equivalent circuit of FIG. 84 (c) according to the fourth embodiment.
FIG. 89 is a block diagram of a pen input device according to a fifth embodiment of the present invention.
FIG. 90 is a view showing a driving sequence of the pen input device according to the fifth embodiment;
FIG. 91 is a diagram showing a configuration of an X drive circuit according to the fifth embodiment;
FIG. 92 is a diagram showing a configuration of a Cs drive circuit according to the fifth embodiment;
FIG. 93 is a diagram showing operations of the X drive circuit and the Cs drive circuit according to the fifth embodiment 1;
FIG. 94 is a view showing a state in which the detection pen is arranged on the display device in the fifth embodiment.
FIG. 95 is a diagram showing a pen coordinate detection method in the fifth embodiment;
FIG. 96 is a view showing a pen coordinate detection method in the fifth embodiment;
FIG. 97 is a view showing a pen coordinate detection result in the fifth embodiment;
98 is a view showing the structure of the array substrate in the fifth embodiment; FIG.
99 is a view showing an equivalent circuit of the coupling capacitance in the fifth embodiment; FIG.
FIG. 100 is a diagram for illustrating a conventional example.
FIG. 101 is a diagram for illustrating a conventional example.
[Explanation of symbols]
30 ... colored layer
33 ... Photodiode array substrate
44. Operational amplifier
66, 193 ... D flip-flop with clear function
67, 68, 184, 185, 231, 232 ... Counter
73-73, 237-240 ... Full adder
88, 96, 175, 178 ... Comparator
87, 95 ... operational amplifier
DFA to DFF ... Photodiode

Claims (5)

In a pen input integrated display device including a pen input device and a display device,
The pen in the pen input device includes a light sensor,
Movement amount detecting means for detecting the movement amount of the pen moved on the display device by detecting the light transmittance of the surface that changes corresponding to the position change on the surface of the display device by the optical sensor. A pen input integrated display device characterized by comprising: In a pen input integrated display device including a pen input device and a display device,
The pen in the pen input device includes a light sensor,
And a movement amount detecting means for detecting the movement amount of the pen moved on the display device by detecting a difference in light transmittance between a light shielding portion and an opening disposed in the display device by the light sensor. A pen input integrated display device characterized by that. Contact Keru pen to the input device, the housing of the pen, via a buffer mechanism provided with a light receiving portion which is connected to the housing, so that the light receiving surface of the light receiving portion is parallel to the display device surface 3. The pen input integrated display device according to claim 1, wherein the pen input integrated display device is controlled.   4. The pen input integrated display device according to claim 3, wherein the buffer mechanism includes a spring.   4. The pen input integrated display device according to claim 3, wherein the buffer mechanism includes rubber.

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