JP3865756B2 - Network compatible image transmission device - Google Patents

Description

  The present invention relates to a network-compatible image transmission apparatus.

  The network-compatible image transmission device obtains image data by A / D (Analog to Digital) conversion of a video signal captured by an imaging device such as a camera. This image data is composed of each frame of the video signal, and this is compressed by an image encoding method, for example, JPEG (Joint Photographic Experts Group). The compressed image data obtained as a result is distributed to a receiving apparatus connected to a transmission medium such as a LAN (Local Area Network) or a WAN (Wide Area Network) network. Further, the network-compatible image transmission apparatus receives compressed image data from a transmission medium such as a network, expands it, and outputs it as image data or displays it on a monitor.

  In a network-compatible image transmission apparatus, a CPU (Central Processing Unit) is adopted as a data processing unit in order to realize low cost and multiple functions. For example, the CPU reads compressed image data from a JPEG compression circuit that compresses image data using the image encoding method JPEG, and stores it in a storage device such as a memory. Further, the CPU reads the compressed image data stored in the storage device, formats it into a predetermined format, stores it again in the storage device, and transfers it to a network control circuit that controls transmission / reception of data by a transmission medium at a predetermined timing. . The network control circuit converts the formatted compressed image data into data reconstructed into a format corresponding to the communication protocol of the network, and transmits the data to the network.

  As described above, in the data processing of the CPU, the compressed image data is fetched from the JPEG compression circuit, the data is transferred for storage in the storage device, the compressed image data is fetched, formatted into a predetermined format, and written again into the storage device. And data transfer to a network control circuit of compressed image data formatted in a predetermined manner. In order to perform such data transfer at high speed, a plurality of dedicated bus systems may be employed. For example, in this dedicated bus system, in addition to the system bus for the CPU to access its own execution instruction data and data to be processed, the CPU can exchange data with a JPEG compression circuit or a network control circuit at the same time. Some have a dedicated bus to enable this.

  Recent CPUs have a plurality of DMA (Direct Memory Access) transfer functions for executing data access between an internal buffer and an external device independently from the execution of instructions of the CPU itself. And a plurality of interfaces for transmitting and receiving data in a state where no load is applied.

  The CPU can be connected to the JPEG compression circuit or the network control circuit via the dedicated bus by using this DMA transfer function and interface. When a predetermined amount of data is stored in the built-in buffer by the DMA transfer function, the CPU reads the data from the built-in buffer and performs predetermined data processing and stores it in the storage device, or at the same time, the network control circuit by another DMA transfer function It is also possible to exchange predetermined processed data with the.

  However, the multiple dedicated bus method not only increases the mounting area of the signal wiring of each bus, but also increases various loads such as stray capacitance generated in the signal wiring of each dedicated bus. This also means that the drive current for driving with the bus increases. In order to avoid an increase in mounting area and drive current due to having such a dedicated bus, the above-described data transfer is performed in a time-sharing manner using a CPU system bus instead of a dedicated bus system. In this method, the system bus is responsible for data transfer such as a JPEG compression circuit, a network control circuit, and a storage device.

  The CPU occupies the system bus in a time-sharing manner and efficiently performs the above data transfer so that the compressed image data from the JPEG compression circuit is not missed and the distribution data to the user is not interrupted. Therefore, process scheduling is executed. Further, the CPU must cope with irregular processing request events of input / output, and data transfer and data processing are temporarily interrupted, and the processing efficiency of the CPU decreases.

  Data transfer on the system bus along with the adoption of a CPU capable of higher-speed processing and a storage device capable of higher-speed access (for example, a memory capable of clock-synchronized burst transfer) to compensate for a decrease in CPU processing efficiency The speed can be increased. However, if the system bus speed is increased, data errors may occur in the signal transmission path due to the relationship between the signal rise or fall time and the signal propagation time, and the system bus signal wiring. Effects such as reflection and crosstalk noise appear as signal waveform distortion.

  The occurrence of reflection causes overshoot and undershoot waveform distortion in the transmission signal, causes a data error exceeding the threshold for identifying the signal, and causes crosstalk noise to cause unstable operation. Become.

  Such a phenomenon will be described with reference to FIGS. It is assumed that part of the configuration of the bus through which data is exchanged is as shown in FIGS. FIG. 5A shows a configuration in which a driver 40d and receivers 40r,..., 40n are connected by a signal line 40s. 5B is the same configuration as FIG. 5A with a distance dl from FIG. 5A, and the driver 41d, the receivers 41r,..., 41n, and the signal line 41s are connected to the bus. Part is configured. When the pulse waveform of FIG. 6A is at the input point a of the driver 40d, the pulse waveform as shown in FIG. 6B is obtained at the output point b of the driver 40d.

  Here, when transmitting a signal at high speed, it is necessary to increase the driving capability of the driver 40d to shorten the rise time tr or the fall time tf of the pulse waveform driven on the bus. Then, the round trip time τ 2 required for the driven pulse waveform signal from the driver 40d to reciprocate the signal line 40s to the receiver 40r is the rise time of the pulse waveform signal driven by the driver 40d shown in FIG. May be longer than tf. In such a time relationship of τ> tr, tf, after the signal falls, it reaches the receiving end (input point c) of the receiver 40r and is reflected, so at the input point c as shown in FIG. Undershoots 42u and 43u and overshoots 42v and 43v are generated as if they wavy after falling. The same phenomenon occurs after the signal rises. When the receiver 40r receives a signal having a pulse waveform as shown in FIG. 6C and exceeds the threshold of the signal level of the receiver 40r in the time period of occurrence of the overshoots 42v and 43v, as shown in FIG. 6D. Signals as noises 44n and 45n are generated. As a result, a data error or an unstable factor of circuit operation occurs on the receiving side. Although the generation of noise after the fall of the signal has been described, the same data error and the unstable factor of the operation of the circuit occur even when the pulse waveform is distorted after the rise of the signal.

  Further, in FIG. 5B, when the signal state is at a zero level, the pulse waveform of FIG. 5A is caused to rise or fall at high speed, or the accompanying undershoot or overshoot. ), The crosstalk noises 46n,..., 50n as shown in FIG. When the crosstalk noises 46n,..., 50n exceed the signal level threshold of the receiver 41r, signals as noises 51n, 52n, 53n are generated as shown in FIG. Even in this case, on the receiving side, these noises may cause data errors or cause unstable circuit operation. For example, when the noises 44n and 45n in FIG. 6D or the noises 51n, 52n, and 53n as shown in FIG. 6G are generated on the signal line of the bus to the storage device, the data of logic “0” is originally stored. When data is written, a data error occurs in which data of logic “1” is written. Alternatively, when noise occurs on the control signal line of the memory, indefinite control or data access is performed, and if other connection circuits occupy the bus at this time, the signals on the bus collide and the circuit It will cause unstable operation.

  As described above, although the speed of signal transmission has been increased, these problems have occurred and it has not been possible to realize a network-compatible image transmission apparatus capable of sufficiently increasing the speed. As a result, the upper limit of the amount of data that can be delivered by the camera via the network is kept low, and the delivery service is limited.

  For the CPU, as described above, data processing and data transfer of compressed image data, or input / output processing is a large processing load. For example, in a conventional network-compatible image transmission apparatus, the amount of compressed image data with a frame rate of 30 fps (frames per second) that can be delivered to one user is approximately 3.6 Mbps (Megabits per second) (0.12 Mb / frame × 30 frames / sec). ), The number of users that can be distributed simultaneously is limited to 2 or less, and the maximum data amount that can be distributed is about 7.2 Mbps.

  Under such CPU processing capability, in order to obtain a high-quality playback image on the receiving side, if the amount of data distributed to one user is doubled, the number of users who can simultaneously distribute 30 fps compressed image data is At most, the user becomes one user and the image distribution service is lowered. Conversely, if the number of users that can be distributed is doubled to 4 users, the amount of data that can be distributed per user is halved, and only low-quality reproduced images can be obtained. Alternatively, there is a method of reducing the frame rate from 30 fps to half of 15 fps. This method ensures the image quality of each frame although there is a frame drop. However, this method also has a problem that it becomes an unnatural reproduction image in a moving image.

The above-described prior art has the following problems, and the amount of data that can be distributed by an image captured by a camera via a network is limited, which limits the distribution service.
That is, a compressed image data amount of 3.6 Mbps or more per user cannot be distributed to at least four users at the same time. In addition, in order to provide a distribution service for higher-quality reproduced images, it is impossible to distribute compressed image data of 7.2 Mbps or more, which is doubled per user to at least two users at the same time.

  An object of the present invention is to provide a network-compatible image transmission apparatus that can realize simplification of the structure of a housing.

  In order to achieve the above object, in the network-compatible image transmission device according to the present example, a video processing unit that processes a video signal from the imaging device to generate image data, and transmission of the image data via the network are controlled. A network control unit, a central processing unit for processing the image data, and a storage unit for storing the image data from the video processing unit, the central processing unit is disposed at a substantially central portion on the mounting substrate, The bus connecting the central processing unit, the storage unit, the network control unit, and the video processing unit in series is configured to be signal-wired so as to spread toward the outer periphery starting from the central processing unit. .

  According to the present invention, a video processing unit that processes video signals from an imaging device to generate image data, a network control unit that controls transmission of image data via a network, and a central processing unit that processes image data And a storage unit for storing image data from the video processing unit, and the central processing unit is arranged at a substantially central part on the mounting substrate, and the central processing unit, the storage unit, the network control unit, and the video processing unit are in series. Since the bus to be connected is a network-compatible image transmission device in which signal wiring is performed so as to spread toward the outer periphery starting from the central processing unit, there is an effect that simplification of the structure of the housing can be realized.

The network-compatible image transmission apparatus of the present invention will be described below.
First, the configuration and operation of the network-compatible image transmission apparatus of the present invention will be described based on the conceptual diagram shown in FIG. Reference numeral 30 denotes a network-compatible image transmission apparatus, 1 denotes a CPU, 5 denotes a ROM (Read Only Memory) in which processing program data describing a processing procedure of the CPU 1 is stored, and 3 denotes processing of compressed image data or processing program data of the CPU 1 A RAM (Random Access Memory) 4 transferred from the ROM 5 and stored before the start, 4 is a central control circuit for controlling access to the CPU 1, the RAM 3, the ROM 5, and each circuit in the peripheral circuit block 32 described later, 2 and 6 Are a peripheral circuit bus buffer and an extended external bus buffer having a driver function and a receiver function for transmitting / receiving data signals between an external peripheral block 32 and a CPU block 31, which will be described later. These connection circuits are connected to the series without any branch point in the order of the RAM 3, the ROM 5, the central control circuit 4, the peripheral circuit bus buffer 2, and the extended external bus buffer 6 starting from the CPU 1 on the CPU bus A.

  Hereinafter, a series connection such as “one-stroke drawing” in which each connection circuit has no branch point is referred to as a series connection. By connecting these connection circuits in series, it is possible to suppress signal reflection and crosstalk noise during high-speed signal transmission. This is because if the bus is made into a branched wiring pattern, the transmission pattern characteristic impedance of the wiring pattern is discontinuous at the branch point, and signal reflection and crosstalk noise occur during high-speed signal transmission.

  Needless to say, the RAM 3 can be replaced with an SDRAM (Synchronous Dynamic RAM) capable of high-speed access by clock-synchronized burst transfer, and the ROM 5 can be replaced with a flash memory capable of remotely rewriting processing program data of the CPU 1.

  Further, in FIG. 3, reference numeral 14 denotes a camera, and 9 denotes a serial control circuit for performing imaging control (zoom, focus, etc.) of the camera 14 by a serial communication signal F (RS-232C, RS-485, etc. are given as serial transmission standards). , 8 is a JPEG compression circuit for A / D converting the video signal E input from the camera 14 and compressing the compressed image data into compressed image data of the image encoding method JPEG, and 7 is transferred from the CPU 1. A network control circuit that receives data in a predetermined format of compressed image data and sends data D to the network 40 in accordance with a communication protocol corresponding to the network 40. Reference numeral 10 denotes an operation state of the network-compatible image transmission apparatus 30 (for example, access of a distribution request). Number, distribution overflow, malfunction etc.) LED (Light Emitting Diode) lighting or LED circuit to notify the apparatus operator due flashing, 11 is a switch circuit for this information is read by the set specified information in the operation or function of the network video transmission device 30 CPU 1.

  The operation or function designation information includes, for example, the normal or test operation mode designation or reset request of the network-compatible image transmission apparatus 30, the number of simultaneous delivery users, the maximum transmission speed per user, and the like. These connection circuits are connected in series by the peripheral circuit bus B, and are responsible for data exchange from an external device of the network-compatible image transmission apparatus 30 or a network. Needless to say, the JPEG compression circuit 8 can be replaced with an MPEG compression circuit that performs moving image compression by a moving picture experts group (MPEG).

The external peripheral block 32 includes expansion connectors 12 and 13.
These connection circuits are connected in series by an extended external bus C separately from the peripheral circuit bus B. Optional expansion boards can be mounted on the expansion connectors 12 and 13. For example, a modem board that can be connected to a telephone line, an ISDN board that can be connected to an ISDN (Integrated Services Digital Network) line, a contact input / output board for external device control, and the like can be mounted.

  Further, the extended external bus C is also connected in series with a JPEG decompression circuit 25 for decompressing compressed image data compressed by the image coding method JPEG and a termination resistor 27 described later. The CPU 1 and the JPEG expansion circuit 25 input compressed image data from the network 40 and expand it, and display the expanded reproduced image on the monitor 33. Alternatively, it is also possible to output or input the compressed image data input from the network 40 or the decompressed image data to the expansion boards of the expansion connectors 12 and 13. Needless to say, the JPEG decompression circuit 25 can be replaced with an MPEG decompression circuit in a system using the moving image compression method MPEG. Also, voice can be handled in the same manner.

  The expansion external bus C, which is different from the peripheral circuit bus B, is that when an extension board is connected to the peripheral circuit bus B, other connections including the peripheral circuit bus buffer 2 connected to the peripheral circuit bus B are provided. This is to avoid this point because the driver of the circuit drives a large load and the driving capability of each driver of the connection circuit is required to be considerably high. If the driver of each connection circuit drives a large load with a considerably high driving capability, the drive current flows instantaneously, so the reference based on reflection on the bus, crosstalk noise, unwanted radiation, or feedback current to the drive source Potential fluctuations and the like are likely to occur, and high-speed signal transmission by the peripheral circuit bus B becomes difficult. For this reason, the two buffers 2 and 6 suppress the signal transmission drive capability of each connection circuit as much as possible, thereby suppressing the influence of a large drive current and facilitating the realization of high-speed signal transmission. Similarly, the CPU bus A and the peripheral circuit bus B and the extended external bus C are separated from each other by connecting each connection circuit connected to the peripheral circuit bus B and the extended external bus C to the CPU bus A. This is because, if the connection is to be made, it becomes necessary for the driver of the other connection circuit including the CPU 1 to drive a higher load, so that high-speed signal transmission on the CPU bus A becomes impossible.

  For the reasons described above, data exchange between the buses is performed via the peripheral circuit bus buffer 2 or the extended external bus buffer 6. Each connection circuit is connected to each bus to suppress the drive capability of the driver of each connection circuit in each bus as much as possible. Each connection circuit is connected in series to reduce drive current and avoid discontinuity in the transmission line characteristic impedance to reduce reflection on the bus, unwanted radiation, or fluctuations in the reference potential due to feedback current to the drive source. I tried to suppress it as much as possible. Needless to say, the bus buffers 2 and 6 can have a waveform shaping function.

  In FIG. 3, reference numeral 21 denotes a series resistor inserted as a circuit element for suppressing signal reflection or crosstalk noise, which is inserted in series with a signal wire connected in series at the start point of the CPU bus A located near the CPU 1. A terminal resistor 22 is connected to a series-connected signal wiring located at the end point of the CPU bus A and serves as a circuit element that suppresses signal reflection and crosstalk noise. Similarly, 23 is a series resistance inserted as a circuit element that suppresses signal reflection, crosstalk noise, and the like inserted in series at the start point of the peripheral circuit bus B located near the peripheral circuit bus buffer 2 in series connection signal wiring. A terminating resistor 24 is connected to a series-connected signal wiring at the end point of the peripheral circuit bus B and serves as a terminating resistor as a circuit element for suppressing signal reflection, crosstalk noise, and the like.

Next, the operation of the network-compatible image transmission apparatus 30 of the present invention shown in FIG. 3 will be described below.
During an initial operation after operating power is supplied to the network-compatible image transmission device 30, the central control circuit 4 writes the processing program data of the CPU 1 from the ROM 5 to the RAM 3, and each process is started under the control of the CPU 1. .

  The CPU 1 sets the preset control information for setting the imaging state (zoom, pan, tilt, etc.) of the camera 14 or the control information of the camera 14 input from another location via the network 40 in the serial control circuit 9. The camera 14 controlled by these control information images the required visual field range, and supplies a 30 fps video signal E to the JPEG compression circuit 8 as an output thereof. The JPEG compression circuit 8 A / D converts a 30 fps video signal E and compresses the data. For example, one frame of image data is compressed into compressed image data having a data amount of at least 0.12 Mb per frame.

  The CPU 1 controls the JPEG compression circuit 8 together with the central control circuit 4 to transfer the compressed image data to the peripheral circuit bus B, the peripheral circuit bus buffer 2, and the data transfer speed at a rate of 1/30 fps at least 3.6 Mbps. The data is transferred and stored in the RAM 3 via the CPU bus A. The CPU 1 formats the stored compressed image data in a predetermined format and then stores it again in the RAM 3.

  Then, the CPU 1 controls access to the devices coupled to the buses A, B, and C together with the central control circuit 4. For example, in response to a user distribution request sent via a network, if the number of users is 4, predetermined formatted compressed image data is transferred at a data transfer rate of at least 3.6 Mbps × 4 = 14.4 Mbps. The data is read from the RAM 3 and transferred to the network control circuit 7 via the CPU bus A, the peripheral circuit bus buffer 2 and the peripheral circuit bus B. Here, the processing scheduling of the CPU 1 or the execution scheduling of the DMA transfer function is adjusted so that the data transfer does not compete with the transfer of the compressed image data from the JPEG compression circuit 8 described above. The network control circuit 7 converts the compressed image data formatted into a predetermined format into a format conforming to the communication protocol of the network, and sends it as data D to the network 40.

  4, each connection circuit and data transfer from the data transfer of the compressed image data of the JPEG compression circuit 8 to the RAM 3 to the transmission of the image data of 4 users to the network 40 in the network compatible image transmission apparatus 30 of the present invention. An example of timing will be described.

  In FIG. 4, the number of video frames of the camera 14 is FPS (fps), and the time of one frame is 1 / FPS (sec) (for example, if the number of frames FPS is 30 fps, the time of one frame is about 33 ms). . In FIG. 4, for ease of explanation, the time of one frame is divided into eight sections at times tx0, tx1, tx2,..., Tx7 (where x = 1, 2, 3, ...). Further, it is assumed that the network-compatible image transmission device 30 operates in synchronization with the frame period 1 / FPS (sec) after starting the operation at time t10. Further, it is assumed that the camera 14 captures an image by the progressive scan method.

  The JPEG compression circuit 8 sequentially compresses the video signal from the camera 14 at a predetermined timing and temporarily stores it as compressed image data A1. When the time t14 corresponding to half the time of one frame period is reached, the central control circuit 4 stores the compressed image data A1 stored in the JPEG compression circuit 8 up to the half time of one frame period in the RAM 3 In order to transfer the data, the control signal for starting the transfer is supplied to each connection circuit (not shown). When the CPU 1 receives this control signal, it reads the compressed image data A1 via the peripheral circuit bus B, the peripheral circuit bus buffer 2, and the CPU bus A and stores them in the RAM 3. Here, the compressed image data A1 may be stored in the RAM 3 by a DMA transfer function not via the CPU 1.

  When the storage of the compressed image data A1 in the RAM 3 is completed, the CPU 1 generates data FA1 in which the compressed image data A1 is in a predetermined format in accordance with the four users who are distribution destinations. The data FA1 is stored in the RAM 3 via the CPU bus A. The data FA1 is transferred to the network control circuit 7 via the RAM 3, the CPU bus A, the peripheral circuit bus buffer 2, and the peripheral circuit bus B by the CPU 1 in the time zone before and after the time t17. The network control circuit 7 directs the data FA1 to the four users who are the distribution destinations according to a predetermined communication protocol (data D is the distribution data of the four users, and “1, 2, 3, 4 in FIG. 4H). (Indicated by “”).

  The elapsed time of the next frame No. 2 reaches the start time t20 of the frame No. 2, the central control circuit 4 stores the frame number stored in the JPEG compression circuit 8. In order to transfer the compressed image data A2 of the latter half of one video signal to the RAM 3, a transfer start control signal is supplied to each connection circuit. Thereafter, the CPU 1 and the central control circuit 4 transfer, store and format the compressed image data (B1, B2, C1, C2,...) And the formatted data (FA2, FB1,. FB2, FC1,...) Are stored in the RAM 3. The data FA2 is transferred to the network control circuit 7 by the CPU 1 in the time zone before and after the time t23. The network control circuit 7 sends the data FA2 to the network 40 as data D in accordance with a predetermined communication protocol toward the four users as distribution destinations. Thereafter, the compressed image data of the video signal of each frame is transferred to the RAM 3 via the JPEG compression circuit 8, the peripheral circuit bus B, the peripheral circuit bus buffer 2, the CPU bus A, or the CPU 1 with the above operation and timing. Stored. Thereafter, the compressed image data stored in the RAM 3 is read from the RAM 3 as data formatted in a predetermined manner, and transferred to the network control circuit 7 via the CPU bus A, the peripheral circuit bus buffer 2 and the peripheral circuit bus B. Is done. Such a series of processes is repeated.

  As described above, in the transfer of the compressed image data from the JPEG compression circuit 8 and the distribution data to the network control circuit 7, no signal collision occurs on the CPU bus A, the peripheral circuit bus buffer 2, and the peripheral circuit bus B. Thus, each data transfer is performed in a time-sharing manner under the process scheduling of the CPU 1 or the execution scheduling of the DAM transfer function and the control of the central control circuit 4.

  The CPU 1 must execute irregular processing in addition to periodic control of access control and transfer of these data. When receiving a camera control request (zoom, pan, tilt, etc.), the CPU 1 sets camera control information in the serial control circuit 9. In addition, a control signal for LED display for notifying the outside of the operation state such as the number of users of the distribution request and the data transfer speed is set in the LED circuit 10. Furthermore, in preparation for operation mode switching and operation parameter change, external information (normal or test operation mode designation or reset request, number of simultaneous delivery users, maximum transmission speed per user, etc.) is switched. 11, the operation mode and parameter change processing must be performed.

Further, if the extension board 12 is mounted on the expansion connectors 12 and 13, the CPU 1 needs to perform data access control and data transfer processing with these boards.
Next, the bus buffers 2 and 6 will be described in detail. High-speed data transfer of at least 14.4 Mbps needs to be performed on the buses A, B, and C so that four users can receive a high-quality reproduced image distribution service at the same time. For example, if a long signal wiring from the CPU 1 to the switch circuit 11 is connected by one bus, signal distortion is likely to occur, and the upper limit of data transfer is determined. In order to raise this upper limit, the network-compatible image transmission device 30 is divided into a CPU block 31 and an external peripheral block 32 by the peripheral circuit bus buffer 2 and the extended external bus buffer 6 for the reasons described above. Each connection circuit in each of the blocks 31 and 32 is connected to each other by buses A, B, and C through series connection signal wiring.

  Then, as shown in FIG. 3, by connecting each connection circuit with the bus for each block in the bus buffer 2 or 6, the signal wiring is shortened and the round trip time of the signal is shortened (the signal rise time tr). By making the fall time tf> the round trip time τ, the influence of reflection and the like can be reduced), and there is no inadvertent branch signal wiring in the series connection, and the transmission line characteristic impedance can be made constant. The driving load is reduced and the driving current is reduced. As a result, signal reflection, crosstalk noise, unwanted radiation, or fluctuations in the reference potential due to feedback current to the drive source are suppressed.

  Accordingly, the upper limit of the data transfer rate can be increased in each of the blocks 31 and 32. Further, a series resistor 21 as a damping resistor of several ohms to several tens of ohms in series with the start point of the CPU bus A near the CPU 1 is equivalent to the transmission line characteristic impedance of the CPU bus A at the end point of the CPU bus A. By arranging the termination resistor 22 of several tens ohms to several hundreds ohms as a simple circuit element between the power source and the ground, the generation of transmission signal reflection, crosstalk noise, and the like can be further suppressed. Thus, the upper limit of the data transfer rate can be increased. Similarly, in the buses B and C, series resistors 23 and 26 as damping resistors and termination resistors 24 and 27 as circuit elements equivalent to the transmission path characteristic impedance of each bus are arranged.

Next, the implementation of the signal wiring of the series connection of each connection circuit and the bus connecting the connection circuits, which is a second means for increasing the data transfer speed, will be described with reference to FIGS.
FIG. 2 is a conceptual diagram showing a mounting system of signal wiring for series connection of buses connecting the connection circuits of FIG. 3 described above. FIG. 2 shows that the CPU 1 is arranged substantially at the center, and the buses are spirally connected in series so as to spread from the start point toward the outer periphery. Similarly to FIG. 3, the CPU bus A, the peripheral circuit bus B, and the extended external bus C exchange data via the peripheral circuit bus buffer 2 and the extended external bus buffer 6. FIG. 1 shows an example of a mounting structure in which each connection circuit of FIG. 3 and signal connection of series connection of buses are arranged on a printed circuit board in accordance with the mounting method of signal wiring of series connection of each bus of FIG.

  FIG. 1 is a diagram showing a mounting structure of the present invention. In FIG. 1, reference numeral 35 denotes a printed circuit board on which each connection circuit of the network-compatible image transmission device 30 in FIG. 3 and a series connection signal wiring for connecting them are mounted. Each connection circuit is connected to a series-connected signal wiring bus so as to spread in a spiral shape toward the periphery of the printed circuit board 35 starting from the position where the CPU 1 is arranged. The CPU bus A, the peripheral circuit bus B, and the extended external bus C exchange data via the peripheral circuit bus buffer 2 and the extended external bus buffer 6. On the outermost side, each connection circuit of the external peripheral block 32 shown in FIG. 3 for exchanging data with the outside in the peripheral part of the printed circuit board 35 is connected by the peripheral circuit bus B and the extended external bus C. .

  In other words, the CPU block 30 is arranged almost at the center of the printed circuit board 35, and the external peripheral block 32 is arranged at the peripheral part of the CPU block 30. When each connection circuit of the external peripheral block 32 is arranged in the peripheral portion of the printed circuit board 35, it becomes easy to receive a signal cable for exchanging signals with the outside of the printed circuit board 35, and the operation of the switch 11 for designating an operation mode and the like. Or it becomes easy to visually recognize the blinking status of the LED circuit 10 that informs the operating status to the outside.

  The arrangement of each connection circuit is in the order of the RAM 3, ROM 5, central control circuit 4, peripheral circuit bus buffer 2, and extended external bus buffer 6 of the connection circuit that requires higher speed access starting from the CPU 1. Further, from the peripheral circuit bus buffer 2, the network control circuit 7, the JPEG compression circuit 8, the serial control circuit 9, and the slowest access that are required to be accessed at a higher speed toward the peripheral portion of the printed circuit board 35 are permitted. The LED circuit 10 and the switch circuit 11 are arranged in this order. Further, starting from the extended external bus buffer 6, the expansion connectors 12 and 13 and the JPEG expansion circuit 25 are connected by the extended external bus C of the series connection signal wiring in the peripheral portion of the printed circuit board 35. The connection circuit that requires high-speed access is arranged closer to the CPU 1 or the bus buffers 2 and 6 because the signal transmission distance is shortened as much as possible to minimize the signal propagation delay, so that the driver such as the CPU 1 This is because the set-up time and hold time of the received signal on the side are ensured so that the signal can be input / output reliably in high-speed signal transmission.

  Further, series resistors 21, 23, and 26 as damping resistors for suppressing signal reflection, crosstalk noise, and the like are connected in series to the signal wiring of the series connection of the bus close to the CPU 1 or the peripheral circuit bus buffer 2. Has been inserted. Also, termination resistors 22, 24, and 27 equivalent to the transmission line characteristic impedance of each bus are arranged and connected to each bus between the power supply line and the ground.

  The operation of the network-compatible image transmission apparatus using the series connection signal wiring of each connection circuit and each bus connecting them in FIG. 1 is the same as that in FIG.

  According to the present invention, 3.6 Mbps × 4 = 14.4 Mbps data distribution is possible, in which compressed image data of 3.6 Mbps (= 0.12 Mbps × 30 fps) per user can be distributed to at least four users simultaneously via the network. It is possible to realize a service that can provide high-quality reproduced images with natural movement to each user.

  In addition, external peripheral blocks connected by a series-connected signal wiring bus that realizes a data transfer rate of at least 14.4 Mbps can be arranged in the peripheral portion of the printed circuit board, so that the external interface Connectors, operating status indicators, or switches for setting operating conditions can be directly mounted on a printed circuit board. This eliminates the need to connect a cable by connecting a connector, display, or switch to the device housing on a separate printed circuit board, simplifying the structure of the housing and reducing the cost. Can be realized.

The figure which shows the mounting structure of the network corresponding | compatible image transmission apparatus of one Example in this invention. The figure which shows the concept of the mounting system of the network corresponding | compatible image transmission apparatus of one Example in this invention. The figure which shows the concept of the network corresponding | compatible image transmission apparatus of one Example in this invention. The figure which shows an example of the data transfer timing of the network corresponding | compatible image transmission apparatus of one Example in this invention. The schematic diagram which shows a part of structure of the bus | bath in which data exchange is performed. The schematic diagram which shows an example of the generation | occurrence | production factor of a data error.

Explanation of symbols

  1: CPU, 2: bus buffer, 3: RAM, 4: central control circuit, 5: ROM, 6: bus buffer, 7: network control circuit, 8: JPEG compression circuit, 9: serial control circuit, 10: LED circuit , 11: switch circuit, 12, 13: connector for expansion, 14: camera, 21, 23, 26: series resistor, 22, 24, 27: termination resistor, 25: JPEG expansion circuit, 30: network compatible image transmission Device: 31: CPU block, 32: External peripheral block, 33: Monitor, 35: Printed circuit board, 40: Network, A: CPU bus, B: Peripheral circuit bus, C: Expansion external bus, D: Data, E: Video Signal, F: Serial communication signal.

Claims (1)

A video processing unit that processes video signals from the imaging device to generate image data;
A network control unit for controlling transmission of the image data via a network;
A central processing unit for processing the image data;
A storage unit for storing image data from the video processing unit,
The central processing unit is disposed at a substantially central part on the mounting substrate,
The bus connecting the central processing unit, the storage unit, the network control unit, and the video processing unit in series is signal-wired so as to spread spirally from the central processing unit toward the outer periphery.
A network-compatible image transmission apparatus characterized by the above.