JP3865065B2 - Waveform generation circuit and planar matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a planar matrix type display device such as a plasma display panel (PDP) display device having such a waveform generation circuit in a waveform generation circuit and a drive signal generation unit, and in particular, a waveform and data related to its generation are stored in a ROM. The present invention relates to a waveform generation circuit that stores data, sequentially reads the stored data, and converts it into a waveform, and a flat matrix display device having such a circuit.
[0002]
[Prior art]
In recent years, flat matrix display devices using PDP, LCD, etc. have been used instead of CRT because of the advantage that it is easy to reduce the thickness. In particular, the PDP display device is a simple process, the size of the display screen can be easily increased, and since it is a self-luminous type, the display quality is good and the response speed is fast. Production is also increasing.
[0003]
In these flat matrix display devices, there is an increasing demand for color display. In the case of full color, more precise drive waveform control of the drive circuit of the display panel is required. The PDP display device includes a two-electrode type that performs selective discharge (address discharge) and sustain discharge (discharge for display light emission) with two electrodes, and a three-electrode type that performs address discharge using a third electrode. However, in a color PDP that performs gradation display, a three-electrode structure using surface discharge is generally used.
[0004]
FIG. 1 is an overall configuration diagram of a three-electrode surface discharge type color PDP apparatus, FIG. 2 is a block configuration diagram of a control circuit, FIG. 3 is a time chart showing an example of a drive waveform, and FIG. It is a block block diagram of a generation circuit. A driving waveform generation circuit of a conventional color PDP display device will be briefly described with reference to FIGS.
As shown in FIG. 1, the PDP display device uses a scan pulse on the panel 1, a Y scan driver 4 that sequentially applies a scan pulse to the Y scan electrode of the panel 1, and an address electrode corresponding to a lighted cell on the panel 1. An address driver 2 that applies a drive signal in synchronization, an X driver 3 and a Y driver 5 that apply a sustain waveform between the X common electrode and all Y scan electrodes of the panel 1, and each of the drivers 2 to 5 Display voltage and driver control signals are supplied to the power supply circuit 7 for supplying the voltages Vsy, Vsx and Va, the address driver 2 and driver control signals are supplied to the other drivers 3 to 5, respectively. It comprises a control circuit 6 for supplying a power control signal.
[0005]
As shown in FIG. 2, the control circuit 6 includes a multi-gradation means 61, a frame memory 62, a frame memory write / read address generation circuit 63, a pulse generator 64, and a drive waveform generation circuit 65. ing.
FIG. 3 is a diagram showing drive signals generated by the control circuit 6. 3 is a signal applied to the address electrode from the address driver 2, the second signal is a signal applied to the X electrode from the X driver 3, and the third and subsequent signals are Y scan drivers. 4 and a signal applied from the Y driver 5 to the Y electrode. In FIG. 3, among the signals applied to the address electrodes, signals A (1), A (2),..., A (n) in the address period are display data, and other signals are generated by the drive waveform generation circuit 65. Generated.
[0006]
As a circuit for generating a waveform such as the drive waveform generation circuit 65, data indicating a waveform and a signal related to its control is stored in the ROM for each basic period of waveform generation, and the data stored in the ROM is sequentially stored. Circuits that read out and generate waveforms are widely used. When the required data amount cannot be obtained by one reading, the data for each basic period is divided into a plurality of data and stored so that the necessary data amount is output by reading a plurality of times for each basic period. Yes.
[0007]
The present applicant discloses a drive waveform generating circuit for a PDP display device in Japanese Patent Laid-Open No. 4-284491. FIG. 4 is a diagram showing a configuration example of a conventional driving waveform generation circuit 65 disclosed therein. As shown in FIG. 4, the conventional drive waveform generation circuit 65 includes a drive waveform / control signal ROM 651, ROM address counter 652, address storage means 653, ROM data conversion means 655, ROM address counter 652 and address storage. And a drive waveform generation control means 654 for outputting a control signal to the ROM data conversion means 655.
[0008]
As a driving method for performing gradation display in a PDP display device, one display frame is divided into a plurality of subframes, and a sustain period (sustain discharge period) for determining effective luminance of each subframe is relatively set. The multi-address method is generally used in which the gradation ratio is displayed by displaying the gradation data in the subframes corresponding to the weighting, with the ratio of 1: 2: 4: 8: 16:. The control signal ROM 651 stores a drive waveform for one subframe and a control signal output to the drive waveform generation control means 654. The length of the sustain period is defined by the number of repetitions of the repeated portion described later. As shown in FIG. 3, one subframe is divided into a reset period, an address period, a sustain period, and a post-processing period. When all the drive waveforms and control signals for one subframe are stored as data, it is necessary to provide a drive waveform / control signal ROM 651 with a large storage capacity. Therefore, in a portion where the same waveform is repeated, a predetermined address range is repeatedly read and the same The waveform is repeatedly generated. In the drive signal of FIG. 3, since the same waveform is repeated in the address period and the sustain period, only the minimum unit of the repetitive cycle is stored for this part. The data stored in the drive waveform / control signal ROM 651 is the head in which data corresponding to the minimum unit of the drive waveform repetition cycle of the output of the ROM address counter 652 is stored in the address storage means 653 during the drive waveform repetition cycle. Holds the address. When the drive waveform / control signal ROM 651 is 8 bits, the 8-bit data is not enough to generate a necessary drive waveform, and therefore the ROM data conversion means 655 converts the data into data of 8 bits or more. For example, if a 32-bit drive waveform and its control signal data are required in a cycle of 3 MHz to generate a required drive waveform, a drive waveform / control signal ROM 651 having a data width of 8 bits is shown in FIG. The data is stored in such a memory map, and read out in the order of A area, B area, C area, and D area at 12 MHz, and the ROM data conversion means 655 collects the read data four times into 32 bits of 3 MHz data. Convert to The ROM data output from the ROM data conversion means 655 is the same as the address driver 2, the X driver 3, except that the control signal and the control signal ADDT of the frame memory write / read address generation circuit are input to the drive waveform generation control means 654. A driver control signal is output to each of the Y scan driver 4 and the Y driver 5. Each driver is provided with a circuit for generating a signal of a predetermined voltage to be applied to each electrode based on the supplied control signal, and a signal as shown in FIG. 3 is generated to drive the panel 1. By performing the above operation for the number of subframe divisions, the display of one screen is completed.
[0009]
[Problems to be solved by the invention]
In the PDP display device, it is necessary to control the driving of the panel by each driver more precisely in order to further improve display quality and durability. For this reason, it is required to make the driving waveform supplied to each driver more precise. However, in order to make the drive waveform more precise, it is necessary to increase the capacity of the drive waveform / control signal ROM 651 and increase the amount of data read from the drive waveform / control signal ROM 651 within the basic period. This means that the data reading speed from the drive waveform / control signal ROM 651 is increased. However, in order to increase the reading speed from the ROM, it is necessary to use a high-speed ROM, which causes a problem that the cost of the ROM increases. Therefore, in the PDP display device, the drive waveform cannot be easily refined.
[0010]
In the PDP display device, as described above, the multiple address method is used in which gradation display is performed by displaying gradation data in subframes corresponding to weighting. When the user adjusts the brightness of the screen, the length of the sustain period of each subframe is changed accordingly. In practice, the sustain period of the least weighted subframe is very short, and when darkening brightness adjustments are made, it can happen that the sustain period of the least weighted subframe is shorter than one cycle period. . In such a case, the minimum weighted subframe need not be lit. In such a case, there is a risk of causing a lighting error in the next subframe. Therefore, the entire subframe cannot be omitted, and the reset period, the address period, and the post-processing period are performed, but the sustain period is performed. There will be no. For this reason, it is necessary to generate a waveform that performs a post-processing period immediately after the address period, but the conventional waveform generation circuit can only change the address in order or repeat a predetermined range. In response to an external request, the ROM read cannot be skipped to an address away from a certain address. Therefore, it was not possible to not perform the sustain period as described above.
[0011]
The above is not limited to the waveform generation circuit used in the PDP display device, but is the same in the waveform generation circuit used in other applications. The same applies when generating a precise waveform or deforming the waveform. It is a problem that occurs.
The present invention is for solving the above-described problems, and realizes a waveform generation circuit capable of generating a complex waveform without increasing the amount of ROM data and without increasing the reading speed. An object of the present invention is to make a drive waveform more precise without increasing the cost of the waveform generation circuit by applying a simple waveform generation circuit to a PDP display device.
[0012]
[Means for Solving the Problems]
FIG. 6 is a principle configuration diagram of the first aspect of the present invention.
As shown in FIG. 6, the waveform generation circuit of the present invention includes a ROM 651 that stores waveforms and waveform data related to the generation for each cycle, and an address generation circuit 71 that sequentially generates address signals for sequentially reading the waveform data. And a waveform data output circuit 73 that sequentially reproduces the read waveform data into a waveform signal, the waveform data includes extension information that instructs to extend and reproduce the waveform data of the cycle. Whether or not the extension information is present is determined from the read waveform data. When the extension information is included, the waveform data output circuit 73 controls the output of the corresponding waveform signal, and the address generation circuit 71 An extension determination / control circuit for controlling the address signal generation operation to be delayed is provided.
[0013]
In the conventional waveform generation circuit, even when the same state continues for a plurality of cycles, the same data is stored in the ROM for each cycle and read out in order. For this reason, a phenomenon has occurred in which the same waveform data continues. According to the present invention, when the same data continues for a plurality of cycles, one waveform data can be extended and generated with the extension information, so that the amount of waveform data can be reduced, and the ROM capacity can be reduced accordingly. Can be reduced.
[0014]
As described above, in the conventional waveform generation circuit, when the same waveform is repeated, the basic waveform is stored in the ROM, and the address range is repeatedly read to reduce the capacity of the ROM. However, it repeatedly reads out a certain address range that stores waveform data of a plurality of cycles constituting the periodically changing portion of the waveform, and as in the present invention, it extends and reproduces waveform data of a certain cycle as it is. Was not done.
[0015]
Although the extension period may be constant, extension period information indicating the extension period may be provided in the waveform data together with extension information indicating whether the waveform data is extended. Thereby, the extension period can be set arbitrarily. When the waveform data includes extension information, the extension determination / control circuit 72 further extracts extension period information, and the waveform data output circuit 73 maintains the output of the corresponding waveform signal for the period specified by the extension period information. To control.
[0016]
If the length of a certain state of the waveform can be set arbitrarily, the drive waveform can be further refined.
There are various methods for providing extension information and extension period information in waveform data. One method is to make the extension period information included in the waveform data of the next cycle of the extension information. FIG. 7 is a time chart for explaining the read operation in this method. As shown in FIG. 7, when the read waveform data D (n) includes the extension information (during the cycle in which the control bit is “H”), the extension determination / control circuit 72 has a waveform data output circuit. 73 is controlled to maintain the output of the corresponding waveform signal WD (n), and then the extended period information is extracted from the waveform data D (n + 1) of the next cycle. In this case, the extension period indicated by the extension period information needs to be longer than one cycle (in fact, a period that is an integral multiple of one cycle) in order to read the extension period information. Thereafter, during a period (m-1) obtained by subtracting one cycle for reading the extension period information from the period m indicated by the extension period information, the waveform data output circuit 73 maintains the output and generates an address. The circuit 71 controls to delay the address signal generation operation. Therefore, the waveform signal WD (n) is maintained for m + 1 cycles.
[0017]
As another method, the extension information is composed of a plurality of bits, the extension period information is also represented by a plurality of bits of the extension information, and depending on the combination value of the plurality of bits, whether or not to extend the extension period. To be directed. FIG. 8 is a time chart for explaining the read operation in this method. For example, if 3 bits of waveform data are assigned to extension information, 8 states can be represented by 3 bits of extension information. One of these states, for example, 0 is assigned to a condition that does not extend, and the other 7 states are assigned an extension amount from 1 to 7. If the minimum extension amount is TC, the extension amount can be changed from TC to 7TC. As shown in FIG. 8, the amount of extension is counted by counting the clock CLK. However, if the period of the clock CLK is made smaller than the cycle of waveform data at the normal time, the minimum unit of the extension period can be controlled more precisely.
[0018]
FIG. 9 is a principle configuration diagram of the second aspect of the present invention.
As shown in FIG. 9, the waveform generation circuit of the present invention includes a ROM 651 that stores waveforms and waveform data related to the generation for each cycle, and an address generation circuit 74 that sequentially generates address signals for sequentially reading the waveform data. When an external instruction signal instructing to skip reading is input from the outside in a waveform generation circuit comprising: When the address signal generated by the address generation circuit reaches a predetermined value, a skip address is assigned to the address generation circuit. And a skip determination circuit configured to control the address generation circuit to continue the generation operation of the address signal from the skip address.
[0019]
According to the second aspect of the present invention, it is possible to skip reading from a predetermined address to a desired address. In addition, whether or not to skip reading can be determined according to the external instruction signal, so that the waveform can be changed according to the situation.
FIG. 10 is a time chart for explaining the read operation in the second mode. In FIG. 10, for example, skip information is stored in data D (n) stored in address A (n) of ROM 651, and address A (m) is stored in skip destination address storage circuit 76. To do. When the external instruction signal is “L” and not active, the waveform is reproduced while sequentially changing the address even if the data D (n) is read. On the other hand, when the external instruction signal is “H” and active, when the data D (n) is read, the skip information included therein is detected, the load signal is turned on, and the skip destination address is turned on. The address A (m) stored in the storage circuit 76 is loaded into the address generation circuit 74. Since the address generation circuit 74 outputs the address A (m) in the next cycle, the data D (m) is read, and the address generation circuit 74 subsequently changes the address sequentially from the address A (m).
[0020]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment in which the present invention is applied to a color PDP waveform generating circuit will be described below.
FIG. 11 is a diagram showing a format of waveform data in the embodiment of the present invention. As described with reference to FIG. 5, in this embodiment, the ROM data bit width is insufficient as waveform data for one cycle, so the ROM storage area is divided into four areas A, B, C, and D. The waveform data of each region is sequentially read out at a speed of 4 times, and the data for 4 times is collected and converted into data having a width of 4 times. Specifically, as shown in FIG. 11, the ROM has an address of 12 bits, a data width of 8 bits, and is divided into four areas from the A area to the D area. Since the waveform data is stored, a total of 32 types of waveform data are stored. Among these, the bit for determining extension is included in the bits of the A area.
[0021]
In the driving waveform of the PDP, the driving waveform in the reset period is a waveform that changes every certain cycle period or an integral multiple of that period. Therefore, in the waveform data in the reset period, the extension method described in FIG. 7 is an extension method in which the extension period is an integral multiple of the cycle, and data indicating the extension amount is stored in the cycle following the cycle in which the waveform data to be extended is stored. The first data bit D0 of the 8-bit data in the A area is assigned to the extension information, and the data indicating the extension amount is stored as 8-bit data in the A area in the next cycle. Therefore, the maximum amount that can be extended is 256 cycles.
[0022]
In addition, it is desired to change the length of the waveform finely in the address period and the sustain period. Therefore, in the address period and the sustain period, the adjustment unit of the extension amount described in FIG. 8 is ¼ cycle, and 2 bits of the 8-bit data in the A area are assigned to the extension information. When the numerical value is “0”, no extension is performed. When “1” is set, 1/4 cycle is extended, when “2” is set, 1/2 cycle is extended, and when “3” is set, 3/4 cycle is extended. use.
[0023]
Furthermore, as described above, since the sustain period of the subframe with the minimum weight may be omitted, when the signal SUS0 instructing omission is “H”, when the address period is switched to the sustain period, the post-processing period Use skipping to ROM address.
FIG. 12 is a diagram showing the driving sequence of the color PDP. Each time the address generated by the address generation circuit becomes a value indicating the end of the reset period, address period, sustain period, and post-processing period of the color PDP, the signal CTQEN And the signals CTQ0 and CTQ1 change as shown. Therefore, it is possible to determine which period is based on the combination of the values of the signals CTQ0 and CTQ1. Specifically, it is a reset period when the values of the signals CTQ0 and CTQ1 are “0” and “0”, an address period when “1” and “0”, and “0” and “1”. It is a sustain period, and “1” and “1” are post-processing periods.
[0024]
FIG. 13 is a diagram showing the overall configuration of the waveform generation circuit according to the embodiment of the present invention. As shown in the figure, this waveform generation circuit includes a ROM 651, an address generation circuit 81, a ROM address storage circuit 82, a drive state counter 83, a ROM data conversion circuit 84, a waveform data extension circuit 85, and a read stop circuit. 86. The specific configuration of each circuit is shown in FIGS. 14 to 21, FIG. 14 shows a driving state counter 83, FIG. 15 shows an address generation circuit 81 and ROM 651, FIGS. 16 to 18 show a ROM address storage circuit, and FIG. FIG. 20 shows a ROM data conversion circuit 84, FIG. 20 shows a read stop circuit, and FIG. 21 shows a waveform data extension circuit.
[0025]
The driving state counter 83 is a circuit that generates a signal indicating the driving sequence state of the color PDP shown in FIG. In FIG. 14, reference numeral 831 is a counter, and XFCLR is an initialization / start signal for the entire circuit. The pulse signal CTQEN shown in FIG. 12 is generated according to the RMADCP output from the address storage circuit 82 at the end of each period and the carry of the counter of the address generation circuit. At that time, the count value is counted up, and signals CTQ0 and CTQ1 indicating the driving sequence state of the color PDP change. Further, as described above, when the signal SUS0 instructing the omission of the sustain period of the subframe having the minimum weight is “H”, the address sequence skips to the ROM address in the post-processing period, and the drive sequence state is accordingly changed. It is also necessary to change the signal indicating. In order to realize this, a multi-input NAND gate 832 is provided. When the address period CTQ0 is “L”, CTQ1 is “H”, RMADCP is “H”, and QACO is “H”, SUS0 is “ When it is “H”, the output XCTQLD of the NAND gate 832 changes to “L”, “H” is input to the counter 831 as D0 and D1, and both CTQ0 and CTQ1 are “H” so as to correspond to the post-processing period. To change.
[0026]
The address generation circuit 81 and the ROM 651 have almost the same configuration as the conventional one. In FIG. 15, reference numerals 812 and 813 are counters. The counter 812 is for sequentially reading the areas A to B shown in FIG. 11 within one cycle, and generates an upper address of the ROM 651. The counter 813 generates an address in each area. When XCTQLD output from the drive state counter changes to “L”, the first address (RMADD0 to RMADD0) output from the ROM address storage circuit 82 is output. 9) is loaded and the count operation is continued from there. As a result, processing for omitting the sustain period of the minimum subframe is realized.
[0027]
The ROM address storage circuit 82 has the configuration shown in FIGS. In the figure, 871 and 872 are registers, and 829 is a comparator. The ROM address storage circuit 82 stores the lower 10 bits (address in each area) of the ROM address at the end of each period of the drive sequence shown in FIG. 12, and the ROM address generated by the address generation circuit 81 A signal RMADCP is generated to indicate that each period has ended when it coincides with QB0 to QB9. The ROM address at the start of the post-processing period is stored, and the address to be loaded into the counter 813 of the address generation circuit 81 is output when the above XCTQLD changes to “L”.
[0028]
The ROM data conversion circuit 84 has a configuration as shown in FIG. Reference numbers 845A through 845C and 846A through 846D are all registers. This circuit is a circuit for sequentially reading four sets of 8-bit data from the A area to the D area shown in FIG. Have substantially the same configuration. These descriptions are omitted.
[0029]
Read stop circuit 86 has the configuration shown in FIG. Reference numeral 864 is a counter. As described above, in the reset period, when the bit D0 of the first ROM data in the A area is “1” (“H”), the waveform data of the cycle is held so as to be output and extended. This period is included in the ROM data of the next cycle. The read stop circuit 86 is a circuit for performing this process. When the bit D0 of the first ROM data in the A area is “H” in the reset period, the output of the multi-input NAND gate 861 becomes “H”. Since the signal XLoad becomes “H”, the data in the area A indicating the extension period is loaded into the counter 864 in the next cycle. The signal LATDMK is input to the ROM data conversion circuit 84. While LATDMK is “H”, the ROM data conversion circuit 84 maintains the output of the previous cycle, and the signal CTQAMKO stops the counting operation of the address generation circuit. The counter 864 counts the data indicating the loaded extension period, and when the count ends, the signal CTQAMK0 returns to “L” and returns to the normal state. Thus, the extension process of the 1st system in a reset period is performed.
[0030]
The waveform data extension circuit 85 has the configuration shown in FIG. Reference numeral 856 is a counter. The waveform data extension circuit 85 does not extend when the bits D0 and D1 of the ROM data in the A area are both “0” in the address period and the sustain period, but performs extension processing at other times, and D0 and D1 When “1” and “0”, 1/4 cycle is extended, when D0 and D1 are “0” and “1”, 1/2 cycle is extended, and when D0 and D1 are “1” and “1”, 3 cycles are extended. This is a circuit for processing to extend / 4 cycles.
[0031]
22 to 37 are time charts showing the operation of each part of the drive waveform generating circuit of the embodiment. 22 to 27, FIG. 28 to FIG. 31, FIG. 32 and FIG. 33, FIG. 34 and FIG. 35, and FIG. 36 and FIG. 22 to 24 are the same time axis. FIGS. 25 to 27 are portions subsequent to FIGS. 22 to 24 in terms of time. FIG. 28 and FIG. 29 are also the same time axis, and FIG. 30 and FIG. 31 are portions following FIG. 28 and FIG. 29 in terms of time. The time axes of FIGS. 32 and 33, FIGS. 34 and 35, and FIGS. 36 and 37 are also common.
[0032]
22 to 27 show the operation from the start of the normal operation. In this case, the skip process in the drive state counter 83 and the extension process in the read stop circuit 86 and the waveform data extension circuit 85 do not occur, so the same process as in the prior art is performed.
FIG. 28 to FIG. 31 show an example in the case where the ROM data bit for instructing extension is “H” in cycle n−1 in the reset period. (Value of 255 or less) "is stored, and this is loaded into the counter 864 of the read stop circuit 86, and the waveform data of the cycle n-1 continues to be output until the carry is output at 255.
[0033]
32 and 33 show a case where both ROM data bits D0 and D1 instructing extension are “1” in the address period or the sustain period. FIGS. 34 and 35 show that D0 and D1 are “0”. ”And“ 1 ”, the output of the waveform data of cycle n is extended by 3/4 cycle (three clocks) in FIGS. 32 and 33, and the waveform data of cycle n is shown in FIGS. 34 and 35. Is extended by 1/2 cycle (2 clocks).
[0034]
FIG. 36 and FIG. 37 show operations near the end of the address period when SUS0 is “H”, that is, when an instruction to omit the sustain period of the minimum subframe is issued. XCTQLD is output upon detecting the end address, and “H” is loaded as CTQ0 and CTQ1 accordingly. As a result, the post-processing period immediately follows the address period.
[0035]
The embodiment in which the present invention is applied to the waveform generation circuit used in the PDP apparatus has been described above. However, the waveform generation circuit of the present invention is not limited to the PDP display apparatus, and the waveform data stored in the ROM and the control for controlling the generation thereof. The present invention is applicable to any device that reads data and generates a waveform.
[0036]
【The invention's effect】
As described above, according to the present invention, the storage capacity of the ROM can be reduced, and a more precise waveform signal can be generated. As a result, it becomes possible to further refine the drive control of the driver and improve the quality of the color plasma display (PDP) display device.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a three-electrode surface-discharge type color plasma display device.
FIG. 2 is a block diagram of a control circuit of a color plasma display device.
FIG. 3 is a time chart showing driving waveforms of the plasma display device.
FIG. 4 is a block diagram of a conventional drive waveform generation circuit.
FIG. 5 shows a conventional ROM memory map.
FIG. 6 is a diagram showing a principle configuration of a first aspect of the present invention.
FIG. 7 is a diagram for explaining the operation of the first aspect of the present invention.
FIG. 8 is a diagram illustrating another operation of the first aspect of the present invention.
FIG. 9 is a diagram showing a principle configuration of a second aspect of the present invention.
FIG. 10 is a diagram for explaining the operation of the second aspect of the present invention.
FIG. 11 is a diagram showing a ROM memory map in the embodiment of the present invention.
FIG. 12 is a time chart showing signals related to the color PDP drive sequence in the embodiment of the present invention.
FIG. 13 is a block diagram showing an overall configuration of a waveform generation circuit according to an embodiment of the present invention.
FIG. 14 is a diagram illustrating a circuit configuration of a drive counter according to the embodiment.
FIG. 15 is a diagram illustrating a circuit configuration of an address generation circuit and a ROM according to an embodiment.
FIG. 16 is a diagram illustrating a circuit configuration of a part of the ROM address storage circuit according to the embodiment.
FIG. 17 is a diagram illustrating a circuit configuration of a part of a ROM address storage circuit according to an embodiment.
FIG. 18 is a diagram illustrating a circuit configuration of a part of a ROM address storage circuit according to an embodiment.
FIG. 19 is a diagram illustrating a configuration of a ROM data conversion circuit according to an embodiment.
FIG. 20 is a diagram illustrating a configuration of a read stop circuit according to an embodiment.
FIG. 21 is a diagram illustrating a configuration of a waveform data extension circuit according to an embodiment.
FIG. 22 is a time chart (No. 1) showing a normal operation in the embodiment.
FIG. 23 is a time chart (part 2) illustrating the normal operation in the embodiment.
FIG. 24 is a time chart (No. 3) showing a normal operation in the embodiment.
FIG. 25 is a time chart (No. 4) showing a normal operation in the embodiment.
FIG. 26 is a time chart (No. 5) showing a normal operation in the embodiment.
FIG. 27 is a time chart (No. 6) showing a normal operation in the embodiment.
FIG. 28 is a time chart (part 1) illustrating an operation when reading is stopped and output is held in the embodiment.
FIG. 29 is a time chart (part 2) illustrating an operation when reading is stopped and output is held in the embodiment.
FIG. 30 is a time chart (part 3) illustrating an operation when reading is stopped and output is held in the embodiment.
FIG. 31 is a time chart (No. 4) showing an operation when reading is stopped and output is held in the embodiment.
FIG. 32 is a time chart (part 1) showing an operation at the time of extension in the embodiment.
FIG. 33 is a time chart (part 2) illustrating an operation during extension in the embodiment.
FIG. 34 is a time chart (part 1) illustrating another operation during extension in the embodiment.
FIG. 35 is a time chart (part 2) illustrating another operation during extension in the embodiment.
FIG. 36 is a time chart (part 1) showing an operation at the time of skipping in the embodiment.
FIG. 37 is a time chart (part 2) showing an operation at the time of skipping in the embodiment.
[Explanation of symbols]
1. Color plasma display panel
2 ... Address driver
3 ... X driver
4 ... Y scan driver
5 ... Y driver
6 ... Control circuit
7 ... Power circuit
71, 74 ... Address generation circuit
72 ... Extension judgment / control circuit
73 ... Waveform data output circuit
75. Skip determination circuit
76 ... Skip destination address register
651 ... ROM

Claims (1)

A display panel having a plurality of cells for selectively discharge light emission, and set to a state corresponding to Oite display data of the plurality of cells to display data setting period by the display data setting means, wherein the display light emitting means a plurality of cells wherein light is emitted according to the set state in the light emitting display period after the display data setting period, a plane matrix for performing post-processing the plurality of cells in the predetermined post period after the emission display period A display device,
A drive waveform generating circuit for generating a drive control signal to be supplied to the display data setting means and the display light emitting means;
The drive waveform generation circuit includes:
ROM storing waveform and waveform data related to its generation for each cycle;
An address generation circuit for sequentially generating address signals for sequentially reading the waveform data ;
And an input unit to which a control signal for controlling the skip operation of the waveform data output from the ROM is are entered,
When the control signal is input, when the address signal generated by the address generation circuit has a value corresponding to the end of the display data setting period, the start address of the post-processing period is set in the address generation circuit. A flat matrix display device which is operated so as to skip the light emitting display period.

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