JP3863283B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

ここで、εは酸化膜の誘電率、Ｗはチャネル幅とする。
【００２３】
残りの領域１０は、絶縁破壊が発生しない限りにおいて、その容量Ｃ10の値は有限値となる。よって、この谷部における全容量Ｃ1 は、次の（２）式のようになる。
【００２４】
【数２】

一方で、浮遊ゲートＦＧの上部におけるトンネル酸化膜１４の容量Ｃ2 は、
【００２５】
【数３】

のように表される。
【００２６】
従って、絶縁膜１３の容量Ｃ1 に対するトンネル酸化膜１４の容量Ｃ2 の容量結合比γは、以下のようである。
【００２７】
【数４】

但し、簡単のため、絶縁膜１３とトンネル酸化膜１４とは比誘電率が等しい酸化膜で構成されているものとした。
【００２８】
ここで、本実施の形態の特徴である浮遊ゲートＦＧと制御ゲートＣＧとの間においてＦＮトンネリング現象を利用したデータの書き込み又は消去を可能にするためには、以下の（５）式のような条件が成立する必要がある。
【００２９】
【数５】

ここで、電圧に関する単位は全て〔Ｖ〕とする。
【００３０】
（５）式において、第１項及び第２項から成る不等式は、浮遊ゲートＦＧと制御ゲートＣＧとの間でＦＮトンネリングが発生するための制御電圧ＶG の下限を示し、第２項及び第３項から成る不等式は、半導体基板１１と浮遊ゲートＦＧとの間でＦＮトンネリングが発生しないための制御電圧ＶG の上限値を示す。
【００３１】
また、高電圧を印加するデータの書き込み又は消去時において、基板と浮遊ゲートＦＧとの間の薄い絶縁膜１３に直接トンネル電流が流れても、浮遊ゲートＦＧと制御ゲートＣＧとの間で電子の注入又は引き抜きが可能となるためには、以下の（６）式が成立する必要がある。
【００３２】
【数６】

さらに、電子の注入速度及び引き抜き速度が低下しないようにするためには、トンネル酸化膜１４に印加される電界Ｆ2 は、１０⁹ 〔Ｖ／ｍ〕程度が要求されるので、この部分の電圧Ｖ2 をトンネル酸化膜１４の膜厚ｔ2 で除した値Ｆ2 は、以下のようである。
【００３３】
【数７】

ここで、長さに関する単位は、全てオングストロームとする。
【００３４】
上記（５）式及び（７）式より、以下の（８）式が導かれる。
【００３５】
【数８】

さらに上記（６）式においてγを０とすると、上記（８）式を用いることにより次の（９）式が得られる。
【００３６】
ｔ1 ＞２４ （９）
この（８）式及び（９）式より、絶縁膜１３の膜厚ｔ1 とトンネル酸化膜１４の膜厚ｔ2 と、容量結合比γとの関係式が明らかにされた。
【００３７】
次に、本実施の形態における最大閾値電圧Ｖthと制御電圧ＶG との関係について考察する。浮遊ゲートＦＧに電子を注入した後に、データを読み出す際の閾値電圧Ｖthは、Ｖthより高い読み出し時の電圧によって浮遊ゲートＦＧから電子が引き抜かれないように設定しなければならない。
【００３８】
基板１１の谷部における絶縁膜１３に印加される電圧Ｖ1 によって、その表面に反転層が形成されるが、そのときの閾値電圧Ｖthは次の（１０）式のように表される。
【００３９】
【数９】

ここで、ＮA はアクセプター不純物密度であり、その単位は〔cm^-3〕とする。この（１０）式において不等号が用いられているが、第１項及び第２項から成る不等式は、制御電圧ＶG が閾値Ｖthよりも高くなければならないことを示し、第２項及び第３項から成る不等式は、データ読み出し時において上述したように制御電圧ＶG がＦＮトンネリングを発生させる値よりも低くなければならないことを示している。
【００４０】
また、この場合に製造工程に対して、以下の（１１）式で表されるような条件が必要となる。
【００４１】
【数１０】

この（１１）式で示された条件と、上記（８）式が示す条件とを考慮すると、次の（１２）式が成立しなければならない。
【００４２】
【数１１】

ここで、ＮA を１０¹⁷〔cm^-3〕とすると、ｔ1 ＜２１００オングストロームとなる。実際のセルにおける絶縁膜１３の膜厚ｔ1 は、２１００オングストロームよりもはるかに小さい値をとるので、殆ど考慮する必要のない条件である。
【００４３】
次に、絶縁膜１３の膜厚ｔ1 に対するトンネル酸化膜ｔ2 の膜厚比ｔ2 ／ｔ1 の上限を、上記（６）式を用いて図３に示す。この図からも明らかなように、膜厚比ｔ2 ／ｔ1 は容量結合比の逆数１／γに対して、単調に増加することがわかる。また、膜厚比ｔ2 ／ｔ1 は制御ゲート電圧ＶG に対しても、３〜１０〔Ｖ〕の範囲内では単調に増加する。
【００４４】
ここで、この図３に示された範囲内では、膜厚比ｔ2 ／ｔ1 は常に０．５以上の値を取っている。そこで、具体的なセルの一例として、絶縁膜ｔ1 の膜厚を１００オングストローム、トンネル酸化膜ｔ2 の膜厚を５０オングストロームとし、さらに、ｓ1 がｓ2 の２倍以上ある場合を考えると、上記（８）式より、次の（１３）式を導くことができる。
【００４５】
γ^-1＞ｓ1 ／ｓ2 ＞２ （１３）
この（１３）式と上記（５）式とを用いることにより、データの書き込み又は消去時には、次の（１４）式で表されるような制御ゲート電圧ＶG が必要となることがわかる。
【００４６】
４．５＜ＶG ＜８．１ （１４）
この（１４）式で示されたように、本実施の形態によれば、基板と制御ゲートとの間に印加する電圧は、４．５〜８．１〔Ｖ〕というように従来のものよりも大幅に低減される。
【００４７】
以下に、本実施の形態による半導体記憶装置の製造方法について図４及び図５を用いて説明する。
【００４８】
先ず、図４を用いて半導体基板の表面に鋸歯状の加工を行う手順を説明する。図４（ａ）のように、ｐ型半導体基板１１の（１００）表面に、ｎ型不純物拡散層１２を形成する。この形成は、例えば基板１１の表面上にシリコン酸化膜又はシリコン窒化膜をｎ型不純物を導入させながら形成し、あるいは形成後に不純物をイオン注入し、熱拡散を行ってシリコン酸化膜又はシリコン窒化膜内の不純物を半導体基板１１表面に拡散することで行うことができる。ｎ型不純物拡散層１２上にシリコン窒化膜５１をマスク材としてＣＶＤ法により形成する。シリコン窒化膜５１上に、所定の形状にパターニングされたレジスト膜５２を形成する。
【００４９】
図４（ｂ）のように、レジスト膜５２を用いてシリコン窒化膜５１にエッチングを行う。得られたシリコン窒化膜５１をマスク材として、図４（ｃ）のように半導体基板１１に結晶学的面異方性エッチング（ＬＳＩハンドブック、オーム社、第２６４〜２６５頁参照）を行い、（１１１）面が露出するようにＶ字型の溝を掘る。この時、溝の底面に半導体基板１１の表面が露出するように溝の深さ及び不純物拡散層１２の深さを設定する必要がある。
【００５０】
図４（ｄ）のように、溝の内部をＣＶＤ法によりシリコン酸化膜５３で埋めた後、図４（ｅ）のようにシリコン窒化膜５１を剥離する。
【００５１】
シリコン酸化膜５３をマスクとして、半導体基板１１に再び結晶学的面異方性エッチングを行い、図４（ｆ）のようにＶ字型の溝を掘る。このような工程を経ることで、山部にｎ⁺ 型不純物拡散層１２が形成され、谷部により拡散層１２が相互に分離された鋸歯状に半導体基板１１の表面が加工される。
【００５２】
次に、図５を用いて谷部に浮遊ゲート及び制御ゲートを形成する手順について述べる。図５（ａ）のように、半導体基板１１の表面が最小加工寸法Ｆの間隔で鋸歯状に加工されている。このような半導体基板１１の表面に対してラジカル酸化を行い、図５（ｂ）に示されたように薄いシリコン酸化膜２１を形成する。この場合に、半導体基板１１の谷部２２において酸化剤が集中するので、シリコン酸化膜２１は谷部２２において他の部分よりも膜厚が相対的に厚くなる。
【００５３】
図５（ｃ）のように、グラフォーエピタキシャル成長を行うことで、谷部においてシリコン酸化膜２１の表面上に、結晶性シリコンから成る浮遊ゲート２３を形成する。ここで、浮遊ゲート２３を構成するシリコンはエピタキシャル状であるので、従来の多結晶シリコンから成る浮遊ゲートよりも界面の状態は良好である。
【００５４】
さらに、もう一度ラジカル酸化処理を行うと、谷部の表面に表れた基板１１の（１１１）面の酸化速度が速いために、図５（ｄ）に示されたように浮遊ゲート２３の上部が尖塔状に加工されて行く。又、浮遊ゲート２３の下部は酸化剤が集まらないため、他の部分より酸化の進行が遅く、その結果として谷部は丸見をおびる。
【００５５】
さらに酸化処理を進めて、図５（ｅ）に示されたように、浮遊ゲート２３の表面及びシリコン酸化膜２１の表面を覆うように、シリコン酸化膜２４を形成する。
【００５６】
図５（ｆ）のように、浮遊ゲート２３の上部に、シリコン酸化膜２４を介して再度グラフォーエピタキシャル成長を行うことで、制御ゲート２５を形成する。このようにして形成された制御ゲート２５の下部は、谷部の形状に対応した形状を有し、上部が尖塔状である浮遊ゲート２３とセルフアライメントでその先端の位置が一致し対向するように配置される。この後、図５（ｇ）のようにＣＶＤ法を用いてシリコン酸化膜２６を全体に堆積する。以上のような工程を経ることで、本実施の形態による半導体記憶装置を製造することが可能である。
【００５７】
次に、本実施の形態による半導体記憶装置をＮＡＮＤ型Ｅ² ＰＲＯＭに適用した場合について述べる。この場合の回路構成は、図６に示されているようである。ソース側のセレクトゲート用トランジスタＴ１の一方の端子はセレクト線ＳＬに接続され、このトランジスタＴ１の他方の端子と、浮遊ゲート及び制御ゲートを有するメモリセルＭＣ１〜ＭＣ４の両端子と、ドレイン側のセレクトゲート用トランジスタＴ２の一方の端子が直列に接続され、トランジスタＴ２の他方の端子がビット線コンタクトＢＬＣを介してビット線ＢＬに接続されている。トランジスタＴ１のセレクトゲートにはセレクトゲート線ＳＧＳが接続され、メモリセルＭＣ１〜ＭＣ４のそれぞれの制御ゲートにはワード線ＷＬ１〜ＷＬ４が接続され、トランジスタＴ２のセレクトゲートにはセレクトゲート線ＳＧＤが接続されている。
【００５８】
このような回路構成を有するＮＡＮＤ型Ｅ² ＰＲＯＭに本実施の形態による半導体記憶装置を適用すると、図７に示されるような断面構成を有するものとなる。ｐ型半導体基板１１の表面が鋸歯状に加工されており、それぞれの山部にｎ型不純物領域１２が形成されている。半導体基板１１において順に隣接した６つの谷部を単位として、トランジスタＴ１、メモリセルＭＣ１〜ＭＣ４、トランジスタＴ２がそれぞれ配置され、トランジスタＴ１は谷部にセレクトゲートＳＧＳを有し、メモリセルＭＣ１〜ＭＣ４は、それぞれの谷部に浮遊ゲートＦＧ１〜ＦＧ４と制御ゲートＣＧ１〜ＣＧ４とを有し、トランジスタＴ２は谷部にセレクトゲートＳＧＤを有する。トランジスタＴ１の一方の端子に対応するｎ型不純物領域１２（Ｔ１ａ）はセレクト線ＳＬに接続され、トランジスタＴ２の一方の端子に対応するｎ型不純物領域１２（Ｔ２ｂ）はビット線ＢＬに接続される。
【００５９】
トランジスタＴ１の他方の端子に対応するｎ型不純物領域１２（Ｔ１ｂ）は、メモリセルＭＣ１の一方のｎ型不純物領域１２（ＭＣ１ａ）と同一の山部において共有し、メモリセルＭＣ１の他方のｎ型不純物領域１２（ＭＣ１ｂ）とメモリセルＭＣ２の一方のｎ型不純物領域１２（ＭＣ２ａ）とは同一の山部により共有する。メモリセルＭＣ２の他方のｎ型不純物領域１２（ＭＣ２ｂ）とメモリセルＭＣ３の一方のｎ型不純物領域１２（ＭＣ３ａ）とは同一の山部において共有し、メモリセルＭＣ３の他方のｎ型不純物領域１２（ＭＣ３ｂ）とメモリセルＭＣ４の一方のｎ型不純物領域１２（ＭＣ４ａ）とは同一の山部において共有する。同様に、メモリセルＭＣ４の他方のｎ型不純物領域１２（ＭＣ４ｂ）とトランジスタＴ２の他方の端子に対応するｎ型不純物領域１２（Ｔ２ａ）とは、同一の山部で共有している。
【００６０】
また、トランジスタＴ１のセレクトゲートＳＧＳ及びトランジスタＴ２のセレクトゲートＳＧＤは、メモリセルトランジスタＭＣ１〜ＭＣ４の浮遊ゲートＦＧ１〜ＦＧ４と同一の工程で形成してもよく、あるいはメモリセルトランジスタＭＣ１〜ＭＣ４の制御ゲートＣＧ１〜ＣＧ４と同一の工程で形成してもよい。
【００６１】
このように、本実施の形態をＮＡＮＤ型Ｅ² ＰＲＯＭに適用することで、鋸歯状に加工された半導体基板の谷部を単位としてトランジスタＴ１、Ｔ２、メモリセルＭＣ１〜ＭＣ２を連続的に配置することで集積度が向上し、さらにそれぞれの不純物領域１２の素子分離も谷部を利用することで容易に行うことができる。
【００６２】
上述した実施の形態は一例であり、本発明を限定するものではない。例えば、上記実施の形態による製造方法における各種製造条件や膜厚、材質等は一例であり、必要に応じて変えることができる。また、本発明による半導体記憶装置は、ＮＡＮＤ型Ｅ² ＰＲＯＭに限らず他の各種記憶装置に適用してもよい。
【００６３】
【発明の効果】
以上説明したように、本発明の半導体記憶装置及びその製造方法によれば、鋸歯状に加工された半導体基板の谷部において、上部が尖塔状の形状を有する浮遊ゲートと、谷部の形状に応じて下方に向かって鋭角的な形状を有する制御ゲートとが対向するように配置されていることで、データの書き込み又は消去時に必要な最大動作電圧が低減されると共に、集積度を向上させることが可能である。
【図面の簡単な説明】
【図１】本発明のー実施の形態による半導体記憶装置の構成を示した縦断面図。
【図２】同半導体記憶装置における浮遊ゲートの断面をより詳細に示した縦断面図。
【図３】同半導体記憶装置における膜厚比、制御ゲート電圧、容量結合比の関係を示したグラフ。
【図４】同半導体記憶装置を製造する前段階として半導体基板の表面に鋸歯状の加工を行う手順を示した縦断面図。
【図５】同半導体記憶装置を製造するときの工程別の素子の断面構造を示した縦断面図。
【図６】ＮＡＮＤ型Ｅ² ＰＲＯＭの回路構成を示した回路図。
【図７】同ＮＡＮＤ型Ｅ² ＰＲＯＭに本実施の形態を適用した場合の断面構造を示した縦断面図。
【符号の説明】
１１ ｐ型半導体基板
１２ ｎ⁺ 型不純物領域
１３、１５、２１、２２、２６、５３ シリコン酸化膜
１４、２４ トンネル酸化膜
５１ シリコン窒化膜
５２ レジスト膜
ＦＧ、２３ 浮遊ゲート
ＣＧ、２５ 制御ゲート
ＷＬ１〜ＷＬ４ ワード線
ＳＬ セレクト線
ＳＧＳ、ＳＧＤ セレクトゲート
ＢＬ ビット線
ＭＣ１〜ＭＣ４ メモリセル
Ｔ１、Ｔ２ セレクトゲート用トランジスタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
[0002]
[Prior art]
Semiconductor memory devices have made great strides due to recent miniaturization. However, in line with the trend toward lower power consumption required by higher integration of LSIs, reducing the operating voltage while ensuring the reliability of the tunnel oxide film will lead to the phenomenon of reduced efficiency of electron injection into the floating gate. I get up.
[0003]
For example, in the current general nonvolatile semiconductor memory device, when the minimum processing dimension length is F, the cell structure is the simplest and the cell area is the smallest, and an element area of about 5.5 F ² is required. . Even in such a cell, when data is written by injecting electrons into the floating gate, or when data is erased by extracting the injected electrons, FN tunneling is caused in the tunnel oxide film. For example, it is necessary to apply a very high electric field such as 18V.
[0004]
In addition, a high electric field is applied not only to the tunnel oxide film interposed between the substrate and the floating gate but also to the insulating film existing between the floating gate and the control gate. Therefore, by adjusting the thickness ratio of the tunnel oxide film to the insulating film so that the tunnel current flows only in the tunnel oxide film and the data is written or erased efficiently, the tunnel oxide film has a capacitance C1 with respect to the capacitance C1 of the insulating film. A measure is taken to reduce the capacitance coupling ratio γ (= C2 / C1) of the capacitor C2. However, even with such a device, the maximum operating voltage when writing or erasing in the conventional semiconductor memory device is considerably high at about 18V.
[0005]
On the other hand, a device whose maximum operating voltage is as low as 12 V is devised to reduce a voltage required for writing or erasing by using, for example, a channel hot electron injection method. However, as a result, there is a problem that the cell structure becomes complicated and the cell area becomes considerably large as 11.5F ² .
[0006]
[Problems to be solved by the invention]
As described above, the conventional semiconductor memory device has a problem that the reduction of the cell area and the reduction of the maximum operating voltage cannot be achieved at the same time.
[0007]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device and a manufacturing method thereof that can simultaneously achieve miniaturization and a significant reduction in the maximum operating voltage.
[0008]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a semiconductor substrate having a crest and a trough formed by processing the surface into a sawtooth shape, and a first insulating film formed in the trough of the semiconductor substrate via the first insulating film. A floating gate processed into a spire shape, and a control gate formed in a valley portion of the semiconductor substrate above the floating gate via a second insulating film, and a lower portion having a shape corresponding to the valley portion The top end of the floating gate and the bottom end of the control gate are arranged so as to face each other with the second insulating film interposed therebetween.
[0009]
The upper part of the floating gate is processed into a steeple shape, and the tip of the upper part of the floating gate and the lower part of the control gate having a shape corresponding to the valley are arranged so as to face each other. The maximum operating voltage required for electron injection or extraction can be reduced. In addition, a floating gate and a control gate are formed in a trough on the surface of the semiconductor substrate processed into a sawtooth shape, and an element is formed with this trough as a unit, so that the element area is reduced.
[0010]
Here, the injection of electrons into the floating gate or the extraction of the injected electrons may be performed by generating a tunnel current between the floating gate and the control gate via the second insulating film. Good.
[0011]
A first capacitor formed by the semiconductor substrate, the first insulating film and the floating gate; and a second capacitor formed by the floating gate, the second insulating film and the control gate. May be set by a ratio between the dimension of the bottom surface of the floating gate and the dimension of the bottom surface of the control gate.
[0012]
The NAND type nonvolatile memory device of the present invention has one terminal of a first transistor having a select gate, both terminals of at least two memory cell transistors each having a floating gate and a control gate, and a first gate having a select gate. One terminal of the second transistor is connected in series, the other terminal of the first transistor is connected to the select line, and the other terminal of the second transistor is connected to the bit line. In a semiconductor substrate having a crest and a trough formed by processing the surface in a sawtooth shape, an impurity diffusion layer is formed in the crest, and each impurity diffusion layer is separated from each other by a trough The first transistor includes a select gate formed in the valley via the first insulating film or the first and second insulating films, and peaks on both sides of the valley. And at least two of the memory cell transistors are formed in at least two valleys adjacent to the valley where the select gate of the first transistor is formed, respectively. Floating gates formed through an insulating film and processed in a spire shape at the top, control gates formed so as to face the upper part of the floating gate through the second insulating film, and respective troughs And the impurity diffusion layer formed on the crests on both sides of the memory cell, and the second transistor further includes a trough portion adjacent to at least two continuous trough portions where the floating gate of the memory cell transistor is formed. A select gate formed via the first insulating film or the first and second insulating films, and an impurity diffusion layer formed at the crests on both sides of the trough One of the two impurity diffusion layers of the first transistor that is not shared with the adjacent memory cell transistor is connected to the select line, and is adjacent to the two impurity diffusion layers of the second transistor The memory cell transistor that is not shared is connected to a bit line.
[0013]
According to the method of manufacturing a semiconductor device of the present invention, the surface of the semiconductor substrate is processed into a sawtooth shape to form a crest and a trough, and the first insulating film is formed on the top of the trough of the semiconductor substrate. Performing a step of forming a floating gate by depositing a conductive material on the surface of the first insulating film in a valley portion of the semiconductor substrate, and further performing a process of forming an insulating film. A step of processing the upper portion of the semiconductor substrate into a spire shape, a step of forming a second insulating film so as to cover the surface of the floating gate and the first insulating film in a valley portion of the semiconductor substrate, In the valley portion, a step of forming a control gate by depositing a conductive material on the floating gate via the second insulating film, the lower portion of the control gate is convex downward, The position of the top of the floating gate spire It is characterized by comprising the step of dynamically match.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0015]
The semiconductor memory device according to the present embodiment has a cell structure as shown in FIG. The surface of the p-type semiconductor substrate 11 is processed in a sawtooth shape so as to have the same interval as the minimum processing dimension F. An n ⁺ -type impurity diffusion region 12 is formed in the sawtooth crest, the impurity regions 12 are separated from each other by a trough, and an insulating film 13 having a thickness t1 is formed on the surface of the trough. Has been.
[0016]
A floating gate FG is formed on the insulating film 13. The floating gate FG has an upper portion processed into a spire shape.
[0017]
A tunnel oxide film 14 having a thickness t 2 is formed on the floating gate FG, and a control gate CG is formed on the tunnel oxide film 14. The upper portions of the control gate CG and the tunnel oxide film 14 are covered with an insulating film 15. Here, the lower portion of the control gate CG has a shape corresponding to the shape of the valley portion of the semiconductor substrate 11, and the spire-like upper portion of the floating gate FG is disposed so that the positions of its tips coincide with each other and face each other. Is done. The floating gate FG and the control gate CG are greatly different in relative size, and the floating gate FG is formed to be considerably smaller.
[0018]
Due to the ratio of the size of the floating gate FG and the control gate CG, the capacitance coupling ratio γ (= C 2 / C 1) of the capacitance C 2 of the tunnel oxide film 14 to the capacitance C 1 of the insulating film 13 is small. As a result, even if the control gate voltage VG applied between the substrate 11 and the control gate CG is low, FN tunneling occurs in the tunnel oxide film 14 between the floating gate FG and the control gate CG to generate a tunnel current, Data can be written or erased.
[0019]
In addition, the surface of the semiconductor substrate 11 is processed into a sawtooth shape, n ⁺ -type impurity diffusion regions 12 are formed in the peaks, and the impurity regions 12 are separated from each other by valleys. As a result, the source and drain regions formed of the n ⁺ -type impurity regions 12 can be stored in one valley. As a result, the width of the cell area can be made substantially the same as F, and miniaturization is achieved.
[0020]
Hereinafter, it will be described in detail with reference to FIG. 2 that the maximum operating voltage is reduced based on the capacitive coupling ratio between the insulating film 13 and the tunnel oxide film 14 according to the present embodiment. The insulating film 13 below the floating gate FG in the valley portion of the semiconductor substrate 11 is divided into three portions of regions 10, 11 and 12, and the respective capacities are C 10, C 11 and C 12.
[0021]
Each of the regions 11 and 12 is a parallel plate MOS capacitor having an area of s 1 · W, and each capacitance is represented by the following equation (1).
[0022]
[Expression 1]

Here, ε is the dielectric constant of the oxide film, and W is the channel width.
[0023]
The remaining region 10 has a finite value of the capacitance C10 unless dielectric breakdown occurs. Therefore, the total capacity C1 in the valley is expressed by the following equation (2).
[0024]
[Expression 2]

On the other hand, the capacitance C2 of the tunnel oxide film 14 above the floating gate FG is:
[0025]
[Equation 3]

It is expressed as
[0026]
Therefore, the capacitance coupling ratio γ of the capacitance C2 of the tunnel oxide film 14 to the capacitance C1 of the insulating film 13 is as follows.
[0027]
[Expression 4]

However, for the sake of simplicity, it is assumed that the insulating film 13 and the tunnel oxide film 14 are composed of oxide films having the same relative dielectric constant.
[0028]
Here, in order to enable data writing or erasing using the FN tunneling phenomenon between the floating gate FG and the control gate CG, which is a feature of the present embodiment, the following equation (5) is used. The condition needs to be met.
[0029]
[Equation 5]

Here, all the units related to the voltage are [V].
[0030]
In the equation (5), the inequality consisting of the first term and the second term indicates the lower limit of the control voltage VG for causing FN tunneling between the floating gate FG and the control gate CG. The inequality consisting of the terms indicates the upper limit value of the control voltage VG so that FN tunneling does not occur between the semiconductor substrate 11 and the floating gate FG.
[0031]
Further, even when a tunnel current flows directly through the thin insulating film 13 between the substrate and the floating gate FG at the time of writing or erasing data to which a high voltage is applied, electrons are transferred between the floating gate FG and the control gate CG. In order to allow injection or extraction, the following equation (6) needs to be satisfied.
[0032]
[Formula 6]

Further, in order to prevent the electron injection rate and the drawing rate from decreasing, the electric field F2 applied to the tunnel oxide film 14 is required to be about 10 ⁹ [V / m]. The value F2 obtained by dividing the above by the film thickness t2 of the tunnel oxide film 14 is as follows.
[0033]
[Expression 7]

Here, all the units relating to the length are angstroms.
[0034]
From the above formulas (5) and (7), the following formula (8) is derived.
[0035]
[Equation 8]

Further, when γ is 0 in the above equation (6), the following equation (9) is obtained by using the above equation (8).
[0036]
t1> 24 (9)
From the equations (8) and (9), the relational expression between the film thickness t1 of the insulating film 13, the film thickness t2 of the tunnel oxide film 14, and the capacitive coupling ratio γ is clarified.
[0037]
Next, the relationship between the maximum threshold voltage Vth and the control voltage VG in this embodiment will be considered. After injecting electrons into the floating gate FG, the threshold voltage Vth for reading data must be set so that electrons are not extracted from the floating gate FG by a reading voltage higher than Vth.
[0038]
An inversion layer is formed on the surface of the substrate 11 by the voltage V1 applied to the insulating film 13 in the valley of the substrate 11, and the threshold voltage Vth at that time is expressed by the following equation (10).
[0039]
[Equation 9]

Here, NA is the acceptor impurity density, and its unit is [cm ⁻³ ]. The inequality sign is used in this equation (10), but the inequality expression consisting of the first and second terms indicates that the control voltage VG must be higher than the threshold value Vth. From the second and third terms, This inequality indicates that the control voltage VG must be lower than the value that causes FN tunneling, as described above, when reading data.
[0040]
In this case, the conditions represented by the following formula (11) are required for the manufacturing process.
[0041]
[Expression 10]

Considering the condition indicated by the expression (11) and the condition indicated by the expression (8), the following expression (12) must be established.
[0042]
[Expression 11]

Here, when NA is 10 ¹⁷ [cm ⁻³ ], t 1 <2100 Å. Since the film thickness t1 of the insulating film 13 in an actual cell takes a value much smaller than 2100 angstroms, it is a condition that hardly needs to be considered.
[0043]
Next, the upper limit of the film thickness ratio t2 / t1 of the tunnel oxide film t2 to the film thickness t1 of the insulating film 13 is shown in FIG. 3 using the above equation (6). As is apparent from this figure, it can be seen that the film thickness ratio t2 / t1 monotonously increases with respect to the reciprocal 1 / γ of the capacitive coupling ratio. The film thickness ratio t2 / t1 also increases monotonously within the range of 3 to 10 [V] with respect to the control gate voltage VG.
[0044]
Here, within the range shown in FIG. 3, the film thickness ratio t2 / t1 always takes a value of 0.5 or more. Therefore, as a specific example of the cell, the case where the thickness of the insulating film t1 is 100 angstroms, the thickness of the tunnel oxide film t2 is 50 angstroms, and s1 is more than twice s2 is considered. ), The following equation (13) can be derived.
[0045]
γ ^-1 > s1 / s2> 2 (13)
By using this equation (13) and the above equation (5), it can be seen that a control gate voltage VG represented by the following equation (14) is required when data is written or erased.
[0046]
4.5 <VG <8.1 (14)
As shown in the equation (14), according to the present embodiment, the voltage applied between the substrate and the control gate is 4.5 to 8.1 [V], compared with the conventional one. Is also greatly reduced.
[0047]
Hereinafter, a method for manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIGS.
[0048]
First, the procedure for performing sawtooth processing on the surface of a semiconductor substrate will be described with reference to FIG. As shown in FIG. 4A, the n-type impurity diffusion layer 12 is formed on the (100) surface of the p-type semiconductor substrate 11. In this formation, for example, a silicon oxide film or a silicon nitride film is formed on the surface of the substrate 11 while introducing an n-type impurity, or after the formation, impurities are ion-implanted and thermal diffusion is performed to form a silicon oxide film or a silicon nitride film. This can be done by diffusing the impurities in the surface of the semiconductor substrate 11. A silicon nitride film 51 is formed on the n-type impurity diffusion layer 12 as a mask material by a CVD method. A resist film 52 patterned into a predetermined shape is formed on the silicon nitride film 51.
[0049]
As shown in FIG. 4B, the silicon nitride film 51 is etched using the resist film 52. Using the obtained silicon nitride film 51 as a mask material, crystallographic plane anisotropic etching (see LSI Handbook, Ohm Co., pages 264 to 265) is performed on the semiconductor substrate 11 as shown in FIG. 111) A V-shaped groove is dug so that the surface is exposed. At this time, it is necessary to set the depth of the groove and the depth of the impurity diffusion layer 12 so that the surface of the semiconductor substrate 11 is exposed on the bottom surface of the groove.
[0050]
As shown in FIG. 4D, after the trench is filled with the silicon oxide film 53 by the CVD method, the silicon nitride film 51 is peeled off as shown in FIG.
[0051]
Using the silicon oxide film 53 as a mask, crystallographic plane anisotropic etching is performed again on the semiconductor substrate 11 to dig a V-shaped groove as shown in FIG. Through these steps, the n ⁺ -type impurity diffusion layer 12 is formed in the peak portion, and the surface of the semiconductor substrate 11 is processed into a sawtooth shape in which the diffusion layers 12 are separated from each other by the valley portion.
[0052]
Next, the procedure for forming the floating gate and the control gate in the valley will be described with reference to FIG. As shown in FIG. 5A, the surface of the semiconductor substrate 11 is processed into a sawtooth shape at intervals of the minimum processing dimension F. Radical oxidation is performed on the surface of the semiconductor substrate 11 to form a thin silicon oxide film 21 as shown in FIG. In this case, since the oxidizing agent concentrates in the valley portion 22 of the semiconductor substrate 11, the silicon oxide film 21 is relatively thicker in the valley portion 22 than in other portions.
[0053]
As shown in FIG. 5C, the floating gate 23 made of crystalline silicon is formed on the surface of the silicon oxide film 21 in the valley portion by performing grapho epitaxial growth. Here, since the silicon constituting the floating gate 23 is epitaxial, the state of the interface is better than that of the conventional floating gate made of polycrystalline silicon.
[0054]
Further, when the radical oxidation treatment is performed again, the oxidation rate of the (111) plane of the substrate 11 appearing on the surface of the trough is high, so that the upper part of the floating gate 23 is a spire as shown in FIG. It is processed into a shape. In addition, since the oxidant does not collect in the lower part of the floating gate 23, the progress of oxidation is slower than in other parts, and as a result, the valley is rounded.
[0055]
Further, an oxidation process is performed to form a silicon oxide film 24 so as to cover the surface of the floating gate 23 and the surface of the silicon oxide film 21 as shown in FIG.
[0056]
As shown in FIG. 5F, the control gate 25 is formed on the floating gate 23 by performing grapho epitaxial growth again via the silicon oxide film 24. The lower part of the control gate 25 formed in this way has a shape corresponding to the shape of the valley part, and the top part of the floating gate 23 having a spire shape coincides with and faces the floating gate 23 by self-alignment. Be placed. Thereafter, as shown in FIG. 5G, a silicon oxide film 26 is deposited on the entire surface using the CVD method. Through the steps as described above, the semiconductor memory device according to the present embodiment can be manufactured.
[0057]
Next, a case where the semiconductor memory device according to the present embodiment is applied to a NAND type E ² PROM will be described. The circuit configuration in this case is as shown in FIG. One terminal of the source side select gate transistor T1 is connected to the select line SL, the other terminal of the transistor T1, both terminals of the memory cells MC1 to MC4 having the floating gate and the control gate, and the drain side select. One terminal of the gate transistor T2 is connected in series, and the other terminal of the transistor T2 is connected to the bit line BL via the bit line contact BLC. A select gate line SGS is connected to the select gate of the transistor T1, word lines WL1 to WL4 are connected to the control gates of the memory cells MC1 to MC4, and a select gate line SGD is connected to the select gate of the transistor T2. ing.
[0058]
When the semiconductor memory device according to the present embodiment is applied to the NAND type E ² PROM having such a circuit configuration, it has a cross-sectional configuration as shown in FIG. The surface of the p-type semiconductor substrate 11 is processed into a sawtooth shape, and an n-type impurity region 12 is formed at each peak. The transistor T1, the memory cells MC1 to MC4, and the transistor T2 are arranged in units of six valleys adjacent to each other in order in the semiconductor substrate 11. The transistor T1 has a select gate SGS in the valley, and the memory cells MC1 to MC4 are Each of the valleys has floating gates FG1 to FG4 and control gates CG1 to CG4, and the transistor T2 has a select gate SGD in the valley. The n-type impurity region 12 (T1a) corresponding to one terminal of the transistor T1 is connected to the select line SL, and the n-type impurity region 12 (T2b) corresponding to one terminal of the transistor T2 is connected to the bit line BL. .
[0059]
The n-type impurity region 12 (T1b) corresponding to the other terminal of the transistor T1 is shared at the same peak as the one n-type impurity region 12 (MC1a) of the memory cell MC1, and the other n-type of the memory cell MC1. Impurity region 12 (MC1b) and one n-type impurity region 12 (MC2a) of memory cell MC2 are shared by the same peak. The other n-type impurity region 12 (MC2b) of the memory cell MC2 and one n-type impurity region 12 (MC3a) of the memory cell MC3 are shared at the same peak, and the other n-type impurity region 12 of the memory cell MC3 is shared. (MC3b) and one n-type impurity region 12 (MC4a) of memory cell MC4 are shared in the same peak. Similarly, the other n-type impurity region 12 (MC4b) of the memory cell MC4 and the n-type impurity region 12 (T2a) corresponding to the other terminal of the transistor T2 are shared by the same peak portion.
[0060]
The select gate SGS of the transistor T1 and the select gate SGD of the transistor T2 may be formed in the same process as the floating gates FG1 to FG4 of the memory cell transistors MC1 to MC4, or the control gates of the memory cell transistors MC1 to MC4. You may form in the same process as CG1-CG4.
[0061]
In this way, by applying this embodiment to the NAND type E ² PROM, the transistors T1 and T2 and the memory cells MC1 to MC2 are continuously arranged in units of troughs of the semiconductor substrate processed into a sawtooth shape. As a result, the degree of integration is improved, and element isolation of each impurity region 12 can be easily performed by utilizing the valleys.
[0062]
The above-described embodiment is an example and does not limit the present invention. For example, various manufacturing conditions, film thicknesses, materials, and the like in the manufacturing method according to the above embodiment are examples, and can be changed as necessary. The semiconductor memory device according to the present invention is not limited to the NAND type E ² PROM, and may be applied to other various memory devices.
[0063]
【The invention's effect】
As described above, according to the semiconductor memory device and the method of manufacturing the same of the present invention, in the valley portion of the semiconductor substrate processed into a sawtooth shape, the floating gate having a spire-shaped upper portion and the valley portion shape. Correspondingly, the control gate having an acute shape facing downward is arranged so as to oppose, so that the maximum operating voltage required for data writing or erasing is reduced and the degree of integration is improved. Is possible.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view showing a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a longitudinal sectional view showing a cross section of a floating gate in the semiconductor memory device in more detail.
FIG. 3 is a graph showing a relationship among a film thickness ratio, a control gate voltage, and a capacitive coupling ratio in the semiconductor memory device.
FIG. 4 is a longitudinal sectional view showing a procedure for performing sawtooth processing on the surface of the semiconductor substrate as a pre-stage for manufacturing the semiconductor memory device;
FIG. 5 is a longitudinal sectional view showing a sectional structure of an element for each process when manufacturing the semiconductor memory device;
FIG. 6 is a circuit diagram showing a circuit configuration of a NAND E ² PROM.
FIG. 7 is a longitudinal sectional view showing a sectional structure when the present embodiment is applied to the NAND type E ² PROM;
[Explanation of symbols]
11 p-type semiconductor substrate 12 n ⁺ -type impurity regions 13, 15, 21, 22, 26, 53 Silicon oxide films 14, 24 Tunnel oxide film 51 Silicon nitride film 52 Resist film FG, 23 Floating gate CG, 25 Control gate WL1 WL4 Word line SL Select line SGS, SGD Select gate BL Bit lines MC1-MC4 Memory cells T1, T2 Select gate transistors

Claims (5)

A semiconductor substrate having a crest and a trough formed by processing the surface into a sawtooth shape;
A floating gate formed in the valley portion of the semiconductor substrate via the first insulating film, and the upper portion processed into a spire shape;
A control gate formed in a valley portion of the semiconductor substrate above the floating gate via a second insulating film, and a lower portion having a shape corresponding to the valley portion;
With
A semiconductor memory device, wherein the top end of the floating gate and the bottom end of the control gate are arranged to face each other with the second insulating film interposed therebetween. Injecting electrons into the floating gate or extracting the injected electrons is performed by generating a tunnel current between the floating gate and the control gate through the second insulating film. The semiconductor memory device according to claim 1. A first capacitor formed by the semiconductor substrate, the first insulating film, and the floating gate; and a second capacitor formed by the floating gate, the second insulating film, and the control gate. 3. The semiconductor memory device according to claim 1, wherein the capacitive coupling ratio is set by a ratio of a dimension of the bottom surface of the floating gate and a dimension of the bottom surface of the control gate. One terminal of the first transistor having the select gate, both terminals of at least two memory cell transistors having the floating gate and the control gate, and one terminal of the second transistor having the select gate are connected in series. A NAND type nonvolatile memory device in which the other terminal of the first transistor is connected to a select line, and the other terminal of the second transistor is connected to a bit line;
In the semiconductor substrate in which the surface has a crest and a trough formed by processing in a sawtooth shape, an impurity diffusion layer is formed in the crest, and each impurity diffusion layer is separated from each other by the trough,
The first transistor includes a select gate formed in the valley via the first insulating film or the first and second insulating films, and impurity diffusion formed in the peaks on both sides of the valley. And having a layer
At least two of the memory cell transistors have an upper portion formed through the first insulating film in at least two continuous valleys adjacent to the valley where the select gate of the first transistor is formed. A floating gate, a control gate formed on the floating gate so as to be opposed to each other with the second insulating film interposed therebetween, and an impurity diffusion layer formed on the crests on both sides of each trough Have
The second transistor may include the first insulating film or the first and second insulating films in a valley portion further adjacent to at least two continuous valley portions where the floating gate of the memory cell transistor is formed. And a select gate formed through, and an impurity diffusion layer formed in each of the peaks on both sides of the valley,
Of the two impurity diffusion layers of the first transistor, the one not shared with the adjacent memory cell transistor is connected to a select line, and the adjacent memory cell of the two impurity diffusion layers of the second transistor What is not shared with a transistor is connected to a bit line. Processing the surface of the semiconductor substrate into a sawtooth shape, forming a crest and a trough;
Forming a first insulating film on the top of the valley of the semiconductor substrate;
Forming a floating gate by depositing a conductive material on the surface of the first insulating film in the valley portion of the semiconductor substrate;
Further, by performing a process of forming an insulating film, processing the top of the floating gate into a spire shape,
Forming a second insulating film so as to cover the surface of the floating gate and the first insulating film in the valley portion of the semiconductor substrate;
Forming a control gate by depositing a conductive material on the upper portion of the floating gate via the second insulating film in a valley portion of the semiconductor substrate, wherein the lower portion of the control gate is convex downward And automatically matching the position of the spire-shaped upper part of the floating gate;
A method of manufacturing a semiconductor memory device.

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