JP3862683B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device in which a plurality of photoelectric conversion blocks that can be driven independently and whose output conditions are determined are arranged.

  In general, solid-state imaging devices have various photoelectric readout methods such as a CCD type, a MOS type, and a bipolar type, and a CCD type that is excellent in image quality is often used for video cameras and the like. On the other hand, the latter two have been attracting attention because of their merit that noise resistance has improved in recent years, low power consumption has been achieved, one-chip including peripheral circuits can be realized, and miniaturization is possible.

  In recent years, an example has been proposed in which photoelectric conversion elements are formed into blocks, and photoelectric conversion blocks in which drive and output conditions can be determined independently are formed. An example of one photoelectric conversion block in a solid-state imaging device in which a plurality of photoelectric conversion blocks are arranged will be described with reference to FIG. This figure is a one-dimensional image sensor, 1 is a photoelectric conversion pixel, which is composed of a bipolar transistor 2 and its base reset MOS transistor 3, and in particular a PN junction (not shown) formed in the base region of the bipolar transistor 2. By irradiating the part with light, a signal voltage corresponding to an increase in base potential caused by accumulation of photogenerated charges is output from the emitter of the bipolar transistor 2. As shown in FIG. 3, a plurality of the pixels 1 are arranged over one line.

  Reference numeral 50 is a voltage supply source for resetting the base of the pixel 1, 4 is a pixel output line connected to the emitter of the bipolar transistor 2, 5 is a reset MOS transistor of the pixel output line 4, and 6 is the base of the output line 4. Bipolar transistors to be connected, and their emitters are connected to a common connection line 7 with the emitters of the bipolar transistors 6 in each column. The bipolar transistor 6 serves to detect the maximum output of the photoelectric conversion output, and a voltage corresponding to the maximum output of the pixel array appears on the connection line 7.

  8 is a storage capacitor for storing the output voltage of the pixel, 9 is a switching MOS transistor for connecting and disconnecting the pixel output line 4 and the capacitor 8, 10 is a MOS transistor switch for selecting the capacitor 8, and 11 is a MOS transistor. A shift register that sequentially selects the switch 10 by outputting a control signal to the gate of the switch 10, 12 is an output line that reads the photocharge read from the selected capacitor 8, 13 is an amplifier that receives the output line 12, 14 is an output terminal of the amplifier 13, 15 is a comparator for judging the magnitude of the output value of the output line 7, 16 is a control circuit for driving and controlling the photoelectric conversion block, and 17 is for driving the shift register 11. The clock signal, the inverted clock signal, the drive line for the start signal, 18, 19, and 20 are the gates of the MOS transistors 3, 5, and 9, respectively. A drive line for applying a drive pulse, 21 is a wiring for supplying a comparison potential of the comparator 15, 22 is a latch circuit for latching the output of the comparator 15, and 23 is a control line for controlling the gain of the amplifier 13. is there.

  In the example shown in FIG. 3, after resetting the pixel 1, the capacitor 8, and the latch circuit 22 all at once, the switch 9 is kept conductive while the drive line 20 remains at the high level. As the signal charge is accumulated in the pixel 1, the potentials of the pixel output line 4 and the capacitor 8 also rise. When the output corresponding to the maximum value of these pixel outputs exceeds the comparison potential determined by the wiring 21, the comparator When the output of 15 is inverted and the latch circuit 22 is switched, the wiring 20 becomes Low and the switch 9 is turned off. Therefore, the signal accumulated in the pixel up to that point is held in the storage capacitor 8. The control line 23 that supplies a control voltage that determines the gain of the amplifier 13 is determined by the set potential of the wiring 21 and the time until the latch is switched.

  In a solid-state imaging device having a plurality of photoelectric conversion blocks as shown in FIG. 3, even when the light intensity in each block is significantly different, the accumulation time of pixel signals in each block is different, and an output value of the same level can be obtained. In FIG. 3, a bipolar pixel is taken as an example, but generally any photoelectric conversion pixel may be used, and the monitor of the pixel output is not limited to the maximum value detection, either the minimum value detection or the maximum value and the minimum value. It may be a value difference detection or the like.

  However, there is no problem when there are a small number of photoelectric conversion blocks as in the above-mentioned conventional example and each block is formed at a position away from each other. However, the number of photoelectric conversion blocks increases, and the photoelectric conversion units of each block become dense. When a request to place the drive control circuit 16 is made, a space for placing the drive control circuit 16 and the shift register 11 cannot be allocated.

  An object of the present invention is to provide means for independently driving and controlling a plurality of photoelectric conversion blocks even when they are arranged densely.

In order to achieve the above object, the present invention provides a photoelectric conversion unit in which a plurality of photoelectric conversion blocks each including a plurality of photoelectric conversion pixels are provided, a plurality of signal holding units corresponding to each of the plurality of photoelectric conversion pixels, One or more photoelectric conversion block signals of a photoelectric conversion block are independently output to an output line, and further, a drive circuit for transferring the signal of the output line to the signal holding means, and a signal of the photoelectric conversion pixel as a reference A comparison circuit for comparing with a value, and a memory in which at least a signal accumulation time for each photoelectric conversion block controlled based on an output of the comparison circuit is written and an address is assigned to each photoelectric conversion block, And the drive circuit accesses an address assigned to each photoelectric conversion block of the memory and records the light recorded in the memory. In response to a signal storage time of each transform block, and controlling the transfer of signals to the signal holding means from the output line.

  According to the present invention, it is possible to perform independent driving and control for each block even for blocks of photoelectric conversion units that are required to be arranged densely.

  In addition, even if the number of photoelectric conversion blocks increases and the photoelectric conversion units of each block need to be densely arranged, the space for arranging the drive control circuit and the shift register cannot be allocated. It is possible to easily cope with the majority of photoelectric conversion blocks.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to FIG. In the figure, reference numeral 1 denotes a photoelectric conversion pixel, which is composed of a reset MOS transistor and a bipolar transistor having a PN junction portion of a photoelectric conversion element as a base, as in FIG. 3. In general, in a read operation, a signal is read nondestructively. Shall be. Reference numeral 24 denotes a photoelectric conversion unit block, in which four blocks 24-1, 24-2, 24-3, and 24-4 are formed. Reference numeral 25 denotes a drive line for photoelectric conversion pixels, and 26 denotes an analog memory cell corresponding to each photoelectric conversion pixel. In this figure, the drive circuit includes a capacitor 8 serving as a memory and a switch 51. The gate of the switch 51 is turned on / off. Then, it is driven by a drive line 27 that performs writing and reading of the memory.

  Reference numeral 28 denotes a decoder, and a block driven by the address line 32 is selected. Also, 29 is a buffer for selecting the drive line 25 based on the output of the decoder 28-1, 30 is a buffer for selecting the drive line 27 of the analog memory in response to the output of the decoder 28-2, and 31 is a control condition for each block. The digital memory is accessed by the output of the decoder 28-3. Reference numeral 33 denotes a wiring output from the drive control circuit 16 for driving the photoelectric conversion pixel block. Reference numeral 34 denotes a drive line output from the drive control circuit 16 for the analog memory block. Reference numeral 35 denotes information written in the digital memory 31. A wiring 36 for reading information from the digital memory 31 is provided. In addition, the description which overlaps about the same code number as FIG. 3 is abbreviate | omitted.

  Next, the operation of this embodiment will be described. In this embodiment, first, the photoelectric conversion unit including the pixel 1, the analog memory unit including the capacitor 8, and the digital memory unit including the decoder 28-3 are all reset, and then driving is started. The photoelectric conversion unit is reset by activating the reset MOS transistor 3 with the potential of the drive line 25 being negative and then activating the transistor 1 with the potential of the drive line 25 being positive and simultaneously turning on the MOS transistor 5. At this time, the base current flows, the base of the transistor 1 is reset, and then the drive line 25 is returned to GND, whereby the transistor 1 is reverse-biased. The analog memory section is reset by turning on the switch 51 and the switch 9 and dropping to the ground potential through the MOS transistor 5. The digital memory section is reset by writing “1” or “0” to all addresses.

  Next, the address lines output from the drive control circuit 16 are switched, and readout is repeated in the order of the photoelectric conversion unit blocks 24-1, 24-2, 24-3, 24-4. The information in the digital memory 31 is also accessed.

  After a certain period of time, for example, when the output of the block 24-2 inverts the comparator 15, that is, one of the photoelectric conversion charges in the pixel of the block 24-2 becomes larger than the threshold value from the wiring 21. At this time, a pulse for writing to the block corresponding to the block 24-2 of the analog memory is applied to the wiring 34. At the same time, information such as the signal transfer, the signal accumulation time at that time, and the amplifier gain at the time of output from the analog memory is written into the address address corresponding to the block 24-2 of the digital memory 31. When the block 24-2 is driven once again, even if the comparator 15 is inverted, the drive control circuit 16 transfers the analog memory to the analog memory according to the address address information corresponding to the block 24-2 accessed from the digital memory 31. No write pulse is issued, and rewriting to the digital memory 31 is not performed. For this reason, the analog memory and digital memory 31 hold information when the monitor output of the photoelectric conversion block first reaches a predetermined level.

  When the driving of the photoelectric conversion unit is finally finished, the switch 9 is turned off, and the output from the analog memory is read according to the scan of the shift register 11, but when the analog memory block is designated, the digital memory corresponding to that block is read The information 31 is also accessed, the designated amplifier gain is designated, and the output signal 12 is read from the output line 12 via the amplifier 13.

  As described above, by providing the digital memory 31 that can input and output control information for each block of the photoelectric conversion unit and the analog memory, a plurality of photoelectric conversion blocks 24-1, -2, and -3 arranged densely are provided. , -4 can be independently driven and controlled using a common drive circuit, a common monitor circuit, a common shift register, and a common output amplifier.

(Second Embodiment)
FIG. 2 is a diagram showing a second embodiment of the present invention. In FIG. 2, in the photoelectric conversion pixel array, the first row and the third row are each divided into two photoelectric conversion blocks, That is, a case is shown in which block arrangements such as 24-1-1 and 24-1-2 and 24-3-1 and 24-3-2 are arranged.

  In FIG. 2, reference numeral 40 denotes a switching MOS transistor that connects the detection circuit 6 and the output line 7, and is turned on / off by an output line 41 from the drive control circuit 16. Two drive lines 42 and 43 appear in the first row and the third row so that the analog memory unit also corresponds to the block arrangement of the photoelectric conversion unit. In the photoelectric conversion unit, the drive lines 25 are arranged in the same manner as the first row, the third row, the second row, and the like, and drive the pixels 1 from the decoder 28-1 through the buffer 29. On the other hand, the analog memory unit having the storage capacitor 8 is divided into the drive lines 42 and 43 in accordance with the row-division photoelectric conversion block as described above, and the storage capacitor can be controlled from the decoder 28-2 via the buffer 30. It has become.

  The digital memory unit 37 is a ROM (read-only memory, read-only storage device) indicating whether a row selected by the address line 32 is one block or two blocks. The output 38 of the ROM 37 is determined so as to be Low when the selected row is one block and High when the selected row is two blocks. Therefore, when the drive control circuit 16 designates the address line 32, it can be easily known from the feedback of the output 38 whether the block of the row is divided by the address.

  When the output 38 is High, the selection of two blocks belonging to the selected row is determined by the address line 39. When the output 38 is low, the two control lines 41 are simultaneously turned on. When the output 38 is high, the two control lines 41 are alternately turned on because the two blocks are selected separately. The pulse is output. Therefore, the drive control circuit 16 can easily detect the maximum value of the photoelectric charge from the detection circuit 6 for every two blocks in the row, and outputs the detection level to the output line 7 and the comparator 15 sets the threshold value. In comparison, the photoelectric charge can be accurately stored in the digital memory 31, and can be read out from the analog memory unit to the output line 12 and an image signal can be output via the amplifier 13.

  The address line 39 is also input to the analog memory buffer 30. When there are two blocks for one row, the blocks can be controlled separately.

  2 having the same reference numerals as those in FIG. 1 have a common function, and redundant description is omitted. Thus, even in an arrangement having a plurality of blocks in one row, digital By adding a ROM for distinguishing the block arrangement pattern for each row to the memory 31, a plurality of photoelectric conversion blocks can be independently driven and controlled using a common detection, drive, and circuit. It can be made possible.

It is a circuit diagram explaining a 1st embodiment by the present invention. It is a circuit diagram explaining a 2nd embodiment by the present invention. It is a circuit diagram explaining the photoelectric conversion apparatus of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion pixel 2 Bipolar transistor 3 MOS transistor 4 Output line 5 Reset MOS transistor 6 Output monitor element 7 Output line 8 Storage capacity 9 MOS transistor 10 MOS transistor 11 Shift register 12 Output line 13 Amplifier 14 Output terminal 15 Comparator
16 drive circuit 17, 18, 19, 20 drive wiring 21 reference potential 22 latch circuit 23 gain control line 24 photoelectric conversion block 25 row selection line (drive line)
26 Analog Memory Pixel 27 Row Selection Line 28 Decoder 29, 30 Buffer Circuit 31 Digital Memory 32 Address Line 33, 34 Drive Line 35 Write Line 36 Read Line 37 ROM
38 Memory output line 39 Address line 40 Switch MOS transistor 41 Control line 42, 43 Drive line

Claims (4)

A photoelectric conversion unit provided with a plurality of photoelectric conversion blocks each including a plurality of photoelectric conversion pixels ;
A plurality of signal holding means corresponding to each of the plurality of photoelectric conversion pixels;
A drive circuit for independently outputting a signal of one or a plurality of the photoelectric conversion blocks of the photoelectric conversion block to an output line, and further transferring a signal of the output line to the signal holding unit;
A comparison circuit that compares a signal of the photoelectric conversion pixel with a reference value;
A signal storage time for each photoelectric conversion block controlled based on an output of the comparison circuit is written at least, and an address is assigned to each photoelectric conversion block, and
The drive circuit accesses an address assigned to each photoelectric conversion block of the memory, and from the output line to the signal holding means according to the signal accumulation time for each photoelectric conversion block recorded in the memory. A solid-state imaging device that controls signal transfer . 2. The amplifier according to claim 1, further comprising an amplifier that amplifies the signal output from the signal holding unit, wherein an amplifier gain based on a signal accumulation time for each photoelectric conversion block is recorded in the memory. Solid-state imaging device. The signal accumulation time for each photoelectric conversion block based on the comparison result of the comparison circuit is recorded in the memory, and the recorded information in the memory is held at the signal accumulation time for the first photoelectric conversion block based on the comparison result of the comparison circuit. The solid-state imaging device according to claim 1 , wherein the solid-state imaging device is provided. 4. The solid-state imaging according to claim 1, wherein a ROM in which an array pattern of the photoelectric conversion blocks that are independently driven by the drive circuit is recorded is added to the memory. 5. Equipment .

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