JP3854572B2 - Microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor capable of preventing runaway of a microprocessor used in an environment where noise is generated, particularly in a game hall, and prohibiting the execution of an illegally altered program in real time. .
[0002]
[Prior art]
The conventional way to stop the runaway of the microprocessor is to compare the output of the PROM with two or more identical contents storing the microprocessor and microprocessor program and the output of the control PROM when the microprocessor is in operation, and the output data is different A function is provided to stop the microprocessor when it is in the middle (see Patent Document 1).
[0003]
Also, a program counter that counts the program execution address, an adder that cumulatively adds the contents of the program counter each time the program counter is incremented, a checksum buffer that holds the addition result, and stored in advance in the object program instruction A comparator that compares the checksum data with the output data from the checksum buffer, and has a function of stopping the microprocessor by using the mismatch output signal of the comparator as a reset signal (see Patent Document 2) ).
[0004]
Further, when the microprocessor reads a work area or an operand as an operation code, the microprocessor is interrupted to initialize the program to prevent the microprocessor from malfunctioning (see Patent Document 3).
[0005]
Corresponding to the address and stored contents of the ROM for storing the program of the microprocessor, the signal storing one logic level is stored in the address corresponding to the address in which the ROM storing the program stores the operation code, A ROM that stores the program stores an address corresponding to an address that stores other than an opcode, a storage circuit that stores a signal of the other logic level, an output signal of a fetch timing detection circuit provided in a microprocessor, The microprocessor is stopped by checking for coincidence and inconsistency with the output signal of the memory circuit (see Patent Document 4).
[0006]
Also, a discrimination bit indicating whether it is an opcode or an operand is added to the instruction word, the discrimination bit of the stored instruction word is output from the instruction register, and the instruction word stored in the instruction register is decoded as an opcode from the instruction decoder A signal indicating whether to decode as an operand is output, the outputs of the instruction register and instruction decoder are compared, and if they do not match, an interrupt is requested and the microprocessor is stopped (see Patent Document 5).
[Patent Document 1]
JP-A-2-307125
[Patent Document 2]
JP-A-9-319621
[Patent Document 3]
JP-A-5-233339
[Patent Document 4]
JP 7-319734 A
[Patent Document 5]
JP-A-5-020058
[0007]
[Problems to be solved by the present invention]
One of the causes of the runaway of the microprocessor may occur when the microprocessor reads the instruction code from the program storage means storing the program by mistakenly reading the code. The program including the instruction code is stored in the program storage means, and the program storage means is connected to the microprocessor by a data bus (for example, eight in the current gaming machine microprocessor). The instruction code for the microprocessor is read into the microprocessor via the data bus and executed. At this time, if the relationship between 0 and 1 breaks down even with one data bus due to the influence of noise generated from static electricity or power, etc., it is executed as an incorrect instruction code. The instruction code to the microprocessor consists of only the opcode or the pair of opcode and operand. The instruction length (1 step instruction length) is 1 byte instruction if only the opcode is specified, and if it consists of a pair of opcode and operand. There are also 2-byte instructions, 3-byte instructions, and some 4-byte instructions. There are many different steps with different lengths, and they are lined up in the program storage means. For example, if an actual 3-byte instruction is mistakenly interpreted as a 2-byte instruction, the remaining 1 byte is the next. It is recognized as an order and is wrong.
[0008]
Thus, when the runaway of the microprocessor occurs, even if the conventional microprocessor detects the runaway, all of them are reset to the initial state by reset and the instruction program is executed again from the initial state. Therefore, even if it was detected that the microprocessor was running out of control, it was not possible to return to the state immediately before the runaway and continue the program. In particular, in the game hall, a large amount of static electricity was generated mainly due to replenishment of pachinko balls, movement of balls for recovery, etc., which was not a good operating condition for the microprocessor. In addition, in gaming machines, from the standpoint of mounting illegal parts by illegal groups and preventing falsification of programs, the state of the board on which the chip is mounted is housed in a transparent case so that it can be seen from the outside. The noise countermeasures could not be done. For this reason, we have sought a method that is strong against noise, such as the arrangement of components in the chip, the ingenuity of the wiring pattern, and shielding, with regard to the runaway of the microprocessor, but none has been decisive.
[0009]
[Means for Solving the Problems]
The present invention provides an area different from an area in which the instruction code is stored in a first encryption code generated by a predetermined calculation method from an operation code of an operation code of a machine language program or an operation code and an operand pair. And when the microprocessor reads the instruction code, the second encryption code calculated by the certain calculation method is compared with the first encryption code. If the result of comparing the second encryption code with the first encryption code does not match, the value of the program counter is returned to the value before reading the instruction code and the instruction is executed again. It is a microprocessor characterized by reading a code.
[0010]
Also, it has a program counter and a copy program counter for saving the value of the program counter, and if the second encryption code and the first encryption code are compared, if they match, the program counter value is written to the copy program counter. If they do not match, the value of the copy program counter can be written to the program counter.
[0011]
Further, if the second encryption code and the first encryption code do not match, the counter has a counter that counts the number of times that they do not match, and this counter knows this value externally at an arbitrary time. Can be squeezed. Further, when the value of the counter reaches a certain value, recording can be stopped, and a reset signal can be output to return to the initial state.
[0012]
All of such microprocessors can be used as microprocessors for gaming machines.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a calculation logic in accordance with a certain calculation rule is prepared for each instruction code of one step, and a value calculated there (hereinafter referred to as a first encryption code) is stored in advance in an instruction code. The code is derived from the calculation result (hereinafter referred to as second encryption code) and the stored first encryption code is compared.
[0014]
In the present invention, the constant calculation method may be any calculation method such as simple addition / subtraction / division / division, a constant equation, or a hash function. For example, when a microprocessor for gaming machine reads an operation code consisting of an operation code or an operation code / operand pair, the same calculation logic is used in the microprocessor before the operation code is executed.
[0015]
In the present invention, the first encryption code is stored in an area different from the area where the instruction code is stored. However, the storage area for storing the first encryption code is provided separately from the other area. Alternatively, a common bank switching method may be used in which two storage units are arranged at the same address and switched as necessary. If the bank switching method is used, it is not necessary to calculate the offset between the address of the instruction code and the address of the first encryption code, which is convenient.
[0016]
If the instruction code is encrypted one byte at a time, it is assumed that the first encryption code and the second encryption code coincide by chance when jumping into the middle of the program due to the influence of noise etc. It is preferable that 3 bytes are agitated with 3 bytes and 2 bytes are agitated with 2 bytes. The calculation results may be the same length or may be reduced in size by a hash function or the like. In the case where a security effect for preventing unauthorized decoding and tampering of the code is required, a complicated object using a variable key is more preferable.
[0017]
The length of the code of the instruction code may be any number of bytes, but if the Z80 microprocessor is taken as an example, it will be either a 1-byte instruction or a 4-byte instruction. To create a 1-byte encryption code from an instruction code with a different code length from 1-byte instruction to 4-byte instruction using a hash function, a maximum number, that is, a 4-byte buffer is prepared and a constant (such as 00) is used. Insert. The operation of encrypting the instruction code and creating the first encryption code is performed for all steps of the program. The storage means for storing the first encryption code basically needs to be equivalent to the program size, but there is no need to consider the data area, so when used in the current gaming machine microprocessor, a maximum of 3 kilobytes Just increase.
[0018]
The microprocessor of the present invention is provided with a program counter and a copy program counter for storing the value of the program counter. At the initial stage, both the program counter and the copy program counter are set as the values at the head address of the program.
[0019]
When the gaming machine microprocessor reads an instruction code consisting of an opcode or an opcode / operand pair, the second encryption code calculated by the calculation logic before executing the instruction and the area where the instruction code is stored Of the first encryption codes stored in advance in another area, the first encryption code at the position corresponding to the instruction code is put in a comparator to check the consistency. If they match, the instruction code is executed after the value of the program counter is written to the copy program counter. If they do not match, the value of the copy program counter is written into the program counter, returned to the beginning of the program step, and the instruction code is read again. Even if part of the contents of the program is tampered with, the microprocessor does not tamper with the first encryption code placed in an area other than the area where the instruction code is stored. Only the comparison operation of the second encryption code is repeated, and the next instruction code is never executed. For this reason, when this microprocessor is used as a gaming microprocessor, the game stops and helps prevent falsification of the program.
[0020]
Even if it is a legitimate program, it can be imagined that reading frequently occurs again in the operation in a place where the noise environment is bad. In the present invention, a counter that increments every time reading occurs and a circuit that outputs the counter to the outside at an arbitrary time or resets the counter from the outside are provided. By examining the value of this counter at a certain time, it is possible to grasp the operating state of the gaming machine under noise, which is useful for improving the noise environment.
[0021]
Since an actual program is packed with instruction codes, it is not known where the instructions are separated. How to encrypt in such a state is described. A pseudo processor that does not operate an instruction execution circuit by using an instruction decode circuit of a microprocessor used in a gaming machine is used. The pseudo processor can be easily realized by adopting a configuration in which the left part of the vertical dotted line (register A101, register B102, calculation unit 106) in FIG. Since the pseudo processor does not execute an instruction, even if there is a jump instruction or a conditional branch, for example, only the instruction length is notified in the order written in the storage means. The rest can be done efficiently by generating a cryptographic code using calculation logic according to the instruction length.
[0022]
(Specific examples of the invention)
Based on the figure, the structure of a microprocessor that prevents runaway and prohibits the operation of an illegally tampered program will be described.
[0023]
FIG. 1 is a block diagram of an arithmetic unit of a Z80 microprocessor generally used for gaming machines and the like. The flow is such that an instruction is decoded, a value is set in a necessary register, and then an operation is performed. In the description of the present invention, this Z80 microprocessor will be described as an example, but other microprocessors are basically unchanged.
[0024]
FIG. 2 shows a structure for determining whether or not the instruction code read from the storage means by the microprocessor via the data bus is a correct code in the present invention. The AA BB CC code written in the program bank 209 in the storage means surrounded by a dotted line is a 3-byte instruction, and these 3 bytes are the same as the DD using the same calculation method as the encryption calculation logic 205. One encryption code is written in advance at the next address of the encryption data bank 210. Note that the same calculation method as that of the encryption calculation logic 205 may be set as appropriate according to the environment in which the microprocessor is used. When used in a place where tampering or unauthorized decryption does not occur, the encryption calculation logic 205 may only perform simple calculations such as addition, or when it is necessary to prevent tampering or unauthorized decryption, Calculations using esoteric encryption keys may be performed. A value (null code or the like) that cannot exist in calculation is put in an address that is not used in the encryption data bank 210, or is filled with DD. In this example, DD is 1 byte, but of course, 2 bytes or 3 It may be the same size as the byte or instruction code.
[0025]
When the Z80 microprocessor reads the operation code AA, the instruction decode circuit (not shown) in the CPU controller 201 decodes the 3-byte instruction and reads the remaining 2-byte operand. At this time, instruction codes read by the Z80 microprocessor are sequentially transferred to the 4-byte buffer 204 via a circuit (hereinafter referred to as an additional circuit) added to the microprocessor to execute the present invention.
[0026]
While the Z80 microprocessor stores the value in the required register based on the operand, the additional circuit generates a 1-byte second encryption code through the encryption calculation logic 205. At the same time, the additional circuit switches the storage means bank to the encryption data bank 210 and sends the data at the address pointed to by the program counter, that is, the first encryption code DD to the comparator 206. If the encryption value generated by the encryption calculation logic 205, that is, the second encryption code is DD, the comparator 206 issues a coincidence signal, and the Z80 microprocessor that has confirmed this coincidence signal executes the instruction code and program counter. The value 202 is written into the copy program counter 203. In the case of mismatch, the comparator 206 outputs a mismatch signal, increments the value of the error counter 207, and simultaneously writes the value of the copy program counter 203 into the program counter 202 to read AA which is the opcode portion of the instruction code again.
[0027]
The error counter 207 is a counter that records the number of times the runaway has occurred, and the value of the error counter 207 can be notified to the outside. Further, the error counter 207 outputs a signal to the reset means 208 of the microprocessor when the number of times of runaway exceeds a certain number. The reset means 208 of the microprocessor that has received the signal from the error counter 207 outputs a reset signal for returning the microprocessor to the initial state.
[0028]
If the microprocessor calculates the 3-byte instruction mistakenly as the 2-byte or 1-byte instruction, the first encryption code stored at the address indicated by the program counter 202 is a null code or DD, and the calculations match. There is nothing.
[0029]
No matter how complicated the calculation is, encryption from 1 byte to 4 bytes can be decrypted just by sampling which instruction becomes what kind of encryption if many encryption programs are analyzed There is. Therefore, it is also conceivable that an encryption code XX or the like obtained by stirring all program codes with a hash function or the like is separately created and mixed as encryption information in a DD made from AA, BB, and CC. In this way, if all the information of the program is involved in the creation of the code, it will not be easily deciphered.
[0030]
FIG. 3 is a data processing flow of a known Z80 microprocessor. First, the microprocessor reads the operation code from the instruction code in S301, and increments the program counter in S302. In step S303, the instruction code is decoded to recognize how many bytes the instruction is. The Z80 microprocessor only has a maximum of 4 byte instructions. If the instruction is a 1-byte instruction (only the operation code) in S304, the process proceeds to S305 as it is.
[0031]
In the case of a 2-byte instruction (opcode + operand) in S306, the byte counter is set to 1 in S307, the operand is read in S308, transferred to the CPU buffer in S309, the pointer is incremented in S310, and the program counter in S311 In step S312, the byte counter is decremented. In step S313, the byte counter is checked. If the instruction is a 2-byte instruction, it is confirmed here that the byte counter is 0, and the process proceeds to step S305.
[0032]
In the case of a 3-byte instruction (opcode + operand + operand) in S314, the byte counter is set to 2 in S315, and the same steps S308 to S312 are performed as in the 2-byte instruction until the byte counter becomes 0 in S313. Thereafter, execution is performed in S305.
[0033]
If it is determined in S314 that the instruction is not a 3-byte instruction, it is a 4-byte instruction (opcode + opcode + operand + operand), so the operation code is read in S316, the instruction is decoded in S317, and the byte counter is set to 2 in S315. Set. After S308, after going through the same process as the 3-byte instruction, the process proceeds to S305.
[0034]
FIG. 4 shows a typical flow of the present invention in which the processing of the present invention is added to a Z80 microprocessor. First, the microprocessor reads the operation code from the instruction code in S401, increments the program counter in S402, transfers it to the 4-byte buffer in S403, increments the buffer pointer in S404, and then decodes the instruction code in S405. Recognize how many bytes the code is.
[0035]
In the case of a 1-byte instruction (only an operation code) in S406, the instruction code is encrypted by a certain calculation method in S407, and a second encryption code is acquired. In step S408, the ROM is switched to a bank and switched to the encryption data bank, and the first encryption code at the address indicated by the program counter is acquired. Then, the second encryption code and the first encryption code are compared in S409, and if they match in S410, the value of the program counter is written in the copy program counter in S411, and the instruction code is executed in S412. If it is determined in S410 that they do not match, the value of the copy program counter is written in the program counter in S413, the value of the error counter is incremented in S414, and returned to immediately before the operation code reading process in S401. Note that the value of the error counter can be output to the outside in order to confirm whether the noise environment in which the microprocessor is used is good or bad. By checking the value of the error counter, the number of runaways can be known, and the greater the number of runaways, the greater the noise and the worse the noise environment.
[0036]
If it is determined in S415 that the instruction is a 2-byte instruction (opcode + operand), the byte counter is set to 2 in S416, the operand is read in S417, transferred to the CPU buffer in S418, transferred to the 4-byte buffer in S419, and transferred to S420. The buffer pointer is incremented, the program counter is incremented in S421, and the byte counter is decremented in S422. In step S423, the byte counter is confirmed. If the instruction is a 2-byte instruction, it is confirmed here that the byte counter is 0. In step S407, the instruction code is encrypted by a certain calculation method to obtain a second encryption code. In S408, the ROM is switched to a bank and switched to the encryption data bank, and the first encryption code at the address indicated by the program counter is acquired. Then, the second encryption code and the first encryption code are compared in S409, and if they match in S410, the value of the program counter is written in the copy program counter in S411, and the instruction code is executed in S412. If it is determined in S410 that they do not match, the value of the copy program counter is written in the program counter in S413, the value of the error counter is incremented in S414, and returned to immediately before the operation code reading process in S401.
[0037]
In the case of a 3-byte instruction (opcode + operand + operand) in S424, the byte counter is set to 2 in S425, and after S417, the same process as that of the 2-byte instruction is performed.
[0038]
If it is determined in S424 that the instruction is not a 3-byte instruction, it is a 4-byte instruction (opcode + opcode + operand + operand), so the operation code is read in S426, the instruction is decoded in S427, and transferred to the 4-byte buffer in S428. In step S429, the buffer pointer is incremented. After S425, the same process as the 3-byte instruction is performed.
[0039]
FIG. 5 is an example in which the content of outputting a reset signal is added to the embodiment of FIG. 4 when the number of runaways exceeds a certain number. The process from S501 to S509 is the same as the process from S401 to S409 in FIG. If the comparison result between the second encryption code and the first encryption code does not match in S510, the copy program counter value is written in the program counter in S513, and the error counter value is incremented in S514. When the error counter value does not exceed the predetermined value in S515, it is returned immediately before the operation code reading process in S501.
[0040]
When the value of the error counter exceeds a predetermined value in S515, that is, when the number of runaways exceeds a certain number, a reset signal is output in S516. The default value until the reset is output may be set to an arbitrary value by the user. If the noise environment is good, the default value does not need to be large, but if you want to continue execution without running the microprocessor out of control in a poor noise environment, set the default value to a certain level. There is a need.
[0041]
The timing for returning the value of the error counter to 0 may be variable according to a request from the user, and may be used when collecting data of a noise environment in which the microprocessor is used. For example, the user himself / herself may be set to return to 0 with a switch or the like, or may be set to return to 0 when the power is turned on or when a certain time elapses. Further, the error counter value may be aggregated so that the number of times the microprocessor has run out per unit time in a certain environment can be recorded.
[0042]
In the embodiment of the present invention, only an example of an 8-bit microprocessor used for a gaming machine is shown, but it can be used regardless of the bit length. Of course, it is also effective for other uses other than for gaming machines, and it can be expected to exert a great effect especially for uses related to human life such as in-vehicle use and aircraft. It goes without saying that by using a plurality of the microprocessors of the present invention in parallel and determining the instruction code to be executed by majority vote, the effect of preventing the microprocessor from running away due to noise can be dramatically improved. Nor.
[0043]
【The invention's effect】
According to the present invention, even if the microprocessor runs away due to noise or the like, the wrong instruction code is not executed. Therefore, the destruction of data or the like due to the runaway can be prevented, and the reliability of the microprocessor is improved. In addition, when the microprocessor of the present invention is used for gaming, even if the program is falsified by an unauthorized group, only the legitimate program will be executed, so the operation of the unauthorized program is prohibited, and fraud in the game hall is eliminated. Leads to.
[0044]
When a microprocessor misreads an instruction code, it returns to the most recent instruction code that causes the misreading of the instruction code, and re-executes the instruction code. However, since it operates as if it is not affected by noise, the player can continue the game without feeling abnormal. In addition, the development engineers of each game maker can save enormous effort and cost for noise countermeasures. Furthermore, in non-gaming fields, such as the execution of programs that require a long time for processing such as simulation calculations, the processing can be continued without returning to the initial state even if a runaway occurs. A microprocessor can be provided.
[0045]
Since the number of times the microprocessor has runaway can be measured and notified to the outside, the invisible noise environment can be grasped as a numerical value, and sample data effective for noise countermeasures can be collected.
[Brief description of the drawings]
FIG. 1 is a block diagram of a calculation unit of a Z80 microprocessor.
FIG. 2 is an operation explanatory diagram of the microprocessor of the present invention.
FIG. 3 is a data processing flowchart of the Z80 microprocessor.
FIG. 4 is a data processing flowchart of a microprocessor according to the first embodiment of the present invention.
FIG. 5 is a data processing flowchart of the microprocessor according to the first embodiment of the present invention.
[Explanation of symbols]
109, 201 CPU controller
202 Program counter
203 Copy program counter
204 4-byte buffer
205 Cryptographic calculation logic
206 Comparator
207 Error counter
208 Microprocessor resetting means
209 Program Bank
210 Cryptographic data bank

Claims (10)

Memory including an encryption data area for storing a first encryption code generated by a certain calculation method from an operation code of an operation code of a machine language program or a pair of an operation code and an operand, and a program area in which the instruction code is stored Means, an encryption calculation means for generating a second encryption code by calculating the instruction code by the predetermined calculation method when the microprocessor reads the instruction code from the program area, and the encryption calculation means Comparing means for comparing the second encrypted code with the first encrypted code read from the encrypted data area of the storage means corresponding to the instruction code, and executing the instruction if the comparison result by the comparing means matches And a controller.   The microprocessor according to claim 1, further comprising a program counter that increments every time the instruction code advances by one step, and if the second encryption code and the first encryption code do not match as a result of comparison, the program A microprocessor characterized in that the value of the counter is returned to the value before reading the instruction code and the instruction code is read again.   3. The microprocessor according to claim 2, further comprising a copy program counter for storing the value of the program counter, and when the second encryption code and the first encryption code are compared with each other, the program counter value is set if they match. A microprocessor characterized by being able to write to a copy program counter and write the value of the copy program counter to the program counter if they do not match.   The microprocessor according to any one of claims 1 to 3, further comprising a counter that counts the number of times when the second encryption code and the first encryption code do not match as a result of comparing the second encryption code and the first encryption code, A microprocessor characterized in that a counter value is informed to the outside at an arbitrary time.   5. The microprocessor according to claim 4, wherein when the value of the counter reaches a certain value, recording is stopped and a reset signal is output. Memory including an encryption data area for storing a first encryption code generated by a certain calculation method from an operation code of an operation code of a machine language program or a pair of an operation code and an operand, and a program area in which the instruction code is stored Means, an encryption calculation means for generating a second encryption code by calculating the instruction code by the predetermined calculation method when the microprocessor reads the instruction code from the program area, and the encryption calculation means Comparing means for comparing the second encrypted code with the first encrypted code read from the encrypted data area of the storage means corresponding to the instruction code, and executing the instruction if the comparison result by the comparing means matches A microprocessor for gaming machines, comprising:   7. The microprocessor according to claim 6, further comprising a program counter that increments every time the instruction code advances by one step, and if the second encryption code and the first encryption code do not match, A microprocessor for a gaming machine, wherein a counter value is returned to a value before reading an instruction code and an instruction code is read again.   8. The microprocessor according to claim 7, further comprising: a copy program counter for storing a value of the program counter, and when the second encryption code and the first encryption code are compared with each other, the program counter value is determined to match. A microprocessor for a gaming machine, wherein the value of the copy program counter can be written to the program counter if it does not coincide with the value written in the copy program counter.   The microprocessor according to any one of claims 6 to 8, further comprising: a counter that counts the number of times when the second encryption code and the first encryption code do not match as a result of comparison, A microprocessor for a gaming machine, characterized in that a counter value is informed outside at an arbitrary time.   The gaming machine microprocessor according to claim 9, wherein when the value of the counter reaches a certain value, recording is stopped and a reset signal is output.

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