JP3847103B2 - Optoelectronic mounting circuit board and mounting board - Google Patents

Optoelectronic mounting circuit board and mounting board Download PDF

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Publication number
JP3847103B2
JP3847103B2 JP2001162936A JP2001162936A JP3847103B2 JP 3847103 B2 JP3847103 B2 JP 3847103B2 JP 2001162936 A JP2001162936 A JP 2001162936A JP 2001162936 A JP2001162936 A JP 2001162936A JP 3847103 B2 JP3847103 B2 JP 3847103B2
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circuit board
optoelectronic
layer
semiconductor element
insulating substrate
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JP2002359472A (en
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成樹 山田
猛 松井
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Kyocera Corp
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Kyocera Corp
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    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C8/00—Enamels; Glazes; Fusion seal compositions being frit compositions having non-frit additions
    • C03C8/14—Glass frit mixtures having non-frit additions, e.g. opacifiers, colorants, mill-additions
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C14/00—Glass compositions containing a non-glass component, e.g. compositions containing fibres, filaments, whiskers, platelets, or the like, dispersed in a glass matrix
    • C03C14/004—Glass compositions containing a non-glass component, e.g. compositions containing fibres, filaments, whiskers, platelets, or the like, dispersed in a glass matrix the non-glass component being in the form of particles or flakes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

【０００１】
【発明の属する技術分野】
本発明は、光半導体素子と電子半導体素子及び／又は光電子半導体素子が実装され、高周波信号に適用可能な光電子実装回路基板及び実装基板に関する。
【０００２】
【従来技術】
近年のマルチメディアの普及に伴い、膨大な画像データの送受信が必要になり、高速動作が求められる電子機器に対して高周波信号処理は必須になっている。一方で、高速、大容量の送受信が可能な光通信が注目を集めているが、電子半導体素子やマルチチップモジュール間を光導波路で複雑に接続している為、導波路を頻繁に交差させる必要が生じ、光信号と電気信号処理を同一の実装基板で行うことによる装置の小型化や、複雑な光インターコネクションに対応する為に、セラミック基板上に光導波路を形成すると同時に、光半導体素子や電子半導体素子等を実装した光電子実装回路が用いられている。
【０００３】
このような光電子実装回路が設けられたセラミック配線基板は、高集積化や高周波化に伴う発熱量の増加に伴い、高い放熱性が必要とされるとともに、演算速度の高速化の要求により、導体の低抵抗が要求されており、比較的熱伝導率が高く、信頼性に優れたアルミナを絶縁基板とし、その表面又は内部にＷやＭｏ等の高融点金属からなる導体層を被着形成したセラミック配線基板が多用されている。
【０００４】
ところが、従来から多用されている高融点金属からなる導体層では、抵抗を高々８ｍΩ／□程度までしか低くできず、信号の挿入損失が著しく高くなり、良好な高周波特性が得られなくなるという問題があった。さらに、信号の高周波化に伴い、配線基板、特に、信号入力端子用の導体層が施される絶縁層部分の誘電率が高い場合には信号の反射が大きくなり特性が低下するという問題があった。
【０００５】
そこで、絶縁基板としてアルミナを用い、低抵抗導体であるＣｕ、又はＣｕとＷ又はＭｏとを組み合わせた導体層を同時焼成により形成する方法で挿入損失を低減させることが特開平７−１５１０１号に提案されている。
【０００６】
また、信号伝達特性に関し、信号の反射を抑制する為、信号入力部分の絶縁層に誘電率の低いガラスセラミックスを用い、強化ガラスと一体化する方法等が特開平３−２３９３９４に提案されている。
【０００７】
【発明が解決しようとする課題】
しかしながら、特開平７−１５１０１号に記載の方法では、一旦、すべての導体層を絶縁基板内部に配設して同時焼成した後、研磨等により表面の絶縁層を研磨除去して内部導体層を表面に露出させて表面導体層を形成する、又は焼成後の配線基板の表面に、厚膜法や薄膜法によって表面導体層を形成するものであるため、表面導体層を形成するために研磨工程、厚膜形成工程、薄膜形成工程等が不可欠の工程となるために、製造工程が増え、歩留りの低下やコスト高になるという問題があった。
【０００８】
また、特開平３−２３９３９４に記載の方法では、絶縁基板にガラスセラミックス等を用いるため、基板の誘電率を低く設定でき、且つ配線金属の抵抗を低く出来るものの、半導体素子から生じる熱の発散がスムーズに行われず、素子自体の誤動作を招くという問題があった。
【０００９】
従って、本発明は、放熱性に優れ、外部電気信号の入力信号の損失が少ない光電子実装回路基板を提供することを目的とする。
【００１０】
【課題を解決するための手段】
本発明者等は、上記課題に対して検討を重ねた結果、アルミナ絶縁層と、低誘電率の誘電体層とからなる積層体の誘電体層上に高周波入力用外部接続端子を設けることにより、高周波信号の入力損失が小さく、放熱性に優れた熱伝導の光電子実装回路基板が得られるという知見に基づくものである。
【００１１】
即ち、アルミナ焼結体からなる絶縁層と、該絶縁層よりも低誘電率の誘電体層とが一体的に積層されてなり、且つ表面及び／又は内部にＡｕ、Ａｇ、Ｃｕ、Ｐｔのうち少なくとも１種の導体層が形成された絶縁基板と、該絶縁基板の一方の表面側に搭載された光導波路及び光半導体素子と、前記絶縁基板の一方又は他方の表面に搭載された電子半導体素子と、前記絶縁基板の前記誘電体層上に設けられた高周波入力用外部接続端子を具備するものである。これにより、高周波信号の入力部において低損失の光電子実装回路基板を実現したものである。
【００１２】
特に、前記絶縁層及び／又は前記誘電体層が積層体からなることが好ましい。これにより、複数の半導体を実装しても積層体の内部にも配線が可能となり、高密度実装が容易となる。
【００１３】
また、前記電子半導体素子と光半導体素子とが前記絶縁基板の対向する表面に搭載されていることが好ましい。これにより、小型化が可能で、且つ高い信頼性が得られる。
【００１４】
さらに、前記絶縁基板の表面に設けられたキャビティの内部に電子半導体素子が収納され、且つ該キャビティが蓋体によって気密封止されていることが好ましい。これにより、電子半導体素子の特性が安定し、信頼性を向上することができる。
【００１５】
さらにまた、前記絶縁基板の前記誘電体層が、前記絶縁層の表面の一部に形成されてなることが好ましい。これにより、誘電体層の設けられた熱伝導率の高い絶縁層の上に電子半導体素子等の発熱量の大きな部品を搭載することが可能となる。
【００１６】
また、前記光半導体素子が、前記光導波路の内部に設けられてなることが好ましい。これにより、光半導体素子の特性が安定し、信頼性を向上することができる。
【００１７】
さらに、前記誘電体層がムライト、フォルステライト、エンスタタイト、シリカ、コーデイエライトのうち少なくとも１種を主成分とする焼結体であることが好ましい。これにより、高周波のより高い周波数に対応することが容易となる。
【００１８】
さらにまた、前記アルミナ焼結体が、シリカ及びＭｎ2Ｏ3を含有することが好ましい。これにより、低温焼成が可能となり、製品歩留まりを高めることができる。
【００１９】
また、前記導体層が、Ｗ及び／又はＭｏを含むことが好ましい。これにより、低抵抗配線が可能で、内部回路においても導体損失の小さい高周波に対応可能な光電子実装回路基板を得ることが容易になる。
【００２０】
さらにまた、前記導体層のシート抵抗が導体厚み１５μｍ換算で８ｍΩ／□以下であることが好ましい。これにより、配線幅の縮小により部品の小型化が容易となる。
【００２１】
また、本発明の実装基板は、母基板の表面に、コンデンサ、抵抗体及び配線導体を含む電子回路が形成され、且つ請求項１乃至１０のうちいずれかに記載の光電子実装回路基板が高周波入力用外部接続端子を介して前記電子回路に実装されてなり、４０ＧＨｚの高周波信号が前記光電子実装回路基板に入力するときの反射損失が−１０．０ｄＢ以下であることを特徴とするものであり、これにより、高速、大容量の送受信が可能な光通信を実現することができる。
【００２２】
【発明の実施の形態】
本発明の光電子実装回路基板を、図を用いて説明する。図１は、本発明の光電子実装回路基板の概略断面図である。即ち、アルミナを主体とする薄層焼結体であるアルミナ焼結体１ａ〜１ｄからなる絶縁層１と、このアルミナ焼結体１ａ〜１ｄよりも誘電率の低い誘電体層２が一体的に積層されている。
【００２３】
絶縁層１はアルミナ焼結体１層から構成されていてもかまわないが、半導体の高密度実装及び配線並びに小型化を考慮すると複数のアルミナ焼結体１ａ〜１ｄからなる積層体であることが好ましい。 また、図1において、絶縁層１は４層のアルミナ焼結体１ａ〜１ｄから構成されているが、アルミナ焼結体の数は特に限定されるものではなく、配線の量や半導体の位置等によって適宜決定すればよい。
【００２４】
絶縁層１を構成するアルミナ焼結体１ａ〜１ｄの表面又は界面には、表面導体層３ａや内部導体層３ｂが形成され、誘電体層２とアルミナ絶縁層１間にはグランド導体層３ｃが設けられている。また、アルミナ焼結体を１枚又は複数貫くビアホール導体３ｄが設けられている。従って、導体層３は、絶縁基板の表面及び／又は内部に設けられている。
【００２５】
絶縁基板の一方の表面側に光半導体素子５が搭載され、光導波路６が形成されている。この光導波路６は、光半導体素子５と光学的に接続された構造を有し、光導波路コア６ａの周囲に光導波路クラッド６ｂが設けられた構造を有している。また、光導波路６は、絶縁層１の一方の表面側少なくとも一部に存在しており、光半導体素子５が光導波路６の外側に位置していても良いが、光半導体素子５の信頼性を高め、誤動作を防ぐため、特に、光半導体素子５が光導波路６の内部に設けられていることが好ましい。
【００２６】
さらに、絶縁層１の他方の表面には、電子半導体素子７が搭載されている。即ち、電子半導体素子７と光半導体素子５とは絶縁基板の対向する表面にそれぞれ搭載されている。このような構成にすることで、多数の電子半導体素子７及び光半導体素子５を一つの絶縁基板上に搭載することができ、より高密度な実装による製品の小型化を推進し、信頼性も高めることができる。
【００２７】
ここで、誘電体層２は、絶縁基板を構成するアルミナ焼結体１ｄの全面に一体的に積層されていてもよいが、図１のように、アルミナ焼結体１ｄの一部に形成されていることが好ましい。この構成により、絶縁基板の誘電体層２側の表面に絶縁層１の表面も露出することとなり、そこに電子半導体素子７を実装することができ、実装密度を高めることができる。
【００２８】
また、電子半導体素子７は、光半導体素子５及び光導波路６の設けられた絶縁層１の一方の表面に設けることも可能である。つまり、光導波路６は表面の一部に形成し、光導波路６の設けられていない表面に電子半導体素子７を実装すればよい。
【００２９】
この電子半導体素子７は、絶縁基板の表面に設けられたキャビティ８の内部に収納されており、電子半導体素子７は半田等によりボール実装及び／又はベアチップ実装によってアルミナ焼結体１ｄの表面に実装されている。また、キャビティ８は、蓋体９によって気密封止され、キャビティ８内部に外気が混入しない構造になっているため、電子半導体素子７の誤動作を防止でき、信頼性を高めることができる。
【００３０】
また、誘電体層２の表面には、高周波入力用外部接続端子１０が設けられている。この高周波入力用外部接続端子１０は外部から高周波を入力するためのもので、外部回路と電気的に接続している。この高周波入力用外部接続端子１０が誘電率の低い誘電体層２に形成されているため、高周波入力用外部接続端子１０と内部導体層３ｂ間に発生する浮遊容量が低減され、入力信号の反射が抑制され、信号損失を小さくすることができる結果、高周波対応の可能な光電子実装回路基板を実現することができる。
【００３１】
絶縁層１は、アルミナを主体とし、所望の焼結助剤を加えた成形体を焼成してなるアルミナ焼結体で構成され、単一又は複数のアルミナ焼結体からなる。実装密度を高めるためには複数のアルミナ焼結体を積層して用いることが好ましい。また、焼結助剤としてシリカ及びＭｎ2Ｏ3を含有することが好ましい。これらの焼結助剤は、低温での焼成を可能とし、導体層３の金属の溶融による流出を防止し、製品歩留まりを高めることができる。なお、焼結助剤等のアルミナ以外の成分は、アルミナ主結晶相の粒界に非晶質相あるいは結晶相として存在することが望ましい。
【００３２】
本発明によれば、絶縁層１のアルミナ焼結体は、絶縁基板の熱伝導性および高強度化のため、相対密度が９５％以上、特に９７％、更には９８％以上が望ましく、また熱伝導率が１０Ｗ／ｍ・Ｋ以上、特に１５Ｗ／ｍ・Ｋ以上、更には１７Ｗ／ｍ・Ｋ以上であることが望ましい。
【００３３】
また、絶縁層１を形成するアルミナ質焼結体の主結晶相は、粒状または柱状の結晶として存在するが、これら主結晶相の平均結晶粒径は、１．５〜５μｍであることが望ましい。なお、主結晶相が柱状結晶からなる場合、上記平均結晶粒径は、短軸径に基づくものである。この主結晶相の平均結晶粒径が１．５μｍよりも小さいと、高熱伝導化が難しくなる傾向があり、また平均粒径が５μｍよりも大きいと基板材料として用いる場合に要求される十分な強度が得られにくくなる傾向にあるためである。
【００３４】
誘電体層２は、アルミナよりも低誘電率であれば本発明の目的である信号の入力損失を低減できるが、特に、ムライト、フォルステライト、エンスタタイト、シリカ、コーデイエライトのうち少なくとも１種を主成分とする焼結体であることがアルミナとの同時焼結性の点で好ましい。これ以外に、その他の成分としてとしてＭｎ2Ｏ3、ＳｉＯ2、ＺｎＯ、ＣａＯ、Ｎｂ2Ｏ5、ＭｏＯ3、ＷＯ3又はガラス等を添加してもよい。さらに１０重量％以下のガラスを含有とすることも可能であるが、基板の高強度化を達成するために１０重量％以下、特には５重量％以下であることが望ましい。
【００３５】
導体層３は、低抵抗化のため、Ａｕ、Ａｇ、Ｃｕ、Ｐｔのうち少なくとも１種を含むことが好ましい。また、アルミナとの密着性向上のため、Ｗ及び／又はＭｏを含むことが好ましい。例えば、Ｃｕを１０〜７０体積％、Ｗ及び／又はＭｏを３０〜９０体積％を含有する組成とする。
【００３６】
この導体層３のシート抵抗が、導体厚み１５μｍ換算で８ｍΩ／□以下であることが好ましい。このような低いシート抵抗を有することによって、配線幅の縮小が可能となり、小型化ができる。
【００３７】
次に、本発明の光電子実装回路基板の製造方法について説明する。
【００３８】
まず、絶縁層１を作製するために、アルミナ粉末、所望の焼結助剤粉末を準備する。アルミナ原料粉末として、平均粒径が０．５〜２．５μｍ、特に０．５〜２．０μｍの粉末を用いる。これは、平均粒径は０．５μｍよりも小さいと、粉末の取扱いが難しく、また粉末のコストが高くなり、２．５μｍよりも大きいと、１５００℃以下の温度で焼成することが難しくなるためである。
【００３９】
第２の成分として、Ｍｎ2Ｏ3粉末を２〜１５重量％、並びにＳｉＯ2粉末を２〜１５重量％の割合で添加する。Ｍｎ2Ｏ3粉末等のＭｎ化合物粉末の添加によって１２００〜１５００℃で緻密化が促進され、また、高い絶縁性を維持することができ、ＳｉＯ2粉末の添加によって緻密化を促進し、高い熱伝導率を維持することができ。また、適宜、第３の成分として、Ｍｇ、Ｃａ、Ｓｒ、Ｂ、Ｎｂ、Ｃｒ、Ｃｏの酸化物、炭酸塩、水酸塩のうち少なくとも１種を、Ｃｕ含有導体との同時焼結性を高めるために、０．１〜４重量％含有し、第４の成分として、Ｗ、Ｍｏ、Ｃｒ等の遷移金属の金属粉末や酸化物粉末を着色成分として金属換算で２重量％以下の割合で添加する。
【００４０】
一方、誘電体層にはムライト、フォルステライト、エンスタタイト、シリカ、コーデイエライトの内から選ばれる１種以上の主成分粉末と、第２の成分としてＭｎ２Ｏ３、ＳｉＯ２、ＺｎＯ、ＣａＯ、Ｎｂ２Ｏ５、ＭｏＯ３、ＷＯ３のうち少なくとも１種、さらに第３の成分として１０重量％以下のガラスを添加することができる。ガラスの添加を１０重量％以下にすることにより、焼成時における低誘電率層の変形並びにアルミナ層への拡散による熱伝導率の低下を抑制しながら、焼結性を高めることができる。
【００４１】
ここで上記の主成分粉末の粒径は０．５〜５μｍ、特に０．５〜３μｍの粉末を用いる。これは、粒径が５μｍよりも大きい場合には焼結後の粒内にクラックが生じ著しく強度が低下するためである。また、０．５μｍよりも小さい場合には粉末の取り扱いが困難になるためである。上記酸化物の添加に当たっては、酸化物粉末以外に、焼成によって酸化物を形成し得る炭酸塩、硝酸塩、酢酸塩等として添加してもよい。
【００４２】
そして、各々の混合粉末を用いて絶縁層を形成するためのシート状成形体を作製する。シート状成形体は、周知の成形方法によって作製することができる。例えば、上記混合粉末に有機バインダや溶媒を添加してスラリーを調製した後、ドクターブレード法によって形成したり、混合粉末に有機バインダを加え、プレス成形、圧延成形等により所定の厚みのシート状成形体を作製できる。そしてこのシート状成形体に対して、マイクロドリル、レーザー等によりビアホール導体用スルーホールを形成してもよい。
【００４３】
次いで、導体層が低抵抗金属（Ａｕ、Ａｇ、Ｃｕ、Ｐｔ）と高融点金属（Ｗ、Ｍｏ）とを含むように、導体ペーストが少なくともＡｕ粉末、Ａｇ粉末、Ｃｕ粉末及びＰｔ粉末のうち少なくとも1種を含み、更にはＷ粉末及び／又はＭｏ粉末を含むことが好ましい。例えば、Ｃｕ粉末とＷ粉末、ＡｕとＭｏ粉末等であり、具体的な例として１〜１０μｍのＣｕ１０〜７０体積％、特に３０〜６０体積％、１〜１０μｍのＷ及び／もしくはＭｏを３０〜９０体積％、４０〜７０体積％の割合で含有してなる導体ペーストを調製する。Ｃｕ等の金属は、低抵抗に寄与し、高融点金属は絶縁層１との熱膨張係数差による導体層の剥離を防止するとともに、焼成温度がＣｕの融点よりも高いため、高融点金属が保型剤としても機能する。
【００４４】
また、上記導体ペーストには、所望によりＮｉ、Ｚｒ、Ａｌ、Ｌｉ、Ｍｇ及びＺｎのうち少なくとも１種を金属元素換算で０．０５〜３．０重量％含有することが望ましい。これは、導体層の低抵抗化並びに絶縁基板との同時焼結性を改善するとともに、導体層の同時焼成後の保形性を維持するためである。なお、Ｎｉ、Ｚｒ、Ａｌ、Ｌｉ、Ｍｇ及びＺｎは酸化物、ホウ化物、窒化物或いは炭酸塩として添加してもよく、このときの平均粒径は０．６〜４μｍ、特には１．５〜３．０μｍが望ましい。
【００４５】
また、本発明においては、導体層の抵抗、Ｃｕ成分の分離、にじみ等の観点から、Ｗ粉末及び／又はＭｏ粉末は平均粒径１〜１０μｍ、特に１．３〜５μｍ、更には１．３〜３μｍの球状あるいは数個の粒子による焼結粒子としてＣｕからなるマトリックス中に分散するように調製することも重要である。
【００４６】
これらの導体ペースト中には、絶縁層との密着性を高めるために、アルミナ粉末や、絶縁層を形成する酸化物セラミック成分と同一の組成物粉末を０．０５〜２体積％の割合で添加することも可能である。
【００４７】
次いで、上記の導体ペーストを各絶縁層１ａ〜１ｄ上にスクリーン印刷、グラビア印刷等の方法により印刷塗布し、導体層３を形成する。また、絶縁層１ａ〜１ｄに設けられたビアホールの内部に上記導体ペーストを充填し、ビアホール導体層３ｄを形成する。
【００４８】
その後、導体ペーストを充填したシート状成形体を位置合わせして積層圧着した後、この積層体を、この焼成を、非酸化性雰囲気中、焼成最高温度が１２００〜１５００℃の温度となる条件で焼成する。
【００４９】
この時の焼成温度が１２００℃より低いと、通常の原料を用いた場合において、アルミナ絶縁基板が相対密度９５％以上まで緻密化できず、熱伝導性や強度が低下すると同時に、低誘電率層の緻密化も達成できなくなる。一方、焼成温度が１５００℃よりも高いと、ＷあるいはＭｏ自体の焼結が進み、Ｃｕの流動により均一組織を維持できなく、強いては低抵抗を維持することが困難となる。好適には、１２５０〜１４００℃の範囲がよい。
【００５０】
また、この焼成時の非酸化性雰囲気としては、窒素、あるいは窒素と水素との混合雰囲気であることが望ましいが、特に、導体層中のＣｕの拡散を抑制する上では、水素及び窒素を含み露点＋３０℃以下、特に０〜２５℃の非酸化性雰囲気であることが望ましい。なお、この雰囲気には所望により、アルゴンガス等の不活性ガスを混入してもよい。焼成時の露点が＋３０℃より高いと、焼成中に導体材料と雰囲気中の水分とが反応し酸化膜を形成し、絶縁層とＣｕ含有導体のＣｕが反応してしまい、導体の低抵抗化の妨げとなるのみでなく、Ｃｕの拡散を助長してしまうためである。
【００５１】
さらに、本発明の絶縁基板においては、Ｃｕの融点を越える温度での同時焼成によって、表面導体層３ａや内部導体層３ｂ中のＣｕ成分が絶縁層１及び誘電体層２中に拡散する場合があるが、本発明によれば、上記少なくともＣｕを含む導体層の周囲の絶縁基板のセラミックスへのＣｕの拡散距離が２０μｍ以下、特に１０μｍ以下であることが望ましい。これは、Ｃｕのセラミックス中への拡散距離が２０μｍを超えると、導体層間の絶縁性が低下し、配線基板としての信頼性が低下するためである。
【００５２】
また、上記の方法により作製した絶縁基板表面に光導波路を形成する方法としては、アルミナ絶縁層上にゾルーゲル法によってシリカ系光導波路を形成したり、ポリイミド、ポリメチルメタクリレート、ポリカーボネート等の有機系材料を用いた光導波路の形成、またはＣＶＤ法を用いた光導波路の形成が可能である。
【００５３】
また、光半導体素子をアルミナ絶縁層上に設置して、基板の導体層と電気的に接続すると同時に、光導波路クラッド内に埋設することも可能である。アルミナ絶縁層上に光導波路を形成するのは、光導波路形成層が高強度であることと、光導波路と光学的に接続される素子の熱膨張係数がアルミナと近い為に接続信頼性に優れ、かつ半導体素子の発熱に対し熱伝導性が優れる為である。
【００５４】
電子半導体素子はアルミナを絶縁層とする表面に載置することが望ましい。なぜならば、アルミナはガラスセラミック等と異なり熱伝導率が比較的高いことから素子から発生した熱を効率的かつ速やかに発散することが出来るからである。更にポリイミド等の樹脂基板と異なり熱膨張係数が半導体素子に近いことから高い一次実装信頼性を確保することが出来る。このときの基板への半導体素子の実装形態は半田を用いたボール実装又は／及びベアチップ実装等で行うことができる。
【００５５】
また、本発明の実装基板は、プリント基板等の母基板の表面に、コンデンサ、抵抗体及び配線導体を含む電子回路が形成され、上記光電子実装回路基板は、高周波入力用外部接続端子１０を介して電子回路に実装されている。本発明によれば、光電子実装回路基板として上記の構成の実装基板を用いることによって、４０ＧＨｚの高周波信号が前記光電子実装回路基板に入力するときの反射損失を−１０．０ｄＢ以下、特に−７ｄＢ以下、更には−５ｄＢ以下とすることができる。従って、本発明の光電子実装回路基板を用いることによって、４０ＧＨｚ以上の高周波信号の入力が可能で、大容量の光通信に対応できる。
【００５６】
【実施例】
絶縁層を作製するため、アルミナ粉末（平均粒径１．８μｍ）に対して、Ｍｎ2Ｏ3及びＳｉＯ2をそれぞれ６重量％、ＭｇＯを０．５重量％の割合で調合し、これに結合剤（バインダ）用有機樹脂としてアクリル系バインダと溶媒のトルエンを加えてスラリーを調製した後、ドクターブレード法にて厚さ２５０μｍのシート状に成形した。
【００５７】
また、誘電体層を作成するため、ムライト、フォルステライト、エンスタタイト、シリカ、コーディエライトの内から選ばれる１種以上を主成分とし、表１に示す添加物を加えて、シート状成形体を作製した。ここで誘電体層の誘電率はシリカ量の調整で行った。そして、所定箇所に焼成後のホール径が１００〜２００μｍのビアホールを形成した。
【００５８】
次に、平均粒径が５μｍのＣｕ粉末、Ａｇ粉末、Ａｕ粉末及びＰｔ粉末のうち１種と、平均粒径が０．８〜１２μｍのＷ粉末又はＭｏ粉末とを表１に示す比率で混合し、この混合粉末とアクリル系バインダとをアセトンを溶媒として導体ペーストを作製した。
【００５９】
そして、シート状成形体上に上記導体ペーストを印刷塗布し、各シート状成形体のビアホール導体層にも上記導体ペーストを充填した。上記のようにして作製した各シート状成形体を位置合わせして積層圧着して成形体積層体を作製した。その後、この成形体積層体を実質的に水分を含まない酸素含有雰囲気中（Ｈ2＋Ｏ2）で脱脂を行った後、露点２０℃の窒素水素混合雰囲気、１３００℃で焼成し、図１の光電子実装回路基板を得た。
【００６０】
得られた基板の密度をアルキメデス法により測定した。また、回路基板における導体層の電気抵抗（シート抵抗換算）を４端子法にて測定した。さらに、比誘電率は、ＪＩＳ Ｒ１６２７に基づいて空洞共振器法により測定周波数４０ＧＨｚで比誘電率を測定した。
【００６１】
また、反射損失はネットワークアナライザ―とウエハープローブを用い４０ＧＨｚにおける測定を行った。詳細には、図２に示すように、光電子実装回路基板２１を実装する母基板２２と光電子実装回路基板２１内に設けた測定用電極間の値を測定した。このときの測定試料の断面構成を。高周波入力用外部接続端子を表面に形成する誘電体層及び絶縁層の厚みはそれぞれ０．２５ｍｍ、ヴィア径は０．１ｍｍφであった。また、高周波入力用外部接続端子を構成する電極パッド（ボールパッド）径は０．４ｍｍφ、半田ボール径は０．３ｍｍφ、ボールピッチ０．８ｍｍ、光電子実装回路基板を実装する母基板には厚み０．２ｍｍで誘電率３．５のテフロン（登録商標）基板を用いた。
【００６２】
セラミック層の抗折強度は高周波入力用外部接続端子形成層に用いる低誘電率絶縁層厚みが０．５ｍｍ、該絶縁層以外の絶縁層厚みが２．５ｍｍの同時焼成された試料を用いて３点曲げ強度を測定した。さらに、セラミック層の熱伝導率に関しても抗折強度測定に用いた積層構造をもつ試料を用いてレーザーフラッシュ法により室温における熱伝導率を測定した。
【００６３】
【表１】

Figure 0003847103
【００６４】
本発明の試料Ｎｏ．２〜１８は、誘電体層の誘電率が４．４〜８と絶縁層のアルミナの９より小さく、反射損失が−１０ｄＢ以下であった。
【００６５】
一方、絶縁層と誘電体層が同一材質からなる試料Ｎｏ．１は、反射損失が−６.４ｄＢであった。
【００６６】
また、導体層がＷ又はＭｏからなる本発明の範囲外の試料Ｎｏ．１９及び２０は、シート抵抗が２８ｍΩ／□以上と大きく、反射損失が−６.５ｄＢと大きかった。
【００６７】
【発明の効果】
本発明の光電子実装回路基板は、機械的、熱的特性に優れるアルミナ質絶縁層と低誘電率の誘電体層とを一体的に設けた絶縁基板の絶縁層表面に光導波路、光半導体素子及び電子半導体素子を載置し、誘電体層上に高周波入力用外部接続端子を形成することによって、高周波入力信号の反射損失並びに挿入損失を改善し、高信頼性、小型の光電子実装回路基板を実現できる。
【図面の簡単な説明】
【図１】本発明の光電子実装回路基板を示す概略断面図である。
【図２】本発明の実装基板の一部を示す概略断面図である。
【符号の説明】
１・・・絶縁層
１ａ、１ｂ、１ｃ、１ｄ・・・アルミナ焼結体
２・・・誘電体層
３・・・導体層
３ａ・・・表面導体層
３ｂ・・・内部導体層
３ｃ・・・グランド導体層
３ｄ・・・ビアホール導体層
５・・・光半導体素子及び／又は光電子半導体素子
６・・・光導波路
６ａ・・・光導波路コア
６ｂ・・・光導波路クラッド
７・・・電子半導体素子
８・・・キャビティ
９・・・蓋体
１０・・・高周波入力用外部接続端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optoelectronic mounting circuit board and a mounting board on which an optical semiconductor element and an electronic semiconductor element and / or an optoelectronic semiconductor element are mounted and applicable to a high-frequency signal.
[0002]
[Prior art]
With the recent spread of multimedia, it is necessary to transmit and receive a large amount of image data, and high-frequency signal processing is essential for electronic devices that require high-speed operation. On the other hand, optical communication capable of high-speed and large-capacity transmission / reception has been attracting attention, but it is necessary to cross the waveguides frequently because electronic semiconductor elements and multichip modules are complexly connected by optical waveguides. In order to reduce the size of the device by performing optical signal and electrical signal processing on the same mounting substrate and to cope with complicated optical interconnection, an optical waveguide is formed on a ceramic substrate, and at the same time, an optical semiconductor element or An optoelectronic mounting circuit on which an electronic semiconductor element or the like is mounted is used.
[0003]
A ceramic wiring board provided with such an optoelectronic mounting circuit is required to have high heat dissipation as the amount of heat generation increases with higher integration and higher frequency, and conductors are required to increase the calculation speed. A low resistance is required, alumina having relatively high thermal conductivity and excellent reliability is used as an insulating substrate, and a conductive layer made of a refractory metal such as W or Mo is deposited on the surface or inside thereof. Ceramic wiring boards are frequently used.
[0004]
However, the conventional high-melting point metal layer made of a refractory metal has a problem that the resistance can be lowered only to about 8 mΩ / □, signal insertion loss becomes remarkably high, and good high-frequency characteristics cannot be obtained. there were. Furthermore, as the frequency of signals increases, there is a problem that when the dielectric constant of the wiring substrate, particularly the insulating layer portion on which the conductor layer for signal input terminals is applied, the signal reflection increases and the characteristics deteriorate. It was.
[0005]
Japanese Patent Laid-Open No. 7-15101 discloses a method for reducing insertion loss by using alumina as an insulating substrate and forming a low resistance conductor Cu or a conductor layer in which Cu and W or Mo are combined by simultaneous firing. Proposed.
[0006]
Further, regarding signal transmission characteristics, Japanese Patent Laid-Open No. 3-239394 proposes a method of using glass ceramics having a low dielectric constant for an insulating layer of a signal input portion and integrating with tempered glass in order to suppress signal reflection. .
[0007]
[Problems to be solved by the invention]
However, in the method described in JP-A-7-15101, all the conductor layers are once disposed inside the insulating substrate and fired at the same time, and then the insulating layer on the surface is removed by polishing or the like to remove the inner conductor layer. A surface conductor layer is formed by exposing to the surface, or a surface conductor layer is formed on the surface of the wiring substrate after firing by a thick film method or a thin film method, so that a polishing process is performed to form the surface conductor layer. However, since the thick film forming process, the thin film forming process, and the like are indispensable processes, there are problems in that the manufacturing process increases, yield decreases, and costs increase.
[0008]
Further, in the method described in JP-A-3-239394, glass ceramics or the like is used for the insulating substrate. Therefore, although the dielectric constant of the substrate can be set low and the resistance of the wiring metal can be lowered, the heat dissipation generated from the semiconductor element can be reduced. There is a problem that the operation is not performed smoothly and the device itself malfunctions.
[0009]
Accordingly, an object of the present invention is to provide an optoelectronic packaging circuit board that is excellent in heat dissipation and has little loss of input signals of external electric signals.
[0010]
[Means for Solving the Problems]
As a result of repeated investigations on the above problems, the present inventors have found that on the dielectric layer of the laminate composed of an alumina insulating layer and a low dielectric constant dielectric layer. For high frequency input This is based on the knowledge that by providing the external connection terminal, an input board of a high-frequency signal is small and a heat conductive optoelectronic mounting circuit board having excellent heat dissipation can be obtained.
[0011]
That is, an insulating layer made of an alumina sintered body and a dielectric layer having a dielectric constant lower than that of the insulating layer are integrally laminated, and the surface and / or the inside thereof is Au, Ag, Cu, or Pt. An insulating substrate on which at least one kind of conductor layer is formed, an optical waveguide and an optical semiconductor element mounted on one surface side of the insulating substrate, and an electronic semiconductor element mounted on one or the other surface of the insulating substrate And provided on the dielectric layer of the insulating substrate For high frequency input An external connection terminal is provided. As a result, a low-loss optoelectronic circuit board is realized at the high-frequency signal input section.
[0012]
In particular, it is preferable that the insulating layer and / or the dielectric layer is a laminate. As a result, even if a plurality of semiconductors are mounted, wiring can be performed inside the stacked body, and high-density mounting is facilitated.
[0013]
Further, it is preferable that the electronic semiconductor element and the optical semiconductor element are mounted on opposing surfaces of the insulating substrate. Thereby, miniaturization is possible and high reliability is obtained.
[0014]
Furthermore, it is preferable that an electronic semiconductor element is accommodated in a cavity provided on the surface of the insulating substrate, and the cavity is hermetically sealed by a lid. Thereby, the characteristic of an electronic semiconductor element is stabilized and reliability can be improved.
[0015]
Furthermore, it is preferable that the dielectric layer of the insulating substrate is formed on a part of the surface of the insulating layer. Thereby, it is possible to mount a component having a large calorific value such as an electronic semiconductor element on the insulating layer having a high thermal conductivity provided with the dielectric layer.
[0016]
Further, it is preferable that the optical semiconductor element is provided inside the optical waveguide. As a result, the characteristics of the optical semiconductor element are stabilized and the reliability can be improved.
[0017]
Furthermore, it is preferable that the dielectric layer is a sintered body mainly containing at least one of mullite, forsterite, enstatite, silica, and cordierite. Thereby, it becomes easy to cope with a higher frequency.
[0018]
Furthermore, the alumina sintered body is composed of silica and Mn. 2 O Three It is preferable to contain. Thereby, low temperature baking becomes possible and a product yield can be improved.
[0019]
Moreover, it is preferable that the said conductor layer contains W and / or Mo. As a result, low resistance wiring is possible, and it becomes easy to obtain an optoelectronic packaging circuit board that can handle high frequencies with low conductor loss even in internal circuits.
[0020]
Furthermore, the sheet resistance of the conductor layer is preferably 8 mΩ / □ or less in terms of the conductor thickness of 15 μm. This facilitates the miniaturization of the component by reducing the wiring width.
[0021]
The mounting board of the present invention is such that an electronic circuit including a capacitor, a resistor, and a wiring conductor is formed on a surface of a mother board, and the optoelectronic mounting circuit board according to any one of claims 1 to 10 is provided. For high frequency input It is mounted on the electronic circuit via an external connection terminal, and a reflection loss when a high frequency signal of 40 GHz is input to the optoelectronic mounting circuit board is -10.0 dB or less. As a result, optical communication capable of high-speed and large-capacity transmission / reception can be realized.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The optoelectronic packaging circuit board of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view of an optoelectronic packaging circuit board according to the present invention. That is, the insulating layer 1 made of alumina sintered bodies 1a to 1d, which are thin-layer sintered bodies mainly composed of alumina, and the dielectric layer 2 having a lower dielectric constant than the alumina sintered bodies 1a to 1d are integrally formed. Are stacked.
[0023]
The insulating layer 1 may be composed of a single alumina sintered body, but in consideration of high-density mounting of semiconductors, wiring, and miniaturization, the insulating layer 1 may be a laminate composed of a plurality of alumina sintered bodies 1a to 1d. preferable. In FIG. 1, the insulating layer 1 is composed of four layers of alumina sintered bodies 1a to 1d. However, the number of alumina sintered bodies is not particularly limited, and the amount of wiring, the position of the semiconductor, etc. May be determined as appropriate.
[0024]
A surface conductor layer 3 a and an inner conductor layer 3 b are formed on the surfaces or interfaces of the alumina sintered bodies 1 a to 1 d constituting the insulating layer 1, and a ground conductor layer 3 c is interposed between the dielectric layer 2 and the alumina insulating layer 1. Is provided. Further, a via-hole conductor 3d that penetrates one or a plurality of alumina sintered bodies is provided. Therefore, the conductor layer 3 is provided on the surface and / or inside of the insulating substrate.
[0025]
An optical semiconductor element 5 is mounted on one surface side of the insulating substrate, and an optical waveguide 6 is formed. The optical waveguide 6 has a structure optically connected to the optical semiconductor element 5 and has a structure in which an optical waveguide cladding 6b is provided around the optical waveguide core 6a. The optical waveguide 6 exists on at least a part of one surface side of the insulating layer 1, and the optical semiconductor element 5 may be located outside the optical waveguide 6. In particular, it is preferable that the optical semiconductor element 5 is provided inside the optical waveguide 6 in order to increase malfunction and prevent malfunction.
[0026]
Furthermore, an electronic semiconductor element 7 is mounted on the other surface of the insulating layer 1. That is, the electronic semiconductor element 7 and the optical semiconductor element 5 are mounted on the opposing surfaces of the insulating substrate, respectively. By adopting such a configuration, a large number of electronic semiconductor elements 7 and optical semiconductor elements 5 can be mounted on one insulating substrate, and the miniaturization of the product by higher density mounting is promoted, and the reliability is also improved. Can be increased.
[0027]
Here, the dielectric layer 2 may be integrally laminated on the entire surface of the alumina sintered body 1d constituting the insulating substrate, but is formed on a part of the alumina sintered body 1d as shown in FIG. It is preferable. With this configuration, the surface of the insulating layer 1 is also exposed on the surface of the insulating substrate on the dielectric layer 2 side, so that the electronic semiconductor element 7 can be mounted there, and the mounting density can be increased.
[0028]
The electronic semiconductor element 7 can also be provided on one surface of the insulating layer 1 provided with the optical semiconductor element 5 and the optical waveguide 6. That is, the optical waveguide 6 may be formed on a part of the surface, and the electronic semiconductor element 7 may be mounted on the surface where the optical waveguide 6 is not provided.
[0029]
The electronic semiconductor element 7 is accommodated in a cavity 8 provided on the surface of the insulating substrate. The electronic semiconductor element 7 is mounted on the surface of the alumina sintered body 1d by ball mounting and / or bare chip mounting with solder or the like. Has been. Further, since the cavity 8 is hermetically sealed by the lid body 9 and has a structure in which outside air is not mixed into the cavity 8, malfunction of the electronic semiconductor element 7 can be prevented and reliability can be improved.
[0030]
In addition, on the surface of the dielectric layer 2, For high frequency input An external connection terminal 10 is provided. this For high frequency input The external connection terminal 10 is for inputting a high frequency from the outside, and is electrically connected to an external circuit. this For high frequency input Since the external connection terminal 10 is formed on the dielectric layer 2 having a low dielectric constant, For high frequency input A stray capacitance generated between the external connection terminal 10 and the internal conductor layer 3b is reduced, reflection of an input signal is suppressed, and signal loss can be reduced. As a result, an optoelectronic packaging circuit board capable of high frequency is realized. Can do.
[0031]
The insulating layer 1 is composed of an alumina sintered body formed by firing a molded body mainly composed of alumina and added with a desired sintering aid, and is composed of a single or a plurality of alumina sintered bodies. In order to increase the mounting density, it is preferable to use a plurality of laminated alumina bodies. Silica and Mn as sintering aids 2 O Three It is preferable to contain. These sintering aids enable firing at a low temperature, prevent the conductor layer 3 from flowing out due to melting of the metal, and increase the product yield. In addition, it is desirable that components other than alumina, such as a sintering aid, exist as an amorphous phase or a crystalline phase at the grain boundary of the alumina main crystalline phase.
[0032]
According to the present invention, the alumina sintered body of the insulating layer 1 desirably has a relative density of 95% or higher, particularly 97%, more preferably 98% or higher, in order to increase the thermal conductivity and strength of the insulating substrate. It is desirable that the conductivity is 10 W / m · K or more, particularly 15 W / m · K or more, and more preferably 17 W / m · K or more.
[0033]
The main crystal phase of the alumina sintered body forming the insulating layer 1 exists as a granular or columnar crystal, and the average crystal grain size of these main crystal phases is preferably 1.5 to 5 μm. . In addition, when the main crystal phase is composed of columnar crystals, the average crystal grain size is based on the minor axis diameter. If the average crystal grain size of this main crystal phase is smaller than 1.5 μm, it tends to be difficult to achieve high thermal conductivity, and if the average grain size is larger than 5 μm, sufficient strength required for use as a substrate material is required. This is because it tends to be difficult to obtain.
[0034]
The dielectric layer 2 can reduce the signal input loss, which is the object of the present invention, if it has a lower dielectric constant than alumina. In particular, at least one of mullite, forsterite, enstatite, silica, and cordierite. From the viewpoint of simultaneous sinterability with alumina, a sintered body containing as a main component is preferable. In addition to this, as another component, Mn 2 O Three , SiO 2 , ZnO, CaO, Nb 2 O Five , MoO Three , WO Three Alternatively, glass or the like may be added. Further, it is possible to contain 10% by weight or less of glass, but in order to achieve high strength of the substrate, 10% by weight or less, particularly 5% by weight or less is desirable.
[0035]
The conductor layer 3 preferably contains at least one of Au, Ag, Cu, and Pt in order to reduce resistance. Moreover, it is preferable to contain W and / or Mo for the adhesive improvement with an alumina. For example, it is set as the composition containing 10-70 volume% Cu and 30-90 volume% of W and / or Mo.
[0036]
The sheet resistance of the conductor layer 3 is preferably 8 mΩ / □ or less in terms of a conductor thickness of 15 μm. By having such a low sheet resistance, the wiring width can be reduced, and the size can be reduced.
[0037]
Next, the manufacturing method of the optoelectronic mounting circuit board of this invention is demonstrated.
[0038]
First, in order to produce the insulating layer 1, an alumina powder and a desired sintering aid powder are prepared. As the alumina raw material powder, a powder having an average particle size of 0.5 to 2.5 μm, particularly 0.5 to 2.0 μm is used. This is because if the average particle size is smaller than 0.5 μm, it is difficult to handle the powder, and the cost of the powder becomes high. If it is larger than 2.5 μm, it is difficult to fire at a temperature of 1500 ° C. or less. It is.
[0039]
As the second component, Mn 2 O Three 2-15% by weight of powder, as well as SiO 2 The powder is added in a proportion of 2 to 15% by weight. Mn 2 O Three By adding Mn compound powder such as powder, densification is promoted at 1200 to 1500 ° C., and high insulation can be maintained. 2 The addition of powder promotes densification and maintains high thermal conductivity. In addition, as the third component, at least one of Mg, Ca, Sr, B, Nb, Cr, Co oxides, carbonates, and hydrates may be simultaneously sintered with the Cu-containing conductor. In order to increase the content, 0.1 to 4% by weight is contained, and as a fourth component, a metal powder or oxide powder of a transition metal such as W, Mo, or Cr is used as a coloring component at a ratio of 2% by weight or less in terms of metal Added.
[0040]
On the other hand, the dielectric layer has mullite, forsterite, enstatite, silica, cord Yes One or more main component powders selected from light, and Mn as the second component 2 O 3 , SiO 2 , ZnO, CaO, Nb 2 O 5 , MoO 3 , WO 3 Among them, at least one kind, and 10% by weight or less of glass as a third component can be added. By making the addition of glass 10% by weight or less, the sinterability can be enhanced while suppressing the deformation of the low dielectric constant layer during firing and the decrease in thermal conductivity due to diffusion into the alumina layer.
[0041]
Here, a powder having a particle size of 0.5 to 5 μm, particularly 0.5 to 3 μm is used. This is because when the particle size is larger than 5 μm, cracks are generated in the sintered particles and the strength is remarkably lowered. Moreover, when it is smaller than 0.5 μm, it is difficult to handle the powder. In addition to the oxide powder, the oxide may be added as carbonate, nitrate, acetate or the like capable of forming an oxide by firing.
[0042]
And the sheet-like molded object for forming an insulating layer using each mixed powder is produced. The sheet-like molded body can be produced by a known molding method. For example, organic mixed with the above mixed powder Da After preparing a slurry by adding a solvent, it is formed by the doctor blade method or mixed with organic binder. Da In addition, a sheet-like molded body having a predetermined thickness can be produced by press molding, rolling molding, or the like. And a through-hole for via-hole conductors may be formed on the sheet-like molded body by a micro drill, a laser or the like.
[0043]
Next, the conductor paste includes at least Au powder, Ag powder, Cu powder, and Pt powder so that the conductor layer includes a low resistance metal (Au, Ag, Cu, Pt) and a refractory metal (W, Mo). It is preferable that 1 type is included and also W powder and / or Mo powder are included. For example, Cu powder and W powder, Au and Mo powder, etc., and specific examples include 10 to 70% by volume of Cu of 1 to 10 μm, particularly 30 to 60% by volume, and 30 to 30% of W and / or Mo of 1 to 10 μm. A conductor paste containing 90% by volume and 40 to 70% by volume is prepared. A metal such as Cu contributes to low resistance, and a refractory metal prevents peeling of the conductor layer due to a difference in thermal expansion coefficient with the insulating layer 1 and also has a firing temperature higher than the melting point of Cu. Also functions as a shape-retaining agent.
[0044]
In addition, the conductor paste preferably contains 0.05 to 3.0% by weight of at least one of Ni, Zr, Al, Li, Mg, and Zn in terms of metal element as desired. This is for reducing the resistance of the conductor layer and improving the simultaneous sintering property with the insulating substrate and maintaining the shape retention after the simultaneous firing of the conductor layer. Ni, Zr, Al, Li, Mg and Zn may be added as oxides, borides, nitrides or carbonates. The average particle size at this time is 0.6 to 4 μm, particularly 1.5. ˜3.0 μm is desirable.
[0045]
In the present invention, from the viewpoint of resistance of the conductor layer, separation of Cu component, bleeding, etc., the W powder and / or Mo powder has an average particle size of 1 to 10 μm, particularly 1.3 to 5 μm, more preferably 1.3. It is also important to prepare to be dispersed in a matrix made of Cu as sintered particles of ˜3 μm spherical or several particles.
[0046]
In these conductor pastes, alumina powder and the same composition powder as the oxide ceramic component forming the insulating layer are added at a ratio of 0.05 to 2% by volume in order to improve the adhesion to the insulating layer. It is also possible to do.
[0047]
Next, the conductor paste 3 is formed by applying the conductor paste on each of the insulating layers 1a to 1d by a method such as screen printing or gravure printing. Also, the via hole provided in the insulating layers 1a to 1d is filled with the conductor paste to form a via hole conductor layer 3d.
[0048]
Thereafter, the sheet-like molded body filled with the conductive paste is aligned and laminated and pressure-bonded, and then the laminated body is baked in a non-oxidizing atmosphere under a condition that the maximum baking temperature is 1200 to 1500 ° C. Bake.
[0049]
If the firing temperature at this time is lower than 1200 ° C., the alumina insulating substrate cannot be densified to a relative density of 95% or more in the case of using ordinary raw materials, and the thermal conductivity and strength are reduced, and at the same time, the low dielectric constant layer The densification of can not be achieved. On the other hand, if the firing temperature is higher than 1500 ° C., the sintering of W or Mo itself proceeds, the uniform structure cannot be maintained due to the flow of Cu, and it becomes difficult to maintain low resistance. The range of 1250 to 1400 ° C. is preferable.
[0050]
Further, the non-oxidizing atmosphere at the time of firing is preferably nitrogen or a mixed atmosphere of nitrogen and hydrogen. In particular, in order to suppress diffusion of Cu in the conductor layer, hydrogen and nitrogen are included. A non-oxidizing atmosphere with a dew point of + 30 ° C. or lower, particularly 0 to 25 ° C. is desirable. In addition, you may mix inert gas, such as argon gas, in this atmosphere if desired. If the dew point during firing is higher than + 30 ° C, the conductor material reacts with moisture in the atmosphere during firing to form an oxide film, and the insulating layer and Cu in the Cu-containing conductor react to reduce the resistance of the conductor. This is because it not only hinders the diffusion of Cu but also promotes the diffusion of Cu.
[0051]
Furthermore, in the insulating substrate of the present invention, the Cu component in the surface conductor layer 3a and the inner conductor layer 3b may diffuse into the insulating layer 1 and the dielectric layer 2 by simultaneous firing at a temperature exceeding the melting point of Cu. However, according to the present invention, it is desirable that the diffusion distance of Cu to the ceramic of the insulating substrate around the conductor layer containing at least Cu is 20 μm or less, particularly 10 μm or less. This is because if the diffusion distance of Cu into the ceramic exceeds 20 μm, the insulation between the conductor layers is lowered and the reliability as a wiring board is lowered.
[0052]
In addition, as a method of forming an optical waveguide on the surface of an insulating substrate produced by the above method, a silica-based optical waveguide is formed on an alumina insulating layer by a sol-gel method, or an organic material such as polyimide, polymethyl methacrylate, or polycarbonate. It is possible to form an optical waveguide using the optical waveguide or to form an optical waveguide using the CVD method.
[0053]
It is also possible to place the optical semiconductor element on the alumina insulating layer so as to be electrically connected to the conductor layer of the substrate and at the same time to be embedded in the optical waveguide cladding. The optical waveguide is formed on the alumina insulating layer because the optical waveguide forming layer has high strength and the thermal expansion coefficient of the element optically connected to the optical waveguide is close to that of alumina, so it has excellent connection reliability. This is because the thermal conductivity is excellent with respect to the heat generation of the semiconductor element.
[0054]
It is desirable that the electronic semiconductor element be placed on a surface having alumina as an insulating layer. This is because alumina, unlike glass ceramic, has a relatively high thermal conductivity, so that heat generated from the element can be efficiently and rapidly dissipated. Further, unlike a resin substrate such as polyimide, the thermal expansion coefficient is close to that of a semiconductor element, so that high primary mounting reliability can be ensured. At this time, the semiconductor element can be mounted on the substrate by ball mounting using solder or / and bare chip mounting.
[0055]
In the mounting board of the present invention, an electronic circuit including a capacitor, a resistor, and a wiring conductor is formed on the surface of a mother board such as a printed circuit board. For high frequency input It is mounted on an electronic circuit via the external connection terminal 10. According to the present invention, by using the mounting board having the above configuration as the optoelectronic mounting circuit board, the reflection loss when a high frequency signal of 40 GHz is input to the optoelectronic mounting circuit board is -10.0 dB or less, particularly -7 dB or less. Further, it can be set to -5 dB or less. Therefore, by using the optoelectronic mounting circuit board of the present invention, it is possible to input a high frequency signal of 40 GHz or more, and it is possible to cope with a large capacity optical communication.
[0056]
【Example】
In order to produce an insulating layer, alumina powder (average particle size 1.8 μm), Mn 2 O Three And SiO 2 6 wt% and MgO 0.5 wt%, respectively, and an acrylic binder and toluene as a solvent were added as an organic resin for the binder, and a slurry was prepared. To form a sheet having a thickness of 250 μm.
[0057]
In addition, in order to form a dielectric layer, one or more selected from mullite, forsterite, enstatite, silica, and cordierite as a main component, an additive shown in Table 1 is added, and a sheet-like molded body Was made. Here, the dielectric constant of the dielectric layer was adjusted by adjusting the amount of silica. And the via hole whose hole diameter after baking is 100-200 micrometers was formed in the predetermined location.
[0058]
Next, one kind of Cu powder, Ag powder, Au powder and Pt powder having an average particle diameter of 5 μm and W powder or Mo powder having an average particle diameter of 0.8 to 12 μm are mixed at a ratio shown in Table 1. And With this mixed powder Acrylic vine With A conductor paste was prepared using acetone as a solvent.
[0059]
And the said conductor paste was printed and applied on the sheet-like molded object, and the said conductor paste was filled also into the via-hole conductor layer of each sheet-like molded object. Each sheet-like molded body produced as described above was positioned and laminated and pressure-bonded to produce a molded body laminate. Thereafter, this molded body laminate was placed in an oxygen-containing atmosphere substantially free of moisture (H 2 + O 2 ) And then baked at 1300 ° C. in a nitrogen-hydrogen mixed atmosphere with a dew point of 20 ° C. to obtain the optoelectronic mounted circuit board of FIG.
[0060]
The density of the obtained substrate was measured by the Archimedes method. Moreover, the electrical resistance (sheet resistance conversion) of the conductor layer in a circuit board was measured by the 4-terminal method. Furthermore, the relative dielectric constant was measured at a measurement frequency of 40 GHz by the cavity resonator method based on JIS R1627.
[0061]
The reflection loss was measured at 40 GHz using a network analyzer and a wafer probe. Specifically, as shown in FIG. 2, a value between a mother board 22 on which the optoelectronic mounting circuit board 21 is mounted and a measurement electrode provided in the optoelectronic mounting circuit board 21 was measured. The cross-sectional configuration of the measurement sample at this time. For high frequency input The dielectric layer and the insulating layer forming the external connection terminals on the surface had a thickness of 0.25 mm and a via diameter of 0.1 mmφ, respectively. Also, For high frequency input The electrode pad (ball pad) diameter constituting the external connection terminal is 0.4 mmφ, the solder ball diameter is 0.3 mmφ, the ball pitch is 0.8 mm, and the mother board on which the optoelectronic circuit board is mounted has a thickness of 0.2 mm and a dielectric constant. A 3.5 Teflon substrate was used.
[0062]
The bending strength of the ceramic layer is For high frequency input Outside Connecting terminal The three-point bending strength was measured using a co-fired sample having a low dielectric constant insulating layer thickness of 0.5 mm used for the formation layer and an insulating layer thickness of 2.5 mm other than the insulating layer. Furthermore, regarding the thermal conductivity of the ceramic layer, the thermal conductivity at room temperature was measured by a laser flash method using a sample having a laminated structure used for the bending strength measurement.
[0063]
[Table 1]
Figure 0003847103
[0064]
Sample No. of the present invention. In Nos. 2 to 18, the dielectric constant of the dielectric layer was 4.4 to 8, which was smaller than 9 of alumina of the insulating layer, and the reflection loss was −10 dB or less.
[0065]
On the other hand, Sample No. in which the insulating layer and the dielectric layer are made of the same material. 1 had a reflection loss of -6.4 dB.
[0066]
In addition, sample No. out of the scope of the present invention in which the conductor layer is made of W or Mo. 19 and 20 had a large sheet resistance of 28 mΩ / □ or more and a large reflection loss of −6.5 dB.
[0067]
【The invention's effect】
The optoelectronic mounting circuit board of the present invention includes an optical waveguide, an optical semiconductor element, and an optical waveguide on the insulating layer surface of an insulating substrate in which an alumina insulating layer having excellent mechanical and thermal characteristics and a low dielectric constant dielectric layer are integrally provided. An electronic semiconductor element is placed on the dielectric layer For high frequency input By forming the external connection terminal, the reflection loss and insertion loss of the high-frequency input signal can be improved, and a highly reliable and small optoelectronic circuit board can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an optoelectronic packaging circuit board according to the present invention.
FIG. 2 is a schematic cross-sectional view showing a part of the mounting board of the present invention.
[Explanation of symbols]
1 ... Insulating layer
1a, 1b, 1c, 1d ... alumina sintered body
2 ... Dielectric layer
3. Conductor layer
3a ... surface conductor layer
3b ... Inner conductor layer
3c: Ground conductor layer
3d: Via hole conductor layer
5 ... Optical semiconductor element and / or optoelectronic semiconductor element
6 ... Optical waveguide
6a: Optical waveguide core
6b: Optical waveguide cladding
7 ... Electronic semiconductor element
8 ... cavity
9 ... Lid
10 ... For high frequency input External connection terminal

Claims (11)

アルミナ焼結体からなる絶縁層と、該絶縁層よりも低誘電率の誘電体層とが一体的に積層されてなり、且つ表面及び／又は内部にＡｕ、Ａｇ、Ｃｕ、Ｐｔのうち少なくとも１種の導体層が形成された絶縁基板と、該絶縁基板の一方の表面側に搭載された光導波路及び光半導体素子と、前記絶縁基板の一方又は他方の表面に搭載された電子半導体素子と、前記絶縁基板の前記誘電体層上に設けられた高周波入力用外部接続端子を具備することを特徴とする光電子実装回路基板。An insulating layer made of an alumina sintered body and a dielectric layer having a lower dielectric constant than the insulating layer are integrally laminated, and at least one of Au, Ag, Cu, and Pt on the surface and / or inside thereof. An insulating substrate on which a conductive layer of a seed is formed; an optical waveguide and an optical semiconductor element mounted on one surface side of the insulating substrate; an electronic semiconductor element mounted on one or the other surface of the insulating substrate; An optoelectronic circuit board comprising an external connection terminal for high frequency input provided on the dielectric layer of the insulating substrate. 前記絶縁層及び／又は前記誘電体層が積層体からなることを特徴とする請求項１記載の光電子実装回路基板。2. The optoelectronic circuit board according to claim 1, wherein the insulating layer and / or the dielectric layer is formed of a laminate. 前記電子半導体素子と前記光半導体素子とが前記絶縁基板の対向する表面に搭載されていること特徴とする請求項１又は２記載の光電子実装回路基板。Optoelectronic mounting circuit board according to claim 1 or 2, wherein the said electronic semiconductor element and the optical semiconductor element is mounted on the opposite surface of the insulating substrate. 前記絶縁基板の表面に設けられたキャビティの内部に前記電子半導体素子が収納され、且つ該キャビティが蓋体によって気密封止されていることを特徴とする請求項１乃至３のいずれかに記載の光電子実装回路基板。 Wherein the interior of the cavity provided on the surface of the insulating substrate electronic semiconductor element is accommodated, and the cavity is according to any one of claims 1 to 3, characterized in that it is hermetically sealed by a lid Optoelectronic mounting circuit board. 前記絶縁基板の前記誘電体層が、前記絶縁層の表面の一部に形成されてなることを特徴とする請求項１乃至４のいずれかに記載の光電子実装回路基板。The optoelectronic packaging circuit board according to claim 1, wherein the dielectric layer of the insulating substrate is formed on a part of a surface of the insulating layer. 前記光半導体素子が、前記光導波路の内部に設けられてなることを特徴とする請求項１乃至５のいずれかに記載の光電子実装回路基板。6. The optoelectronic packaging circuit board according to claim 1, wherein the optical semiconductor element is provided inside the optical waveguide. 前記誘電体層がムライト、フォルステライト、エンスタタイト、シリカ、コーデイエライトのうち少なくとも１種を主成分とする焼結体であることを特徴とする請求項１乃至６のいずれかに記載の光電子実装回路基板。7. The photoelectron according to claim 1, wherein the dielectric layer is a sintered body mainly comprising at least one of mullite, forsterite, enstatite, silica, and cordierite. Mounting circuit board. 前記アルミナ焼結体が、シリカ及びＭｎ２Ｏ３を含有することを特徴とする請求項１乃至７のいずれかに記載の光電子実装回路基板。The optoelectronic mounted circuit board according to claim 1, wherein the alumina sintered body contains silica and Mn 2 O 3 . 前記導体層が、Ｗ及び／又はＭｏを含むことを特徴とする請求項１乃至８のいずれかに記載の光電子実装回路基板。9. The optoelectronic packaging circuit board according to claim 1, wherein the conductor layer contains W and / or Mo. 前記導体層のシート抵抗が導体厚み１５μｍ換算で８ｍΩ／□以下であることを特徴とする請求項１乃至９のいずれかに記載の光電子実装回路基板。10. The optoelectronic circuit board according to claim 1, wherein the sheet resistance of the conductor layer is 8 mΩ / □ or less in terms of a conductor thickness of 15 μm. 母基板の表面に、コンデンサ、抵抗体及び配線導体を含む電子回路が形成され、且つ請求項１乃至１０のうちいずれかに記載の光電子実装回路基板が前記高周波入力用外部接続端子を介して前記電子回路に実装されてなり、４０ＧＨｚの高周波信号が前記光電子実装回路基板に入力するときの反射損失が−１０．０ｄＢ以下であることを特徴とする実装基板。An electronic circuit including a capacitor, a resistor, and a wiring conductor is formed on a surface of the mother board, and the optoelectronic circuit board according to any one of claims 1 to 10 is connected to the high-frequency input external connection terminal via the external connection terminal. A mounting board, which is mounted on an electronic circuit and has a reflection loss of -10.0 dB or less when a high frequency signal of 40 GHz is input to the optoelectronic mounting circuit board.
JP2001162936A 2001-03-30 2001-05-30 Optoelectronic mounting circuit board and mounting board Expired - Fee Related JP3847103B2 (en)

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