JP3842917B2 - Power supply circuit using DC-DC converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power supply circuit using a DC-DC converter.
[0002]
[Prior art]
FIG. 4 is a circuit diagram showing a power supply circuit using a conventional DC-DC converter.
[0003]
In FIG. 4, the NPN transistor (1) is turned on and off when a clock signal CK having a predetermined frequency is supplied to the base. That is, when the NPN transistor (1) is turned on, energy is stored in the coil (2). After that, when the NPN transistor (1) is turned off, a counter electromotive voltage is generated in the coil (2). The capacitor (4) is charged via the diode (3). Note that the higher the capacitance of the capacitor (4), the higher the boosting effect can be obtained. The terminal voltage of the capacitor (4) at this time becomes the power supply voltage of the load.
[0004]
The RC oscillator (5) includes a Schmitt inverter (6), a resistor (7), and a capacitor (8), and an oscillation clock CK (about 600 KHz) at an oscillation frequency determined by the resistance value of the resistor (7) and the capacitance of the capacitor (8). ). The drain-source path of the N-type MOS transistor (9) is connected between the input terminal of the Schmitt inverter (6) constituting the RC oscillator (5) and the ground. One end of the pull-down resistor (10) on the non-ground side is connected to the gate of the N-type MOS transistor (9) through the inverter (11). When the 1.5 volt battery (12) is installed, the inverter (11) outputs “L”, the N-type MOS transistor (9) is turned off, and the RC oscillator (5) is the input terminal of the Schmitt inverter (6). Is released from the control of the N-type MOS transistor (9) and starts oscillating. On the other hand, if the battery (12) is removed or the battery (12) is accidentally removed, the input of the inverter (11) is grounded via the pull-down resistor (10), so the inverter (11) outputs “H”. Then, the N-type MOS transistor (9) is turned on, and the RC oscillator (5) stops the oscillation operation when the input terminal of the Schmitt inverter (6) is grounded. The threshold voltages of the Schmitt inverter (6), the N-type MOS transistor (9) and the inverter (11) are set low. Therefore, since the oscillation operation of the RC oscillator (5) can be stopped before the oscillation operation of the RC oscillator (5) becomes indefinite as the power supply voltage decreases, the malfunction of the DC-DC converter can be prevented beforehand.
[0005]
The negative terminal of the comparator (13) is connected to the non-grounded terminal of the capacitor (4), that is, the power supply line of the subsequent load, and the positive terminal is connected to the reference voltage Vref. One input terminal of the AND gate (14) is connected to the output of the RC oscillator (5), the other input terminal is connected to the output of the comparator (13), and the output terminal is connected to the NPN transistor via the resistor (15). It is connected to the base of (1). That is, the comparator (13) performs negative feedback control of the NPN transistor (1). Specifically, when the terminal voltage of the capacitor (4) is lower than the reference voltage, the AND gate (14) is accompanied with the "H" output. And the NPN transistor (1) repeats the switching operation according to the oscillation clock CK. On the other hand, when the terminal voltage of the capacitor (4) is higher than the reference voltage Vref, the AND gate (14) is accompanied by the “L” output. Is closed to stop the switching operation of the NPN transistor (1). Thus, the terminal voltage of the capacitor (4) is always held at Vref regardless of the load fluctuation.
[0006]
[Problems to be solved by the invention]
FIG. 5 is a waveform diagram showing the operation of FIG.
[0007]
In the circuit of FIG. 4, since negative feedback acts on the NPN transistor (1), the power supply voltage generated on the non-grounded side of the capacitor (4) can be held at a constant value Vref regardless of the presence or absence of the load or the fluctuation of the load.
[0008]
However, the frequency of the comparison output signal of the comparator (13) that opens and closes the AND gate (14) may overlap with the voice band (20 Hz to 20 KHz). In this case, there is a problem that a beat sound is generated.
[0009]
Therefore, an object of the present invention is to provide a power supply circuit for a DC-DC converter having a function for preventing the generation of beat sounds.
[0010]
[Means for Solving the Problems]
The present invention has been created to solve the above problems, and is caused by an oscillator that generates an oscillation clock having a predetermined frequency, a switching transistor that is turned on / off according to the oscillation clock, and an on / off state of the switching transistor. A capacitor for charging a counter electromotive voltage generated in the coil, a comparison circuit for comparing a terminal voltage of the capacitor with a reference voltage, and an on period of the switching transistor based on an oscillation clock of the oscillator according to a comparison result of the comparison circuit In a DC-DC converter that supplies the terminal voltage of the capacitor as a power supply voltage for a subsequent stage, and is interposed between the output of the comparison circuit and the input of the restriction circuit, Beat sound prevention that prevents the generation of beat sound when the output frequency of the circuit is audible band frequency Circuit, a changeover switch for selectively outputting one of the outputs of the comparison circuit or the beat sound prevention circuit, and a rewritable characteristic, wherein the changeover switch is connected to the comparison circuit side or the beat signal according to a write value. And a non-volatile memory connected to one of the sound prevention circuits.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Details of the present invention will be specifically described with reference to the drawings.
[0012]
FIG. 1 is a circuit diagram showing a power supply circuit using a DC-DC converter of the present invention. It is assumed that the range of the alternate long and short dash line is integrated, and the same elements as those in FIG.
[0013]
In FIG. 1, the beat sound prevention circuit (16) is provided between the output terminal of the comparator (13) and the other input terminal of the AND gate (14).
[0014]
FIG. 2 is a circuit diagram showing an embodiment of the beat sound prevention circuit (16).
[0015]
In FIG. 2, a frequency signal of 25 KHz that is out of the audio band and three times that of 75 KHz is supplied to the two input terminals of the AND gate (101). The comparison output signal of the comparator (13) is supplied to one input terminal of the AND gate (102), and the inverted output signal of the AND gate (101) via the inverter (103) is supplied to the other input terminal. . The output signals of the AND gates (101) and (102) are supplied to the two input terminals of the OR gate (104). The change-over switch (105) switches between the comparison output signal of the comparator (13) and the output signal of the OR gate (104). For example, when the comparison output frequency of the comparator (13) does not overlap the voice band, the changeover switch (105) may be fixed to the a terminal side, and the comparison output frequency of the comparator (13) may overlap the voice band. In the case of a certain specification, the changeover switch (105) may be fixed to the b terminal side.
[0016]
The operation when the changeover switch (105) of FIG. 2 is fixed to the b terminal side will be described below with reference to the time chart of FIG.
[0017]
The output C of the OR gate (104) becomes “H” only during the addition period of the right-upward oblique line and the right-downward oblique line, and becomes a constant signal at 25 KHz where the frequency exceeds the audio band. “H” in the right-upward diagonal line period is the logical product signal A of the AND gate (101), and “H” in the right-down diagonal line period is the comparison output signal itself of the comparator (13). Accordingly, the AND gate (14) opens only during the period when the OR signal C of the OR gate (104) is “H”, and the NPN transistor (1) performs the switching operation based on the oscillation clock CK. At this time, the logical sum signal C of the OR gate (104) for opening and closing the AND gate (14) is forcibly set to a frequency band higher than the voice band by the logical product signal A of the AND gate (101). Generation of beat sound can be prevented.
[0018]
In FIG. 1, a non-volatile memory (17) has characteristics that data can be electrically erased and data can be repeatedly written and read, and is integrated in an integrated circuit when the range of the alternate long and short dash line is integrated. The nonvolatile memory (17) is an EEPROM, a flash memory, or the like. In the nonvolatile memory (17), a logical value corresponding to whether or not the comparison output frequency of the comparator (13) overlaps the voice band may be written in advance. For example, in the case where the comparison output frequency of the comparator (13) does not overlap the voice band, the logical value “0” is written in the nonvolatile memory (17) and the changeover switch (105) is connected to the a terminal side. On the other hand, in the case where the comparison output frequency of the comparator (13) may overlap the voice band, the logical value “1” is written in the nonvolatile memory (17) and the changeover switch (105) is connected to the b terminal side. Just do it. The bit line of the non-volatile memory (17) is connected to the change control line of the changeover switch (105), and the changeover switch (105) is controlled by hardware simultaneously with power-on.
[0019]
【The invention's effect】
According to the present invention, even when the comparison output signal of the comparison circuit overlaps the voice band, it can be forced to be higher than the voice band, and the generation of beat sound can be prevented. Depending on whether the comparison circuit outputs a comparison signal for the voice band, the use of the beat sound prevention circuit can be controlled by the value written in the non-volatile memory, reducing design time, reducing design cost, and generalization It becomes possible to adapt to. The following advantages are obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a power supply circuit using a DC-DC converter of the present invention.
2 is a circuit diagram showing one embodiment of the beat sound prevention circuit of FIG. 1; FIG.
FIG. 3 is a time chart showing the operation of FIG. 2;
FIG. 4 is a circuit diagram showing a power supply circuit using a conventional DC-DC converter.
FIG. 5 is a waveform diagram showing the operation of FIG. 4;
[Explanation of symbols]
(1) NPN transistor (2) Coil (4) Capacitor (5) RC oscillator (9) N-type MOS transistor (10) Pull-down resistor (13) Comparator (14) AND gate (16) Beat sound prevention circuit (17) Non-volatile memory

Claims (4)

An oscillator that generates an oscillation clock having a predetermined frequency, a switching transistor that is turned on / off according to the oscillation clock, a capacitor that charges a counter electromotive voltage generated in a coil due to the on / off of the switching transistor, and a terminal voltage of the capacitor A comparison circuit for comparing with one reference voltage, and a control circuit for controlling an on period of the switching operation of the switching transistor based on an oscillation clock of the oscillator according to a comparison result of the comparison circuit, In a power supply circuit using a DC-DC converter that supplies a terminal voltage as a power supply voltage of a subsequent load,
A beat sound prevention circuit that applies an output signal from the comparison circuit and a first frequency signal, combines the output signal of the comparison circuit and the first frequency signal, and generates a frequency higher than an audible band frequency.
The power supply circuit using a DC-DC converter, wherein the beat sound prevention circuit prevents the switching operation of the switching transistor from becoming an audible band frequency. The beat sound prevention circuit shapes the waveform of the first frequency signal using a second frequency signal having a frequency higher than that of the first frequency signal, and after changing the ratio of the high level period and the low level period, 2. A power supply circuit using a DC-DC converter according to claim 1, wherein the power supply circuit is combined with an output signal of a comparison circuit. 2. The power supply circuit using a DC-DC converter according to claim 1, wherein the first frequency signal is higher than 20 KHz. The changeover switch includes a changeover switch that selectively outputs one of an output signal from the comparison circuit and a signal obtained by combining the output signal and the first frequency signal. A power supply circuit using the DC-DC converter according to Item 1.

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