JP3842269B2 - Receiving device, communication system using the same, and sampling rate conversion means - Google Patents

Description

Technical field
The present invention relates to a receiving apparatus capable of demodulating a signal with less waveform distortion with a simpler circuit configuration than multi-bit based on a digital signal received via a packet communication network, a communication system using the same, and a sampling rate It relates to conversion means.
Background art
With the rapid development of the Internet and computers in recent years, digital signal transmission networks such as IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 1394 and USB (Universal Serial Bus) or Ethernet (registered trademark) are used. Communication systems that use analog audio signals and video signals to transmit are becoming widespread.
For example, in the transmission apparatus 103 of the communication system 101 shown in FIG. 18, the PCM modulation circuit 111 performs a PCM (Pulse Code Modulation) modulation on an input signal from a signal source (not shown) to form a data sequence consisting of a multi-bit code sequence. 111 is generated. Further, the transmitter 112 converts the data string S111 into a digital signal S103 in a format that can be transmitted by the network 102 by dividing the packet into packets or attaching a destination address, for example, and then transmitting the data sequence S111 to the network 102. To do.
On the other hand, in the receiving apparatus 104, when the receiver 121 receives the digital signal S103 from the transmitting apparatus 103 from the network 102, the receiver 121 sequentially outputs a multi-bit code based on the digital signal S103. Further, the sequentially output multi-bit code sequence (data sequence S121) is demodulated by the demodulation circuit 122 and output from the reception device 104 as a demodulated signal S104 of an analog signal.
Here, if the period at which the PCM modulation circuit 111 outputs each code in the transmission apparatus 103 and the period at which the demodulation circuit 122 processes each code in the reception apparatus 104 are different, the code processed by the demodulation circuit 122 As a result of lack of sound, skipping of the sound occurs, or as a result of deleting excess codes, the waveform of the demodulated signal S104 is distorted. Note that if the sampling rate converter that absorbs the difference in period is provided in the receiving device 104 to prevent the sound skip and waveform distortion, the transfer function becomes complicated and a large number of bit widths can be calculated. Since a digital filter is required, the circuit configuration of the receiving device 104 becomes complicated.
Therefore, in the communication system 101, a PLL (Phase Locked Loop) circuit 123 is provided in the receiving device 104. The PLL circuit 123 adjusts the frequency and phase of the clock signal S123 according to the digital signal S103 itself transmitted from the transmission device 103 via the network 102 or the clock signal S113 transmitted together with the digital signal S103. . Further, the demodulation circuit 122 operates in synchronization with the clock signal S123 from the PLL circuit 123. As a result, the demodulation circuit 122 can process the code from the receiver 121 in the period in which the PCM modulation circuit 111 outputs each code, and can prevent the occurrence of sound skipping and waveform distortion. In the example of FIG. 18, the PCM modulation circuit 111 of the transmission apparatus 103 operates in synchronization with a clock signal S113 given from the clock signal generation circuit 113 and having a predetermined period.
An example of a conventional sampling rate converter is disclosed in Japanese Patent Laid-Open No. 4-35111 (published on February 5, 1992). Japanese Laid-Open Patent Publication No. 6-104833 (published on April 15, 1994) discloses a demodulating means for transmitting a digital signal using an optical fiber after converting the analog signal into a digital signal by delta-sigma modulation. A technique for transmitting an analog signal with high quality by returning the signal to an analog signal using a signal is disclosed. Furthermore, a technique for transmitting a SACD signal using IEEE 1394 is standardized by 1394TA (Trading Association). IEEE 1394 is a standard for communication using packets, and SACD is a standard for recording music using a signal obtained by delta-sigma modulation.
However, in the above-described conventional configuration, a demodulator circuit capable of higher-speed operation processing with a larger bit width is required to further reduce the waveform distortion. Therefore, with the conventional configuration, it is difficult to realize both high-quality signal waveform transmission and simplification of the circuit configuration of the receiving apparatus.
Furthermore, especially when the signal cannot be transmitted with the time accuracy necessary for the PLL circuit 123 to operate stably as in the Internet or a wireless communication network, the PLL circuit 123 is not stable. Therefore, there is a possibility that waveform distortion due to the period variation of the clock signal S123 may occur.
The present invention has been made in view of the above problems, and its object is to provide a signal with less waveform distortion with a simpler circuit configuration than multi-bit based on a digital signal received via a network for packet communication. Is to realize a receiver capable of demodulating the signal, a communication system using the same, and a sampling rate conversion means.
Disclosure of the invention
In order to achieve the above object, a receiving apparatus according to the present invention receives from a network a digital signal generated by dividing a pulse number modulation signal in which the number of pulses per unit time varies according to the signal waveform. And receiving means for extracting a bit string indicating a pulse number modulation signal from the digital signal, and pulse number modulation signal output means for outputting a pulse corresponding to each bit of the bit string in a predetermined cycle. It is said.
In the above configuration, the transmission device generates a pulse number modulation signal by modulating a signal waveform such as an audio signal by a modulation method such as delta-sigma modulation, for example. Further, the pulse number modulation signal is divided into packets and transmitted as a digital signal to a network capable of transmitting packets.
On the other hand, when the digital signal reaches the receiving device, the receiving means of the receiving device extracts a bit string indicating the pulse number modulation signal from the digital signal, and the pulse number modulation signal output means corresponds to each bit of the bit string. Pulses are output at a predetermined cycle. As a result, a digital signal indicating a pulse number modulation signal is not necessarily transmitted at the same time interval as each pulse of the pulse communication network, that is, each pulse of the pulse number modulation signal may be transmitted. When transmitting via a certain network, the receiver unit achieves both a reduction in waveform distortion during demodulation and a simple circuit configuration compared to the case of transmitting a digital signal indicating a multi-bit signal. A possible pulse number modulation signal can be generated without any trouble. As a result, a receiving apparatus capable of demodulating a signal with less waveform distortion can be realized with a simple circuit configuration compared to the case of multi-bit.
Other objects, features, and advantages of the present invention will be fully understood from the following description. The benefits of the present invention will become apparent from the following description with reference to the accompanying drawings.
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
An embodiment of the present invention will be described with reference to FIGS. 1 to 9 as follows. That is, as shown in FIG. 1, the communication system 1 according to the embodiment transmits a digital signal S3 indicating a signal waveform from a transmission device 3 to a reception device 4 via a network 2 that transmits digital signals in packets. It is. The communication system 1 is preferably used when, for example, an analog signal (for example, an audio signal) input in real time is transmitted with high accuracy.
The network 2 is a digital signal transmission network such as IEEE 1394, USB, Ethernet (registered trademark), or a combination thereof. The network 2 has a sufficient bandwidth for the transmission of the digital signal S3 in the communication path from the transmission device 3 to the reception device 4.
As will be described later, the receiving device 4 according to the present embodiment determines the output period of the received delta-sigma modulated signal S23 based on the clock signal S22 independent of the network 2. Therefore, the network 2 may include an intermediate node that operates with a clock signal independent of the transmission device 3 and the reception device 4, such as a repeater. In each node of the network 2, the accuracy of the clock signal used as a reference is sufficient for the transmission of the digital signal S3 regardless of the accuracy required when the receiving device 4 reproduces the delta-sigma modulated signal S23. Any accuracy is sufficient.
The transmission device 3 according to the present embodiment modulates an analog signal input from a signal source (not shown) into a delta sigma modulation signal S11 and outputs the delta sigma modulation circuit S11 and a pulsed delta sigma modulation signal S11 A transmitter 12 that transmits a digital signal S3 to the network 2 and a clock signal generation circuit 13 that inputs a clock signal S13 indicating sampling timing to the delta-sigma modulation circuit 11 are provided.
The delta-sigma modulation circuit 11 performs first-order or higher-order integration on the difference between the input signal Si and the feedback signal Sf, and quantizes the integration result at the sampling period indicated by the clock signal S13. The quantization result is output to the transmitter 12 as a pulsed delta sigma modulation signal S11 and also input to the delta sigma modulation circuit 11 as a feedback signal Sf.
Here, when the delta-sigma modulation signal S11 is generated as a 1-bit data string by being quantized into two values, when the delta-sigma modulation signal S11 is at a high level, the signal of the feedback signal Sf is compared with the case of the low level. Since the level also increases, the integration result decreases unless the input signal Si is sufficiently large. Therefore, the possibility that the delta-sigma modulation circuit 11 outputs the high-level delta-sigma modulation signal S11 decreases. On the contrary, when the delta-sigma modulation signal S11 is at a low level, the signal level of the feedback signal Sf is small, so that the integration result increases according to the input signal Si. Therefore, there is a high possibility that the delta sigma modulation circuit 11 outputs the high level delta sigma modulation signal S11. As a result, the frequency (number of pulses per unit time) of the delta-sigma modulation signal S11 is controlled to a frequency according to the signal level of the input signal Si.
Further, the clock signal generation circuit 13 according to the present embodiment generates the clock signal S13 independently of the clock of the network 2. The frequency of the clock signal S13 is set so that the sampling frequency by the delta-sigma modulation circuit 11 becomes a predetermined frequency. For example, when the delta-sigma modulation circuit 11 detects each rising point of the clock signal S13 and determines the sampling timing, it is set to the same frequency as the sampling frequency, and when both edges are detected, the sampling frequency Is set to half the frequency.
Further, the transmitter 12 is configured according to the network 2 connected to the transmission device 3, and converts the pulse train of the delta-sigma modulated signal S 11 into the digital signal S 3 having a format that can be transmitted by the network 2. The digital signal S3 can be transmitted to the network 2. Since the network 2 according to the present embodiment packet-transmits the digital signal S3, the transmitter 12 divides the pulse train of the delta-sigma modulated signal S11 into packets. Further, in the case of the network 2 that needs to add an address indicating a transmission destination to a packet, the address can be added to the packet. Further, for example, in the case of the network 2 that needs to perform a predetermined operation before or after transmission of the digital signal S3, such as a request to acquire a bus use right, these operations can be performed as necessary.
On the other hand, the receiving device 4 according to the present embodiment receives a digital signal S3 from the network 2, and based on the digital signal S3, a receiver 21 that sequentially generates a data sequence S21 indicating each pulse of the delta-sigma modulated signal S11. Independently of the network 2, the clock signal generation circuit 22 that generates a clock signal S22 having a predetermined frequency and the output cycle of the data string S21 are converted into the cycle indicated by the clock signal S22. A sampling rate converter 23 that generates the delta-sigma modulation signal S23 and a low-pass filter (LPF) 24 that demodulates the delta-sigma modulation signal S23 are provided.
The period of the clock signal S22 is determined in advance so that the period at which the sampling rate converter 23 outputs the delta sigma modulation signal S23 has the same value as the sampling period in the delta sigma modulation circuit 11 of the transmission device 3. For example, when the sampling rate converter 23 detects each rising point of the clock signal S22 and determines the output timing of the delta sigma modulation signal S23, the cycle of the clock signal S22 is set to be the same as the sampling cycle. . When both edges are detected, the cycle of the clock signal S22 is set to twice the sampling cycle.
Here, the clock signal generation circuit 22 generates a clock signal S22 having a predetermined cycle independently of the network 2. Therefore, unlike a case where a clock signal is transmitted from a transmission device to a reception device via a network, or a case where the reception device adjusts the phase of the PLL circuit of its own device according to the signal from the network, a delta-sigma modulation signal While the digital signal S3 corresponding to S11 is received and demodulated, the cycle of the clock signal S22 does not fluctuate.
However, in the above configuration, the clock signal generation circuit 22 of the reception device 4 generates the clock signal S22 independently of the network 2. Therefore, even if the oscillation accuracy of the clock signal generation circuit 22 is improved, the sampling period of the transmission apparatus 3 and the period indicated by the clock signal S22 are influenced by the individual differences of the transmission apparatus 3 and the reception apparatus 4 and the ambient temperature. Is not exactly the same. For example, an error of about 100 ppm may occur.
However, in the above configuration, the sampling rate converter 23 is provided to compensate for the error. Therefore, even if the sampling period of the transmission device 3 does not coincide with the period indicated by the clock signal S22, the output period of the sampling rate converter 23 is aligned with the period indicated by the clock signal S22.
As a result, the sampling rate converter 23 can output the delta sigma modulation signal S23 having a fixed period indicated by the clock signal S22 and input it to the LPF 24.
Here, unlike the case where a digital signal having a value indicating the level of the demodulated signal (multi-bit digital signal) is transmitted, a digital signal S3 indicating a delta-sigma modulated signal S11 is transmitted to the network 2 and digital. The delta-sigma modulation signal S23 generated based on the signal S3 is demodulated by removing high-frequency components in the LPF 24.
The removal of this high frequency component can be realized by an integrator composed of a capacitor, a coil or the like or a circuit including an integration process. The integrator described below shows not only a circuit that performs a pure integration operation, but also a circuit that includes an integration process for removing high-frequency components.
Therefore, for example, the following conversion operations (1) and (2) that can be performed with a relatively simple circuit, that is,
(1) When the sampling frequency of the delta-sigma modulated signal S11 transmitted through the network 2 (the frequency of the timing indicated by the clock signal S13) is higher than the frequency of the timing indicated by the clock signal S22, the sampling rate converter 23 To delete
(2) Operation in which the sampling rate converter 23 inserts bits when the sampling frequency of the delta-sigma modulation signal S11 transmitted through the network 2 is lower than the timing frequency indicated by the clock signal S22.
Thus, even if the sampling rate is converted, unlike the case of multi-bit, an error accompanying the conversion hardly appears in the demodulated signal S4.
That is, as shown in FIG. 2, when the digital signal indicating the multi-bit value x is transmitted, one unit of digital signal S3 is transmitted as compared to the case of transmitting the 1-bit digital signal S3 as in the present embodiment. The time (1 unit time) occupied by data (multi-bit data) becomes long. Therefore, when the receiving apparatus determines the period for outputting multi-bit data to the demodulation circuit based on the clock signal generated independently of the network, it is inserted to compensate for the difference between the sampling period and the output period. / Data to be deleted greatly affects the demodulated signal. Also, if the sampling rate is converted using a multi-bit digital filter, the operation with the digital filter becomes more complicated than the case of 1 bit, and the circuit scale of the digital filter increases significantly. . If a digital filter having a complicated transfer function is used to suppress the influence, the circuit scale further increases.
On the other hand, when a 1-bit digital signal is transmitted as in this embodiment, the time occupied by 1 unit of data (1 bit of data) is shortened. Therefore, when the sampling rate converter 23 generates the delta sigma modulation signal S23, the time points at which the data string S21 is operated can be dispersed. The demodulated signal S4 is generated by integrating the delta-sigma modulated signal S23. Therefore, the influence of data / bit deletion / insertion is reduced.
As a result, the sampling rate converter 23 can be configured with a simple circuit and the quality of the demodulated signal S4 output from the LPF 24 can be improved as compared with the case of transmitting a multi-bit digital signal.
Hereinafter, as a configuration example of the sampling rate converter 23, a configuration in which bits of random values are inserted will be described. For example, as shown in FIG. 3, the sampling rate converter 23 generates a 1-bit random number and a FIFO (First In First Out) buffer 31 that receives a 1-bit data string S21 sequentially output from the receiver 21. A random number generator 32, a switch 33 connecting one of the FIFO buffer 31 and the random number generator 32 and the output terminal T23, and an attempt to read 1-bit data from the FIFO buffer 31 at a cycle indicated by the clock signal S22; A control circuit 34 is provided that causes the switch 33 to select the FIFO buffer 31 if the switch is successful, and causes the switch 33 to select the random number generator 32 if the switch 33 is unsuccessful.
In the above configuration, when the sampling frequency of the delta-sigma modulation signal S11 is lower than the output frequency of the sampling rate converter 23, the reading speed is faster than the writing speed to the FIFO buffer 31, as shown in FIG. Therefore, as shown by P1 and P2 in FIG. 4, the FIFO buffer 31 is emptied at a time interval corresponding to the ratio of both speeds, and reading fails.
In this case, the switch 33 outputs a signal from the random number generator 32 instead of the signal from the FIFO buffer 31 in accordance with an instruction from the control circuit 34. As a result, random values of bits are inserted between the data sequences S21, and the sampling rate converter 23 inserts the bits between the data sequences S21 at the timing period indicated by the clock signal S22. Can be output.
Here, in the configuration of FIG. 3, the sampling rate converter 23 inserts random bits between the data strings S21. Therefore, the problem that periodic distortion occurs in the demodulated signal S4 is prevented.
On the other hand, when the sampling frequency of the delta sigma modulation signal S11 is higher than the output frequency of the sampling rate converter 23, the reading speed is slower than the writing speed to the FIFO buffer 31, as shown in FIG. Therefore, as shown by P3 and P4 in FIG. 5, data overflows in the FIFO buffer 31 at time intervals corresponding to the ratio between the two speeds. In this case, the FIFO buffer 31 cannot store either the data received from the receiver 21 or the stored data. Thereby, the sampling rate converter 23 can output the delta-sigma modulation signal S23 from which some bits of the data sequence S21 are deleted at the timing cycle indicated by the clock signal S22.
4 and 5 exemplify the case where the sampling frequency of the delta sigma modulation signal S11 and the output frequency of the sampling rate converter 23 are greatly different for convenience of explanation. However, by improving the oscillation accuracy of the clock signal generation circuits 13 and 22, the difference between the two can be suppressed to a sufficiently low value, for example, about 100 ppm. Therefore, the frequency at which the data sequence S21 is operated when the sampling rate converter 23 generates the delta-sigma modulated signal S23 is also extremely low, for example, about 100 ppm. As a result, the influence of the operation on the demodulated signal S4 that is demodulated by integrating the delta-sigma modulated signal S23 is suppressed, and the receiving device 4 can obtain the highly accurate demodulated signal S4. In order to suppress the noise level in the audible frequency band, it is desirable that the random number generated by the random number generator 32 has more high frequency components than uniform frequency components.
Incidentally, in FIG. 3, the configuration in which the sampling rate converter 23 inserts a random value bit has been described, but the present invention is not limited to this. For example, instead of the random number generator 32 shown in FIG. 3, a generation circuit 35 that changes the output value every time the switch 33 selects the generation circuit 35 may be provided as in the sampling rate converter 23 a shown in FIG. 6. .
The sampling rate converter 23a can alternately insert 0 and 1 bits when inserting bits between the data strings S21. Therefore, the DC balance of the waveform (the waveform of the demodulated signal S4) indicated by the delta-sigma modulated signal S23 can be maintained for a longer time than the configuration of FIG.
Further, when the receiving device 4 is disconnected from the network 2 and the FIFO buffer 31 is emptied, the 0 and 1 bits are output alternately and continuously. Therefore, along with the leakage of charges inside the LPF 24, the LPF 24 The output converges to zero. Therefore, if the sampling rate converter 23a is used, the output of the receiving device 4 disconnected from the network 2 is muted without performing special processing.
As another configuration example, a D-flip flop (D−) that holds the value output last time by the FIFO buffer 31 instead of the random number generator 32 shown in FIG. 3, like a sampling rate converter 23b shown in FIG. 7. FF) 36 may be provided.
The sampling rate converter 23b inserts the previous data when inserting a bit between the data strings S21. Thereby, bits according to the tendency of the data string S21 can be inserted, and the waveform distortion of the demodulated signal S4 caused by the bit insertion can be reduced.
Although FIG. 7 illustrates a configuration that holds only the previous data, the history of the data string S21 may be stored, and the value of the bit to be inserted may be determined based on the history. However, when simplification of the circuit configuration is required, it is desirable to determine the value of the bit to be inserted based only on the previous data as shown in FIG.
In the above description, the case where the output cycle of the sampling rate converter 23 is converted into the cycle of the timing indicated by the clock signal S22 by inserting bits when the data string S21 from the FIFO buffer 31 is insufficient has been described. Instead of inserting a bit, the output terminal T23 of the sampling rate converter 23 may be kept at high impedance.
For example, in the sampling rate converter 23c shown in FIG. 8, the random number generator 32 shown in FIG. 3 is deleted, and the input that is not connected to the FIFO buffer 31 among the two input terminals of the switch 33 in FIG. The terminal is open. As a result, when the switch 33 does not select the FIFO buffer 31, that is, when the data string S21 from the FIFO buffer 31 is insufficient, the output terminal T23 of the sampling rate converter 23c is kept at high impedance.
As described above, when the output terminal T23 of the sampling rate converter 23c is kept at high impedance, the LPF 24 can hold the integrated value up to one cycle before, so that the demodulated signal S4 resulting from the operation of the data string S21. Waveform distortion can be reduced.
Each of the sampling rate converters 23 to 23c shown here has a function of automatically outputting a signal corresponding to silence when the input signal S21 is interrupted. Therefore, even if the packet arrival from the network 2 is stopped for some reason, no unpleasant noise is output from the receiving device 4.
In the sampling rate converters 23 to 23c described above, the switch 33 is switched depending on whether or not the control circuit 34 has successfully read data from the FIFO buffer 31, but the present invention is not limited to this configuration. . That is, instead of the success or failure of the reading, the switch 33 may be switched depending on whether or not a predetermined first threshold value is exceeded. Note that the determination based on the success or failure of the reading is when the first threshold value is empty. Further, instead of deleting the bit of the data string S21 when the FIFO buffer 31 is full, the bit of the data string S21 may be deleted when the second threshold value is exceeded. In any case, when the first threshold value and the second threshold value (including fullness) are fixed values, the sampling rate converters 23 to 23c receive the sampling frequency F1 in the transmission device 3 and the reception. In the device 4, the data string S21 is periodically operated at a time interval corresponding to the ratio to the frequency F2 of the timing indicated by the clock signal S22. Therefore, the output cycle of the sampling rate converters 23 to 23c can be matched with the timing cycle indicated by the clock signal S22.
In the above description, the case where the control circuit 34 of the sampling rate converter 23 (23a to 23c) determines the cycle for operating the data string S21 based on the amount of the data string S21 accumulated in the FIFO buffer 31 has been described. However, the conversion rate of the sampling rate may be determined with reference to information transmitted in advance from the transmission device 3.
Specifically, in the transmission device 3 according to this modification, as indicated by a broken line in FIG. 1, the clock signal generation circuit 13 instructs the transmitter 12 prior to transmission of the digital signal S3, for example, the clock Information indicating the sampling frequency of the delta-sigma modulation circuit 11 such as the frequency of the signal S13 is transmitted to the receiving device 4.
On the other hand, in the receiving device 4, when the receiver 21 receives the information from the network 2, the information is transmitted to the sampling rate converter 23 (23a to 23c) as indicated by a broken line in the figure. Here, in this modification, the sampling rate converter 23 (23a to 23c) receives information indicating the frequency of the clock signal S22 from the clock signal generation circuit 22, as indicated by a broken line in the figure. Therefore, the control circuit 34 of the sampling rate converter 23 (23a to 23c) can determine the ratio between the sampling period in the transmission device 3 and the output period of the sampling rate converter 23 (23a to 23c) by comparing the two. . Thereby, the control circuit 34 can determine the cycle for operating the data string S21 and whether or not to delete the bit.
Hereinafter, another notification method will be described with reference to FIG. That is, in the communication system 1d according to this modification, the network 2d between the transmission device 3d and the reception device 4d includes a clock signal source 5 for generating a clock signal S5 indicating one unit time of the network. . Further, the transmitting device 3d transmits the digital signal S3 to the network 2d in synchronization with the clock signal S5 from the clock signal source 5, and the receiving device 4d is synchronized with the clock signal S5 from the clock signal source 5. The digital signal S3 is received from the network 2d.
Further, in the transmission device 3d according to this modification, a transceiver 12d is provided in place of the transmitter 12 in order to receive data from the network 2d. Further, the transmission device 3d includes a counter 14d that measures one unit time of the network with the clock signal S13 based on the clock signal S5 received from the network 2d by the transceiver 12d and the clock signal S13 of the clock signal generation circuit 13. ing. The counter 14d can instruct the transceiver 12d to transmit the measurement result to the receiving device 4d.
On the other hand, the receiving device 4d according to the present modification is also provided with a counter 25d. The counter 25d can measure one unit time of the network with the clock signal S22 based on the clock signal S5 received by the receiver 21 from the network 2d and the clock signal S22 of the clock signal generation circuit 22. Further, the control circuit 34 of the sampling rate converter 23 (23a-23c) converts the sampling rate conversion ratio based on the measurement result notified from the transmission device 3d via the network 2d and the measurement result by the counter 25d. Can be determined, and the cycle of operating the data string S21 and whether or not the bits should be deleted can be determined.
Furthermore, the control circuit 34 determines the operation timing of the data string S21 based on the notification from the transmission device 3 (3d), or the data string S21 stored in the FIFO buffer 31 shown in FIGS. 3 and 6 to 8. Regardless of whether or not it is determined based on the amount of data, the control circuit 34 changes the data string S21 by, for example, changing the first and second threshold values or changing the conversion ratio itself. You may control the period to operate. Specifically, the control circuit 34e according to the present modification controls so that the period fluctuates and the average value of each period becomes a value that makes the sampling frequency F1 coincide with the frequency F2. When the control circuit 34e is included, fluctuations are provided in the cycle in which the sampling rate converters 23 to 23c operate the data string S21. Therefore, it is possible to prevent the occurrence of a problem that a periodic distortion occurs in the demodulated signal S4 by a periodic operation.
In the present embodiment, a case where a packet is directly transmitted from the transmission apparatus 3 to the reception apparatus 4 is shown, but the present invention is not limited to this.
That is, as shown in FIG. 10, the present invention can also be applied to a configuration in which a network 2a and a network 2b are connected by a bus bridge 8. At this time, the network 2a and the network 2b may be the same type of network or different types of networks. For example, a configuration in which both are IEEE 1394 or a configuration in which one is IEEE 1394 and the other is Ethernet is possible. Furthermore, a wired network and a wireless network may be mixed.
Further, as shown in FIG. 11, a packet editing device 9 that performs voice processing such as echo addition and treble / bass emphasis and editing of time information and copyright information is transmitted from the transmission device 3 to the packet. You may provide between the apparatus 3 and the receiver 4.
Thus, even when the configuration of FIG. 10 or FIG. 11 is adopted, the deviation between the clock signal S13 generated by the clock signal generation circuit 13 and the clock signal S22 generated by the clock signal generation circuit 22 is different from the receiving device. 4 sampling rate converter 23 can absorb.
[Second Embodiment]
In the present embodiment, a receiver 4f that amplifies power during demodulation will be described with reference to FIG. That is, the receiving device 4f according to the present embodiment includes a digital switching amplifier 26 instead of the LPF 24 shown in FIG.
The digital switching amplifier 26 includes a level adjustment circuit 41 that adjusts the peak value of the delta-sigma modulation signal S23 output from the sampling rate converter 23 (23a to 23c), and a delta that uses the output signal of the level adjustment circuit 41 as an input signal. A sigma modulation circuit 42, a power amplification circuit 43 that amplifies the output signal S42 of the delta sigma modulation circuit 42, and an LPF 44 connected to the output of the power amplification circuit 43 are provided. Further, the output signal of the power amplifier circuit 43 is fed back to the delta sigma modulation circuit 42. Further, in the present embodiment, the clock signal S22 from the clock signal generation circuit 22 is input to the delta-sigma modulation circuit 42.
The delta sigma modulation circuit 42 performs first-order or higher-order integration of the difference between the input signal Si and the feedback signal Sf in substantially the same manner as the delta sigma modulation circuit 11 of the transmission device 3, and the integration result is the clock signal S22. Is quantized with the sampling period indicated by. On the other hand, the power amplifier circuit 43 is realized by, for example, a switching element that switches a power supply voltage applied from a power supply circuit (not shown) based on the quantization result based on the quantization result.
As a result, the pulse signal S42 indicating the quantization result is output with the power amplified so that the peak value becomes the power supply voltage level. The high-frequency component is removed from the power-amplified pulse signal S43 by the LPF 44 and output to an unillustrated speaker or the like as an analog demodulated signal S4.
Here, in the digital switching amplifier 26, the output signal S 43 of the power amplifier circuit 43 is fed back to the delta sigma modulation circuit 42. Therefore, for example, even if the peak value of the pulse signal S43 fluctuates due to fluctuations in the level of the power supply voltage and the signal level of the demodulated signal S4 tends to fluctuate, the delta-sigma modulation circuit 42 It controls its own output signal S42 so as to cancel the fluctuation. Thus, the digital switching amplifier 26 can amplify the input signal S23 with higher accuracy than when the output signal S42 of the delta-sigma modulation circuit 42 is fed back.
In the receiving device 4f configured as described above, the delta-sigma modulation circuit 42 operates based on the clock signal S22, similarly to the sampling rate converter 23 (23a to 23c), and the sampling rate converter 23 (23a to 23c). Adjusts its own output cycle (output cycle of the level adjustment circuit 41) so as to coincide with the sampling cycle of the delta-sigma modulation circuit. Therefore, the waveform distortion of the demodulated signal S4 due to the mismatch between the two does not occur, and the receiving device 4f can output the high-quality demodulated signal S4.
In the above description, the case where the power amplification factor of the digital switching amplifier 26 is fixed has been described as an example. For example, the attenuation factor when the output signal S43 of the power amplification circuit 43 is fed back to the delta-sigma modulation circuit 42 is controlled. Alternatively, the power amplification factor of the digital switching amplifier 26 may be changed by controlling the attenuation / amplification factor in the level adjustment circuit 41.
The transmitter 3 not only transmits a digital signal S3 indicating the delta-sigma modulated signal S11 using the network 2, but also transmits a control signal such as a signal input from a control button (not shown) by the transmitter 12. You may be comprised so that the receiving device 4f can be controlled by transmitting. Examples of the control signal include a signal for instructing power on / off, volume control by controlling the level adjustment circuit 41, and the like. The control signal transmission method may include a method of including control signal information in a part of the packet of the digital signal S3, or a method of transmitting a packet other than the packet of the digital signal S3 via the network 2. But you can. The trigger for transmitting the control signal is not limited to the instruction from the control button described above. For example, when a predetermined condition is satisfied such as transmission when the input signal Si exceeds a certain level. The transmission device 3 may transmit spontaneously.
[Third Embodiment]
In the present embodiment, a transmission / reception device 6 used instead of the transmission device 3 (3d) and the reception device 4 (4d · 4f) shown in FIG. 1, FIG. 9, or FIG. 12 will be described with reference to FIG. In the following, as an example, a case where the transmission device 3 and the reception device 4 illustrated in FIG. 12 are used instead will be described.
The transmitter / receiver 6 includes a transmitter 12 of the transmitter 3 shown in FIG. 12 in addition to the configuration of the receiver 4f shown in FIG. The transmitter 12 is connected to the delta sigma modulation circuit 42 instead of the delta sigma modulation circuit 11 of the transmission apparatus 3, and can transmit the delta sigma modulation signal S 42 output from the delta sigma modulation circuit 42 through the network 2. Can be converted into a digital signal S3 of a proper format and sent to the network 2.
Further, the transceiver 6 selects one of an input terminal Ti to which an input signal from a signal source (not shown) and an output terminal of the sampling rate converter 23 (23a to 23c) are selected to adjust the level. The switch 27 that outputs to the circuit 41, the switch 28 that selects one of the output signal S42 of the delta sigma modulation circuit 42 and the output signal S43 of the power amplification circuit 43 and feeds back to the delta sigma modulation circuit 42, and the transmission / reception device 6 A control circuit 29 is provided for controlling the switching of the switches 27 and 28 depending on whether the digital signal S3 is output or the demodulated signal S4 is output.
When the transmission / reception device 6 outputs the digital signal S3 to the network 2, the control circuit 29 causes the switch 27 to select the input terminal Ti side and causes the switch 28 to select the output signal S42 of the delta-sigma modulation circuit 42. In this state, similar to the delta sigma modulation circuit 11, the output signal S42 is fed back to the delta sigma modulation circuit. Therefore, like the delta sigma modulation circuit 11, the delta sigma modulation circuit 42 can output a signal S42 obtained by delta sigma modulating a signal input from a signal source (not shown) to the delta sigma modulation circuit 42. As a result, the transmission / reception device 6 can output the digital signal S3 corresponding to the delta-sigma modulation signal S42 to the network 2, similarly to the transmission device 3 (3d) shown in FIG. 1, FIG. 9, or FIG.
On the other hand, when the transmission / reception device 6 outputs the demodulated signal S4 based on the digital signal S3 received from the network 2, the control circuit 29 switches to select the output terminal side of the sampling rate converter 23 (23a-23c). 27, and instructs the switch 28 to feed back the output signal S43 of the power amplifier circuit 43. In this state, the members 41 to 44 shown in FIG. 13 are connected in the same manner as the digital switching amplifier 26 shown in FIG. Therefore, similarly to the digital switching amplifier 26, the demodulated signal S4 obtained by amplifying and demodulating the output signal of the sampling rate converter 23 (23a to 23c) can be output.
In the above configuration, the same delta-sigma modulation circuit 42 is used both when the digital signal S3 is output (when transmitted) and when the demodulated signal S4 is output (when received). Therefore, the circuit configuration of the transmitting / receiving device 6 capable of transmitting and receiving can be simplified as compared with the case where both are provided separately or when the amplifier circuit is provided for generating the demodulated signal S4 separately from the transmission.
In particular, when generating a high-quality delta-sigma modulation signal S42 or reducing waveform distortion during amplification / demodulation, the circuit scale of the delta-sigma modulation circuit for transmission and the amplification circuit for amplification / demodulation is complicated. It tends to be. However, in the above configuration, since the same delta-sigma modulation circuit 42 is used for both transmission and demodulation / amplification, the circuit scale can be reduced by setting the delta-sigma modulation circuit 42 with sufficiently high accuracy. The accuracy of both transmission and demodulation / amplification can be improved without much increase.
Further, since transmission and reception (demodulation amplification) can be switched only by switching both the switches 27 and 28, the transmission / reception apparatus 6 that can easily switch between transmission and reception can be realized.
By the way, the control circuit 29 determines whether or not the transmission / reception device 6 is connected to the network 2. If the transmission / reception device 6 is not connected, the control circuit 29 causes the switch 27 to select the input terminal Ti side and causes the switch 28 to select the power amplification circuit 43. May be selected. In this case, for example, when it is not connected to the network 2, it operates as a headphone amplifier, and when it is connected to the network 2, it can be used as a stand-alone amplifier like a portable audio device that operates as the transmission device 3. An operable transceiver 6 can be realized.
The connection to the network 2 is, for example, an output from a contact for detecting whether or not a plug is connected, or a carrier signal detection circuit or a bias voltage detection circuit used inside the receiver 21. It can be detected based on the output.
[Fourth Embodiment]
By the way, in each said embodiment, the case where the digital signal S3 which shows the input signal Si input in real time was transmitted as a suitable example was demonstrated. On the other hand, in the present embodiment, as another suitable example, a configuration in which the transmission device generates the input signal Si by reading and decoding the encoded digital data from the network-connected storage, This will be described with reference to FIG. Note that the configuration for generating the input signal Si can be applied to any of the first to third embodiments described above. Hereinafter, a case where the configuration is applied to the configuration of the first embodiment will be described as an example.
That is, the storage 7 provided in the communication system 1g according to the present embodiment stores encoded digital data such as MP3 (Moving Picture Expert Group-1 Audio Layer 3) and ATRAC (Adaptive Transform Acoustic Coding). And a transmitter 52 that transmits the digital data S7 to the transmission device 3g via the network 2.
On the other hand, the transmission device 3g according to the present embodiment is substantially the same as the transmission device 3 shown in FIG. 1, but a transceiver 12d similar to that in FIG. Further, the transmission device 3g according to the present embodiment decodes the digital data S7 received from the storage 7 and also provides a decoding unit (decoding means) 15 for giving the decoded signal as an input signal Si to the delta-sigma modulation circuit 11. Is provided. The decoding unit 15 is configured to be able to decode digital data S7 encoded by any one of a plurality of predetermined methods such as MP3 and ATRAC described above.
In the present embodiment, the transmission device 3g is realized by, for example, a personal computer on which an expansion board including the delta sigma modulation circuit 11, the transmitter 12, and the clock signal generation circuit 13 illustrated in FIG. The decoding unit 15 is realized as a functional block that is realized when the computer executes a program.
Also, the decoding unit 15 sets the sampling frequency of the delta-sigma modulation circuit 11 by setting the oscillation frequency of the clock signal generation circuit 13 according to the format of the encoded digital data S7. Transmission rate arbitrating means) 16 is also provided.
When the reduction of the transmission band of the network 2 is required, it is desirable to set the sampling frequency as low as possible within a range that does not hinder the deterioration of the input signal Si. Further, from the viewpoint of copyright protection, it is desirable that the data amount of the delta-sigma modulation signal S11 generated at the sampling frequency is set sufficiently larger than the data amount of the encoded digital data S7.
The set value is limited to several types in advance. For example, in the transmission speed arbitration unit 16 according to the present embodiment, 24.1 of 44.1 [kHz] which is the sampling frequency of the CD. ⁿ The double frequency is set as the sampling frequency of the delta-sigma modulation circuit 11. Note that n is a natural number. As described above, since the set values are limited to several types, the clock provided in the transmission device 3g or the reception device 4 is not complicated as compared with the case where the setting values can be arbitrarily set. The signal generation circuits 13 and 22 can generate the clock signals S13 and S22 with sufficient accuracy.
Further, the transmission rate arbitration unit 16 can instruct the transceiver 12d to transmit data indicating the sampling frequency (for example, n) to the receiving device 4 via the network 2. On the other hand, the receiving device 4 can determine the output period of the sampling rate converter 23 (23a to 23c) by adjusting the oscillation frequency of the clock signal generation circuit 22 based on the data.
According to the above configuration, after the transmission device 3g decodes the digital data S7 from the storage 7, based on the decoded signal, the delta sigma modulation signal S11 is generated, and the digital signal S3 indicating the delta sigma modulation signal S11 is generated. Is transmitted to the receiving device 4. Therefore, the receiving device 4 only needs to be able to receive and demodulate the digital signal S3 indicating the delta-sigma modulated signal S11 regardless of the encoding method of the digital data S7 sent from the storage 7.
As described above, since the decoding functions are concentrated in the transmission device 3g, the encoding is performed by one of many encoding methods as compared with the configuration in which the plurality of receiving devices 4 include the decoding unit 15 corresponding to all the encoding methods. The communication system 1g that can reproduce the digital data S7 by each receiving device 4 can be easily realized. Therefore, for example, the present invention can be used particularly preferably in a system in which many receiving devices 3g are indispensable, such as a system that requires a large number of speakers to construct a realistic sound field space such as a 5.1 channel system.
In the above configuration, since the decoding function is concentrated in the transmission device 3g, the reception device 4 that generates the final analog output does not require a complicated decoding circuit. Accordingly, it is possible to avoid the problem that high-frequency noise caused by the decoding circuit affects the analog output.
Furthermore, since the delta-sigma modulation signal S11 can be regarded as a random number locally, it is difficult to compress. Therefore, the encoded digital data S7 is decoded and then modulated to the delta sigma modulation signal S11, and the digital signal S3 indicating the delta sigma modulation signal S11 is transmitted, and the data amount of the delta sigma modulation signal S11 is equal to the digital value. By setting the setting value of the transmission rate arbitration unit 16 so as to be larger than the data amount of the data S7, it becomes difficult to perform illegal copying in which packets on the network 2 are recorded and copied as they are. Can prevent to some extent.
In the above description, the case where the transmission rate arbitration unit 16 determines the setting value based on the format of the digital data S7 has been described. For example, information on a management node connected to the network 2 (for example, IEEE 1394). , Or a bus manager), or may be determined with reference to the capability of the receiving device 4 (which value can be set).
In the above description, the case where the delta-sigma modulation circuit 11 is realized by hardware has been described as an example. However, part or all of the delta-sigma modulation circuit 11 may be realized by software. Furthermore, in the above description, the case where the decoding unit 15 is realized by software has been described as an example. However, part or all of the decoding unit 15 may be realized by hardware that performs the same operation. However, in any case, the decoding unit 15 should be extensible so that the types of digital data S7 that can be decoded by the decoding unit 15 can be increased by adding software or hardware. Is desirable.
[Fifth Embodiment]
As shown in FIG. 15, the communication system 1 h according to the present embodiment is similar to the communication system 1 f shown in FIG. 12, but instead of the network 2, a network having the clock signal source 5 as in FIG. 9. 2d is provided.
Further, in the transmission device 3h according to the present embodiment, a transceiver 12d is provided instead of the transmitter 12, as in FIG. Further, the transmission device 3h includes a PLL circuit 13h that generates a clock signal S13h synchronized with the clock signal S5 received by the transceiver 12d, instead of the clock signal generation circuit 13.
On the other hand, the receiving device 4h according to the present embodiment is provided with a PLL circuit 22h that generates a clock signal S22h synchronized with the clock signal S5 received by the receiver 21, instead of the clock signal generating circuit 22. Accordingly, the sampling rate converter 23 (23a to 23d) is deleted, and the receiver 21 sequentially generates a data sequence S21 indicating each pulse of the delta sigma modulation signal S11, and the period indicated by the clock signal S22h. Thus, each bit of the data string S21 is sequentially generated.
Even with the above configuration, if the accuracy of the clock signal source 5 is sufficient to demodulate the delta sigma modulation signal S11, the receiving device 4h can be used without any problem based on the digital signal S3 indicating the delta sigma modulation signal S11. Thus, the delta sigma modulation signal S11 can be demodulated.
For example, in IEEE 1394, information for time adjustment is transmitted at a relatively short period of 125 [μs]. Therefore, based on the information, the PLL circuits 13h and 22h generate clock signals S13h and S22h of 11.2896 [MHz], respectively, so that the receiving device 4h generates the digital signal S3 generated by the transmitting device 3h. And can be demodulated with sufficient quality as HiFi audio.
As described above, in the receiving device 4h configured as described above, the digital signal S3 indicating the delta-sigma modulated signal S11 is transmitted in the network 2d for packet communication, that is, each pulse of the delta-sigma modulated signal S11 is transmitted at the same time interval. Not limited to this, the digital signal S3 can be demodulated without any problem even though other data may be transmitted via the network 2d. Therefore, the receiving device 4h that can output the demodulated signal S4 with less waveform distortion can be realized with a simple circuit as compared with the case of transmitting a digital signal indicating a multi-bit signal.
Further, when the accuracy of the network 2 is sufficient, for example, as in the communication system 1i illustrated in FIG. 16, a signal referred to by the PLL circuit 22h of the reception device 4h may be transmitted from the transmission device 3i to the reception device 4h. Good.
Specifically, the communication system 1i according to the present modification includes the network 2 shown in FIG. 1, the reception device 4h shown in FIG. 15, and the transmission device 3i. The transmission device 3i has substantially the same configuration as the transmission device 3 shown in FIG. 1, but the clock signal generation circuit 13 instructs the transceiver 12 to transmit a digital signal synchronized with the clock signal S13 to the reception device 4h. The point is different.
On the other hand, the PLL circuit 22h of the receiving device 4h generates the clock signal S22h based on the digital signal instead of the clock signal S5 from the network 2d. As a result, if the time accuracy when the network 2 transmits the digital signal synchronized with the clock signal S13 is sufficient to demodulate the delta-sigma modulation signal S11, the receiving device 4h can perform the delta-sigma modulation without any problem. Based on the digital signal S3 indicating the signal S11, the delta-sigma modulated signal S11 can be demodulated.
As still another modification, a signal referred to by the PLL circuit 13h of the transmission device 3h may be transmitted from the reception device 4j to the transmission device 3h as in the communication system 1j illustrated in FIG.
Specifically, the communication system 1j according to the present modification includes the transmission device 3h, the network 2, and the reception device 4j shown in FIG. The receiving device 4j is substantially the same as the receiving device 4h shown in FIG. 15, but includes a clock signal generation circuit 22 similar to that in FIG. 1 instead of the PLL circuit 22h. The receiving device 4j is provided with a transceiver 22j capable of transmitting and receiving data to and from the network 2 instead of the receiver 21. In addition to receiving the digital signal S3, the receiving device 4j transmits a digital signal synchronized with the clock signal S22. Can be sent to 3h.
On the other hand, the PLL circuit 13h of the transmission device 3h generates the clock signal S13h based on the digital signal instead of the clock signal S5 from the network 2d. Thus, if the time accuracy when the network 2 transmits a digital signal synchronized with the clock signal S22 is sufficient to demodulate the delta-sigma modulation signal S11, the transmission device 3h performs the sampling required by the reception device 4j. A frequency delta-sigma modulated signal S11 can be generated. On the other hand, the receiving device 4j can generate a high-quality demodulated signal S4 based on the digital signal S3 indicating the delta-sigma modulated signal S11. However, in the communication system 1j according to the present modification, the sampling period of the transmission device 3h is adjusted by a signal from the reception device 4h. Therefore, as the transmission apparatus 3h according to the present modification, for example, as in the configuration of the fourth embodiment, for example, a CD− is used rather than the configuration of modulating a generated signal input in real time from a signal source (not shown). It is more suitable to modulate a signal stored in a medium such as a ROM or a semiconductor storage medium.
15 to FIG. 17, as in FIG. 12, the case where the transmission devices 3... And the reception devices 4... Are different from each other and the reception device 4 includes the digital switching amplifier 26 is described as an example. However, it is not limited to this. For example, the LPF 24 may be provided instead of the digital switching amplifier 26 as in the communication system 1 shown in FIG. Similarly to FIG. 13, the transmission / reception device 6 may be realized by adding the switches 27 and 28, the control circuit 29, and the transmitter 12 to the configuration of each reception device 4. In this case, the delta sigma modulation circuit for transmission and the delta sigma modulation circuit for amplification can be shared.
As described above, in the communication systems 1h to 1j according to the present embodiment, if the network 2 (2d) can transmit a clock signal or a signal synchronized therewith with sufficient accuracy, it is substantially the same as the first to fourth embodiments. Similar effects can be obtained.
However, as in the case where the network 2 is a wireless communication network or the Internet, a signal having a sufficiently stable cycle (for example, a signal having a period of 125 [μs] in the case of IEEE 1394, etc.) between the transmission devices 3. ) Cannot be transmitted / received, it is preferable that the receivers 4... Have the clock signal generation circuit 22 as in the first to fourth embodiments.
As described above, the receiving apparatus according to the present invention receives a digital signal generated by dividing a pulse number modulation signal in which the number of pulses per unit time varies according to the signal waveform from the network, and receives the digital signal. Receiving means for extracting a bit string indicating a pulse number modulation signal from the signal, and pulse number modulation signal output means for outputting a pulse corresponding to each bit of the bit string in a predetermined cycle.
When the receiving apparatus of the present invention includes an amplifier that amplifies and demodulates the output signal of the pulse number modulation signal output means, the amplifier may be an analog amplifier. However, when demodulation of a signal with reduced power consumption and less waveform distortion is required, the amplifier includes a delta-sigma modulation unit that delta-sigma-modulates an input signal, and a pulse train output by the delta-sigma modulation unit. A digital switching amplifier having a power amplifying means for amplifying power and a demodulating means for demodulating the output of the power amplifying means is desirable.
According to this configuration, the output signal of the pulse number modulation signal output means is delta-sigma modulated by the delta-sigma modulation means. Further, the output of the delta sigma modulation means is power amplified by the power amplification means and then demodulated by the demodulation means. The delta sigma modulation means integrates the difference between the input signal and the feedback signal according to the output of the amplifier and quantizes the integration result to perform delta sigma modulation. There is no need to provide a low-pass filter separate from the demodulating means.
Here, since the power amplifying means only needs to amplify the power of the pulse train, the power amplifying means can be constituted by a switching element that takes either a conduction state or a cutoff state. Therefore, after demodulating the output signal of the pulse number modulation signal output means with a low-pass filter, the demodulated signal with less power consumption and less waveform distortion is compared with the case of amplifying with an analog amplifier composed of transistors operating in the active region. Can be generated.
Further, in addition to the above configuration, the pulse number modulation signal output from the delta sigma modulation means is packet-divided to generate a digital signal, and the digital signal is transmitted to the network. In the reception mode for demodulating the signal, the output signal of the pulse number modulation signal output means is input to the input terminal of the delta sigma modulation means, and in the transmission mode for transmitting a digital signal, it is input from the signal source of the signal to be transmitted. Input switching means for inputting the received signal to the input terminal may be provided.
In the above configuration, in the transmission mode, the input switching unit inputs the signal input from the signal source to the delta sigma modulation unit of the digital switching amplifier, and the pulse number modulation signal output from the delta sigma modulation unit is transmitted. The packet is divided by the means and transmitted to the network. Thereby, the receiving apparatus can operate as a transmitting / receiving apparatus.
Here, in the above configuration, the delta sigma modulation means for amplifying and demodulating at the time of reception is also used for generating a pulse number modulation signal by performing delta sigma modulation at the time of transmission. Therefore, the configuration of a receiving device (transmitting / receiving device) capable of transmitting a digital signal indicating a pulse number modulation signal can be simplified as compared with the case where delta-sigma modulation means is provided for each application.
Here, even in the reception mode, the output signal of the delta sigma modulation means may be fed back to the delta sigma modulation means. However, when improvement in accuracy when the digital switching amplifier amplifies is required, the following configuration is provided. It is desirable to be.
That is, in addition to the above configuration, in the reception mode, the output signal of the power amplifying means is fed back to the delta sigma modulation means, and in the transmission mode, the feedback path switching is fed back to the output signal of the delta sigma modulation means. It is desirable to have a means.
According to this configuration, in the reception mode, the output signal of the power amplification unit is fed back to the delta sigma modulation unit. Therefore, even if the output signal of the power amplification means changes undesirably due to power supply voltage level fluctuations, the delta sigma modulation means can output a pulse train that cancels the waveform distortion of the demodulated signal caused by the change. As a result, in the reception mode, the demodulation means can output a demodulated signal with higher quality.
In addition to the above configuration, when the receiving apparatus is not connected to the network, the input switching unit selects the signal input from the signal source, and the feedback path switching unit causes the power amplification. The output signal of the means may be selected.
According to this configuration, when not connected to the network, it is possible to operate as an amplifier that amplifies the above-described signal source by switching the both switching means. As a result, it is possible to realize a receiving apparatus that can operate as a simple amplifier only by changing the switching method of both switching means.
By the way, if the network can transmit the clock signal with sufficient accuracy, the pulse number modulation signal output means of the reception device transmits a clock signal indicating the period of outputting each pulse of the pulse number modulation signal from the transmission device to the reception device. May be. In addition, when a sufficiently accurate clock signal source is provided in the network, the transmission device and the reception device may operate based on the clock signal from the clock signal source. Alternatively, when the network can transmit the clock signal with sufficient accuracy and the signal source stored above is reproduced, the clock signal on the reception side may be transmitted to the transmission side.
However, when the network transmits a digital signal, even if the accuracy in the time direction is sufficient for data transmission, the receiving device transmits a clock signal indicating the period of outputting each pulse of the pulse number modulation signal. For that, it is often not enough. In particular, when there is a possibility that communication may be interrupted, such as wireless communication, or when data is transmitted via many nodes, such as the Internet, all the paths from the transmission device to the reception device, It is difficult to build a network with sufficient accuracy. On the other hand, if the stability of the clock signal is reduced, the waveform may be distorted.
Therefore, when there is a possibility of receiving a digital signal from a network having a node whose accuracy in the time direction is not sufficient in any of the paths from the transmission device to the reception device, or in the reception device, there is less waveform distortion When output of a pulse number modulation signal is required, it is desirable to have the following configuration.
That is, during transmission of the digital signal indicating the pulse number modulation signal, a reception side clock signal generation means for generating a reception side clock signal indicating the timing of the same frequency as the sampling frequency of the pulse number modulation signal, independently of the network And the pulse number modulation signal output means is a sampling rate conversion means for converting each pulse of the pulse number modulation signal extracted by the reception means into a frequency at a timing indicated by the reception side clock signal and outputting the converted signal. Is preferable.
The reception-side clock signal may be set in advance to a fixed frequency as long as it is generated independently of the network during transmission of the digital signal indicating the pulse number modulation signal. Before transmission, the frequency may be set according to an instruction transmitted from the transmission device to the reception device via the network.
In the above configuration, during the transmission of the digital signal indicating the pulse number modulation signal, the reception-side clock signal generation means of the reception device generates the reception-side clock signal independently of the network. Therefore, unlike the case where the receiving side clock signal is generated by the PLL circuit based on the signal transmitted through the network, the receiving side clock signal fluctuates during transmission of the digital signal indicating the pulse number modulation signal, and the pulse Problems such as changes in the frequency and reproduction time of the signal obtained by demodulating the number modulation signal do not occur. Therefore, the sampling rate conversion means can output a pulse number modulation signal capable of demodulating a signal with less waveform distortion as compared with the case where the receiving side clock signal fluctuates.
Here, since the receiving side clock signal generating means generates the receiving side clock signal independently of the network, the frequency of the timing indicated by the receiving side clock signal is the sampling frequency of the pulse number modulation signal transmitted through the network. For example, the sampling frequency of the pulse number modulation signal transmitted through the network and the timing indicated by the receiving side clock signal may be set, for example, due to the influence of the ambient temperature or individual differences in the receiving device. It is difficult to perfectly match the frequency of
However, in the above configuration, the sampling rate conversion means converts each pulse of the pulse number modulation signal transmitted via the network into a frequency of the timing indicated by the reception side clock signal and outputs it. Therefore, the sampling rate conversion means needs to transmit an instruction for flow control to the transmission side even when the sampling frequency and the frequency of the timing indicated by the reception side clock signal do not completely match. There is no. As a result, even when the transmission device transmits a pulse number modulation signal having the same contents to a plurality of reception devices via a network, or even when the transmission device transmits a pulse number modulation signal modulated in real time. The receiving apparatus can output a pulse number modulation signal capable of demodulating a high-quality signal, that is, a pulse number modulation signal capable of demodulating a signal that does not cause waveform distortion due to a period variation of the clock signal.
Here, unlike the case of transmitting a digital signal having a value indicating the level of the demodulated signal (multi-bit digital signal), a pulse number modulation signal is transmitted to the network, and the pulse number modulation signal is integrated. Demodulated by Therefore, unlike the case of multi-bit, for example, when the sampling frequency of the pulse number modulation signal transmitted through the network is higher than the frequency of the timing indicated by the receiving side clock signal, the sampling rate conversion means deletes the bit. Even if the sampling rate is converted by a conversion operation that can be performed with a relatively simple circuit, such as an operation, or if the sampling rate conversion means inserts a bit or keeps the output at a high impedance when the operation is low, conversion is possible. The error accompanying this is unlikely to appear in the demodulated signal.
As a result, even if the sampling rate conversion means is configured with a simple circuit as compared with the case of transmitting a multi-bit digital signal, the receiving apparatus can output a pulse number modulation signal capable of demodulating the high-quality signal. .
As a result, when the transmitter transmits a pulse number modulation signal having the same content to a plurality of receivers via a network with a simple circuit configuration, or the pulse number modulation modulated in real time by the transmitter Even when a signal is transmitted, a receiving apparatus capable of generating a pulse number modulation signal capable of demodulating the high-quality signal can be realized.
In addition to the above configuration, the sampling rate conversion means may receive the received pulse number modulation signal when the frequency of the timing indicated by the receiving clock signal is lower than the sampling frequency of the pulse number modulation signal transmitted through the network. A pulse may be inserted between the pulse trains, and the frequency of the output signal may be set to the timing frequency indicated by the reception side clock signal. Note that the value of the pulse to be inserted may be determined at random, or may be controlled to be 0 and 1 alternately. Alternatively, a predetermined number of pulse train histories of the pulse number modulation signal may be stored and determined based on the history.
According to this configuration, the sampling rate conversion means can reliably output an output signal having the frequency indicated by the reception-side clock signal. In addition, since the output signal is a pulse number modulated digital signal, for example, it is transmitted to other devices via a network, accumulated in a recording medium for storing digital data, or processed as digital data. Various digital processing becomes possible.
On the other hand, when the output terminal of the sampling rate conversion means is connected to an integrator that integrates a signal input as a potential to the input terminal, the sampling rate conversion means is a pulse number modulation signal transmitted through the network. When the frequency of the timing indicated by the receiving side clock signal is lower than the sampling frequency of the output signal, a period for keeping the output terminal in a high impedance is provided between the pulse trains of the received pulse number modulation signal, and the frequency of the output signal May be set to the frequency of the timing indicated by the receiving side clock signal. The integrator may be the above-described digital switching amplifier or a demodulation low-pass filter.
According to this configuration, since the sampling rate conversion means provides a high impedance period between pulse trains, it is possible to reliably output an output signal having the same frequency as that of the timing indicated by the reception-side clock signal. Also, if the sampling rate conversion means keeps the output terminal at high impedance, the integrator can hold the integrated value up to one cycle before, so that errors in the integration result due to sampling rate conversion can be suppressed. It is possible to suppress the occurrence of waveform distortion due to the error. As a result, a receiving apparatus that can output a signal with less waveform distortion can be realized.
Regardless of whether the sampling rate conversion means inserts a bit between pulse trains or provides a period of high impedance, the sampling rate conversion means periodically operates the pulse train of the received pulse number modulation signal, You may set the frequency of an output signal to the frequency of the timing which the said receiving side clock signal shows.
In this case, since the operation is performed periodically, the output signal of the sampling rate conversion means can be converted with a simple circuit configuration as compared with the case where the operation is not periodic.
Further, instead of periodically operating, the sampling rate converting means, the sampling rate converting means, the period for operating the pulse train of the received pulse number modulation signal varies, and the average value of each period is output. The period may be controlled so that the frequency of the signal becomes a value that matches the frequency of the timing indicated by the receiving side clock signal.
In this case, since the average value of each period is controlled to the above value, the sampling rate conversion means can set the frequency of the output signal to a frequency according to the reception side clock signal without any trouble. Further, since the operation cycle of the pulse train fluctuates, even if waveform distortion occurs in the demodulated signal of the pulse number modulation signal due to the operation of the pulse train, it is difficult to perceive the distortion. As a result, a pulse number modulation signal capable of demodulating a higher quality signal can be output.
On the other hand, in order to solve the above problems, a communication system according to the present invention generates a pulse number modulation signal by performing delta sigma modulation on a signal to be transmitted with any of the reception devices having the above-described configurations. And a transmission device that divides the signal into packets to generate a digital signal and transmits the digital signal to the reception device via the network.
Therefore, as with each of the above receiving devices, a digital signal indicating a pulse number modulation signal is transmitted in a packet communication network, that is, each pulse of the pulse number modulation signal is not always transmitted at the same time interval. In the case where data is also transmitted through a network that may be transmitted, the receiving device reduces waveform distortion during demodulation compared to the case of transmitting a digital signal indicating a multi-bit signal. Thus, it is possible to generate a pulse number modulation signal compatible with a simple circuit configuration without any trouble. As a result, compared with the multi-bit case, the circuit configuration of the receiving device can be simplified, and a communication system capable of demodulating a signal with less waveform distortion can be realized.
Furthermore, when bidirectional transmission of a pulse number modulation signal is desired, in addition to the above-described configuration, the transmitting device and the receiving device are preferably receiving devices having transmitting means among the above-described receiving devices.
In this configuration, the delta sigma modulation means for generating the pulse number modulation signal for transmission and the delta sigma modulation means for amplifying and demodulating at the time of reception are shared, so that both are provided separately. A communication system capable of transmitting a pulse number modulation signal in both directions can be realized with a simple circuit configuration.
The transmitter may transmit a digital signal indicating the pulse number modulation signal to a network including an intermediate node that operates based on a clock signal independent of a sampling clock of the pulse number modulation signal as the network. Good.
In this configuration, since the network includes the intermediate node, when the clock signal is transmitted from the transmission device to the reception device, the clock signal on the reception side is transmitted even during transmission of the digital signal indicating the pulse number modulation signal. The frequency of the signal tends to fluctuate, and the quality of the signal obtained by demodulating the pulse number modulation signal tends to deteriorate.
On the other hand, in the receiving apparatus having the above-described configuration, the frequency of the receiving clock signal does not vary during transmission of the digital signal indicating the pulse number modulation signal, so that quality degradation due to the variation does not occur. As a result, it is particularly suitable when the transmission apparatus transmits a pulse number modulation signal to the network including the intermediate node.
In addition to the above configuration, the transmission device may be provided with a decoding unit that decodes digital data encoded by any of a plurality of encoding methods and generates the signal to be transmitted.
According to this configuration, since a decoding process corresponding to each method is performed in the transmission device, it is not necessary to change the reception device regardless of which method the digital data is encoded. Therefore, each receiving device can demodulate digital data encoded by one of a plurality of encoding methods with a simple structure compared to a configuration in which each receiving device has a member for performing decoding processing corresponding to each method. A possible communication system can be realized.
The digital data may be stored in the transmission device, but the transmission device may acquire the digital data via the network. Even in this case, since the network transmits the packetized digital signal, the encoded digital data can be acquired simultaneously with the pulse number modulated signal.
In addition to the above configuration, transmission rate arbitration means may be provided for selecting a sampling frequency for performing delta-sigma modulation from a plurality of predetermined options. The transmission rate arbitration means may be provided in the network, or may be provided in the transmission device or the reception device. Further, the transmission speed arbitration unit may be realized by the cooperative operation of the transmission apparatus member and the reception apparatus member.
In this configuration, the sampling frequency can be changed and set to a value according to the signal to be transmitted. Furthermore, since the sampling frequency is one of a plurality of predetermined options, a signal for determining the sampling timing is generated in the transmission device such as a PLL circuit or a clock signal generation circuit as compared with a configuration that can be arbitrarily set. In the receiving member and the receiving apparatus, the configuration of the member that generates a signal for determining the output timing of the pulse number modulation signal output means can be simplified without reducing the accuracy of each signal.
Further, in addition to the above configuration, the transmission device includes transmission rate arbitration means for selecting a sampling frequency for delta-sigma modulation from a plurality of predetermined options, and the transmission rate arbitration unit is encoded with the encoded The sampling frequency may be determined such that the data amount of the pulse number modulation signal per unit time is larger than the data amount per unit time of digital data.
Here, the pulse number modulation signal generated by the delta-sigma modulation can be regarded as a random number locally, and thus is difficult to compress easily. Therefore, as described above, by determining the sampling frequency, it becomes difficult to record and copy packets on the network as they are, and illegal copying can be prevented to some extent.
On the other hand, the sampling rate conversion means according to the present invention provides the pulse number modulation extracted from the digital signal generated by dividing the pulse number modulation signal in which the number of pulses per unit time varies according to the signal waveform. In this configuration, a pulse corresponding to each bit of a bit string indicating a signal is output at a predetermined cycle.
In the above configuration, each pulse of the extracted pulse number modulation signal is transmitted at the same frequency as the sampling frequency of the pulse number modulation signal independently of the network during transmission of the digital signal indicating the pulse number modulation signal. It is desirable to convert and output the frequency of the timing indicated by the reception side clock signal generated as the signal indicating the timing.
Further, in the above configuration, when the frequency of the timing indicated by the receiving clock signal is lower than the sampling frequency of the input pulse number modulation signal, a pulse is inserted between the pulse trains of the input pulse number modulation signal. Thus, it is preferable to set the frequency of the output signal to the frequency of the timing indicated by the receiving side clock signal.
Further, in the above configuration, it is desirable that the value of the pulse to be inserted is controlled to be 0 and 1 alternately.
In the above configuration, when the frequency of the timing indicated by the receiving clock signal is higher than the sampling frequency of the input pulse number modulation signal, the pulse is deleted from the pulse train of the input pulse number modulation signal, You may comprise so that the frequency of an output signal may be set to the frequency of the timing which the said receiving side clock signal shows.
Alternatively, in the above configuration, the output terminal is connected to an integrator that integrates a signal input as a potential to the input terminal, and the reception-side clock signal indicates the sampling frequency of the input pulse number modulation signal. When the timing frequency is lower, a period for maintaining the output terminal in a high impedance is provided between the pulse trains of the input pulse number modulation signal, and the frequency of the output signal is the frequency of the timing indicated by the receiving clock signal. You may comprise so that it may set to.
Further, in the above configuration, it is desirable to periodically operate the pulse train of the input pulse number modulation signal and set the frequency of the output signal to the frequency of the timing indicated by the receiving side clock signal.
Alternatively, in the above configuration, the cycle for operating the pulse train of the input pulse number modulation signal varies, and the average value of each cycle matches the frequency of the output signal with the frequency of the timing indicated by the receiving side clock signal. It is desirable to control the period so as to be a value.
According to the sampling rate converting means having the above-described configuration, it is possible to obtain the same operational effects as those of the receiving apparatus according to the present invention.
The specific embodiments or examples made in the best mode for carrying out the invention are merely to clarify the technical contents of the present invention, and are limited to such specific examples. The present invention should not be interpreted in a narrow sense but can be implemented with various modifications within the spirit of the present invention and the scope of the following claims.
Industrial applicability
As described above, according to the receiving apparatus of the present invention, compared with the case of transmitting a digital signal indicating a multi-bit signal, a pulse capable of achieving both a reduction in waveform distortion during demodulation and a simple circuit configuration. The number modulation signal can be generated without any trouble. Therefore, the present invention is suitable for realizing a receiving apparatus capable of demodulating a signal with less waveform distortion with a simple circuit configuration as compared with the case of multi-bit.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention, and is a block diagram showing a main configuration of a communication system.
FIG. 2 shows a 1-bit pulse number modulation signal transmitted by the communication system and a multi-bit pulse code modulation signal transmitted by the prior art, and the time that the operation of the data sequence affects. It is explanatory drawing which shows a width | variety.
FIG. 3 is a block diagram showing a configuration example of a sampling rate converter provided in the receiving apparatus of the communication system.
FIG. 4 shows the operation of the sampling rate converter, and is a timing chart showing a case where the sampling cycle on the transmission side is longer.
FIG. 5 shows the operation of the sampling rate converter, and is a timing chart showing a case where the sampling cycle on the transmission side is shorter.
FIG. 6 is a block diagram showing a modification of the sampling rate converter.
FIG. 7 is a block diagram showing still another modification of the sampling rate converter.
FIG. 8 is a block diagram showing another modification of the sampling rate converter.
FIG. 9 is a block diagram showing a modification of the communication system.
FIG. 10 is a block diagram showing still another modification of the communication system.
FIG. 11 is a block diagram showing still another modification of the communication system.
FIG. 12 shows another embodiment of the present invention, and is a block diagram showing a main configuration of a communication system.
FIG. 13 shows still another embodiment of the present invention, and is a block diagram showing a main configuration of a transmitting / receiving apparatus.
FIG. 14 shows another embodiment of the present invention, and is a block diagram showing a main configuration of a communication system.
FIG. 15 shows still another embodiment of the present invention, and is a block diagram showing a main configuration of a communication system.
FIG. 16 is a block diagram showing a modification of the communication system.
FIG. 17 is a block diagram showing still another modification of the communication system.
FIG. 18 shows a conventional example and is a block diagram showing a main configuration of a communication system.

Claims (25)

A receiving apparatus used in a system for transmitting a digital signal indicating a signal waveform from a transmitting apparatus to a receiving apparatus via a network for transmitting digital signals in packets,
Receives a digital signal generated by dividing a pulse number modulated signal whose number of pulses per unit time varies according to the signal waveform from the network, and extracts a bit string indicating the pulse number modulated signal from the digital signal Means,
A receiving apparatus comprising: pulse number modulation signal output means for outputting a pulse corresponding to each bit of the bit string in a predetermined cycle based on a clock signal independent of the network . A receiving apparatus used in a system for transmitting a digital signal indicating a signal waveform from a transmitting apparatus to a receiving apparatus via a network for transmitting digital signals in packets,
Receives a digital signal generated by dividing a pulse number modulation signal whose number of pulses per unit time varies according to the signal waveform from the network, and extracts a bit string indicating the pulse number modulation signal from the digital signal Means,
A pulse number modulation signal output means for outputting a pulse corresponding to each bit of the bit string at a predetermined period;
An amplifier for amplifying and demodulating the output signal of the pulse number modulation signal output means is provided,
The amplifier includes a delta-sigma modulation unit that delta-sigma modulates an input signal, a power amplification unit that power-amplifies a pulse train output from the delta-sigma modulation unit, and a demodulation unit that demodulates the output of the power amplification unit rECEIVER it is a switching amplifier. Transmitting means for generating a digital signal by packet-dividing the pulse number modulation signal output from the delta-sigma modulation means, and transmitting the digital signal to the network;
In the reception mode for demodulating the received pulse number modulation signal, the output signal of the pulse number modulation signal output means is input to the input terminal of the delta sigma modulation means, and in the transmission mode for transmitting a digital signal, the signal to be transmitted The receiving apparatus according to claim 2, further comprising: an input switching unit that inputs a signal input from a signal source to the input terminal.   A feedback path switching means is provided for feeding back the output signal of the power amplification means to the delta-sigma modulation means in the reception mode and feeding back the output signal of the delta-sigma modulation means in the transmission mode. The receiving device according to claim 3.   When the receiving device is not connected to the network, the input switching unit selects the signal input from the signal source, and the feedback path switching unit selects the output signal of the power amplification unit. The receiving apparatus according to claim 4. A receiving-side clock signal generating means for generating a receiving-side clock signal indicating a timing of the same frequency as the sampling frequency of the pulse-number modulated signal, independently of the network, during transmission of the digital signal indicating the pulse number-modulated signal; ,
The pulse number modulation signal output means is a sampling rate conversion means for converting each pulse of the pulse number modulation signal extracted by the receiving means into a frequency at a timing indicated by the receiving side clock signal and outputting it. The receiving apparatus according to claim 1 .   When the frequency of the timing indicated by the reception side clock signal is lower than the sampling frequency of the pulse number modulation signal transmitted through the network, the sampling rate conversion means, between the pulse trains of the received pulse number modulation signal, 7. The receiving apparatus according to claim 6, wherein a pulse is inserted and the frequency of the output signal is set to a timing frequency indicated by the receiving side clock signal. The output terminal of the sampling rate conversion means is connected to an integrator that integrates a signal input as a potential to the input terminal,
The sampling rate conversion means, when the frequency of the timing indicated by the receiving clock signal is lower than the sampling frequency of the pulse number modulation signal transmitted through the network, between the pulse train of the received pulse number modulation signal, 7. The receiving apparatus according to claim 6, wherein a period for keeping the output terminal in high impedance is provided, and the frequency of the output signal is set to the frequency of the timing indicated by the receiving side clock signal.   The sampling rate converting means periodically operates the pulse train of the received pulse number modulation signal to set the frequency of the output signal to the frequency of the timing indicated by the receiving clock signal. The receiving device according to 7 or 8.   In the sampling rate converting means, the cycle for operating the pulse train of the received pulse number modulation signal varies, and the average value of each cycle matches the frequency of the output signal with the frequency of the timing indicated by the receiving clock signal. 9. The receiving apparatus according to claim 6, wherein the period is controlled so as to be a value. A receiving device according to claim 1 ;
The heat Okusu should signal by delta-sigma modulation produces a pulse number modulation signal, transmitting the pulse number modulated signal in packet division to generate a digital signal, the digital signal via the network to the receiving device A communication system comprising: A receiving device according to claim 2;
  A signal to be transmitted is delta-sigma modulated to generate a pulse number modulation signal, the pulse number modulation signal is packet-divided to generate a digital signal, and the digital signal is transmitted to the receiving device via the network. A communication system comprising: a transmission device. 13. The communication system according to claim 12, wherein the transmission device and the reception device are the reception devices according to claim 3, 4 or 5. The transmission apparatus transmits a digital signal indicating the pulse number modulation signal to a network including an intermediate node that operates based on a clock signal independent of a sampling clock of the pulse number modulation signal as the network. The communication system according to claim 11. 12. The communication according to claim 11, wherein the transmitting device is provided with decoding means for decoding the digital data encoded by any of a plurality of encoding methods and generating the signal to be transmitted. system. 12. The communication system according to claim 11, further comprising transmission rate arbitration means for selecting a sampling frequency for performing delta-sigma modulation from a plurality of predetermined options. Transmission rate arbitration means for selecting a sampling frequency for performing delta-sigma modulation from a plurality of predetermined options,
  The transmission rate arbitration unit determines the sampling frequency so that the data amount of the pulse number modulation signal per unit time is larger than the data amount of the encoded digital data per unit time. The communication system according to claim 15.   Sampling rate conversion means used in a system for transmitting a digital signal indicating a signal waveform from a transmitting device to a receiving device via a network for transmitting digital signals in packets,
  The pulse corresponding to each bit of the bit string indicating the pulse number modulation signal extracted from the digital signal generated by dividing the pulse number modulation signal whose number of pulses per unit time varies according to the signal waveform. A sampling rate conversion means for outputting at a predetermined cycle based on a clock signal independent of the network. Sampling rate conversion means used in a system for transmitting a digital signal indicating a signal waveform from a transmitting device to a receiving device via a network for transmitting digital signals in packets,
A pulse corresponding to each bit of the bit string indicating the pulse number modulation signal extracted from the digital signal generated by dividing the pulse number modulation signal whose number of pulses per unit time varies according to the signal waveform. , Output in a predetermined cycle,
Each pulse of the extracted pulse number modulation signal is
During transmission of the digital signal indicating the pulse number modulation signal, the frequency of the timing indicated by the receiving clock signal generated as a signal indicating the same frequency as the sampling frequency of the pulse number modulation signal is independent of the network. Sampling rate conversion means for converting and outputting. When the frequency of the timing indicated by the receiving clock signal is lower than the sampling frequency of the input pulse number modulation signal, a pulse is inserted between the pulse trains of the input pulse number modulation signal, and the output signal 20. The sampling rate conversion means according to claim 19, wherein the frequency is set to a frequency at a timing indicated by the receiving side clock signal. 21. The sampling rate conversion means according to claim 20, wherein the value of the pulse to be inserted is controlled to be 0 and 1 alternately. When the frequency of the timing indicated by the receiving clock signal is higher than the sampling frequency of the input pulse number modulation signal, the pulse is deleted from the pulse train of the input pulse number modulation signal, and the frequency of the output signal is 20. The sampling rate conversion means according to claim 19, wherein the sampling rate conversion means sets the frequency of the timing indicated by the receiving side clock signal.   The output terminal is connected to an integrator that integrates a signal input as a potential to the input terminal, and
  When the frequency of the timing indicated by the receiving side clock signal is lower than the sampling frequency of the input pulse number modulation signal, the period during which the output terminal is kept in high impedance between the pulse trains of the input pulse number modulation signal The sampling rate converting means according to claim 19, wherein the sampling rate converting means is configured to set the frequency of the output signal to the frequency of the timing indicated by the receiving clock signal. 24. The pulse train of an input pulse number modulation signal is periodically manipulated to set the frequency of the output signal to the timing frequency indicated by the receiving side clock signal. The sampling rate conversion means described. The cycle for operating the pulse train of the input pulse number modulation signal varies, and the average value of each cycle is a value that matches the frequency of the output signal with the frequency of the timing indicated by the receiving side clock signal. The sampling rate conversion means according to any one of claims 19 to 23, wherein the period is controlled.

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