JP3836248B2 - Analog / digital converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention effectively uses the difference between a reference level voltage signal and a data level voltage signal that are alternately output in a time-division manner, for example, from a digital still camera or video camera using a CCD (Charge Coupled Image Sensor). The present invention relates to an A / D converter (analog / digital converter) which takes out as data and converts a voltage signal which is the effective data into a digital signal.
[0002]
[Prior art]
Since CCDs vary among elements, a reference level voltage signal is output in addition to a pixel level voltage signal, and the level difference between the two is used as effective data. Specifically, as shown in FIG. 6, a reference level voltage signal and a pixel level voltage signal are alternately output. FIG. 7 shows a block diagram for signal processing of a CCD camera such as a digital still camera or a video camera. An image captured from the lens 11 to the CCD image sensor 12 is converted into an analog voltage signal, and this voltage is shown in FIG. The signal is preprocessed by the preprocessing circuit 13 and then processed by the digital processing unit 15 through the A / D converter 14.
[0003]
FIG. 8 is a circuit diagram embodying this block diagram, and the preprocessing circuit 13 performs correlated double sampling (CDS). Correlated double sampling is a process of holding each signal by sampling the signal twice at different times. In this circuit, the voltage signals of the reference level and the pixel level are sequentially sampled and held by the sample hold units 16a and 16b, the difference is taken out by the adder 17, and the reference component is obtained from each resistance component of the ladder circuit 18. The differential voltage is input to the comparators 19-1, 19-2,... 19-m that take in the voltage, and the encoder 10 outputs a digital signal based on the output.
[0004]
[Problems to be solved by the invention]
By the way, since the number of output bits of an A / D converter used in a CCD camera is generally 10 bits or more, a differential amplifier used as an adder is composed of a bipolar transistor. This is because the CMOS amplifier has a large offset error and does not have a high output linearity with respect to the input, and therefore cannot have a resolution of 10 bits or more. On the other hand, since a CMOS amplifier is used for the A / D converter, the preprocessing circuit and the A / D converter cannot be mounted on the same chip, and must be manufactured separately. As a result, the manufacturing process is simplified and the manufacturing cost is reduced.
[0005]
A method of inputting the reference level and pixel level voltage signals to a common A / D converter and subtracting the output later to extract valid data is also conceivable. Since it is determined by the difference in the step level of the / D converter, high accuracy cannot be obtained.
[0006]
The present invention has been made under such a background, and an object of the present invention is to provide a digital signal corresponding to a level difference between two signals subjected to correlated double sampling such as a CCD camera. In the obtained A / D converter, a manufacturing process is simplified, and a technique capable of keeping costs low is provided.
[0007]
[Means for Solving the Problems]
The analog / digital converter of the present invention alternately takes in the voltage signal of the reference level and the voltage signal of the data level, makes the level difference between the continuous voltage signals effective data, and converts this effective data into digital data. In an analog / digital converter that converts to a code signal,
A reference voltage generator for generating a reference voltage corresponding to each value of the digital code signal;
A sample holding unit for sampling and holding at least one of the reference level voltage signal and the data level voltage signal;
Provided in correspondence with each of the reference voltages, and between an input / output that opens and closes an operational amplifier, between the normal input terminal and the inverting input terminal of the operational amplifier, and between the inverting input terminal and the normal output terminal A switch, a first capacitance component and a second capacitance component, one end of which is connected to the normal rotation input end and the inverting input end of the operational amplifier, respectively, and a charge control connected to the other end of these capacitance components A plurality of differential chopper comparators including a switch group;
A setting voltage source for supplying a common setting voltage to the input side of each differential chopper comparator;
An encoder for inputting a comparison result of each differential chopper comparator and outputting a digital code signal corresponding to the comparison result;
The switch between the input and output is closed and the opening and closing of the switch group for charge control is controlled, and is held in one of the reference level voltage signal and the data level voltage signal and the sample holding unit. And charging one and the other of the first capacitive component and the second capacitive component, respectively,
Next, the switch between the input and output is opened, and the opening and closing of the switch group for charging control is controlled, so that the application point of each reference voltage is determined by the first capacitance component and the second capacitance of the corresponding differential chopper comparator. And the set voltage source is connected to the other one of the first capacitance component and the second capacitance component, respectively.
Thus, a comparison result corresponding to the difference between the reference level voltage signal and the data level voltage signal is obtained from each differential chopper comparator.
[0008]
The analog / digital converter according to another invention has the same configuration as that of the above-described invention except that a differential differential chopper comparator is used.
With the input / output switch closed, one or the other of the first capacitance component and the second capacitance component is set by one of the reference level voltage signal and the data level voltage signal and one of the reference voltage and the set voltage. Control the opening and closing of the charging control switch group to charge each,
Next, the input / output switch is opened, and the other of the reference level voltage signal and the data level voltage signal and the other of the reference voltage and the set voltage are connected to the other of the first capacitance component and the second capacitance component, and Type in one,
Thus, a comparison result corresponding to the difference between the reference level voltage signal and the data level voltage signal is obtained from each differential chopper comparator.
[0009]
In the above invention, the set voltage source is, for example, the ground, and the reference level voltage signal and the data level voltage signal are, for example, a reference level and pixel level signal output from a charge coupled image sensor image sensor. is there.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment according to the A / D converter of the present invention is shown in FIG. In the figure, reference numeral 2 denotes a resistance ladder circuit, and one end and the other end are connected to a high level power source and a low level power source, respectively. The resistor ladder circuit 2 is configured by connecting a plurality of voltage dividing resistance components R for generating a reference voltage in series, and the A / D converter can obtain an n-bit digital code signal. 2 ⁿ (= m) voltage ^dividing points for extracting reference voltages corresponding to the respective values of the code signal can be selected. In this example, the resistor ladder circuit 2, the high-level power supply, and the low-level power supply correspond to the reference voltage generation unit.
[0011]
Differential chopper comparators 3 (3-1 to 3-m), which are 2 ⁿ differential chopper comparators, are provided corresponding to the reference voltages, respectively. The differential chopper comparator 3 will be described with reference to FIG. Reference numeral 31 denotes an operational amplifier, and switches S2 and S5 are provided between the normal rotation input terminal and the inverting output terminal, and between the inverting input terminal and the normal rotation output terminal, respectively. One end of the first capacitance component C1 and the second capacitance component C2 is connected to the normal rotation input terminal and the inverting input terminal of the operational amplifier 31, respectively. The other end of the capacitive component C1 is connected to a signal line 12a through which the output signal of the CCD image sensor 12 is sent via a switch S1, and the other end of the capacitive component C2 is connected via a switch S4 and a sample hold circuit 41. It is connected to the signal line 12a. The other end of the capacitive component C1 is connected to the voltage dividing point of the resistance ladder circuit 2 via the switch S3, and the other end of the capacitive component C2 is connected to the ground G via the switch S6. The switches S2 and S5 are the input / output switches referred to in the claims, the switches S1, S3, S4, and S6 are the charge control switches referred to in the claims, and the sample hold circuit 41 is the claims. Each corresponds to a sample holding section in the range.
[0012]
An encoder (encoder) 5 is connected to the output side of the differential chopper comparator 3. For example, a digital signal corresponding to the number of stages of the differential chopper comparator 3 that outputs logic “H” is output from the encoder 5. .
[0013]
Next, the operation of this embodiment will be described. FIG. 3 is a timing chart showing the output signal of the CCD 12 and the states of the switches S1 to S6 of the differential chopper comparator 3 in association with each other.
[0014]
In this example, assuming that the reference level voltage signal and the pixel level voltage signal are alternately output from the CCD image sensor 12, the sample signal is first sampled by the sample hold circuit 41. Hold. This timing is indicated by a circle with A1 in FIG. The switches S1, S2, S4, and S5 are closed and the switches S3 and S6 are opened at the timing when the pixel level voltage signal appears on the signal path 12a following the reference level voltage signal. As a result, the voltage signal of the pixel level appearing on the signal path 12a is guided to the capacitive component C1 through the switch S1 to charge the capacitive component C1, and at the same time, the capacitive component is generated by the reference level voltage signal already held in the sample hold circuit 41. Charge C2. In FIG. 3, the circles marked with A2 schematically show the timing of charging the capacitive component C1 with a pixel level voltage signal. At this time, if the auto-zero voltage of the differential chopper comparator 3 (the threshold value vt of the differential chopper comparator 3) is Vb, and the pixel level voltage and the reference level voltage are Vin1 and Vin2, respectively, the capacitance component C1 is charged. The charge Q1 and the charge Q2 charged in the capacitive component C2 are expressed by the equations (1) and (2), respectively.
[0015]
However, the capacity component codes C1 and C2 also serve as capacity values for convenience.
Q1 = (Vin1−Vb) C1 (1)
Q2 = (Vin2−Vb) C2 (2)
Thereafter, for example, at the timing when the voltage signal of the next reference level appears on the signal path 12a, the switches S1, S2, S4, and S5 are opened, and the switches S3 and S6 are closed, so that the reference voltage application point, that is, the resistance ladder The voltage dividing point of the circuit 2 is connected to the other end of the first capacitance component C1, and the ground G, which is a set voltage source, is connected to the other end of the second capacitance component C2. At this time, the operational amplifier 31 is opened between the normal input terminal and the inverted output terminal and between the inverted input terminal and the normal output terminal, and the operational amplifier 31 performs comparison processing.
[0016]
In this state, the input voltage V1 inputted to the normal input terminal of the operational amplifier 31 is represented by the equation (3), and the input voltage V2 inputted to the inverting input terminal is represented by (4). It is a VRef reference voltage.
[0017]
V1 = VRef−Q1 / C1 = VRef−Vin1 + Vb (3)
V2 = 0-Q2 / C2 = -Vin2 + Vb (4)
Therefore, the error ΔV (= V1−V2) between V1 and V2 is expressed by the equation (5).
[0018]
ΔV = V1−V2 = VRef− (Vin1−Vin2) (5)
As a result, for example, when one of the normal output terminal and the inverted output terminal of the operational amplifier 31 is the output terminal of the differential chopper comparator 3, for example, the inverted output terminal is in a floating state. If the level difference (Vin1−Vin2) between the level voltage signal and the reference level voltage signal is larger than VRef, the comparison result is logic “1”, and if it is smaller than VRef, the logic is “0”. Thus, since the number of stages of the differential chopper comparator 3 that outputs logic “1” is determined according to the level difference (Vin1−Vin2), the corresponding digital code signal is output from the encoder 5.
[0019]
According to the above-described embodiment, since the differential chopper comparator 3 is used as the comparator of the A / D converter, one of the correlated double sampling function, that is, the pixel level voltage signal and the reference level voltage signal. A function of sequentially sampling and holding the other and the other can be incorporated into the A / D converter. For this reason, it is not necessary to use an adder which has conventionally been required to be composed of bipolar transistors in order to obtain the difference between the two levels, and the operational amplifier 31 of the differential chopper comparator 3 is a CMOS similar to each switch and encoder. It can be configured by a circuit. Accordingly, the manufacturing process can be simplified, and the A / D converter can be configured with one chip, the cost can be reduced and the size can be reduced, and the cost of the CCD camera can be kept low. Further, since the output from the CCD image sensor 12 becomes the input of the A / D converter, the original performance of the A / D converter can be obtained, and there is no problem of deterioration of the input signal by the amplifier of the adder.
[0020]
In the above, the sample hold circuit 41 is provided on the switch S1 side instead of being provided on the switch S4 side as described above, so that the CCD image sensor 12 first outputs a pixel level voltage signal and then a reference level voltage signal. In this case, the pixel level voltage signal which is the earlier signal is held in the sample hold circuit 41, and the sequence of the switches S1 to S6 shown in FIG. 3 is inverted. . In the present invention, the sample hold circuit 41 may be provided on one of the switches S1 and S4, but the configuration provided on both sides is also included in the uninvented range.
[0021]
Here, the set voltage of the set voltage source applied to the other end of the capacitive component C2 through the switch S6 is 0 volt because the ground is used in the above example, but the present invention is not limited to this. Good. Contrary to the above-described embodiment, the first capacitive component C1 and the second capacitive component C2 may be charged with a reference level voltage signal and a pixel level voltage signal, respectively. If the output of the image sensor 12 is inverted by an inverter, the same result is obtained. Furthermore, a ground may be connected to the first capacitive component C1 side via the switch S3, and a voltage dividing point of the resistance ladder circuit 2 may be connected to the second capacitive component C2 side via the switch S6.
[0022]
Next, another embodiment of the present invention will be described with reference to FIGS. This embodiment differs from the previous embodiment in that the sample hold circuits 41 and 42 are not used, and the other end of the first capacitance component C1 is connected to the signal line 12a via the switch S3. In other words, the other end of the second capacitance component C2 is connected to the voltage dividing point of the resistance ladder circuit 2 via the switch S4.
[0023]
In this embodiment, the switches S1 and S2 are closed when the pixel level voltage signal is output, and then the switches S4 and S5 are closed when the reference level voltage signal is output. To do. Charges Q1 and Q2 charged in the capacitance components C1 and C2, respectively, are expressed by equations (6) and (7).
[0024]
Q1 = (Vin1−Vb) C1 (6)
Q2 = (VRef−Vb) C1 (7)
If the switches S3 and S6 are closed and the other switches S1, S2, S4, and S5 are opened while the voltage signal of the reference level is still output, the normal rotation input terminal and the inversion of the operational amplifier 31 are reversed. Input voltages V1 and V2 at the input end are expressed by equations (8) and (9), respectively.
[0025]
V1 = Vin2-Q1 / C1 = Vin2-Vin1 + Vb (8)
V2 = 0−Q2 / C2 = −VRef + Vb (9)
Therefore, ΔV (= V1−V2) is expressed by equation (10).
[0026]
ΔV = VRef− (Vin1−Vin2) (10)
As can be seen from this equation, a logical output (comparison result) corresponding to the magnitude of (Vin1−Vin2) and VRef is obtained from the differential chopper comparator 3 as in the previous embodiment, and an adder is also used. Instead, a digital code output corresponding to the level difference between the pixel level and the reference level is obtained. In this embodiment, Vin1 and Vin2 may be input to the second capacitance component C2 side, and VRef and ground 0V may be input to the first capacitance component C1 side.
[0027]
When the configuration of FIG. 2 is compared with the configuration of FIG. 4, the former case is excellent in that a normal operation can be performed even in a region where there is almost no gain of the differential chopper comparator 3.
[0028]
In the above, the present invention can be applied as long as the reference level voltage signal and the data level voltage signal are alternately taken and the level difference is used as effective data, and is limited to processing an output signal from the CCD image sensor. Is not to be done.
[0029]
【The invention's effect】
According to the present invention, when one of the reference level voltage signal and the data level voltage signal is alternately taken to obtain a digital code signal corresponding to the level difference, the difference is used as a comparator of the A / D converter. The use of a dynamic chopper comparator eliminates the need for an adder. Accordingly, the CMOS circuit can be unified without mixing bipolar transistors and CMOS circuits in the A / D converter, thereby simplifying the manufacturing process. It can be configured with a chip.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a main part of the embodiment of the present invention.
FIG. 3 is a time chart showing the operation of the embodiment of the present invention.
FIG. 4 is a circuit diagram showing a main part of another embodiment of the present invention.
FIG. 5 is a time chart showing the operation of another embodiment of the present invention.
FIG. 6 is a waveform diagram showing a video signal output from a CCD image sensor.
FIG. 7 is a block diagram showing a general configuration of a camera using a CCD.
FIG. 8 is a circuit diagram showing a main part of a camera using a CCD.
[Explanation of symbols]
12 CCD image sensor 12a Signal line 3 (3-1 to 3-m) Differential chopper comparator 31 Operational amplifiers S1, S3, S4, S6 Switches for charge control S2, S5 Input / output switches C1, C2 Capacitance component 41 samples Hold circuit 5 Encoder

Claims (4)

An analog / digital signal that alternately takes in a reference level voltage signal and a data level voltage signal, makes the level difference between these successive voltage signals effective data, and converts this effective data into a digital code signal. In the converter,
A reference voltage generator for generating a reference voltage corresponding to each value of the digital code signal;
A sample holding unit for sampling and holding at least one of the reference level voltage signal and the data level voltage signal;
Provided in correspondence with each of the reference voltages, and between an input / output that opens and closes an operational amplifier, between the normal input terminal and the inverting input terminal of the operational amplifier, and between the inverting input terminal and the normal output terminal A switch, a first capacitance component and a second capacitance component, one end of which is connected to the normal rotation input end and the inverting input end of the operational amplifier, respectively, and a charge control connected to the other end of these capacitance components A plurality of differential chopper comparators including a switch group;
A setting voltage source for supplying a common setting voltage to the input side of each differential chopper comparator;
An encoder for inputting a comparison result of each differential chopper comparator and outputting a digital code signal corresponding to the comparison result;
The switch between the input and output is closed and the opening and closing of the switch group for charge control is controlled, and is held in one of the reference level voltage signal and the data level voltage signal and the sample holding unit. And charging one and the other of the first capacitive component and the second capacitive component, respectively,
Next, the switch between the input and output is opened, and the opening and closing of the switch group for charging control is controlled, so that the application point of each reference voltage is determined by the first capacitance component and the second capacitance of the corresponding differential chopper comparator. And the set voltage source is connected to the other one of the first capacitance component and the second capacitance component, respectively.
An analog / digital converter characterized in that a comparison result corresponding to a difference between a reference level voltage signal and a data level voltage signal is obtained from each differential chopper comparator. An analog / digital signal that alternately takes in a reference level voltage signal and a data level voltage signal, makes the level difference between these successive voltage signals effective data, and converts this effective data into a digital code signal. In the converter,
A reference voltage generator for generating a reference voltage corresponding to each value of the digital code signal;
Provided in correspondence with each of the reference voltages, and between an input / output that opens and closes an operational amplifier, between the normal input terminal and the inverting input terminal of the operational amplifier, and between the inverting input terminal and the normal output terminal A switch, a first capacitance component and a second capacitance component, one end of which is connected to the normal rotation input end and the inverting input end of the operational amplifier, respectively, and a charge control connected to the other end of these capacitance components A plurality of differential chopper comparators including a switch group;
A setting voltage source for supplying a common setting voltage to the input side of each differential chopper comparator;
An encoder for inputting a comparison result of each differential chopper comparator and outputting a digital code signal corresponding to the comparison result;
With the switch between input and output closed, one and the other of the first capacitance component and the second capacitance component are generated by one of the reference level voltage signal and the data level voltage signal and one of the reference voltage and the set voltage. To control the opening and closing of the switch group for charging control so as to charge each,
Next, the input / output switch is opened, and the other one of the reference voltage and the set voltage is connected to the other one of the first capacitance component and the second capacitance component. And enter in one,
An analog / digital converter characterized in that a comparison result corresponding to a difference between a reference level voltage signal and a data level voltage signal is obtained from each differential chopper comparator. 3. The analog / digital converter according to claim 1, wherein the set voltage source is a ground. 4. A reference level voltage signal and a data level voltage signal are signals of a reference level and a pixel level output from a charge coupled image sensor image sensor, respectively. Analog / digital converter.

Images