JP3834327B2 - Graphic processing apparatus, method of using the same, and microprocessor - Google Patents

Description

Industrial application fields

  The present invention relates to a graphic processing method, and more particularly, to a processing method suitable for transferring graphic data between bus-separated memories.

  Conventionally, a Harvard architecture is known as a microprocessor system having two sets of buses for address, data, and control signals. This system separates an instruction bus and a data bus to separate instruction fetch and data access. To avoid conflicts.

Further, as an LSI for graphic processing, a bitmap control processor BM discussed in Toshiba Review Vol. 43 No. 12 (1988), pages 932 to 935 is used.
There is a CP. This BMCP has an 8-bit data bus in the system bus to which the CPU and the system memory are connected. In addition to this, the BMCP has 64 local memory data buses and 24 address buses. The 8-plane local memory (image memory) is accessed by the memory data bus. It is also possible for the BMCP to access the system memory by latching the address.

  Among the above prior arts, the Harvard architecture has a dedicated instruction bus and data bus, and two sets of buses, such as graphic transfer between system memory and frame memory, which is most frequently performed in graphic processing. There is no consideration for using both for data access.

  On the other hand, the BMCP can use two sets of buses for data access, but there is only one address bus, and it is unclear whether two memories can be accessed simultaneously.

  Further, in the execution of so-called read modify write processing often used in graphic processing of reading out data at a certain memory address and performing processing and then writing back to the original address, a conventional general-purpose microprocessor is as follows. There was a problem.

  That is, first, in a general-purpose processor of CISC (Complexed Instruction Set Computer) type, a memory address can be specified for a source operand and a destination operand of an arithmetic instruction, and a read-modify-write process can be described with one instruction. However, there is a problem that the instruction length becomes long, and it is not clear whether it can be executed without inserting a wait cycle between the read cycle and the write cycle. Some processors dedicated to graphics processing execute read-modify-write processing in two continuous memory cycles, but the function of modification is limited. In a RISC (Reduced Instruction Set Computer) type processor, a fixed-length instruction is basically used, and a load instruction and a store instruction can be the target of an operand. Therefore, in order to execute the read-modify-write process, three instructions, that is, a load instruction, an operation instruction, and a store instruction, are necessary, and load and store cannot be executed in two continuous memory cycles.

  An object of the present invention is to simultaneously perform memory accesses on separate buses in a graphics processing device or information processing device, thereby speeding up graphics or data transfer between two memories.

  Another object of the present invention is to enable a read-modify-write process frequently used in graphic processing to be executed in a RISC type processor without inserting an empty cycle between a read cycle and a write cycle. .

  In order to achieve the above object, a graphics processing apparatus according to the present invention comprises a CPU and a system memory respectively connected to a system bus comprising address, data and control buses, and a local comprising an address, data and control buses. A graphic memory having a local memory and a frame memory respectively connected to the bus; a graphic processor having a first port connected to the system bus and a second port connected to the local bus; The processor for the processor allows simultaneous access to the first memory and the second memory via the first and second ports.

  As a method of using this graphic processing apparatus, a graphic transfer program is stored in the system memory or the local memory, various graphic data are stored in the system memory, and the graphic data in the system memory is stored. When transferring to the frame memory, the CPU writes the start address of the graphics transfer program and the start address of the parameter to the system memory or the local memory, and sends the graphics processor to the graphics processor according to the graphics transfer program and parameters. It is conceivable to transfer graphic data on the system memory to the frame memory via the first and second ports. When transferring the graphic data, the graphic processor reads the data in the transfer destination area of the frame memory corresponding to the graphic data in the transfer source area of the system memory, performs a logical operation on both data, and executes the logical operation. The result can be written in the transfer destination area of the frame memory.

  As another method of using the graphic processing apparatus, various graphic drawing programs are stored in the system memory or local memory, and when drawing a graphic in the frame memory, the CPU uses the start address of the graphic drawing program. A work list including the start address of the parameter is created in the system memory or the local memory, and the graphic processor is read by the graphic processor in response to an instruction from the CPU, and the graphic processor is used to read the work list. A method of drawing graphics on the frame memory according to the graphics drawing program and parameters specified by the list can be considered.

  According to another aspect, the graphics processing apparatus according to the present invention includes a CPU and a first memory respectively connected to a system bus including address, data, and control buses, and an address, data, and control buses. A second memory connected to the local bus; a first port connected to the system bus; a second port connected to the local bus; and a graphics processor having a plurality of internal registers. The graphic processor is configured to load graphic data from one of the first and second memories to one internal register via the first port, and from the other internal register to the first and second The process of storing data in the other of the two memories can be executed in parallel.

  The information processing apparatus according to the present invention is connected to a CPU and a first memory respectively connected to a system bus including address, data, and control buses, and to a local bus including address, data, and control buses. A second memory, a first port connected to the system bus, a second port connected to the local bus, and a processor dedicated to specific processing having a plurality of internal registers. The dedicated processor includes a process of loading data from one of the first and second memories to one internal register via the first port, and the other of the first and second memories from the other internal register. It is characterized in that the process of storing data can be executed in parallel.

  The microprocessor according to the present invention includes a processor unit for decoding and executing instructions, two ports for transmitting and receiving addresses, data, and control signals to and from the memory, writing from the processor unit, and reading to the two ports. Through an address buffer, a data buffer that can be read from and written to two ports, and an instruction read by the processor unit, and a port specified by a memory access request and a port designation signal from the processor unit And a means for controlling address transfer from the address buffer to the memory and data transfer between the data buffer and the memory, wherein instruction fetch and data access can be performed for two memories. . The data buffer may be readable and writable from the processor unit.

The processor unit includes, for example, a register that stores the number of words (memory width) in the X direction of the bitmap memory, and three rectangular areas (transfer source area, pattern area, and transfer destination area) defined on the bitmap memory. Registers that store word addresses (transfer source address register, pattern address register, transfer destination address register), transfer source shift number register that stores the difference in bit position between the transfer source area and transfer destination area, pattern area, and transfer destination A pattern shift number register for storing the bit position difference of the area; means for shifting the transfer source data based on the transfer source shift number register; or shifting the pattern data based on the pattern shift number register; Means to perform logical operation of transfer source data, pattern data and transfer destination data, and left end and right of transfer destination area And a masking means for designating a write-inhibited area, and a means for synthesizing the operation result and the transfer destination data based on the masking means, wherein rectangular area transfer of three operands is arbitrarily performed between ports. To do.

  As the means for generating the port designation signal, a port designation means for generating the signal based on the memory address may be provided.

  According to another aspect, the microprocessor according to the present invention includes a processor unit that decodes and executes instructions, two ports that exchange addresses, data, and control signals with a memory, and a dedicated address for each port. A buffer, a data buffer, means for managing the operation status of each port, and means for writing the data read from the memory into a register in the processor unit, and simultaneously accessing the two memories via the two ports It is characterized by being able to do it.

  Another microprocessor according to the present invention is a microprocessor for executing a fixed-length instruction, wherein a first instruction holding means for holding a main instruction read from a program and a first instruction for holding a slave instruction associated with the main instruction. 2 instruction holding means, a decoding means for decoding the main instruction and the sub instruction, and if the main instruction is an instruction using a sub instruction as a result of decoding the main instruction, the sub instruction holding means holds The subordinate instruction is decoded and executed.

  In this microprocessor, the read-modify-write instruction is represented by the above main instruction and subordinate instruction, the main instruction designates the register that holds the subordinate instruction and the register that holds the memory address, and the subordinate instruction reads from the memory. The register for storing the data and the contents of the operation are specified, and when the data is read from the memory in accordance with the main instruction, the slave instruction is executed immediately, and the execution result is written to the memory, so that two consecutive times The read-modify-write process can be performed in the memory cycle.

  According to the present invention, two sets of buses of a two-port microprocessor can be arbitrarily used for instruction fetch and data access, and memory access can be performed at the same time, so that memory access efficiency is improved. In this case, the graphics transfer between the system memory and the frame memory is accelerated. Also, read-modify-write processing, which is frequently used in graphic processing, can be executed without a blank cycle between read and write cycles.

Action

  The microprocessor having the above two ports preferably executes pipeline processing for reading, decoding, executing, and storing data. In the case of a memory access instruction, after entrusting the processing to a unit dedicated to memory access processing, Perform instruction execution. The unit that processes the memory access manages the operation state of the two ports, so that if the port has already been commissioned, the unit that executes instructions until the port becomes available Wait for the execution of the command. Therefore, even if one port is operating, memory access using the other port is accepted.

  The 2-port microprocessor can arbitrarily use two sets of buses for instruction fetch and data access, and can access the memory at the same time, so that the memory access efficiency is improved. Graphic transfer to and from the frame memory is speeded up.

  Also, read / write instructions are placed in a program in the memory, and arithmetic processing instructions are placed in a subordinate instruction buffer different from the normal instruction buffer, and the arithmetic instructions are taken out from the buffer when read data is prepared. By executing it, read-modify-write processing of two consecutive memory cycles can be performed in time for the operation of the read data in time for the write cycle.

  Parameters such as graphic drawing from the CPU to the 2-port microprocessor and rectangular area transfer with logic operation are not directly given to the 2-port microphone and processor by the CPU, but are written continuously into the memory by the CPU and the start address thereof. Is included in the work list on the memory, all graphic processing such as graphic drawing and transfer thereafter can be delegated to the 2-port microprocessor. That is, when the 2-port microprocessor receives the activation of graphic processing from the CPU, the 2-port microprocessor sequentially executes the processing specified in the work list with reference to the processing program and parameters. By creating a plurality of graphic processes as a work list in advance, the CPU does not need to give a parameter to the 2-port microprocessor for each graphic process, so the burden is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a graphic display device according to an embodiment of the present invention.

  In the figure, 8 is a central processing unit (CPU) that controls the entire apparatus.

Reference numeral 1 denotes a microprocessor for instructing graphic drawing and graphic display on the CRT 6, and has a processor unit 101 for executing microinstructions and two sets of ports 102 and 103 therein.

  Reference numeral 3 denotes a local memory for storing microinstructions and data for drawing graphics.

  Reference numeral 4 denotes a frame memory for storing graphic data.

  Reference numeral 5 denotes a shift circuit for outputting display data for a plurality of pixels read out by the microprocessor 1 to the frame memory 4 for graphic display one by one to the CRT 6.

  A circuit 7 supplies a clock for operating the 2-port microprocessor 1, the local memory 3, the frame memory 4, and the shift circuit 5.

  Reference numeral 10 denotes a system memory for storing microinstructions and data executed by the CPU 8 and storing graphic drawing commands and data processed by the microprocessor 1.

  11 receives a use request signal for the system bus 9 output before the microprocessor 1 accesses the system memory 10, requests the CPU 8 for a bus, and if the bus use permission is given, 1 is a bus arbitration circuit that notifies 1.

12, when the CPU 8 accesses a register in the processor unit 101 and accesses the local memory 3 or the frame memory 4 connected to the local bus 2, the CPU 8 decodes an address output from the CPU 8 and interrupts the microprocessor 1. It is a decoder that outputs request and interrupt processing contents.

  Reference numeral 13 denotes a circuit that adjusts the input / output timing of the microprocessor 1 to the system bus 9 and outputs a clock for operating the CPU 8, the system memory 10, and the bus arbitration circuit 11.

  Next, the address allocation method for the system memory, local memory and frame memory in FIG. 1 will be described with reference to FIG.

  The 2-port microprocessor divides the memory space addressable by itself into two and allocates it to the first system memory space 20 and the local memory space frame memory space 40.

  The second system memory space 30 is accessible only by the CPU.

301 is a register built in the 2-port microprocessor, and can be accessed from the CPU by assigning an address to the memory space of the CPU. Among the registers 301, the R0 register and the R1 register are used for dedicated purposes, and will be described with reference to FIG.

  In FIG. 3, the R0 register is called a control register and stores information related to operation control of the 2-port microprocessor. That is, the most significant bit of the R0 register is called an operation control bit. When “0” is stored, it is in a stopped state, and when “1” is stored, it is in an operating state, that is, a microinstruction execution state. The field from 0 to 23 bits is a field for storing a work list address. The work list describes a memory address of a drawing program and graphic parameters executed by the 2-port microprocessor. When the 2-port microprocessor wants to read the work list, the R0 register is used as an address register. However, the valid addresses are 0 to 23 bits. The R0 register can be read and written by CPU access or 2-port microprocessor instruction execution.

  The R1 register is called a program counter, which stores a memory address of a microinstruction read by the 2-port microprocessor and automatically increments the value when the instruction is read out. In the R1 register, 0 to 23 bits are effective, and the entire memory space of the 2-port microprocessor can be used for the program area.

  Next, the graphic drawing method of the embodiment apparatus shown in FIG. 1 will be described.

  In this embodiment, a CPU generates a work list and graphic parameters on a memory, and a 2-port microprocessor refers to the work list and the like to perform graphic drawing.

  FIG. 4 shows a memory map of commands and programs necessary for the 2-port microprocessor to perform graphic drawing.

  The work list 10-1 is a command sequence given from the CPU to the 2-port microprocessor, and draws the start address of the memory storing the parameters of the graphic to be drawn and the start address of the memory storing the drawing program. As long as the figure to be displayed is continuously provided.

  10-1-1 represents the start address of the memory storing the parameter of the figure “c”, and 10-1-2 represents the start address of the memory storing the drawing program of the figure “c”. The part following 10-1-2 stores the parameters of another figure and the start address of the program. 10-1-3 represents the parameter start address of the last figure “h”, and 10-1-4 represents the drawing program start address. 10-1-5 represents the end of the work list and is called the list end. The list end value can be arbitrarily determined.

  10-2 is a parameter of the figure “c”, and the number and order of the parameters correspond to the drawing program of the figure “c”.

  Similarly, 10-3 is a parameter of the figure “h”.

Although the work list 10-1 and the graphic parameters 10-2 and 10-3 are defined on the system memory 10 as described above, they can also be defined on the local memory 3.

  Reference numeral 3-1 denotes a work list reference program which reads a graphic parameter head address from the work list and transfers execution to the graphic drawing program. Reference numerals 3-2-1, 3-2-2, and 3-2-3 are graphic drawing programs.

As described above, the programs 3-1, 3-2-1, 3-2-2, 3-2-3 are defined on the local memory 3, but can also be defined on the system memory 10.

  The 2-port microprocessor 1 stores the address of the work list in the R0 register 1101-1 and uses it as an address register when referring to the work list. The R1 register 1101-2 stores a program address. The R2 register 1101-3 is used as an address register when reading graphic parameters.

  Next, the graphic drawing method of the 2-port microprocessor will be described with reference to FIG.

  50 is a flowchart showing a procedure by which the CPU causes the 2-port microprocessor to start the graphic drawing process.

First, the CPU generates a work list and graphic parameters on the memory (50-1). Next, the CPU writes the start address of the work list reference program in the R1 register (program counter) of the 2-port microprocessor (50-2). Subsequently, the CPU writes the operation control bit in the R0 register (control register) of the 2-port microprocessor to "1", and similarly writes the start address of the work list to the work list address field in the R0 register (50-3). . The process of the CPU ends here. Since the subsequent graphic drawing process is left to the 2-port microprocessor, the CPU can execute other processes during that time.

  The 2-port microprocessor starts its operation when the operation control bit in the R0 register becomes “1”.

  In FIG. 5, reference numeral 60 denotes processing of the 2-port microprocessor. The 2-port microprocessor executes the work list reference program when the R1 register is set in step 50-2. First, data is read using the work list address field of the R0 register as a memory address and written to the R2 register (60-1). At the same time, “1” is added to the value of the work list address of the R0 register. Next, the contents of the R2 register are compared with the list end value indicating the end of the work list (60-2). If they are equal, the operation control bit of the R0 register is rewritten to “0” (60-3-b), and the 2-port microprocessor is stopped (60-6). If the contents of the R2 register and the list end value are not equal, the data is read using the work list address field of the R0 register as a memory address and written to the R1 register (60-3-a). At the same time, “1” is added to the value of the work list address of the R0 register. Depending on the value of the R1 register rewritten in step 60-3-a, the processing of the 2-port microprocessor is one of the graphic drawing programs shown in steps 60-4-a, 60-4-b, and 60-4-c. Move on. In each program, the parameters can be read from the memory by using the R2 register as an address register. When the drawing program is completed, the R1 register is rewritten to the start address of the work list reference program (60-5), and the process again proceeds to step 60-1. The 2-port microprocessor executes the above processing until it detects a list end from the work list.

  Next, the internal configuration of the 2-port microprocessor will be described with reference to FIG.

  An instruction fetch unit 1101 fetches microinstructions. If a cache memory is built in and there is no corresponding instruction in the cache memory, the instruction is fetched from the external memory.

  A decoder 1102 decodes the instruction code given from the instruction fetch unit and performs arithmetic control.

  Reference numeral 1103 denotes an arithmetic unit, which has a register and an arithmetic unit, and executes arithmetic operations.

  A memory access management unit 1104 processes a memory access request generated in the 2-port microprocessor and an interrupt of the CPU 8.

Reference numeral 102 denotes a port 1, an access response from the CPU 8, and a system memory 10
Access to.

Reference numeral 103 denotes a port 2, which accesses the local memory 3 and the frame memory 4.

Reference numeral 1105 denotes a bus switch, which performs a bus connection between the arithmetic unit 1103 and the port 1 (102) and the port 2 (103).

  Hereinafter, each unit will be described in detail.

  The instruction fetch unit 1101 includes a cache control unit 1101-1, an instruction fetch control unit 1101-2, and an instruction buffer 1101-3. The central part of the operation control is the instruction fetch control unit 1101-2, which determines whether or not the instruction fetch can be executed according to the state of the operation control bit of the R0 register 1103-1 in the arithmetic unit 1103. That is, if the operation control bit is “0”, the instruction fetch is not executed, and if it is “1”, the instruction fetch is executed.

  The instruction fetch control unit 1101-2 issues a fetch request to the cache control unit 1101-1. The cache control unit 1101-1 searches the cache memory in the cache control unit 1101-1 using the R1 register 1103-2 in the arithmetic unit 1103 as a program address. If there is an instruction in the cache memory, the cache control unit 1101-1 returns a response signal together with the instruction code to the instruction fetch control unit 1101-2. The instruction fetch control unit 1101-2 stores the instruction in the instruction buffer 1101-3 and increments the program address of the R1 register 1103-2 in the arithmetic unit 1103. If there is no instruction in the cache memory, the cache control unit 1101-1 issues an instruction fetch request to the memory access management unit 1104.

The decoder 1102 decodes an instruction given from the instruction fetch unit, performs read control, write control of the register in the arithmetic unit 1103, and control of the arithmetic unit, and also loads or stores (hereinafter collectively referred to as load / store). In the case of an instruction, the memory access management unit 1104 is given a load / store signal, a port number, and in the case of a load, a register number (load register number) to which the loaded data is written (reference numeral A in the drawing). The port number is a signal designating whether the memory to be accessed is on port 1 (102) or port 2 (103). The port designation method will be described with reference to the drawings.

FIG. 7 shows a port number designating circuit in the decoder 1102. 1102-1 is a port number designating circuit. When the load / store instruction is decoded, the register value designated by the address register number is selected from the n registers in the arithmetic unit by the selection circuit 1102-1-a. , Input to the comparator 1102-1-d. Comparison data 1102-1-c is input to the other input of the comparator 1102-1-d, both input values are compared according to the condition bits 1102-1-b, and the result is output as a port number. The comparison data corresponds to the address of the boundary between the system space 20 and the local memory space 40 of the 2-port microprocessor shown in FIG. 2, and the condition bit determines which side of the boundary is allocated to the system memory. Is.

  FIG. 8 shows a correspondence table between the condition bits 1102-1-b and the port number designation method. When the condition bit is “0”, port 1 is designated when the data in the address register is greater than or equal to the comparison data, and port 2 is designated otherwise. Conversely, when the condition bit is “1”, port 2 is designated when the data in the address register is greater than or equal to the comparison data, and port 1 is designated otherwise. The comparison data and the condition bit can be arbitrarily set, and thereby a memory map of a memory space accessible by the 2-port microprocessor can be arbitrarily determined.

  Returning to FIG. 6, the description of the decoder 1102 will be continued.

When the decoder 1102 requests the memory access management unit 1104 to load / store, if the port is in use or reserved, a wait signal (D) is returned, and the instruction fetch unit 1101 and the decoder 1102 enter a wait state. When the load / store request is accepted, the decoder 1102 decodes the subsequent instruction.

In the case of a load instruction, when data is read from the memory, the memory access management unit 1104 gives a wait signal (D), a forced register write signal and its register number to the decoder 1102, and the decoder 1102 executes the instruction being decoded. Is reserved, and the register read of the data read from the memory is prioritized. This circuit is shown in FIG.

  In the circuit of FIG. 9, the instruction decoding circuit 1102-2 gives register numbers to the control circuits 1102-3, 1102-4, 1102-5, 1102-6, and 1102-7 in order to read and write registers by instructions. Let it run. Upon receiving a forced register access signal and wait signal from the memory access management unit 1104, the instruction decode circuit 1102-2 stops executing the instruction, and the register read control circuit 4 (1102-6) or register write control circuit 1102-7 Reads and writes to the register specified by the forced access register number.

After the load instruction is received by the memory access management unit, there is a possibility that the register is used as a read register by subsequent instruction execution until data is written from the memory to the register. In this case, it is necessary to wait for execution of the instruction until data is loaded from the memory into the register. Therefore, the decoder 1102 gives the read register number to the memory access management unit 1104 earlier than the instruction execution, and makes a comparison with the load register number. If they match, a wait signal (D) is returned, and the execution of the instruction is waited.

  Next, returning to FIG. 6, the arithmetic unit 1103 will be described.

As described above, among the n registers, the R0 register 1103-1 and the R1 register 1103-2 are dedicated registers, and the R2 to Rn-1 registers are general-purpose registers 1103-3. The barrel shifter 1103-4 concatenates 32-bit data into 64-bit data, and outputs 32-bit data generated by shifting the data by an amount specified by a 6-bit shift number. The 3-operand LU 1103-5 performs 256 kinds of logical operations between the three input data. The ALU 1103-6 performs arithmetic logic operations between two input data. There are four internal buses for reading (R3B, R2B, R1B, R0B) and one for writing (WB), among which R1B is the number of shifts of the barrel shifter 1103-4 and the operation of three operands LU1103-5 Used to give mode. When executing a store instruction, R2B is used for address transfer and R3B is used for data transfer. When executing the load instruction, R2B also uses WB for address transfer and WB for data transfer.

  Next, the memory access management unit 1104 will be described with reference to FIG.

First, the load / store management circuit 1104-2 will be described. 1104-2-a is a 3-bit status register 1 indicating the status being executed at port 1, F1 means instruction fetch, L1 is load, and S1 is store. If “1” is set, it means that the operation is in progress. 1104-2-b is a register for storing a register number to which data is written by executing a load instruction.

  Similarly, the port 2 has a status register 2 (1104-2-c) and a load register number register 2 (1104-2-d). However, the status register 2 (1104-2-c) is a 4-bit register, and further has a bit I indicating that the interface is being executed in addition to the bits F2, L2, and S2.

When a load / store request and port number are given from the decoder 1102, the status registers 1104-2-a and 1104-2-c of the specified port are checked, and if the port is in operation, it means that the port is in use immediately To the OR circuit 1104-5. As a result, a wait signal is output and waits for execution of the load / store instruction to be executed. When the status registers 1104-2-a and 1104-2-c are all “0”, the load or store bit is set to “1”. In the case of a load request, the load register number output from the decoder is written to the load register number registers 1104-2-b and 1104-2-d of the designated port.

  The load / store management circuit 1104-2 gives a load or store instruction to a designated port. Also, a control signal for writing an address to an address buffer in the port is output. In the case of store, a control signal for writing data to the data buffer in the port is also output.

  Memory access occurs not only in load / store instructions, but also when an instruction cache miss occurs in the instruction fetch unit. The instruction fetch unit outputs an instruction fetch request and a port number. The load / store management circuit 1104-2 checks the status registers 1104-2-a and 1104-2-c of the designated port. If the port is not used, a read signal of the program address is given to the instruction fetch unit, and the address buffer in the port is written.

When an acknowledge is returned from the corresponding port, in the case of a store instruction, the store bit S1 or S2 of the status register 1104-2-a or 1104-2-c of that port is cleared to “0”. In the case of a load instruction, the register forced access circuit 1104-3 is instructed to process, and the load bit L1 or L2 of the status register 1104-2-a or 1104-2-c of that port is cleared to “0”. The load / store management circuit 1104-2 also operates when the local bus is accessed by the CPU. When a bus interface request is received from port 1, as soon as port 2 becomes unused, bit I of status register 2 (1104-2-c) is set, and bus interface ready is returned to port 1. When the use of the CPU local bus is completed and the bus interface request is canceled, the interface bit I of the status register 1104-2-c is cleared.

  A register forced access circuit 1104-3 receives a load register request and a load register number from the load / store management circuit 1104-2 after data is written from the memory to the data buffer in the port by execution of the load instruction. This causes the decoder 1102 to execute forced register write. At this time, read control of the data buffer in the port is also performed.

  The register forced access circuit 1104-3 also operates when the CPU accesses a register in the 2-port microprocessor. When the CPU register write signal or read signal and the register number are received, the decoder 1102 is caused to execute forced register write or read. At this time, writing / reading control of the data buffer 1202-1 for temporarily storing read data or write data of the CPU in the port 1 is also performed.

Reference numeral 1104-4 denotes a bus switch control circuit, which performs bus connection control for data transfer between the arithmetic unit and each port during load / store execution.

  Reference numeral 1104-1 denotes a register read prohibiting circuit which receives a register number to be read from the decoder 1102 at a timing earlier than execution and compares it with the load register number held in the load / store management circuit 1104-2. Since the arithmetic unit 1103 has four read buses, a maximum of four read register numbers are compared with load register numbers. If there is a matching number, the instruction execution to be executed is weighted.

  Next, returning to FIG. 6, the port 1 (102) will be described.

Port 1 (102) has a memory access unit 1201, a CPU response unit 1202,
It consists of an address latch 1203, a data latch 1204, and a terminal 1205.

  In response to the load / store instruction (G-1) from the memory access management unit 1104, the memory access unit 1201 executes access to the system memory 10. An address buffer 1 (1201-1) and a W data buffer 1 (1201-2) are provided to hold the address and store data given from the arithmetic unit 1103. In addition, an R data buffer 1 (1201-3) is provided to hold data read from the system memory 10.

The memory access unit 1201 first obtains the right to use the system bus 9 prior to memory access. When a response is received from the system memory 10 after acquiring the bus use right and starting access, an acknowledge (G-2) is returned to the memory access management unit 1104. In the case of loading, reading (G-3) of the R data buffer 1 (1201-3) is performed from the memory access management unit 1104.

  The CPU response unit 1202 operates when the CPU 8 accesses the registers 1103-1 to 1103-3 in the 2-port microprocessor and accesses the local memory 3 or the frame memory 4.

In the case of register access, a register access signal and a register number (H-1) are output to the memory access management unit 1104. In the case of register write, the memory access management unit 1104 waits for the instruction fetch unit 1101 and the decoder 1102, reads the data in the CPU data buffer 1202-1 to the bus MRB (H-2), and forcibly writes to the designated register. I do. In the case of register reading, the memory access management unit 1104 also waits for the instruction fetch unit 1101 and the decoder 1102, forcibly reads the register, and writes it to the CPU data buffer 1202-1 (H-3). The CPU response unit 1202 writes data to the latch 1204 and returns an acknowledge to the CPU to read data.

When the CPU accesses the local memory 3 and the frame memory 4, the CPU response unit outputs a bus interface request (I-1) to the memory access management unit 1104. When it is found that the local bus 2 is free in the next memory cycle, the memory access management unit 1104 returns a bus interface ready (I-2). CP
The U response unit 1202 outputs a load or store signal to the memory access unit 1301 of the port 2 (103), and transfers the address from the latch 1203 in the port 1 (102) to the latch 1302 in the port 2 (103). In the case of store, data is transferred from the latch 1204 in the port 1 (102) to the latch 1303 in the port 2 (103). Access to the local memory 3 and the frame memory 4 is executed by the memory access unit 2 (1301). In the case of storing, the CPU response unit 1202 returns an acknowledge to the CPU 8 when the memory access is started and ends the CPU 8 bus cycle. In the case of loading, after the memory access is completed, the data read into the latch 1303 is transferred to the latch 1204 in the port 1 (102), and an acknowledge is returned to the CPU 8 to read the data from the system bus 9.

  Next, the port 2 (103) will be described.

Port 2 (103) includes memory access unit 2 (1301), address latch 1302,
It consists of a data latch 1303 and a terminal 1304.

The memory access unit 2 (1301) executes access to the local memory 3 and the frame memory 4 in response to an instruction from the memory access management unit 1104 or the CPU response unit 1202. In order to hold an address and store data given from the arithmetic unit 1103, an address buffer 2 (1301-1) and a W data buffer 2 (1301-2) are provided. In addition, an R data buffer 2 (1301-3) is provided to hold data read from the local memory 3 and the frame memory 4. The local bus 2 is a synchronous bus and uses six times the internal clock as one memory cycle.

  Next, simultaneous access to two memories of a 2-port microprocessor will be described with reference to FIG.

As a result of decoding the instruction n fetched from the instruction cache with the internal clock k, it is assumed that the instruction is a load instruction and port 1 is designated. The memory access management unit checks the operation status of the port 1, and when it is determined that it is empty, outputs a load 1 (reference numeral 1 in FIG. 11) to the memory access unit 1. The arithmetic unit reads the contents of the register designated as the address register to the bus, and the memory access management unit connects the bus switch to write the address on the bus to the address buffer 1 (2).

  The memory access unit 1 requests acquisition of the system bus. When the bus right is granted, the memory access unit 1 outputs the memory address from the address buffer 1 to the system bus and executes read access to the system memory as indicated by the arrow 3. When a response is returned from the system memory, an acknowledge 1 (4) is returned to the memory access management unit. Further, data is read from the system bus into the R data buffer 1 as indicated by an arrow 5. Upon receipt of Acknowledge 1 (4), the memory access management unit forcibly writes to the register in the arithmetic unit and withdraws Load 1 (6).

  On the other hand, it is assumed that the instruction n + 1 fetched with the internal clock k + 1 is a load instruction to the port 2. The memory access management unit checks the operation status of the port 2 and outputs load 2 (11) to the memory access unit 2. The arithmetic unit reads the contents of the register designated as the address register to the bus, and the memory access management unit writes it in the address buffer of the memory access unit 2 (12). The memory access unit 2 outputs a memory address in a memory cycle starting at clock k + 7 (13), and reads data into the R data buffer 2 at clock k + 11 (15). The memory access management unit reads the R data buffer 2 according to the acknowledge 2 (14) of the clock k + 10, and forcibly writes to the register in the arithmetic unit.

  As described above, the 2-port microprocessor has a function in which the memory access management unit manages the operation state of the two ports and performs register forced writing of data read from the memory, thereby simultaneously using the two ports. Can be accessed.

  Next, register access in the 2-port microprocessor of the CPU will be described.

  FIG. 12 shows a time chart in which the CPU reads the contents of the R0 register in the 2-port microprocessor, modifies it, and writes it again into the R0 register. When the external decoder 12 receives a register read request from the CPU, the CPU response unit outputs a CPU register read signal (1 in FIG. 12) and a register number to the memory access management unit. In response to this, the memory access management unit immediately waits for the instruction fetch unit and the decoder (in the figure, the instruction j + 1 is weighted), forcibly reads the R0 register in the arithmetic unit, and executes the CPU data buffer. Write to (2). The CPU response unit outputs the data in the CPU data buffer to the system bus and returns a response to the CPU. The CPU modifies the read data, and subsequently starts a write cycle.

Upon receiving the CPU register write request, the CPU response unit reads data on the system bus into the CPU data buffer (11), and outputs a CPU register write signal and a register number to the memory access management unit (12). The memory access management unit immediately waits for the instruction fetch unit and the decoder (in the figure, the instruction k + 1 is waited), and forcibly writes to the R0 register in the arithmetic unit (13).

As can be seen from the microinstruction execution stage shown in the figure, forced read (
2) is executed in the next cycle to which the CPU register read signal (1) is given, and the forced write (13) is executed in the second cycle after the CPU register write signal (12) is given.

  Next, access to the local memory and frame memory by the CPU will be described.

  FIG. 13 shows a time chart when the CPU performs read access to the local memory. When a CPU local memory access request is received by the external decoder, the CPU response unit outputs a bus interface request (1) to the memory access management unit.

  The memory access management unit checks the operation status of the port 2. When the acknowledge 2 (2) is returned from the memory access unit 2 at the clock k + 4 and the status register of the port 2 in the memory access management unit is cleared, the bus interface request is accepted, the bit I of the status register is set, and the CPU Return the bus interface ready to the response unit (3). The CPU response unit cancels the bus interface request (4), transfers the memory address read into the address latch in port 1 to the address latch in port 2 (5), and issues a load request to the memory access unit 2. The memory access unit 2 reads data from the local memory and returns an acknowledge to the CPU response unit (6). The CPU response unit transfers the data read into the data latch in port 2 to the data latch in port 1 and outputs it to the system bus (7). In response to the response from port 1, the CPU reads data on the system bus.

  Next, the read modify write instruction of the 2-port microprocessor will be described.

  This instruction is an instruction for performing an operation on the data read from the memory and writing the result back to the original memory address in two consecutive memory cycles. First, a schematic description of the drawings to be used will be given. FIG. 14 shows signal transmission between the units during the read cycle of the read-modify-write instruction. FIG. 15 shows signal transmission between the units during the following modify write cycle. FIG. 16 is a time chart of the operations of FIGS. 14 and 15. FIG. 17 is a conceptual diagram of the microprocessor of the present invention using a modify buffer.

  First, the read cycle will be described with reference to FIG. 14 and FIG.

When the instruction decoder decodes the read-modify-write instruction (1 in FIGS. 14 and 16) fetched with the internal clock k, it immediately returns a wait signal (2) to the instruction fetch unit. This signal continues to be output to the instruction fetch unit until modification is executed. The instruction decoder causes the contents of the Ri register to be output as a memory address to R2B, and gives a load request, a store request, and a port number to the memory access management unit (3). Further, the contents of the Rs register are output to R3B and taken into the modify buffer 1102-9 inside the instruction decoder (4). On the other hand, the memory access management unit that has received the load / store request sets both the load bit and the store bit of the status register of the designated port to “1”, outputs the load signal (7), and the bus switch. (5) and write the memory address to the address buffer (6). The designated port latches the memory address of the address buffer (8), outputs it to the memory (9), and starts a read cycle. When data is read from the memory, the port latches it (10), reads it into the R data buffer (11), and returns an acknowledge (12) to the memory access management unit. The memory access management unit gives a forced write signal to the instruction decoder (13), controls connection of the bus switch, and writes the data read from the R data buffer to the Rq register (14).

  Subsequent processing will be described with reference to FIGS. 15 and 16.

  The memory access management unit resets the load bit of the status register to “0” and gives a store signal to the port (15 in FIGS. 15 and 16). The port latches the memory address of the address buffer (16), outputs it to the memory (17), and starts a write cycle.

  The instruction decoder cancels the wait signal to the instruction fetch unit (18), and causes the arithmetic unit to execute the instruction in the modify buffer (19). In this example, the contents of both the Rq register and the Rr register are operated by the ALU, and the result is stored in the Rq register.

  The memory access management unit controls connection of the bus switch at the timing when the ALU outputs the operation result (20), and writes the data on the WB to the W data buffer in the port (21).

  The port latches the data in the W data buffer (22) and outputs it to the memory (23). Also, an acknowledge (24) is returned to the memory access management unit, and the store bit of the status register is cleared to “0”.

  As shown in the conceptual diagram of FIG. 17, a modification buffer that holds subordinate instructions set in any register in advance is provided separately from the normal instruction buffer that holds program instructions. Accordingly, when it is necessary to execute the sub instruction, the instruction in the modify buffer is immediately decoded, and as can be seen from the time chart of FIG. Can be adapted. Further, an instruction fetched into the modify buffer can be read from any register R2 to Rn-1. In FIG. 17, in order to clarify the concept, the modify buffer is shown as a separate block from the decoder.

  Next, a rectangular transfer method from the system memory to the frame memory will be described with reference to FIG.

  10-1 represents the system memory 10 in the XY coordinate space. The transfer source memory width MWS is the width of the XY coordinate space 10-1 of the system memory that is the transfer source of the rectangular area. ORGS is the origin of the XY coordinate space 10-1 of the transfer source, and its value is a bit address on the system memory 10. Reference numeral 10-2 denotes a transfer source rectangular area, Xss and Yss are the X coordinate and Y coordinate of the transfer start position, and Xse and Yse are the X coordinate and Y coordinate of the transfer end position, respectively.

Reference numeral 4-1 represents the frame memory 4 in the XY coordinate space. The transfer destination memory width MWD is the XY coordinate space 4-1 of the frame memory that is the transfer destination of the rectangular area.
Width. The ORGD is the origin of the transfer destination XY coordinate space 4-1, and the value is a bit address on the frame memory 4. Reference numeral 4-2 denotes a transfer destination rectangular area, and Xds and Yds are the X coordinate and Y coordinate of the transfer start position, respectively.

  First, as indicated by reference numeral 50 in the figure, the CPU 8 generates a work list on the system memory 10 that includes the top address of the graphic transfer program and the top address of the graphic parameter. Also, parameters necessary for graphic transfer are generated at successive addresses after the address indicated by the parameter start address in the work list.

Next, when the CPU 8 starts up (60), the 2-port microprocessor 1 reads the head address of the program to be executed from the work list and fetches the graphic transfer program from the local memory 3 (70). The transfer source address of the rectangular area is calculated from the coordinate value read from the system memory 10, the ORGS, and the transfer source memory width (80). Similarly, the transfer destination address of the rectangular area is calculated from the coordinate value read from the frame memory 4, the ORGD, and the transfer destination memory width (80).

  In order to perform data transfer involving logical operation between the data in the transfer source rectangular area and the data in the transfer destination rectangular area, the system memory is used by using the read modify write instruction described in FIGS. Data calculation is performed between the transfer source data (90-1) read from 10 and the data (90-2) in the frame memory as the transfer destination, and the result is written to the transfer destination address (90-3). By executing the address calculation and the data calculation for the rectangular area, the rectangular area can be transferred from the system memory 10 to the frame memory 4 at high speed.

Although the outline of the configuration of the arithmetic unit has been described with reference to FIG. 6, FIG. 19 shows a specific configuration of the arithmetic unit used for data transfer of this rectangular area for reference. The specific components of the arithmetic unit are a register that stores the number of words (memory width) in the X direction of the bitmap memory, and three rectangular areas defined on the bitmap memory (transfer source area, pattern area, and transfer destination area) ) Word address registers (transfer source address register, pattern address register, transfer destination address register), transfer source shift number register for storing the bit position difference between the transfer source area and the transfer destination area, and the pattern area Pattern shift number register that stores the bit position difference of the transfer destination area, barrel shifter that shifts the transfer source data based on the transfer source shift number register, or shifts the pattern data based on the pattern shift number register, and after the shift 3-operand L that performs a logical operation between the transfer source data, pattern data, and transfer destination data When the left end of the transfer destination area, at the right, and mask means for designating a write prohibit area, based on the mask means, made of a synthetic circuit for synthesizing the arithmetic operation result and the destination data.

  Although only the preferred embodiments of the invention have been described above, various modifications can be made without departing from the spirit of the invention. For example, the configuration of a microprocessor using a modify buffer does not necessarily require two ports, and can be applied to a conventional one-port processor. Although only the graphic processing device has been described, it can be used as a processor dedicated to a specific process such as an application involving data transfer between separated buses, such as printer control and communication control.

1 is a block diagram of a graphics processing apparatus using a 2-port microprocessor of the present invention. It is a memory map of the apparatus of FIG. It is explanatory drawing of the internal register of the processor 1 of FIG. It is a memory map of the command and program of the processor 1 of FIG. It is an operation | movement flowchart of the processor 1 of FIG. It is a block diagram which shows the internal structure of the processor 1 of FIG. FIG. 10 is a block diagram of a port number designation circuit in the decoder 1102 in FIG. FIG. 9 is an operation explanatory diagram of the circuit of FIG. 7. FIG. 10 is a block diagram of a register forced access execution circuit in the decoder 1102 in FIG. FIG. 7 is a block diagram showing an internal configuration of a memory access management unit 1104 in FIG. 7 is a memory access time chart of the processor of FIG. 7 is a memory access time chart of the processor of FIG. 7 is a memory access time chart of the processor of FIG. It is operation | movement explanatory drawing of a read modify write. It is operation | movement explanatory drawing of a read modify write. It is operation | movement explanatory drawing of a read modify write. FIG. 3 is a conceptual diagram of the present invention using a modify buffer. It is explanatory drawing of the figure transfer from a system memory to a frame memory. It is a block diagram which shows the detail of the arithmetic unit in a 2 port microprocessor.

Explanation of symbols

1 ... 2 port microprocessor, 2 ... local bus, 3 ... local memory, 4 ... frame memory, 6 ... CRT, 8 ... CPU, 9 ... system bus, 101 ... processor, 102 ... port 1, 103 ... port 2, 1101 ... instruction fetch unit, 1102 ... decoder, 1103 ... arithmetic unit, 1104 ... memory management unit.

Claims (3)

An instruction fetch unit that fetches an instruction, a decoder that decodes the fetched instruction, and a processor unit that includes an arithmetic unit that executes the decoded instruction;
A first port for transmitting and receiving addresses, data and control signals to and from the system memory;
A second port for exchanging addresses, data and control signals with the frame memory;
A first address buffer capable of writing from the processor unit and reading to the first port; a first address buffer capable of reading from, writing to, and reading instructions from the first port; A first memory access unit comprising a data buffer;
A second address buffer capable of writing from and reading to the second port; a second address buffer capable of reading from and writing to the second port; and instruction reading by the processor unit A second memory access unit comprising: a data buffer;
When the first port is designated in accordance with a memory access request and a port designation signal from the processor unit, address transfer from the first address buffer to the system memory, the first data buffer, and the system Data transfer between memories is controlled. On the other hand, when the second port is designated, address transfer from the second address buffer to the frame memory and between the second data buffer and the frame memory are controlled. A memory access management unit for controlling the data transfer of
The instruction fetch unit can perform an instruction fetch with respect to an instruction stored in the system memory and an instruction stored in the frame memory via the memory access management unit .
The first memory access unit can perform data access to the system memory; and
The microprocessor according to claim 2, wherein the second memory access unit can perform data access to the frame memory . A microprocessor according to claim 1 , comprising:
The microprocessor according to claim 1, wherein the first and second data buffers are writable by the processor. A microprocessor according to claim 1 or 2,
The instruction fetch unit is
An instruction buffer to hold fetched instructions;
A modification buffer for holding a modification instruction prepared in advance;
The decoder
When the result of decoding the instruction held in the instruction buffer is a read-modify-write instruction, a load request, a store request, and a port designation signal are given to the access management unit, and the modify instruction held in the modify buffer is Decrypt and have the arithmetic unit execute it,
The access management unit is:
In accordance with the load request, store request, and port designation signal from the processor unit, a read cycle is started, and the data stored in the memory corresponding to the designated port is transferred to the data buffer corresponding to the designated port. , In the next write cycle of the read cycle, the operation result of the operation unit stored in the data buffer corresponding to the designated port is transferred to the memory corresponding to the designated port,
The arithmetic unit is
Data is stored in the data buffer corresponding to the designated port in the read cycle in accordance with a modify instruction from the decoder, and the result of the computation in the write cycle is the data corresponding to the designated port. A microprocessor characterized by being stored in a buffer.

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