JP3833371B2 - IC test equipment cycle / timing generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a period / timing generator for an IC test apparatus.
[0002]
[Prior art]
(1) When the reference clock period Tc given to the period / timing generator is represented by 2 ^p (p = 0, 1, 2,...) NS, the reference clock period Tc given to the period / timing generator is represented by 2 ^p nS. In this case, since the period / timing data given to the period / timing generator from the system controller is a binary number (binary code), the bit weight is 2 ^m (m = 0, ± 1, ± 2,...) in so represented, as discussed in the following example, the cycle timing generator can be easily configured using a mosquito-down data and the phase accumulator.
[0003]
FIG. 4B shows a period / timing generator that operates with a reference clock having a Tc = 2 ² = 4 nS period (frequency fr = 250 MHz). Taking the case where the input binary data of period / timing represents 11.13125 (nS) as an example, this binary data is data as shown in FIG. 4A. Since the reference clock CLK supplied to the down counter 3 has a period of 4 nS, 1LSB of this counter corresponds to 4 = 2 ² nS. Therefore, it is easy to convert the cycle / timing binary data into the corresponding time by the down counter. is there. Therefore, among the binary data representing 11.13125nS in FIG. 4A, the data of digits 2 ² to 2 ¹⁰ having a weight coefficient of 2 ² (nS) or more is preset in the down counter 3, and the weight coefficient is less than 2 ^2. inputting the digits of data to be 2 ¹ to 2 ^-5 to phase accumulator 4.
[0004]
The phase accumulator 4 includes an adder 5 and a D-type FF (flip-flop) 6. The carry Dc of the adder 5 (Dc “1” represents 2 ² = 4 nS) is applied to the hold terminal of the down counter 3. If the input data of the hold terminal is “1”, even if a clock pulse is input, the count value is not lowered and the previous value is held. The parallel output of the down counter 3 is supplied to a zero detector 7, and when zero is detected, a detection pulse is output (FIG. 6A), is supplied to the variable delay circuit 8, and the enable (EN) terminal of the D-FF 6 and It is given to the load (LOAD) terminal of the down counter 3. Then, data of 2 ² to 2 ¹⁰ digits of the cycle / timing binary data is preset in the down counter 3. In addition, latch data (data of 2 ¹ to 2 ⁻⁵ digits of 4 nS or less) is supplied from the D-FF 6 to the variable delay circuit 8 and fed back to the adder 5 (FIG. 6B).
[0005]
For simplification, considering the state before the carry Dc (representing 4 nS) from the adder 5, the interval between the detection pulse of the zero detector 7 and the previous detection pulse is 2 ² to 2 ¹⁰ . The time T is represented by digit data, and the resolution is 4 nS. The data related to the time interval of less than 4 nS is 2 ¹ to 2 ^-5 digit data (Δ, 2Δ, 3Δ,...) Given from the D-FF 6, and the delay amount of the variable delay circuit 8 is the output of the D-FF 6. Set to data. Therefore, the time interval between the output pulses of the variable delay circuit 8, that is, the period / period of the timing signal is the time (T + Δ = 11.3125 nS) represented by the data of 2 ⁻⁵ to 2 ¹⁰ digits (FIG. 6C).
[0006]
(2) When the reference clock period Tc given to the period / timing generator is expressed by X × 2 ^q (q = 0, 1, 2,...) NS other than 2 ^p nS, the value that the reference clock period cannot be expressed by 2 ^p For example, if 5 nS (X = 5, q = 0, fr = 200 MHz), 1 LSB of the down counter 3 is 5 nS. Therefore, the period / timing data in FIG. 4A is not directly applied to the period / timing generator in which the reference clock period in FIG. 4B is changed to 5 nS, and the weight of the binary data “1” (the first digit) It must be converted into binary data such that (weight) is 5 = 5 × 2 ⁰ (nS). Generally speaking, data must be converted so that the weighting coefficient of each digit is 5 × 2 ^q (q = 0, 1, 2,...). For this purpose, a period / timing generator shown in FIG. 5 was conceived at a stage prior to obtaining the present invention.
[0007]
(A) At initialization, the selection signal SEL of the system controller 12 is set to “1”, binary data WD to be written to the memory is input to the data conversion ROM 19, and the weight of each digit is expressed by 5 × 2 ^q from the data conversion ROM. Write data WD ′ converted to binary code is output and input to the period / timing memory 20. On the other hand, the address data ad given from the system controller 12 is given to the address terminal A of the memory 20 through the selector 18, and the data WD 'is written to the address.
[0008]
When the system controller 12 reads data from the memory 20, when the address data ad is supplied to the memory 20, the corresponding read data RD 'is output from the memory, and is input to the Di terminal of the data conversion ROM 19 through the selector 21. Binary data RD and supplied to the system controller 12 from the DI / O terminal.
[0009]
(B) At the time of actual operation At the time of actual operation, the selection signal SEL = “ 0 ” is set, and the address data AD is given from the pattern generator 11 to the address terminal A of the memory 20 through the selector 18, and the corresponding data (each digit) is sent from the memory. 5 × 2 ^q ) is output, and data having a weight of 2 ² to 2 ⁻⁵ (data less than ⁵ nS) is given to the phase accumulator 4, and the weight is 5 × 2 ^{0 to} 5 ×. 2 ⁸ digit data (more data 5 nS) is preset to the down counter 3 (1LSB represents 5 nS). When the zero detector 7 detects that the output of the down counter 3 becomes zero, a detection pulse (a preset amount of data has elapsed since the start of the down count) is given to the variable delay circuit 8.
[0010]
Data with a digit less than 5 nS is accumulated by the phase accumulator 4, and data less than 5 nS is input to the variable delay circuit 8. The variable delay circuit 8 delays the input pulse by the output data of the phase accumulator and outputs it. The output of the zero detector 7 is input to the EN terminal of the D-FF 6, and data less than 5nS is accumulated again. Further, the output of the zero detector 7 is input to the LOAD terminal of the down counter 3, the data of 5nS or more is preset again, and the above operation is repeated.
[0011]
[Problems to be solved by the invention]
In the period / timing generator of FIG. 5 that operates with a reference clock having a period of X × 2 ^q nS (for example, X = 5, q = 0) other than 2 ^p nS, binary data having a weight coefficient of 2 ^m is obtained. A data conversion ROM 19 is required to convert the data into weights with a weight of X × 2 ^m ′ and vice versa. However, when the number of data bits is large, the number of ROM memories is also large, which increases the cost of the period / timing generator.
[0012]
This invention is to use the reference clock period other than 2 ^p nS, and an object thereof is to provide an economical cycle timing generator than with data conversion ROM.
[0013]
[Means for Solving the Problems]
The invention of claim 1 includes a divisor / multiplier, a period / timing memory, a down counter, a zero detector, a phase accumulator, and a variable delay circuit, and the period Tc is 2 ^p (p = p = 0, 1, 2, ...) relates to a period / timing generator of an IC test apparatus using a reference clock which cannot be expressed in nS.
[0014]
In the memory write mode, the divisor / multiplier divides the period / timing data (WD) given by the system controller by the reference clock period Tc, and data (WD ') consisting of a quotient a and a remainder b. Is written to a predetermined address of the cycle / timing memory, and in the memory read mode, the data (RD ′) read from the cycle / timing memory is multiplied by the reference clock cycle Tc to obtain the original cycle / timing data ( RD) and give it to the system controller.
[0015]
In the actual operation mode, the period / timing memory supplies the quotient a to the down counter and the remainder b to the phase accumulator in the period / timing data (RD ') of the address designated by the pattern generator. The down counter presets the quotient a every time the zero detector detects that the count value has become zero, and counts down by 1 LSB every reference clock. The zero detector generates a period / timing pulse every time it detects that the count value of the down counter becomes zero.
[0016]
The phase accumulator accumulates the remainder b each time a zero detector detects zero, and provides the accumulated value to the variable delay circuit. The variable delay circuit delays the pulse input from the zero detector by a time corresponding to the accumulated value of the phase accumulator and outputs it as a period / timing signal.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention are shown in FIGS. 1 and 2 with portions corresponding to those in FIGS. In the present invention, an inexpensive divider / multiplier 31 is used instead of the expensive data conversion ROM 19 shown in FIG. The divider / multiplier 31 includes an arithmetic data register 22, selectors 23 and 25, and an arithmetic unit 24. The arithmetic unit 24 switches to the multiplication mode when the write / read signal R / W supplied from the system controller 12 is “0”, and to the division mode when it is “1”.
[0018]
(1) As an example of the operation when writing the period / timing data into the memory, the period / timing write data WD given by the system controller 12 represents 11.125 nS, and the reference clock period Tc given from the outside is 5 nS (fr = 200 MHz).
As shown in FIG. 3A (same as FIG. 4A), the write data WD is normal binary data in which the weighting factor of each digit is expressed by 2 ^m = 4 × 2 ^m−2 , but the clock cycle is changed from 4 nS to 5 nS. Therefore, 1 LSB of the down counter 3 corresponds to 5 nS, and as described in the conventional example, among the WD digits, 2 ³ to 2 ¹⁰ = 4 × 2 ¹ to 4 × 2 ^{8 with} a weight coefficient of 5 or more. Need to be converted into a binary code WD 'whose weighting factor can be set from 5 * 2 < ⁰ > to 5 * 2 < ⁸ >. The conversion can be achieved by an arithmetic processing for dividing 11.13125 (nS) by 5 (nS) to obtain a quotient. The 5's complement necessary for the division of the binary number is obtained by inverting the binary display 0101 of 5 to 1010, and adding 0001 to this, it becomes 1011. The arithmetic unit 24 performs division using the 5's complement CD as the added value and the binary data WD of the period / timing as the added value. The 5's complement CD is set in the operation data register 22 in advance.
[0019]
It is well known to divide the period / timing WD (binary number display) by 5 (= 0101), but as shown in FIG. 3, the 5's complement CD (= 1011) from the MSB side of the WD. Are added while shifting right by 1 bit. If you get a carry, the sum of that time as the next augend ND, right shift while adding CD = 1011, LSB of CD is repeated until fit 2 ⁰ digit of ND. Further (in the example of FIG. 4, the weight of the WD / ND 2 ¹ digit) digit LSB of the sum CD = 1011 when the carry comes out gradually raised to "1". If there is no carry, “0” is used instead of “1”. Thus "1" to 2 ⁰ or more digits in the "0" binary data obtained by making a (a) is, WD (= 11.3125nS) quotient (binary number of 5 nS (= 0101) Display). This quotient is nothing but converted period / timing data having a weight of each digit of 5 × 2 ^{0 to} 5 × 2 ⁸ .
[0020]
The digit data (b) whose weight of the data WD / ND is 2 ² to 2 ⁻⁵ having a weight of 5 or less is the final value of the added value, the remainder when divided, and the size of the down counter 3 The data is less than 1 LSB (5 nS) and is given to the phase accumulator 4. The conversion data WD ′ composed of (a) and (b) thus obtained is stored in the address ad designated by the system controller 12 of the period / timing memory 20 through the selector 25.
[0021]
(2) Operation when the system controller reads data in the cycle / timing memory The signals given from the system controller 12 are address ad, SEL = “1”, and R / W = “0”. Data RD ′ at the address ad in the period / timing memory 20 is read out and input to the Di terminal of the divider / multiplier 31 via the selector 21. The divider / multiplier 31 operates in the multiplication mode and performs a conversion operation opposite to that in the division mode. Then, normal binary data RD in which the obtained weight of each digit is expressed by 2 ^m is supplied to the system controller 12 from the DI / O terminal.
[0022]
(3) Generation of cycle / timing data during actual operation In actual operation, SEL = “0”, and the address signal AD of the pattern generator 11 is sent to the address terminal A of the cycle / timing memory 20 via the selector 18. The data of the address is read out, and the data of 5 × 2 ^{0 to} 5 × 2 ⁸ digits having a weight of 5 or more is given to the down counter 3 via the selector 21 and the weight is 5 or less. Data of 2 ^{2 to} 2 ^-5 digits is supplied to the phase accumulator 4.
[0023]
Since the subsequent operation is the same as the conventional operation of FIGS. 4 and 5, detailed description is omitted. However, a detection pulse having a coarse period with a resolution of 5 nS is supplied from the zero detector 7 to the variable delay circuit 8. Entered. Further, time data less than 5 nS is supplied from the phase accumulator 4 to the variable delay circuit 8. The variable delay circuit 8 delays the input pulse by the time data.
[0024]
【The invention's effect】
{Circle around (1)} In the present invention, since a divisor / multiplier obtained at low cost is used in place of the conventional expensive data conversion ROM, the economy of the period / timing generator can be increased accordingly.
(2) In the cycle / timing generator according to the present invention, the reference clock cycle can be set without changing the external data (usually provided from software such as OS), for example, when the operation data register 22 is 4 bits. Can be selected from 5 (= 0101) nS (200 MHz), 6 (= 0110) nS (166.6 MHz), and 7 (= 0111) nS (142.8 MHz).
[0025]
{Circle around (3)} Since the reference clock cycle can be selected in various ways as described above, the range of parts selection when designing an IC test apparatus is expanded.
(4) The period / timing generator of the present invention can be widely applied to IC test apparatuses having different reference clock periods.
(5) When the number of bits of the arithmetic data register 22 is 4 bits, the reference clock cycle that can be changed is 1 nS interval (resolution: 1 nS) of 5, 6 and 7 nS. However, if the number of bits is further increased, the variable range and resolution can be increased. Can be raised. For example, if the complement CD to be added is 6 bits with a weight of 2 ^-1 to 2 ⁴ , a cycle with a resolution of 0.5 nS can be selected in the range of 5 to 15 nS, and the degree of freedom in device design is further expanded.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram of the divider / multiplier 31 of FIG.
FIG. 3 is a diagram for explaining the operation of an arithmetic unit 24 when the divider / multiplier 31 in FIG. 2 is in a division mode;
FIG. 4A is a period / timing data given to a down counter and a phase accumulator of a conventional period / timing generator, and B is a conventional period / timing generator having a reference clock period of 4 nS (fr = 250 MHz). The block diagram which shows the principal part.
FIG. 5 is a block diagram of a period / timing generator conceived at a stage before obtaining the present invention, in which a data conversion ROM is used and a reference clock period is set to 5 nS (fr = 200 MHz).
6 is a timing chart before the carry of FIG.

Claims (2)

A divisor / multiplier, a period / timing memory, a down counter, a zero detector, a phase accumulator, a variable delay circuit, and a period Tc of 2 ^p (p = 0, 1, 2,... A period / timing generator of an IC test apparatus using a reference clock that cannot be expressed in nS,
In the memory write mode, the divisor / multiplier divides the period / timing data (WD) given by the system controller by the reference clock period Tc to obtain data (WD ′) consisting of the quotient a and the remainder b. ) And write to a predetermined address of the period / timing memory ,
In the actual operation mode, the period / timing memory stores the quotient a in the down counter and the remainder b in the phase accumulator in the period / timing data (RD ′) of the address designated by the pattern generator. To supply
The down counter presets the quotient a every time the zero detector detects that its count value has become zero, and counts down by 1 LSB for each reference clock,
The zero detector generates a period / timing pulse every time it detects that the count value of the down counter becomes zero,
The phase accumulator accumulates the remainder b each time the zero detector detects zero, and gives the accumulated value to the variable delay circuit,
The variable delay circuit delays the pulse input from the zero detector by a time corresponding to the accumulated value of the phase accumulator and outputs it as a period / timing signal. -Timing generator. The period / timing generator of the IC test apparatus according to claim 1,
In the division / multiplier, an arithmetic register in which a complement CD of binary data of the cycle Tc of the reference clock is set, and cycle timing data (WD) given by the system controller are set as initial added values, An arithmetic unit for adding the complement CD of the Tc, and the complement CD is set to 1 from the MSB side of the data WD. bit When the carry is generated, the addition result at that time is used as the next added value ND, the right is shifted while adding the complement CD, and the LSB of the complement CD is 2 of the added value ND. ⁰ It repeats until it matches the digit of, and when the carry comes out, "1" is set to the digit of the weight of the data WD / ND where the LSB of the complement CD is located, and if no carry comes out, "0" instead of "1" "And thus 2 ⁰ The binary data obtained by setting “1” and “0” in the above digits is used as the quotient. a And the final value of the added value is the remainder b A cycle / timing generator for an IC test apparatus, characterized in that

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