JP3830414B2 - Semiconductor device having a booster circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a booster circuit for obtaining a high voltage from a low voltage power supply.
[0002]
[Prior art]
Conventionally, as a semiconductor device (hereinafter referred to as an IC) such as an EEPROM or a flash memory becomes a single low-voltage power supply, for example, a power supply is used so that a voltage necessary for writing or erasing stored contents is obtained inside the IC. The voltage is being boosted. For this purpose, a booster circuit such as a charge pump circuit is provided in the IC.
[0003]
This charge pump circuit includes, for example, a plurality of diode-connected MOS field effect transistors (hereinafter referred to as MOS transistors) connected in series, and a plurality of capacitors each having one storage electrode connected to the MOS transistor. Yes. Then, a power supply voltage such as 2 to 3 V is applied to the base-side MOS transistors connected in series, and the capacitors are sequentially charged by sequentially supplying a clock signal having a phase shift to the other storage electrode of the capacitor. Thus, a boosted high voltage such as 10 to 15 V is obtained from the termination-side MOS transistor.
[0004]
Insulator film thickness acting as a dielectric of this capacitor is usually formed of one kind and relatively thick so as to withstand the boosted voltage of the charge pump circuit. In this case, since the capacitance of the capacitor decreases as the insulator film thickness increases, a large area is required to obtain the required capacitance.
[0005]
Japanese Patent Application Laid-Open No. 5-28786 discloses an insulator for a low-voltage capacitor located on the base end side of a charge pump circuit as a method for reducing the necessary area of the capacitor and reducing the area occupied by the charge pump circuit. It has been proposed to reduce the film thickness and increase the thickness of the capacitor located on the terminal side in accordance with the boost voltage. The thickness of the capacitor insulator is reduced on the base side where the voltage is low. Therefore, it is possible to reduce the area occupied by the chip by that amount.
[0006]
[Problems to be solved by the invention]
However, in this booster circuit, a capacitor with a relatively thick insulator is used on the terminal side where the voltage is high, so not only a reduction in the area occupied by the chip in the capacitor on the terminal side can be expected. Rather, there was even a risk of increasing the capacitor area.
[0007]
In view of such a problem, the present invention uses a capacitor having a structure different from that of the capacitor located on the base end side as the capacitor located on the terminal end side of the charge pump circuit. Provided is a semiconductor device including a booster circuit configured to reduce not only the capacitor located in the chip but also the chip-occupying area of the terminal-side capacitor so that the chip-occupying area of the entire charge pump circuit can be reduced. With the goal.
[0008]
[Means for Solving the Problems]
A semiconductor device having a booster circuit according to a first aspect of the present invention is a MOS transistor having an input end side and an output end side, one end connected to the input end side or the output end side of the MOS transistor, and a clock supplied to the other end. A plurality of charge pump units each having a capacitor to be connected in series, a charge pump means for outputting an output voltage obtained by boosting a power supply voltage, and a semiconductor including a boost circuit having a clock generation means for generating the clock In the apparatus, a MOS capacitor is used as a capacitor of one or more charge pump units on the base end side to which the power supply voltage is input, and one or more charge pump units on the terminal end side from which the output voltage is output A first conductor film formed on the semiconductor substrate or on the well as the capacitor; A high dielectric constant film formed conductive film, characterized by using a capacitor and a second conductive film formed on the high dielectric constant film.
[0009]
According to the semiconductor device having the booster circuit of the present invention, a MOS capacitor is used on the low voltage base side and a high dielectric is used on the high voltage terminal side as the capacitors of the charge pump units connected in series. A capacitor with a rate film is used. Therefore, it is possible to reduce the chip-occupied area of the capacitor located on the base end side and the capacitor on the terminal end side as compared with the conventional case, and to reduce the chip-occupied area of the entire charge pump circuit.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a semiconductor device including a booster circuit according to the present invention will be described with reference to FIGS.
[0011]
FIG. 1 is a diagram showing a circuit configuration of a semiconductor device including a booster circuit according to the first embodiment of the present invention. FIG. 2 is a diagram schematically showing a MOS capacitor used as a capacitor of a charge pump unit (hereinafter sometimes referred to as a unit) on the low voltage side. FIG. 3 is a diagram schematically showing a floating type capacitor used as a capacitor of a unit on the high voltage side, and FIG. 4 is a diagram schematically showing a part of one example.
[0012]
In FIG. 1, each charge pump unit is composed of an N-type MOS transistor and a capacitor. The first-stage unit is composed of a transistor Q1 and a capacitor C1, the second-stage unit is composed of a transistor Q2 and a capacitor C2, and the final-stage unit is composed of a transistor Qn and a capacitor Cn.
[0013]
As for the first stage unit, the source S of the transistor Q1 is supplied with the power supply voltage Vcc and is connected to the gate G, which is a so-called diode connection. The drain D is connected to the source S of the transistor Q2 of the next stage unit, and the substrate is connected to the lowest potential point, in this example, the ground potential. The capacitor C1 has one end connected to the source S of the transistor Q1, and the other end connected to a clock line (in this case, the clock line of the first clock CLK1).
[0014]
The other ends of the capacitors C1 to Cn of each unit are connected to the clock line of the first clock CLK1 in the odd-numbered unit, and are connected to the clock line of the second clock CLK2 in the even-numbered unit.
[0015]
The number of stages n of this unit is mainly determined by the power supply voltage Vcc (for example, 3V) and the second output voltage Vout2 (for example, 12V) output from the final stage.
[0016]
The switch SW controls the operation / stop of the booster circuit in response to the operation signal ON / stop signal OFF, and has an N-type MOS transistor Q0 that is turned on or off.
[0017]
The units from the first stage units Q1, C1 to the k stage units Qk, Ck constitute the low voltage side unit group LVU, and the units from the (k + 1) stage unit Q (k + 1), C (k + 1) to the last stage units Qn, Cn Constitutes the high voltage side unit group HVU.
[0018]
A regulator Reg is provided on the output side of the low voltage side unit group LVU to output the first output voltage Vout1. The first output voltage Vout1 is a required voltage (for example, 6 V) that is higher than the power supply voltage Vcc and lower than the second output voltage Vout2, and depends on the specifications of a flash memory that requires a plurality of boosted voltages. It can be decided arbitrarily. The regulator Reg is configured by connecting a backflow prevention diode D, a current limiting resistor R, and a smoothing capacitor Co1 in series as shown in the figure.
[0019]
The clock generation circuit CG controls oscillation and stop of the clock signals CLK1 and CLK2 in accordance with the operation signal ON / stop signal OFF of the booster circuit. The first clock CLK1 and the second clock CLK2 are, for example, two-phase clocks having the same amplitude voltage as the power supply voltage Vcc, a predetermined frequency, and changing in an almost opposite phase state.
[0020]
In the booster circuit of FIG. 1, the switch SW is turned on in response to the operation signal ON, the clock generation circuit CG starts oscillating, and the first clock CLK1 and the second clock CLK2 change in an opposite phase state. Start.
[0021]
In response to the start of the oscillating operation of the first clock CLK1 and the second clock CLK2, the units simultaneously start the charge pump operation, and the power supply voltage Vcc is sequentially charged up for each unit, and the boosted first output voltage Vout1. The second output voltage Vout2 is output. These output voltages 1Vout1 and Vout2 are supplied to predetermined terminals such as a flash memory.
[0022]
FIG. 2 is a diagram schematically showing MOS capacitors used as the capacitors C1 to Ck of the low voltage side unit group LVU of FIG. 1, in which FIG. 2 (a) shows a sectional structure thereof, and FIG. 2 (b) shows a connection. The configuration is shown.
[0023]
In FIG. 2A, an N-type well Nwell is formed in a P-type substrate Psub, and an N-type high concentration region n ⁺ corresponding to the source region and drain region of the MOS transistor is formed therein. A gate insulating film 22 is formed so as to cover the upper side of the N-type well Nwell. The gate insulating film 22 is a silicon dioxide film (hereinafter referred to as an oxide film or a SiO2 film), and may be thin enough to withstand a low voltage (at least the first output voltage Vout1).
[0024]
A conductor film 21 corresponding to the gate electrode of the MOS transistor is formed on the gate insulating film 22 between the high-concentration regions n ⁺ and serves as a first storage electrode. The first storage electrode is drawn out to the terminal G. The conductor film 21 is formed of a polycrystalline silicon film (that is, a polysilicon film; polySi) formed by doping an N-type or P-type semiconductor with an impurity.
[0025]
Further, the high concentration region n ⁺ becomes the second storage electrode, and is drawn out as the terminals S and D through the contacts, respectively. Reference numerals 24 and 25 denote element isolation oxide films called LOCOS.
[0026]
In this MOS capacitor, as shown in FIG. 2B, the terminal (ie, electrode; hereinafter the same) G becomes the terminal T1 of the first storage electrode, and the terminals S and D are connected to each other to connect the second storage electrode. Terminal T2. The terminal T1 is connected to the sources of the transistors Q1 to Qk of the low voltage side unit group LVU, and the terminal T2 is connected to the clock line of the first clock CLK1 or the clock line of the second clock CLK2.
[0027]
Since the gate insulating film 22 of this MOS capacitor is a thin oxide film that can withstand a low voltage (at least about the first output voltage Vout1), the capacitance per unit area also increases. Therefore, it can be used as a capacitor of the low voltage side unit group LVU without increasing the occupied area. Further, it can be formed at the same time as the gate oxide film thickness of a MOS transistor used in a normal, ie, low voltage circuit portion.
[0028]
FIG. 3 is a diagram schematically showing capacitors used for the capacitors Ck + 1 to Cn of the high voltage side unit group HVU of FIG. 1. FIG. 3 (a) shows a sectional structure thereof, and FIG. 3 (b) shows a connection configuration. Is shown. Since these capacitors Ck + 1 to Cn need to have a structure capable of withstanding a high voltage, the MOS capacitor configuration as in the prior art requires a thick gate insulating film (oxide film). It takes a large area to obtain. In the present invention, the structure of the high voltage capacitor is made different from that of the low voltage MOS capacitor to reduce the necessary occupied area.
[0029]
In FIG. 3A, an oxide film 34 is formed on a P-type substrate Psub, and a first polysilicon film 31 is formed on the oxide film 34. A high dielectric constant film 32 made of a material having a high dielectric constant as will be described in detail later is formed on the first polysilicon film 31. Further, a second polysilicon film 33 is formed on the high dielectric constant film 32. The first polysilicon film 31 becomes the first storage electrode, the second polysilicon film 33 becomes the second storage electrode, and the terminals T1 and T2 are drawn out, respectively. This state is shown in FIG.
[0030]
The oxide film 34 is an insulating film that electrically isolates the first polysilicon film 31 from the P-type substrate Psub. The oxide film 34 can be an oxide film for element isolation (that is, LOCOS). In this case, the LOCOS for other elements, for example, the LOCOSs 24 and 25 of the MOS capacitor of FIG. 2 can be used as they are. The capacitor having the structure of FIG. 3 is referred to as a floating capacitor in this specification.
[0031]
In FIG. 3, the high dielectric constant film 32 and the second polysilicon film 33 are formed so as to exclude the right end portion of the first polysilicon film 31 in the drawing, and the first polysilicon film 31 is formed from the right end portion thereof. One electrode T1 is drawn out, and the first electrode T2 is drawn out from the left side of the center of the second polysilicon film 33 in the drawing. The extraction method of the electrodes T1 and T2 is not limited to this. For example, the high dielectric constant film 32 and the second polysilicon film 33 are formed so as to exclude both end portions of the first polysilicon film 31 in the drawing, The first electrode T <b> 1 may be drawn out from both end portions of the first polysilicon film 31, and the first electrode T <b> 2 may be drawn out from the center portion of the second polysilicon film 33. In this way, the parasitic resistance of the capacitor can be reduced, and the characteristics can be further improved.
[0032]
Here, for the high dielectric constant film 32, a material having a dielectric constant higher than that of SiO2 and having a required dielectric strength is selected. As the material, a material whose capacitance per unit area is larger than the MOS capacitors C1 to Ck of the low-voltage unit group LVU is selected from the relationship between the dielectric constant and the dielectric strength. For example, a nitride film, a Ta ₂ O ₅ film (tantalum oxide film), a TiO ₂ film (titanium oxide film), or the like can be suitably used.
[0033]
FIG. 4 is a view showing one embodiment of the high dielectric constant film in FIG. 3, and a part thereof is schematically shown.
[0034]
In FIG. 4, an oxide film 32-1 is formed on the first polysilicon film 31, and the surface of the oxide film 32-1 is nitrided using, for example, NH 3 (ammonia) to form a nitride film (or a nitrided oxide film). 32-2 is formed, an oxide film 32-3 is further formed thereon, and a second polysilicon film 33 is formed thereon. Thus, the nitride film 32-2 is provided between the oxide films 32-1 and 32-3, and the high dielectric film 32 has a three-layer structure. This three-layer structure of oxide film-nitride film-oxide film can be referred to as an ONO film as an abbreviation.
[0035]
By using this ONO film as the high dielectric film 32, it becomes easy to manufacture a floating capacitor having a high breakdown voltage and a large capacitance.
[0036]
In the floating type capacitors shown in FIGS. 3 and 4, the first and second polysilicon electrodes 31 and 33 have lower resistance values than the resistance values of the diffusion layers. Therefore, the resistance value of the capacitor is reduced, the loss accompanying charging / discharging of the capacitor can be reduced, and the time constant of charging / discharging can be shortened.
[0037]
As described above, the first conductor film (first electrode) and the second conductor film (second electrode) of the floating type capacitor are formed by doping impurities into an N-type or P-type semiconductor. It is a silicon film (that is, a polysilicon film; polySi). Thereby, since the resistance value of the polysilicon film is lower than the resistance value of the diffusion layer, the internal parasitic resistance value of the capacitor can be lowered. Therefore, the loss accompanying charging / discharging of the capacitor can be reduced, and the time constant of charging / discharging can be shortened. Furthermore, it is preferable to use Al (aluminum) as the first conductor film (first electrode) and the second conductor film (second electrode), since the internal parasitic resistance value of the capacitor can be further reduced.
[0038]
The high dielectric constant film of the floating capacitor has a three-layer structure of oxide film-nitride film-oxide film. According to this, a high dielectric constant film can be stably formed.
[0039]
In addition, as shown in FIG. 1, if a regulator including a smoothing capacitor and a backflow prevention diode is connected to a required portion of a charge pump unit in which a plurality of charge pump units are connected in series, a high voltage from the termination is generated. A required intermediate voltage can be output as another output voltage together with the output voltage. Therefore, it can be suitably used for a device that requires a plurality of boosted voltages, for example, an IC such as a flash memory.
[0040]
【The invention's effect】
According to the semiconductor device including the booster circuit according to claim 1, a MOS capacitor is used on the base end side of the low voltage as a capacitor of the charge pump unit connected in series. Since a capacitor having a dielectric constant film is used, the chip-occupied area of the entire charge pump circuit can be reduced by reducing the chip-occupying area of the capacitor located on the base end side and the capacitor on the terminal end side.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a semiconductor device including a booster circuit according to an embodiment of the present invention.
FIG. 2 is a diagram schematically showing a MOS capacitor used as a capacitor of a charge pump unit on a low voltage side.
FIG. 3 is a diagram schematically showing a floating capacitor used as a capacitor of a unit on a high voltage side.
4 is a diagram schematically showing a part of one example of the capacitor of FIG. 3;
[Explanation of symbols]
LUV Low voltage side unit group HVU High voltage side unit group Q0 to Qn MOS transistors C1 to Cn Capacitor SW Switch Reg Regulator D Diode R Resistance Co1, Co2 Smoothing capacitor CG Clock generation circuit Vout1 First output voltage Vout2 Second output voltage CLK1 First clock CLK2 Second clock 21 Polysilicon film 22 Gate insulating film (oxide film)
Nwell N-type well Psub P-type substrate 31 First polysilicon film 32 High dielectric constant film 32-1, 32-3 Oxide film 32-2 Nitride film 33 Second polysilicon films 24, 25, 34 Oxide film for element isolation ( LOCOS)

Claims (1)

A plurality of charge pump units having a MOS transistor having an input end side and an output end side and a capacitor having one end connected to the input end side or the output end side of the MOS transistor and a clock supplied to the other end are connected in series. Charge pump means for outputting an output voltage obtained by boosting the power supply voltage; and
In a semiconductor device comprising a booster circuit having a clock generating means for generating the clock,
As a capacitor of one or more charge pump units on the base end side to which the power supply voltage is input, a MOS capacitor is used,
As a capacitor of one or more charge pump units on the termination side from which the output voltage is output, a first conductor film formed on a semiconductor substrate or on a well, and formed on the first conductor film A semiconductor device comprising a booster circuit, wherein a capacitor having a high dielectric constant film and a second conductor film formed on the high dielectric constant film is used.

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