JP3829404B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrophotographic digital copying machine, a printer, and the like, and more particularly to an image processing apparatus suitable for use in outputting a high-quality halftone image.
[0002]
[Prior art]
Conventionally, a halftone image reproduction method and a triangular wave comparison method are known as methods for outputting a halftone image in an electrophotographic digital copying machine, a printer, or the like. The outline will be described below.
[0003]
<Halftone image reproduction method>
In the halftone image reproduction method, there are a dither method and a density pattern method. In these methods, as shown in FIG. 18, a density threshold value matrix corresponding to one-to-one resolution of output pixels is compared with input image data, and on / off of output pixels is controlled based on the result. The configuration is as follows. The dither method and the density pattern method are classified according to whether the correspondence between the input image data and the output image data at this time is one-to-one or one-to-multiple pixels. As shown in FIG. 19, the dither method is used when the input image data and the output image data correspond one-to-one, and the density pattern method is used when the input image data corresponds to a plurality of pixels. Here, such a density threshold value matrix is called a screen pattern.
[0004]
When each density threshold value in the screen pattern is applied to an input image signal of 8 bits (0 to 255), for example, the screen pattern shown in FIG. 19 subtracts the gradation range (0 to 255). Divide evenly by the number of pixels and set to linear quantization (rounded off). When the density pattern method shown in FIG. 19B is applied to an input image signal of 8 bits (0 to 255), as shown in FIG. 20B, each density threshold value is “8”, “ 24 ”,“ 40 ”, and so on.
[0005]
Next, the density threshold value is compared with the density of the input pixel to determine the on / off state of each subpixel. That is, the sub-pixel corresponding to the density threshold lower than the density of the input pixel is turned on, and the other sub-pixels are turned off. As an example, when the density of the input pixel is “120” as shown in FIG. 20A, the on / off state of each sub-pixel is as shown in FIG.
[0006]
By the way, when the halftone image reproduction method is adopted in a color copying machine or the like, the above-described processing may be performed for each primary color (K, Y, M, C). However, when the same screen pattern is used for each color, color unevenness occurs due to a slight positional shift, and the influence of a striped pattern (moire fringe) generated when halftone dots of each primary color overlap is increased. Therefore, as shown in FIG. 21, it is common to use four types of screen patterns having different screen angles θ and to use them corresponding to each primary color (Japanese Patent Publication No. 52-49361).
[0007]
In the field of screen printing and the like, it is known that the screen angle θ is preferably set to 0 °, 15 °, 45 ° and 75 °. However, in order to apply to a copying machine or the like, the screen angle θ must be a value that can be obtained by a rational tangent because the memory capacity is reduced by repeatedly using the same screen pattern. FIG. 22 is a conceptual diagram showing a state in which the same screen pattern is arranged. The numbers shown are density threshold numbers.
[0008]
Furthermore, it is necessary to match the number of subpixels for each primary color as much as possible. In the example shown in FIG. 21, the screen angle θ falls within a preferable range of “± 2 °” and the number of subpixels A falls within the range of “17 ± 1”, which is sufficient in practice. The screen pattern shown in FIG. 20A corresponds to that shown in FIG.
[0009]
<Triangle wave comparison method>
Next, in the triangular wave comparison method, as shown in FIG. 23A, first, the density of the input pixel is converted into an analog signal. Then, the comparator compares the triangular wave having a predetermined period with the analog signal to obtain an output pulse width signal. When the level of the analog signal is equal to or higher than the level of the triangular wave (or lower than the level), the analog signal is turned on (for example, an exposure state of laser light), and otherwise is turned off. That is, the higher the density of the input pixel, the higher the level of the analog signal, the higher the duty ratio at which the comparison result is turned on, and the higher the density of the output image.
[0010]
By the way, in the triangular wave comparison method, even when color printing is performed, a technique for providing a screen angle θ for each primary color is known in order to suppress the influence of color unevenness and moire fringes. For example, Japanese Patent Laid-Open No. 62-183670 discloses a technique for shifting the phase of a triangular wave by a certain amount every time a “1” line is advanced in the sub-scanning direction. Japanese Patent Laid-Open No. 2-296264 discloses a technique for changing the gradation reproduction characteristics every time the “1” line advances in the sub-scanning direction.
[0011]
[Problems to be solved by the invention]
However, the above-described prior art has the following various problems. First, in the halftone image reproduction method, there is a reciprocal relationship between the resolution and the number of reproduced gradations. For example, if the resolution of the output device is “400 dpi (dots / inch)” and a resolution of “200 lpi (lines / inch)” is desired, the screen size needs to be “2 × 2”. . That is, the reproduction gradation number is “4”, and only a very low gradation number can be obtained. Conversely, in order to set the number of reproduced gradations to “64”, the screen size needs to be “8 × 8”. For this reason, the resolution becomes “400/8 = 50 lpi”, which is greatly reduced.
[0012]
When screen printing is performed, the output device originally has a resolution of about “4000 dpi”, so even if the number of reproduced gradations is increased, the roughness of the image is not noticeable with the naked eye. However, in the electrophotographic system, since the resolution of about “400 dpi to 600 dpi” is the limit, the above-described problem occurs.
[0013]
On the other hand, in the triangular wave comparison method, there is no reciprocal relationship between the resolution and the number of reproduced gradations. However, it is not practical to provide the screen angle θ for each primary color by the technique described above. The reason for this will be described with reference to FIG. In FIG. 24A, S1 is an analog signal, and this analog signal S1 is compared with a triangular wave signal. The phase of the triangular wave signal is gradually delayed for each “1” line in the sub-scanning direction.
[0014]
The exposure pattern of the laser obtained by this comparison result is shown in FIG. As is apparent from FIG. 6B, if the phase of the triangular wave is shifted for each “1” line in the sub-scanning direction, the halftone dots or the screen shape is liable to be broken or interrupted. This adversely affects gradation characteristics and graininess reproduction, and it is difficult to obtain satisfactory image quality. Furthermore, the screen angle θ and the number of screen lines (resolution) were also constrained by the period of the triangular wave pattern used, and there were few degrees of freedom.
[0015]
The present invention has been made in view of the above-described circumstances, and there is no conflict between the resolution and the number of reproduced gradations, and the degree of freedom of the screen shape can be increased, and a higher quality output image can be stabilized. An object of the present invention is to provide an image processing apparatus that can be obtained.
[0016]
[Means for Solving the Problems]
In order to solve the above-described problems, in the invention described in claim 1, in the image processing apparatus that converts the input image signal and generates the output image signal to the image recording apparatus, the halftone screen is grown and the grayscale is reproduced. Halftone dot pattern storage means for storing a halftone dot pattern expressing the weight of the image, gradation correction control pattern storage means for storing a gradation correction control parameter corresponding to the halftone dot pattern, the input image signal and the halftone dot Based on the halftone dot pattern stored in the pattern storage means, the intermediate gradation data output means for converting the input image signal into intermediate gradation data and the gradation characteristics of the intermediate gradation data are different from each other. A plurality of gradation correction means for correcting by parameters, and the plurality of gradation correction means based on the gradation correction control pattern stored in the gradation correction control pattern storage means Characterized by comprising an output means for selectively outputting the halftone data corrected by either.
[0017]
According to this invention, the halftone data output means converts the input image signal into halftone data based on the comparison result between the input image signal and the halftone dot pattern stored in the halftone dot pattern storage means. Convert to The plurality of gradation correction means correct the gradation characteristics of the intermediate gradation data with different parameters, using different parameters. The output means selects and outputs the intermediate gradation data corrected by any of the plurality of gradation correction means based on the gradation correction control pattern stored in the gradation correction control pattern storage means. Therefore, there is no reciprocal relationship between the resolution and the number of reproduced gradations, and the degree of freedom of the screen shape can be increased, so that a higher quality output image can be stably obtained.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings.
[0019]
A. Configuration of the first embodiment
FIG. 1 is a block diagram showing the configuration of the image processing apparatus according to the first embodiment of the present invention. In the figure, the image processing apparatus includes a screen angle generation pattern generation circuit 10, an output pixel value calculation circuit 20, and a waveform control multilevel conversion circuit 30. Hereinafter, the configuration of each unit when n = 1 and m = 1 will be described.
[0020]
A-1. Screen angle generation pattern generation circuit
The screen angle generation pattern generation circuit 10 generates a halftone dot pattern having different screen angles for each of C, M, Y, and K at the time of color print output. The sub-scanning direction address counter 102 counts the horizontal synchronization signal H_SYNC and outputs the count value. The main scanning direction address counter 104 counts the pixel clock CLK and outputs the count value.
[0021]
The reset circuit 105 sets the main scanning direction address counter 104 when the horizontal synchronization signal H_SYNC is input to the screen angle generation pattern generation circuit 10 or when the count value of the main scanning direction address counter 104 reaches a predetermined reset value. Reset. As a result, the counter value returns to “0”.
[0022]
For example, in the case of the 15 ° screen shown in FIG. 21B, the developed pattern shown in FIG. 22 is generated by developing the screen by the method disclosed in Japanese Patent Publication No. 52-49361. To do. The L × L rectangular matrix generated at this time is repeatedly used every L pixels in the main scanning direction and every L lines in the sub-scanning direction, thereby generating a screen filled with a desired screen pattern. it can. The reset value in the main scanning direction at this time is “17”.
[0023]
Similarly, when the count value of the sub-scanning direction address counter 102 reaches the reset value (in this case, the reset value in the sub-scanning direction is also “17”), the reset circuit 105 sets the sub-scanning direction address counter 102 to Reset. The halftone dot pattern memory 103 has a memory capacity of “17 × 17 bytes” in this embodiment, and is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104. The halftone dot pattern memory 103 stores the contents of the screen patterns used. That is, the expansion pattern of the L × L rectangular matrix shown in FIG. 22 is stored. In this way, the halftone dot pattern memory 103 outputs a halftone dot pattern value S corresponding to the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104.
[0024]
Next, an example of halftone dot pattern values actually used is shown in FIG. The halftone dot pattern value shown in FIG. 2 corresponds to the screen angle θ of “0 °” shown in FIG. 21A, is converted in the following procedure, and is then stored in the actual halftone dot pattern memory 103. . First, a matrix obtained by subtracting “1” from each pattern value in the matrix shown in FIG. 21A is obtained, and then a step gain value “16 (= 256 / (4 × 4) obtained from a 4 × 4 matrix is obtained. )) ”Is multiplied by the previously obtained matrix to determine the halftone dot pattern to be actually stored in the halftone dot pattern memory 103. As a result, these values in the matrix indicate the ratio (weight) to the whole (256) when the pixel is turned on (black). That is, 1/16 × 256 = 16 when one dot is turned on, and 2/16 × 256 = 32 when two dots are turned on. However, in the halftone dot pattern shown in FIG. 2, as described above, “1” is subtracted from the matrix shown in FIG. Yes.
[0025]
Next, when the screen pattern shown in FIG. 21B is used, the waveform control pattern memory 111 has a memory capacity of “17 × 17 bits” in order to store the L × L matrix shown in FIG. Then, corresponding to each halftone dot pattern in the halftone dot pattern memory 103, a 2-bit waveform pattern indicating any one of “0”, “1”, and “2” as shown in FIG. . At this time, “0” is a waveform pattern when dots are grown from the right side, “1” is a waveform pattern when growing from the left side, and “2” is a waveform pattern when growing from the middle. However, it is not limited to this value. In the present embodiment, since there are a total of three types of patterns, a 17-bit × 17-bit × 2-bit waveform pattern memory is required. Then, the waveform pattern of the waveform control pattern memory 111 is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104, and is output as the screen switching signal SCS. Here, an example of a waveform pattern corresponding to each halftone dot pattern is shown in FIG.
[0026]
Next, the gradation control pattern memory 112 has a memory capacity of “17 × 17 bits” in order to store an L × L rectangular matrix, and corresponds to each halftone pattern of the halftone pattern memory 103. , “1 bit” gradation control pattern indicating either “0” or “1” is stored. The gradation control pattern in the gradation control pattern memory 112 is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104 and is output to the output pixel value calculation circuit 20.
[0027]
A-2. Output pixel value calculation circuit
Next, the configuration of the output pixel value calculation circuit 20 will be described with reference to FIG. In the figure, a subtractor 201 subtracts a halftone dot pattern signal S from an input image signal (pixel density) V. The gradation gain register 210 stores a gradation gain G. Note that the gradation gain G is set to be equal to the number of subpixels (“16”, “17”, or “18” in the above example) of the halftone dot pattern of FIG. Next, the multiplier 202 multiplies the subtraction value N in the subtractor 201 and the gradation gain G, and outputs the multiplication result M. Each of the comparators 203 and 204 determines whether the multiplication result M is smaller than “0” or larger than 255, and inputs two bits obtained by adding one bit of each determination result to the decoder 208, and selects the selector 209. Select signal to On the other hand, the result of the multiplier 202 is input to two LUTs having different characteristics (in this example, two types of LUTs are used, but the present invention is not limited thereto) 205 and 206, and gradation correction is performed. It is supplied to the selector 209 later.
[0028]
The selector 209 outputs a total of four signals including the signals from the LUTs 205 and 206 and the two signals “0” or “255” set in advance in the register, the 2-bit signal from the decoder 208, and the gray level. The grayscale control pattern signal from the control pattern memory 112 is selected according to a total of 3 bits and sent as an output image signal OD. Based on the comparison results of the comparators 203 and 204, the selector 209 outputs a value “0” if the multiplication result M is “0” or less, and outputs a value “255” if it is “255” or more. To do. In the case other than the above two values, the output result of one of the correction LUTs of the LUTs 205 and 207 corresponding to the halftone dot pattern is output according to 1 bit of the gradation control pattern signal.
[0029]
The configurations of the gradation control pattern memory 112, the decoder 208, and the selector 209 are not limited to those described above. One bit of the gradation control pattern is input to the decoder 208, and signals from the two types of LUTs are received. Two signals “0” or “255” set in the register in advance, that is, a 2-bit signal for selecting a total of four signals are input to the selector 209, and the selector 209 selects the two bits, A configuration in which the output image signal OD is transmitted may be used.
[0030]
Here, the conventional halftoning by the binarization method and halftoning by the output pixel value calculation method of the present invention will be described by comparing the respective principles. FIG. 5 is a conceptual diagram showing the principle of halftoning by the conventional binarization method. In the figure, when an input signal is input as a signal having an area ratio of 182/255 = 71%, 11 out of a total of 16 output pixels of 4 × 4 as shown in the figure are turned on (255), The remaining five are off (0). At this time, the area ratio of the output signal is (255 × 11) / (255 × 16) × 100% = 69%, and only the quantization level for 4 × 4 = 16 gradations is ensured. Since a quantization error due to a quantization step of /16=6.25% unit occurs, it was not satisfactory. Even if up to 12 are turned on (255), the area ratio of the output signal at this time is (255 × 12) / (255 × 16) × 100% = 75%, and the quantization error is 6%. Will occur.
[0031]
On the other hand, in the halftone dot obtained by the output pixel value calculation method of the present invention shown in FIG. 6, the weight of each pixel of 4 × 4 = 16 (solid density level “255” when that pixel is turned on) Using the halftone dot pattern matrix representing the ratio), a process for calculating the output density level of each 4 × 4 output pixel is performed without feedback calculation by a determination method described later. According to this, since the output pixel control of the intermediate density level can be performed so as to minimize the reproduction quantization error between the input and output, the area ratio of the output signal is (255 × 11 + 96) / (255 × 16) × 100% = 71%, and when applied to an 8-bit input / output system, gradation reproduction within a quantization step of “256” and a quantization error of 1/256 = 0.4% or less becomes possible.
[0032]
Further, the calculation method will be described with reference to FIG. A specific example will be described assuming that the value of the input image signal V is “182” and each value of “0 °” shown in FIG. 21A is output from the halftone dot pattern memory 103. First, if the input image signal V is “182”, the subtractor 201 applies each pattern value S (“0”, “16”,..., “240”) of the 4 × 4 matrix of the halftone dot pattern. V-S is performed, and the result N is multiplied by the gradation gain G (in this case, 256/16 = 16) by the multiplier 202 to obtain a multiplication result M. If the multiplication result M is smaller than “0”, “0” is output, and if it is larger than “255”, “255” is output. When the halftone dot pattern value is “160” or less, the multiplication result M indicates a value of “255” or more.
[0033]
On the other hand, when the halftone dot pattern value is “192” or more, the multiplication result M indicates a value of “0” or less. Only when the halftone dot pattern value is “176”, the multiplication result M indicates “96” between “0” and “255”. From the above results, the selector 209 determines that “255” when the halftone dot pattern value is “160” or less, “0” when the halftone dot pattern value is “192” or more, and “176” for the halftone dot pattern value. ”, One of the values obtained by converting the M value“ 96 ”by the LUTs 205 and 206 is selected by the gradation control pattern signal and output. The conversion characteristics set in each of these LUTs 205 and 206 will be described later. However, if a linear one is set in any LUT for simplicity, “96” is output as it is from the multiplication value M. The The data flow described above is shown in FIG. As a result, an output result as shown in FIG. 6 is obtained.
[0034]
As described above, according to the above configuration, a gradation reproduction method that is faithful to the input signal and has a small quantization error can be realized. However, depending on the means for reproducing the intermediate density level and its characteristics, it can be realized in principle. It is expected to be different from what can be done.
[0035]
Here, FIGS. 7A and 7B are a conceptual diagram showing the tone reproduction characteristics obtained by the screen generation method having the above-described configuration, and a conceptual diagram showing the effect of the correction tone characteristics. As shown in FIG. 7A, the tone reproduction characteristics according to this method are a continuous gradation reproduction portion of a digital portion that is handled by an ON (255) pixel of a halftone dot pattern and an analog portion that is carried by an intermediate density level pixel. The tone reproduction unit is synthesized. For this reason, unless both of these tone reproduction portions have linear characteristics, the tone characteristics basically have discontinuous points, and pseudo contours are generated. For this purpose, both the tone reproducibility of the analog screen generator responsible for reproducing the intermediate density pixel value and the tone reproducibility of the digital screen generator responsible for the stepwise gradation reproduction consisting of “0” and “255” outputs are corrected. A means to do this is required.
[0036]
The means for correcting the tone reproducibility are the LUT 205 and the LUT 206 shown in FIG. As shown in FIG. 7 (a), before tone correction, the point of contact between the stepwise gradation reproduction area of the digital portion created by the screen pattern threshold and the continuous gradation reproduction area of the analog portion based on the intermediate density pixel value. Thus, a gradation characteristic with fluctuations having discontinuous points is obtained. On the other hand, the tone reproduction characteristics shown in FIG. 7B in which both the staircase gradation reproduction area and the continuous gradation reproduction area are appropriately corrected are characteristics having no linear pseudo contour.
[0037]
FIGS. 8A and 8B are conceptual diagrams showing a procedure in the case of actually correcting the continuous gradation reproduction of the analog portion. In the figure, when the tone reproduction characteristic by the analog screen is FIG. 8A, the tone characteristic of FIG. 8B which is an inverse function is obtained so that this is linear. Further, the rise of the tone curve in the highlight portion and the tone curve y in the high density portion are determined to be as smooth as possible, and are set in the LUT.
[0038]
Here, the problem is the temporal variation and environmental variation of the analog screen generator. It is ideal to obtain the gradation characteristics shown in FIG. 8B, but there is a possibility that fogging may occur when considering the temporal variation and environmental variation of the analog screen generator. In a copying machine that performs pulse width modulation using an analog screen, the analog screen generation unit normally does not cause fogging in consideration of temporal variation and environmental variation of the analog screen generation unit. As shown in a), in the highlight portion, “0” is output until an input value of a certain level (between the dotted line and the dotted line). When the determined tone curve is set in the LUT by the procedure as shown in FIG. 8 while keeping the highlight characteristic, a stagnant density region is generated as shown in FIG.
[0039]
In the present embodiment, in consideration of the above-described circumstances, the procedure shown in FIG. 8 is performed while the characteristics of the highlight portion as shown in FIG. The selected tone curve is selected. Otherwise, the highlight portion characteristic as shown in FIG. 16A is not left, and the selected tone curve is selected according to the procedure shown in FIG. There is little risk of occurrence, and a gradation characteristic that does not generate pseudo contours can be obtained.
[0040]
Specifically, in this embodiment, there are provided two types of LUTs, a gradation correction LUT that retains the characteristics of the highlight portion of the analog screen and a gradation correction LUT that does not retain the characteristics of the highlight portion. Select according to the gradation control pattern. However, the setting of the type, number, etc. of these LUTs is not limited to this, and it may be switched according to information about the position of the halftone dot pattern or the target pixel in the halftone dot pattern.
[0041]
On the other hand, in the stepwise gradation reproduction range of the digital portion shown in FIGS. 7A and 7B, the output pixel value calculation circuit 20 has a uniform step height (quantization step width). Correction is performed by the tone correction means provided in the preceding stage. With such a configuration, it is possible to realize a gradation reproduction characteristic with high linearity without a pseudo contour or the like.
[0042]
A-3. Waveform control multi-value circuit
Next, FIG. 9 is a block diagram showing the configuration of the waveform control multi-value quantization circuit 30. In the figure, a D / A conversion circuit 301 converts an image density signal OD into an analog signal and outputs the analog signal. The pattern generators 302, 303, and 304 output 300-line A-phase and B-phase two-phase triangular wave signals and 600-line triangular wave signals, each having a different “180 °” phase. Comparators 305, 306, and 307 compare the triangular wave signal and the analog signal, respectively, and output the comparison result as a digital signal. That is, the digital signal is “1” when the level of the analog signal is equal to or higher than the level of the triangular wave signal, and is “0” otherwise.
[0043]
The selector 305 selects and outputs one of these analog signals in synchronization with the pixel clock CLK based on the screen switching signal SCS (contents of the waveform control pattern memory 111). This output signal is output as an output pulse modulation signal for the laser diode.
[0044]
Here, the waveform of the triangular wave signal corresponding to the selected analog signal will be described with reference to FIG. Comparing (b) and (c) of the figure, when the screen switching signal SCS (growth pattern) is “0”, one of the pattern generators 302 and 303 is a triangular wave in the rising half cycle. The pulse modulation signal obtained by the pattern is selected by the selection circuit 308, and in this system, dots are made from the right side of the pixel. When the screen switching signal SCS is “1”, the pulse modulation signal obtained by the triangular wave pattern in the falling half cycle is selected by the selection circuit 308 from either of the pattern generators 302 and 303. Dots are made from the left side of the pixel. When the screen switching signal SCS is “2”, the pulse modulation signal obtained by the triangular wave pattern of the 600 line period of the pattern generator 304 is selected by the selection circuit 308, and is dotted from the center of the pixel.
[0045]
Therefore, which of the analog signals output from the comparators 305 and 306 with reference to the two types of triangular wave signal patterns of the 300-phase A-phase and B-phase having different “180 °” phases is selected. It is not uniquely determined only by the screen switching signal SCS. For example, when the pixel clock CLK is input a plurality of times while the screen switching signal SCS remains constant, the selector 305 selects both analog signals alternately. Further, as the triangular wave waveform used here, it is conceivable to use not only the patterns 1 and 2 but also a triangular wave pattern or a sawtooth wave having a ½ period. In addition, the period of the reference signal such as a triangular wave signal is not limited to the combination of the 300 lines and the 600 lines, and may be a combination of 200 lines and 400 lines, for example.
[0046]
B. Operation of the first embodiment
Next, the operation of the first embodiment will be described. When a color image is output using the image processing apparatus of the first embodiment, Y color output processing is first performed.
[0047]
First, each memory, register, counter, etc. are reset, and a halftone dot pattern (weight conversion as described above) and a waveform control pattern related to “0 °” shown in FIGS. 3A and 3B are performed. The halftone dot pattern memory 103 and the waveform control pattern memory 111 shown in FIG. 1 are respectively written, and the reset value in the reset circuit 105 is set to “4”.
[0048]
Further, the value “16” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. Next, the pixel clock CLK is supplied to the main scanning direction address counter 104, and the input image signal V related to Y color is supplied to the output pixel value calculation circuit 20. The main scanning direction address counter 104 counts the pixel clock CLK. When the count value reaches “4”, the count value is reset by the reset circuit 105. Further, “0” is output from the sub-scanning direction address counter 102.
[0049]
Accordingly, in the halftone dot pattern memory 103, “Y (sub-scanning direction) = 0, X (main scanning direction) from the address“ Y (sub-scanning direction) = 0, X (main scanning direction) = 0 ”. ) = 3 ”is repeatedly accessed, and the corresponding“ 4 ”type of dot pattern S is repeatedly supplied to the output pixel value calculation circuit 20. In the output pixel value calculation circuit 20, three intermediate values after the LUT output from the multiplier 202 based on the comparison results of the comparators 203 and 204 and the gradation control pattern, “255” and “0”. Any one of the values is selected, and the selected value is output as the image density signal OD.
[0050]
In the waveform control pattern memory 111, a screen switching signal SCS corresponding to the halftone dot pattern S is output. In this way, when the scan for “1” lines in the main scanning direction is completed, the horizontal synchronization signal H_SYNC is supplied to the screen angle generation pattern generation circuit 10. As a result, the count value of the sub-scanning direction address counter 102 is incremented and the count value of the main scanning direction address counter 104 is reset.
[0051]
Then, scanning for the next line is started. When the horizontal synchronization signal H_SYNC is input to the sub-scanning direction address counter 102 after the scan for “4” lines is completed, the count value of the sub-scanning direction address counter 102 becomes “4”. When detecting this state, the reset circuit 105 resets the count value of the sub-scanning direction address counter 102 to “0”.
[0052]
Thereafter, similarly, when the input image signal V is supplied to the output pixel value calculation circuit 20 in synchronization with the pixel clock CLK, the halftone dot pattern memory 103 and the waveform control pattern memory 111 are accessed, and the subpixel is set to the output pixel value. While being supplied to the calculation circuit 20, the screen switching signal SCS is supplied to the waveform control multi-value conversion circuit 30. As a result, the Y-color image density signal OD for “1” pages is sequentially supplied to the waveform control multilevel circuit 30.
[0053]
When the output of the Y color is completed, an output process for the M color is performed next. First, each memory, register, counter, etc. are reset, and a halftone dot pattern (weight converted as described above) and a waveform control pattern relating to “14 °” shown in FIGS. The halftone dot pattern memory 103 and the waveform control pattern memory 111 are respectively written, and the reset value in the reset circuit 105 is set to “17”.
[0054]
Further, the value “17” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. Then, when the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the M-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the Y color is performed. , “M” image density signals OD for “1” pages are sequentially supplied to the waveform control multi-value conversion circuit 30.
[0055]
When the output of the M color is completed, an output process for the K color is performed next. First, each memory, register, counter and the like are reset, and the halftone dot pattern and the waveform control pattern relating to “45 °” shown in FIGS. 3A and 3B are stored in the halftone dot pattern memory 103 and the waveform control pattern memory 111. Each is written, and the reset value in the reset circuit 105 is set to “6”.
[0056]
Further, the value “18” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. When the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the K-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the Y color is performed. , The image density signal OD of K color for “1” pages is sequentially supplied to the waveform control multi-value conversion circuit 30.
[0057]
When the output of the K color is completed, an output process for the C color is then performed. First, each memory, register, counter and the like are reset, and the halftone dot pattern and the waveform control pattern relating to “75 °” shown in FIGS. 3A and 3B are stored in the halftone dot pattern memory 103 and the waveform control pattern memory 111. Each is written, and the reset value in the reset circuit 105 is set to “17”.
[0058]
Further, the value “17” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. When the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the C-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the Y color is performed. , “C” image density signal OD for “1” pages is sequentially supplied to the waveform control multi-value conversion circuit 30.
[0059]
A dot image having a smooth shape can be generated by controlling the dot by such waveform control. 10A to 10E are conceptual diagrams showing this effect. FIG. 6A shows an example of multi-value conversion using a triangular wave pattern 1 having a fixed period and a fixed phase. According to this, an intermediate density value is output by the above-described output pixel value calculation algorithm, and the density as a sum is obtained. Although the value is guaranteed, the resulting output halftone dot shape is unsatisfactory due to the occurrence of vignetting. On the other hand, based on the waveform control pattern, the smooth halftone dot shape originally assumed can be generated in FIG. This will be specifically described below.
[0060]
Here, an example of the image density signal OD generated based on the density threshold value S and the input image signal V is shown in FIG. In this way, when the image density signal OD relating to each color is supplied to the waveform control multi-value conversion circuit 30, the image density signal OD is converted into an analog signal via the D / A conversion circuit 301. Further, the pattern generation units 302 to 304 output triangular wave signals having different phases and periods. Here, when the image density signal OD is “255”, the digital signal output from the selectors 305 to 307 is always “1”, so the duty ratio of the output pulse modulation signal is “100%”.
[0061]
When the image density signal OD is “0”, the digital signal output from the selectors 305 to 307 is always “0”, so the duty ratio of the output pulse modulation signal is “0%”. When the image density signal OD is an intermediate density, the duty ratio of the output pulse modulation signal becomes a value corresponding to the intermediate density. At that time, the halftone dot shape shown in FIG. 10D or 10E can be considered depending on the triangular wave signal used.
[0062]
For example, as shown in FIG. 10 (d), when multi-value processing is performed using a single triangular wave pattern, a toggling occurs, which is not satisfactory. However, in this embodiment, the selection circuit 308 performs the switching process so that the triangular wave pattern shown in FIG. Therefore, on the other hand, when the waveform control multi-value is made based on the waveform control pattern SCS, a smooth halftone dot shape originally assumed can be generated as shown in FIG.
[0063]
C. Effects of the first embodiment
(1) As described above, according to the first embodiment, the condition “input image signal V <density threshold value S” is satisfied, and “value N (N = V−S + D) is a negative value”. An intermediate density corresponding to the value N is set for a sub-pixel that satisfies the condition “not”. That is, there is no conflict between the resolution and the number of reproduced gradations, and a sufficient number of reproduced gradations can be obtained even when the number of subpixels constituting the screen pattern is small.
[0064]
(2) Furthermore, according to the first embodiment, the second subpixel adjacent to the intermediate density first subpixel in the main scanning direction and having a lower density threshold than the first subpixel is provided. If present, the triangular wave signal is selected so that the on-state portions of the first and second subpixels are continuous. Thereby, the screen shape can be prevented from being deformed, and a high-quality output image can be stably obtained.
[0065]
D. Second embodiment
The second embodiment further proposes a method capable of increasing the degree of freedom of setting the halftone dot shape and generating a smooth halftone dot shape.
[0066]
Basically, the system according to the second embodiment is an extension of the first embodiment described so far. For example, when the resolution of the input / output image signal is set to 600 dpi in both main scanning and sub-scanning, in the above-described embodiment, a halftone dot pattern having the same resolution is created, and based on this, a multi-value signal (final signal) A good pulse width modulation signal). On the other hand, the example here generates a halftone dot pattern having a resolution higher than the resolution of the input / output image signal, for example, 1200 dpi for both main scanning and sub scanning, and based on this, an output pixel value is calculated. After performing the above, by obtaining a multi-value signal converted to match the output resolution of 600 dpi, it is possible to generate a halftone dot signal closer to the ideal shape.
[0067]
Specifically, as shown in FIG. 11, for example, a halftone dot pattern having a resolution of 1200 dpi that is twice the resolution of the input / output image signal resolution of 600 dpi is generated. In this case, the 6 × 6 matrix has a pattern having 36 steps, but as described in the first embodiment, the weight of each pixel of the matrix is 256 / 36≈7. ”,“ 7 ”,“ 14 ”,...,“ 248 ”, and the patterns are arranged in the dot growth order.
[0068]
Next, in the output pixel value calculation circuit 20, calculation is performed by the same algorithm as described above, but the setting of the gradation gain value G used at this time and the value to the comparator executed thereafter is expanded. It is necessary to think about it. The gradation gain value G at this time uses a 6 × 6 halftone dot pattern as a whole, but is interpreted as 3 × 3 = 9 because of the matrix size equivalent to the input resolution. Therefore, the gradation gain value G is “9”. Although the set value to the comparator does not change for the detection of a value of “0” or less, the larger value is not the maximum value “255” of 8-bit data, but the network in the output pixel value calculation circuit 20. The maximum value per dot pattern resolution pixel is set. In this case, since a 2 × 2 (n × m) halftone dot pattern corresponds to one input resolution, the value per halftone dot pattern resolution is 255 / (2 × 2) = 63.75. Become. FIG. 11 shows a calculation example under this condition, but a matrix of “a” values shown in FIG. 11 is obtained as multi-value output values having a resolution of 1200 dpi. The value at this time is a matrix composed of “0” or “64 (true 63.75)” or one intermediate value (in this case “44”).
[0069]
Next, in order to convert this matrix into an output pixel resolution of 600 dpi, a sum is obtained in units of 2 × 2 sub-matrices, and 3 × matching the output pixel resolution as shown in “a” in FIG. 3 final output images are obtained. FIG. 12 shows a comparison with the output result of the first embodiment. In both figures, the output total value does not change, but in the second embodiment (part 1), more occurrence points of intermediate density values appear, and a smoother halftone dot shape is obtained. I understand that.
[0070]
When the resolution of the output pixel is 1200 dpi, “a” in FIG. 11 is output as it is as the final output image. FIG. 13 shows a comparison with the output result of the first embodiment. In both cases, the total output value does not change, but in the second embodiment (part 2), there are more occurrences of intermediate density values, and the higher resolution results in a smoother halftone dot shape. You can see that it is obtained.
[0071]
The actual processing configuration is as shown in FIGS. In FIG. 14, halftone dot patterns are provided for the number of sub-matrix divisions, and in order to perform processing, subtracters 201-1 to 20-n and multipliers 202-1 to 202-n for the number of divisions are performed. -n, provided with selectors 207-1 to 207-n, and after performing parallel calculation, the sum of the multilevel output signals for each division by the adder & selector 211 is finally compared with the comparators 220a, 220b and Input to the LUT 205 and the LUT 206. In the comparators 220a and 220b, it is determined whether the total signal of the multi-value output is “0” or “255”. The decoder 221 outputs a signal indicating whether to select “0”, “255”, or “intermediate value” based on the results of the comparators 220a and 220b. The selector 222 is configured to select and output one of “0”, “255”, the output of the LUT 205, or the output of the LUT 206 based on the signal from the decoder 221 and the gradation control pattern. The LUT 205 and LUT 206 here have the same role as the LUT 205 and LUT 206 shown in FIG.
[0072]
In FIG. 15, halftone dot patterns, waveform control patterns, and gradation control patterns are provided for the number of sub-matrices (n), and in order to process the sub-matrix, subtracters 201-1 to 201- 201-n, multipliers 202-1 to 202-n, comparators 220a-1 to 220a-n, 220b-1 to 220b-n, decoders 221-1 to 221-n, LUT 205-1 to LUT 205-n , LUT 206-1 to LUT 206-n and selectors 222-1 to 222-n, perform parallel calculation and output. The comparators 220a-1 to 220a-n, 220b-1 to 220b-n, decoders 221-1 to 221-n, LUT 205-1 to LUT 205-n, LUT 206-1 to LUT 206-n, and selector 222-1 here. ˜222-n have the same operations and roles as those shown in FIG. The number of divisions n when FIG. 11 is implemented with the configuration shown in FIGS. 14 and 15 is “4” because the sub-matrix is 2 × 2 (n × m).
[0073]
E. Effects of the second embodiment
(1) As described above, according to the second embodiment, even if the output device has a resolution that is n × m times higher than the resolution of the input image signal, the reproduction level can be reduced without special resolution conversion processing. It is possible to realize high-quality image reproduction with good gradation and smoothness of the reproduction halftone dot shape without any tradeoff between the logarithm and the screen resolution.
[0074]
F. Modified example
The present invention is not limited to the first or second embodiment described above, and various modifications can be made. For example, in the first or second embodiment, as the first and second triangular wave signals, triangular wave signals having different phases by “180 °” are used. One of these sawtooth signals may be selected as a reference signal based on the switching signal SCS.
[0075]
In the above-described first or second embodiment, the example in which the density pattern method is used has been described. However, the present invention can be similarly applied even when the dither method is used. That is, the “subpixel” in the first or second embodiment is considered as “one pixel” in the dither method, and an image density signal by the dither method may be used as the image density signal OD. Thereby, the thing of the said embodiment converts n input pixel Q1, Q2, ..., Qn into n output pixel R1, R2, ..., Rn corresponding, respectively.
[0076]
【The invention's effect】
As described above, according to the first aspect of the present invention, the halftone data output means, based on the input image signal and the halftone dot pattern stored in the halftone dot pattern storage means, After the input image signal is converted into intermediate gradation data, the gradation characteristics of the intermediate gradation data are corrected with different parameters by a plurality of gradation correction means using different parameters, and the gradation is corrected by the output means. Based on the gradation correction control pattern stored in the tone correction control pattern storage means, the intermediate gradation data corrected by any of the plurality of gradation correction means is selected and output. There is no reciprocal relationship with the number of reproduction gradations, and it is possible to increase the degree of freedom of the screen shape, and it is possible to stably obtain a higher quality output image. An advantage that can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a conceptual diagram showing a halftone dot pattern conversion method.
FIG. 3 is a conceptual diagram illustrating an example of a halftone dot pattern.
FIG. 4 is a block diagram illustrating a configuration of an output pixel value calculation circuit.
FIG. 5 is a conceptual diagram for explaining the principle of halftoning by a conventional binarization method.
FIG. 6 is a conceptual diagram for explaining the principle of halftoning according to the present embodiment.
FIG. 7 is a conceptual diagram illustrating an example of tone reproduction characteristics and correction tone characteristics.
FIG. 8 is a conceptual diagram showing an example of tone reproduction characteristics and correction tone characteristics of an analog screen generator.
FIG. 9 is a block diagram showing a configuration of a waveform control multilevel circuit.
FIG. 10 is a conceptual diagram illustrating an example of an effect according to the first embodiment.
FIG. 11 is a conceptual diagram for explaining the principle of an image processing apparatus according to a second embodiment of the present invention.
FIG. 12 is a conceptual diagram illustrating an example of halftone dot reproducibility improvement according to the second embodiment (part 1).
FIG. 13 is a conceptual diagram illustrating an example of halftone dot reproducibility improvement according to the second embodiment (part 2).
FIG. 14 is a block diagram illustrating a configuration example of an image processing apparatus (part) according to a second embodiment (part 1);
FIG. 15 is a block diagram illustrating a configuration example of an image processing apparatus (part) according to a second embodiment (part 2);
FIG. 16 is a conceptual diagram for explaining gradation characteristics when a gradation correction LUT is used while maintaining the characteristics of the analog screen generation section and the highlight section.
FIG. 17 is a conceptual diagram for explaining a data flow in the output pixel value calculation method of the present invention.
FIG. 18 is a block diagram illustrating a processing configuration example of a dither method.
FIG. 19 is a conceptual diagram showing a comparison between a dither method and a density pattern method.
FIG. 20 is a conceptual diagram illustrating a binarization example of a density pattern method.
FIG. 21 is a conceptual diagram for explaining a screen angle generation cell (basic pattern).
FIG. 22 is a conceptual diagram for explaining screen angle generation.
FIG. 23 is a block diagram illustrating a configuration example of an analog triangular wave comparison method, and a conceptual diagram illustrating an operation example.
FIG. 24 is a conceptual diagram showing an example of an analog triangular wave comparison method.
[Explanation of symbols]
20 Output pixel value calculation circuit
30 Waveform control multi-value circuit
103 Halftone dot pattern memory (halftone dot pattern memory means)
111 Waveform control pattern memory (waveform control pattern storage means)
112 Gradation control pattern memory (gradation correction control pattern storage means)
201 Subtractor (intermediate gradation data output means)
202 Multiplier (Middle gradation data output means)
203 comparator (intermediate gradation data output means)
204 Comparator (intermediate gradation data output means)
205 LUT (multiple gradation correction means, first gradation correction means)
206 LUT (multiple gradation correction means, second gradation correction means)
208 decoder
209 Selector (output means)
210 gradation gain register
301 D / A converter
302 pattern generator (generating means, first triangular wave signal generating means)
303 pattern generator (generating means, second triangular wave signal generating means)
304 pattern generation unit (generation means, third triangular wave signal generation means)
305, 306, 307 Comparator
308 selector (multi-valued reference pattern selection means)
103-1 to 103-n Halftone dot pattern memory (halftone dot pattern memory means)
111-1 to 111-n Waveform control pattern memory (waveform control pattern storage means)
112-1 to 112-n Gradation control pattern memory (gradation correction control pattern storage means)
201-1 to 201-n subtracter (intermediate gradation data output means)
202-1 to 202-n multipliers (intermediate gradation data output means)
203-1 to 203-n comparator (intermediate gradation data output means)
204-1 to 204-n comparator (intermediate gradation data output means)
205-1 to 205-n LUT (multiple gradation correction means, first gradation correction means)
206-1 to 206-n LUT (multiple gradation correction means, second gradation correction means)
207-1 to 207-n selector (intermediate gradation data output means)
208-1 to 208-n decoder
209-1 to 209-n selector (output means)
211 Adder (intermediate gradation data output means)

Claims (8)

In an image processing device that converts an input image signal and generates an output image signal to an image recording device,
Halftone dot pattern storage means for storing a halftone dot pattern expressing the weight of halftone dot screen growth and shading reproduction;
Gradation correction control pattern storage means for storing gradation correction control parameters corresponding to the halftone dot pattern;
Halftone data output means for converting the input image signal into halftone data based on the input image signal and the halftone dot pattern stored in the halftone pattern storage means;
A plurality of gradation correction means for correcting the gradation characteristics of the intermediate gradation data respectively by different parameters;
Output means for selecting and outputting intermediate gradation data corrected by any of the plurality of gradation correction means based on the gradation correction control pattern stored in the gradation correction control pattern storage means; An image processing apparatus. Comparing means for comparing the intermediate gradation data output by the intermediate gradation data output means with a preset value;
The output means includes intermediate gradation data corrected in advance by the plurality of gradation correction means based on a gradation correction control pattern stored in the gradation correction control pattern storage means and a comparison result by the comparison means, 2. The image processing apparatus according to claim 1, wherein either the predetermined low density data or the predetermined high density data is selected and output.   The intermediate gradation data output means temporarily converts the input image signal into intermediate gradation data based on the input image signal and the halftone dot pattern stored in the halftone dot pattern storage means. Xm (n = 2, 3,..., M = 2, 3,...) Times after calculating the output pixel value, the sum of the output pixel values in n × m in units of n × m. The image processing apparatus according to claim 1, wherein an output pixel value having the same resolution as that of the input image signal is obtained.   The intermediate gradation data output means converts n × m when converting the input image signal into intermediate gradation data based on the input image signal and the halftone dot pattern stored in the halftone dot pattern storage means. The image processing apparatus according to claim 1, wherein an output pixel value at a double resolution is calculated to obtain an output pixel value at a resolution that is n × m times higher than the input image signal. Generating means for generating a plurality of multi-valued reference patterns;
Waveform control pattern storage means for storing a waveform control pattern corresponding to the halftone dot pattern;
Based on the waveform control pattern stored in the waveform control pattern storage means, the multi-valued reference pattern selecting means for selecting one of the plurality of multi-valued reference patterns generated by the generating means and the selection Converting means for converting an output pixel value of each pixel output from the means into an output signal having a pulse width corresponding to the output pixel value by the multi-valued reference pattern selected by the multi-valued reference pattern selecting means; 5. The image processing apparatus according to claim 1, further comprising an image processing apparatus. The plurality of multilevel reference patterns are three types of triangular wave signals, and a first triangular wave signal generating means for generating a first triangular wave signal having a predetermined period;
Second triangular wave signal generating means for generating a second triangular wave signal having the same period and a phase different from that of the first triangular wave signal; and a third triangular wave having a different period with respect to the first and second triangular wave signals. The image processing apparatus according to claim 5, further comprising third triangular wave signal generation means for generating a signal.   The plurality of gradation correction means includes at least a first gradation correction means that retains the characteristics of the highlight portion of the analog screen, and a second gradation correction means that does not retain the characteristics of the highlight portion. An image processing apparatus according to claim 1, wherein: An image processing method performed by an image processing apparatus that converts an input image signal and generates an output image signal to an image recording apparatus,
A conversion step for converting the input image signal into halftone data based on the input image signal and a halftone dot pattern expressing the weight of halftone screen growth and shading reproduction;
A correction step of correcting the gradation characteristics of the intermediate gradation data by any of a plurality of parameters stored in advance;
An output step of outputting intermediate gradation data based on a gradation correction control pattern stored in advance corresponding to the halftone dot pattern, wherein the gradation characteristic is corrected by the correction step;
An image processing apparatus comprising:

Images