JP3684777B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrophotographic digital copying machine, a printer, and the like, and more particularly to an image processing apparatus suitable for use in outputting a high-quality halftone image.
[0002]
[Prior art]
Conventionally, a halftone image reproduction method and a triangular wave comparison method are known as methods for outputting a halftone image in an electrophotographic digital copying machine, a printer, or the like. The outline will be described below.
[0003]
<Halftone image reproduction method>
In the halftone image reproduction method, there are a dither method and a density pattern method. In these methods, as shown in FIG. 12, a density threshold matrix corresponding to one-to-one resolution of output pixels is compared with input image data, and on / off of output pixels is controlled based on the result. The configuration is as follows. The dither method and the density pattern method are classified according to whether the correspondence between the input image data and the output image data at this time is one-to-one or one-to-multiple pixels. As shown in FIG. 13, the dither method is used when the input image data and the output image data correspond one-to-one, and the density pattern method is used when the input image data corresponds to a plurality of pixels. Here, such a density threshold value matrix is called a screen pattern.
[0004]
When each density threshold value in the screen pattern is applied to an input image signal of 8 bits (0 to 255), for example, the screen pattern shown in FIG. 13 subtracts the gradation range (0 to 255). Divide evenly by the number of pixels and set to linear quantization (rounded off). When the density pattern method shown in FIG. 13B is applied to an input image signal of 8 bits (0 to 255), as shown in FIG. 14B, each density threshold value is “8”, “ 24 ”,“ 40 ”, and so on.
[0005]
Next, the density threshold value is compared with the density of the input pixel to determine the on / off state of each subpixel. That is, the sub-pixel corresponding to the density threshold lower than the density of the input pixel is turned on, and the other sub-pixels are turned off. As an example, when the density of the input pixel is “120” as shown in FIG. 14A, the on / off state of each subpixel is as shown in FIG.
[0006]
By the way, when the halftone image reproduction method is adopted in a color copying machine or the like, the above-described processing may be performed for each primary color (K, Y, M, C). However, when the same screen pattern is used for each color, color unevenness occurs due to a slight positional shift, and the influence of a striped pattern (moire fringe) generated when halftone dots of each primary color overlap is increased. Therefore, as shown in FIG. 15, it is common to use four types of screen patterns having different screen angles θ and use them corresponding to each primary color (Japanese Patent Publication No. 52-49361, Japanese Patent Laid-Open No. 54). -18302).
[0007]
In the field of screen printing and the like, it is known that the screen angle θ is preferably set to 0 °, 15 °, 45 ° and 75 °. However, in order to apply to a copying machine or the like, the screen angle θ must be a value that can be obtained by a rational tangent because the memory capacity is reduced by repeatedly using the same screen pattern. FIG. 16 is a conceptual diagram showing a state in which the same screen pattern is arranged. The numbers shown are density threshold numbers.
[0008]
<Triangle wave comparison method>
Next, in the triangular wave comparison method, as shown in FIG. 17A, first, the density of the input pixel is converted into an analog signal. Then, the comparator compares the triangular wave having a predetermined period with the analog signal to obtain an output pulse width signal. When the level of the analog signal is equal to or higher than the level of the triangular wave (or lower than the level), the analog signal is turned on (for example, an exposure state of laser light), and otherwise is turned off. That is, the higher the density of the input pixel, the higher the level of the analog signal, the higher the duty ratio at which the comparison result is turned on, and the higher the density of the output image.
[0009]
By the way, in the triangular wave comparison method, even when color printing is performed, a technique for providing a screen angle θ for each primary color is known in order to suppress the influence of color unevenness and moire fringes. For example, Japanese Patent Laid-Open No. 62-183670 discloses a technique for shifting the phase of a triangular wave by a certain amount every time a “1” line is advanced in the sub-scanning direction. Japanese Patent Laid-Open No. 2-296264 discloses a technique for changing the gradation reproduction characteristics every time the “1” line advances in the sub-scanning direction.
[0010]
[Problems to be solved by the invention]
However, the above-described prior art has the following various problems. First, in the halftone image reproduction method, there is a reciprocal relationship between the resolution and the number of reproduced gradations. For example, if the resolution of the output device is “400 dpi (dots / inch)” and a resolution of “200 lpi (lines / inch)” is desired, the screen size needs to be “2 × 2”. . That is, the reproduction gradation number is “4”, and only a very low gradation number can be obtained. Conversely, in order to set the number of reproduced gradations to “64”, the screen size needs to be “8 × 8”. For this reason, the resolution becomes “400/8 = 50 lpi”, which is greatly reduced.
[0011]
When screen printing is performed, the output device originally has a resolution of about “4000 dpi”, so even if the number of reproduced gradations is increased, the roughness of the image is not noticeable with the naked eye. However, in the electrophotographic system, since the resolution of about “400 dpi to 600 dpi” is the limit, the above-described problem occurs.
[0012]
On the other hand, in the triangular wave comparison method, there is no reciprocal relationship between the resolution and the number of reproduced gradations. However, it is not practical to provide the screen angle θ for each primary color by the technique described above. The reason for this will be described with reference to FIG. In FIG. 18A, S1 is an analog signal, and this analog signal S1 is compared with a triangular wave signal. The phase of the triangular wave signal is gradually delayed for each “1” line in the sub-scanning direction.
[0013]
The exposure pattern of the laser obtained by this comparison result is shown in FIG. As is apparent from FIG. 6B, if the phase of the triangular wave is shifted for each “1” line in the sub-scanning direction, the halftone dots or the screen shape is liable to be broken or interrupted. This adversely affects gradation characteristics and graininess reproduction, and it is difficult to obtain satisfactory image quality. Furthermore, the screen angle θ and the number of screen lines (resolution) were also constrained by the period of the triangular wave pattern used, and there were few degrees of freedom.
[0014]
The present invention has been made in view of the above-described circumstances, and there is no conflict between the resolution and the number of reproduced gradations, and the degree of freedom of the screen shape can be increased, and a higher quality output image can be stabilized. An object of the present invention is to provide an image processing apparatus that can be obtained.
[0015]
[Means for Solving the Problems]
To solve the problems mentioned above, Book In the invention, in the image processing apparatus that corrects the gradation of the density data of the input pixel, a plurality of gradations that have different mutually different correction rules and correct the gradation of the input pixels according to the correction rule that each has Correction means According to the position in the sub-scanning direction where the input pixel exists, the sub-scanning direction switching unit that switches the gradation correcting unit to be used and the sub-scanning direction switching unit among the plurality of gradation correcting units are switched. A means for switching the gradation correction means in the main scanning direction at a cycle of 3 pixels, wherein the input pixel row aligned in the sub-scanning direction as the first pixel of the 3 pixel cycle is “L”, and the second of the 3 pixel cycle is When the input pixel column aligned in the sub-scanning direction as the pixel of “C” is “C” and the input pixel column aligned in the sub-scanning direction as the third pixel of the three-pixel period is “R”, the input pixel column L Main scanning direction switching means for switching the gradation correction means so as to correct the pixel growth rate of the input pixel column R to be slow and to correct the pixel growth rate of the input pixel column C to be high. It is characterized by comprising.
[0016]
According to the present invention, the sub-scanning direction switching unit switches the tone correction unit to be used from among the plurality of tone correction units according to the position in the sub-scanning direction where the input pixel exists, thereby changing the input pixel. Correct the gradation of density data. Therefore, there is no reciprocal relationship between the resolution and the number of reproduced gradations, and the degree of freedom of the screen shape can be increased, and a higher quality output image can be stably obtained.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings.
[0018]
A. Configuration of the embodiment
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. In the figure, the image processing apparatus includes a screen angle generation pattern generation circuit 10, an output pixel value calculation circuit 20, a waveform control multi-value conversion circuit 30, an edge detection circuit 40, an edge screen generation pattern generation circuit / output pixel value calculation circuit 50. And a switch 60.
[0019]
A-1. Screen angle generation pattern generation circuit
The screen angle generation pattern generation circuit 10 generates a halftone dot pattern having different screen angles for each of C, M, Y, and K at the time of color print output. The sub-scanning direction address counter 102 counts the horizontal synchronization signal H_SYNC and outputs the count value. The main scanning direction address counter 104 counts the pixel clock CLK and outputs the count value.
[0020]
The reset circuit 105 sets the main scanning direction address counter 104 when the horizontal synchronization signal H_SYNC is input to the screen angle generation pattern generation circuit 10 or when the count value of the main scanning direction address counter 104 reaches a predetermined reset value. Reset. As a result, the counter value returns to “0”.
[0021]
For example, in the case of the (b) 18.4 ° screen shown in FIG. 15, the developed pattern shown in FIG. 16 obtained by developing the screen by the method disclosed in Japanese Patent Publication No. 52-49361. Is generated. The L × L rectangular matrix generated at this time is repeatedly used every L pixels in the main scanning direction and every L lines in the sub-scanning direction, thereby generating a screen filled with a desired screen pattern. it can. The reset value in the main scanning direction at this time is “10”.
[0022]
Similarly, when the count value of the sub-scanning direction address counter 102 reaches the reset value (in this case, the reset value in the sub-scanning direction is also “10”), the reset circuit 105 sets the sub-scanning direction address counter 102 to Reset. The halftone dot pattern memory 103 has a memory capacity of “10 × 10 bytes” in this embodiment, and is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104. The halftone dot pattern memory 103 stores the contents of the screen patterns used. That is, the expansion pattern of the L × L rectangular matrix shown in FIG. 16 is stored. In this way, the halftone dot pattern memory 103 outputs a halftone dot pattern value S corresponding to the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104.
[0023]
Next, an example of halftone dot pattern values actually used is shown in FIG. As a halftone dot pattern with a screen angle θ of “0 °”, (a0) shown in FIG. 15 can be considered, but in this embodiment, a halftone dot pattern shown in FIG. 15 (a1) is used. In the halftone dot pattern, first, “3 (L)”, “1 (C)”, and “2 (R)” are set in the first main scanning direction (E), and the second main scanning direction (O) is set. “2 (L)”, “1 (C)”, and “3 (R)” opposite to the first main scanning direction. By using the halftone dot pattern of (a1) in FIG. 15, the lines with the screen angle θ “0 °” grow in a zigzag pattern. There are a large number of halftone dot patterns having the relationship as shown in (a0) of FIG. 15 and (a1) of FIG. 15 by changing the size of the halftone dot pattern or the cycle of staggering. Show. FIG. 11A shows a basic pattern of 2 × 1 lines, and FIG. 11D shows a basic pattern of 3 × 1 lines. Moreover, FIG.11 (b) and FIG.11 (c) are the staggered pattern derived from the basic pattern of Fig.11 (a). The derivation method is infinite by changing the zigzag cycle or changing the growth pattern and waveform pattern, but the one that can maintain the necessary resolution and gradation is selected.
[0024]
Next, the halftone dot pattern of (a1) shown in FIG. 15 is converted by the following procedure and then stored in the actual halftone dot pattern memory 103. First, a matrix obtained by subtracting “1” from each pattern value in the matrix shown in (a0) of FIG. 15 is obtained, and then a step gain value “85 (= 256/3)” obtained from the 4 × 4 matrix. Is multiplied by the previously obtained matrix to determine a halftone dot pattern to be actually stored in the halftone dot pattern memory 103. As a result, these values in the matrix indicate the ratio (weight) to the whole (256) when the pixel is turned on (black). That is, 1/3 × 256 = 85 when one dot is turned on, and 2/3 × 256 = 170 when two dots are turned on. However, in the halftone dot pattern shown in FIG. 2, as described above, “1” is subtracted from the matrix shown in (a1) of FIG. It is said.
[0025]
Next, when the screen pattern shown in FIG. 15B is used, the waveform control pattern memory 111 has a memory capacity of “10 × 10 bits” in order to store the L × L matrix shown in FIG. Corresponding to each halftone dot pattern in the halftone dot pattern memory 103, and stores a 2-bit waveform pattern indicating "0", "1", or "2" as shown in FIG. To do. At this time, “0” is a waveform pattern when dots are grown from the right side, “1” is a waveform pattern when growing from the left side, and “2” is a waveform pattern when growing from the middle. However, it is not limited to this value. In the present embodiment, since there are a total of three types of patterns, a 10-bit × 10-bit × 2-bit waveform pattern memory is required. Then, the waveform pattern of the waveform control pattern memory 111 is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104, and is output as the screen switching signal SCS. Here, an example of a waveform pattern corresponding to each halftone dot pattern is shown in FIG.
[0026]
Next, the gradation control pattern memory 112 has a memory capacity of “10 × 10 bits” in order to store an L × L rectangular matrix, and corresponds to each halftone pattern of the halftone pattern memory 103. , “1 bit” gradation control pattern indicating either “0” or “1” is stored. The gradation control pattern in the gradation control pattern memory 112 is accessed by the count values of the sub-scanning direction address counter 102 and the main scanning direction address counter 104 and is output to the output pixel value calculation circuit 20.
[0027]
A-2. Output pixel value calculation circuit
Next, the configuration of the output pixel value calculation circuit 20 will be described with reference to FIG. In the figure, a subtractor 201 subtracts a halftone dot pattern signal S from an input image signal (pixel density) V. The gradation gain register 210 stores a gradation gain G. The gradation gain G is set to be equal to the maximum value of the halftone dot pattern in FIG. Next, the multiplier 202 multiplies the subtraction value N in the subtractor 201 and the gradation gain G, and outputs the multiplication result M. Each of the comparators 203 and 204 determines whether the multiplication result M is smaller than “0” or larger than 255, and inputs two bits obtained by adding one bit of each determination result to the decoder 208, and selects the selector 209. Select signal to On the other hand, the result of the multiplier 202 is input to two gradation correction LUTs (in this example, two types of LUTs are used, but not limited thereto) 205 and 206 having different characteristics, After the tone correction, the signal is supplied to the selector 209.
[0028]
The selector 209 outputs a total of four signals including the signals from the LUTs 205 and 206 and the two signals “0” or “255” set in advance in the register, the 2-bit signal from the decoder 208, and the gray level. The grayscale control pattern signal from the control pattern memory 112 is selected according to a total of 3 bits and sent as an output image signal OD. Based on the comparison results of the comparators 203 and 204, the selector 209 outputs a value “0” if the multiplication result M is “0” or less, and outputs a value “255” if it is “255” or more. To do. In the case other than the above two values, the output result of one of the gradation correction LUTs of the LUTs 205 and 207 corresponding to the halftone dot pattern is output according to the gradation control pattern signal 1 bit.
[0029]
The configurations of the gradation control pattern memory 112, the decoder 208, and the selector 209 are not limited to those described above. One bit of the gradation control pattern is input to the decoder 208, and signals from the two types of LUTs are received. Two signals “0” or “255” set in the register in advance, that is, a 2-bit signal for selecting a total of four signals are input to the selector 209, and the selector 209 selects the two bits, A configuration in which the output image signal OD is transmitted may be used.
[0030]
Here, the conventional halftoning by the binarization method and halftoning by the output pixel value calculation method of the present invention will be described by comparing the respective principles. FIG. 5 is a conceptual diagram showing the principle of halftoning by the conventional binarization method. In the figure, when an input signal is input as a signal having an area ratio of 182/255 = 71%, 11 out of a total of 16 output pixels of 4 × 4 as shown in the figure are turned on (255), The remaining five are off (0). At this time, the area ratio of the output signal is (255 × 11) / (255 × 16) × 100% = 69%, and only the quantization level for 4 × 4 = 16 gradations is ensured. Since a quantization error due to a quantization step of /16=6.25% unit occurs, it was not satisfactory. Even if up to 12 are turned on (255), the area ratio of the output signal at this time is (255 × 12) / (255 × 16) × 100% = 75%, and the quantization error is 6%. Will occur.
[0031]
On the other hand, in the halftone dot obtained by the output pixel value calculation method of the present invention shown in FIG. 6, the weight of each pixel of 4 × 4 = 16 (solid density level “255” when that pixel is turned on) Using the halftone dot pattern matrix representing the ratio), a process for calculating the output density level of each 4 × 4 output pixel is performed without feedback calculation by a determination method described later. According to this, since the output pixel control of the intermediate density level can be performed so as to minimize the reproduction quantization error between the input and output, the area ratio of the output signal is (255 × 11 + 96) / (255 × 16) × 100% = 71%, and when applied to an 8-bit input / output system, gradation reproduction within a quantization step of “256” and a quantization error of 1/256 = 0.4% or less becomes possible.
[0032]
Further, the calculation method will be described with reference to FIG. A specific example will be described assuming that the value of the input image signal V is “182” and each value of “0 °” shown in FIG. 15A is output from the halftone dot pattern memory 103. First, if the input image signal V is “182”, the subtractor 201 applies each pattern value S (“0”, “85”,..., “170”) of the 3 × 2 matrix of the halftone dot pattern. V-S is performed, and the result N is multiplied by the gradation gain G (in this case, 256/85 = 3) by the multiplier 202 to obtain a multiplication result M. If the multiplication result M is smaller than “0”, “0” is output, and if it is larger than “255”, “255” is output. Only when the halftone dot pattern value is “170”, the multiplication result M indicates a value of “36” between “0” and “255”.
[0033]
From the above results, the selector 209 converts “255” when the halftone pattern value is “0” or “85”, and converts the M value “36” using the LUTs 205 and 206 when the halftone pattern value is “170”. One of these values is selected by the gradation control pattern signal and output. The conversion characteristics to be set in each of these LUTs 205 and 206 will be described later. For the sake of simplicity, if a linear one is set in any LUT, “36” is output as it is from the multiplication value M. The
[0034]
As described above, according to the above configuration, a gradation reproduction method that is faithful to the input signal and has a small quantization error can be realized. However, depending on the means for reproducing the intermediate density level and its characteristics, it can be realized in principle. It is expected to be different from what can be done.
[0035]
Here, FIGS. 7A and 7B are a conceptual diagram showing the tone reproduction characteristics obtained by the screen generation method having the above-described configuration, and a conceptual diagram showing the effect of the correction tone characteristics. As shown in FIG. 7A, the tone reproduction characteristics according to this method are a continuous gradation reproduction portion of a digital portion that is handled by an ON (255) pixel of a halftone dot pattern and an analog portion that is carried by an intermediate density level pixel. The tone reproduction unit is synthesized. For this reason, unless both of these tone reproduction portions have linear characteristics, the tone characteristics basically have discontinuous points, and pseudo contours are generated. For this purpose, both the tone reproducibility of the analog screen generator responsible for reproducing the intermediate density pixel value and the tone reproducibility of the digital screen generator responsible for the stepwise gradation reproduction consisting of “0” and “255” outputs are corrected. A means to do this is required.
[0036]
The means for correcting the tone reproducibility are the LUT 205 and the LUT 206 shown in FIG. As shown in FIG. 7 (a), before tone correction, the point of contact between the stepwise gradation reproduction area of the digital portion created by the screen pattern threshold and the continuous gradation reproduction area of the analog portion based on the intermediate density pixel value. Thus, a gradation characteristic with fluctuations having discontinuous points is obtained. On the other hand, the tone reproduction characteristics shown in FIG. 7B in which both the staircase gradation reproduction area and the continuous gradation reproduction area are appropriately corrected are characteristics having no linear pseudo contour.
[0037]
FIGS. 8A and 8B are conceptual diagrams showing a procedure in the case of actually correcting the continuous gradation reproduction of the analog portion. In the figure, when the tone reproduction characteristic by the analog screen is FIG. 8A, the tone characteristic of FIG. 8B which is an inverse function is obtained so that this is linear. Further, the rise of the tone curve in the highlight portion and the tone curve y in the high density portion are determined to be as smooth as possible, and are set in the LUT.
[0038]
Here, the problem is the temporal variation and environmental variation of the analog screen generator. For example, when a halftone dot pattern such as (a0) shown in FIG. 15 is used and the document is gradation, if the analog screen generator fluctuates due to temporal variation and environmental variation, the pattern “1” grows. When the pattern “2” starts growing, or after the pattern “2” grows, when the pattern “3” starts growing, the pseudo contour becomes very conspicuous. In the present embodiment, by using a staggered halftone dot pattern such as (a1) shown in FIG. 15, even if the analog screen generator fluctuates and gradation reproduction becomes somewhat discontinuous, pseudo contours are unlikely to occur. It has become.
[0039]
The stepwise gradation reproduction area of the digital portion shown in FIG. 7 is corrected by the tone correction means in the previous stage of the output pixel value calculation circuit so that the height of the steps (the width of the quantization step) is uniform. With such a configuration, it is possible to realize gradation reproduction characteristics with high linearity without pseudo contours.
[0040]
A-3. Waveform control multi-value circuit
Next, FIG. 9 is a block diagram showing the configuration of the waveform control multi-value quantization circuit 30. In the figure, a D / A conversion circuit 301 converts an image density signal OD into an analog signal and outputs the analog signal. The pattern generators 302, 303, and 304 each output two types of 200-line A-phase and B-phase triangular wave signals and 400-line triangular wave signals that are different in phase by “180 °”. Comparators 305, 306, and 307 compare the triangular wave signal and the analog signal, respectively, and output the comparison result as a digital signal. That is, the digital signal is “1” when the level of the analog signal is equal to or higher than the level of the triangular wave signal, and is “0” otherwise.
[0041]
The selector 305 selects and outputs one of these analog signals in synchronization with the pixel clock CLK based on the screen switching signal SCS (contents of the waveform control pattern memory 111). This output signal is output as an output pulse modulation signal for the laser diode.
[0042]
Here, the waveform of the triangular wave signal corresponding to the selected analog signal will be described with reference to FIG. Comparing (b) and (c) of the figure, when the screen switching signal SCS (growth pattern) is “0”, one of the pattern generators 302 and 303 is a triangular wave in the rising half cycle. The pulse modulation signal obtained by the pattern is selected by the selection circuit 308, and in this system, dots are made from the right side of the pixel. When the screen switching signal SCS is “1”, the pulse modulation signal obtained by the triangular wave pattern in the falling half cycle is selected by the selection circuit 308 from either of the pattern generators 302 and 303. Dots are made from the right side of the pixel. When the screen switching signal SCS is “2”, the pulse modulation signal obtained by the triangular wave pattern of the 600 line period of the pattern generator 304 is selected by the selection circuit 308, and is dotted from the center of the pixel.
[0043]
Therefore, which of the analog signals output from the comparators 305 and 306 with reference to the two types of triangular wave signal patterns of the 200 phase A phase and the B phase having different “180 °” phases is selected. It is not uniquely determined only by the screen switching signal SCS. For example, when the pixel clock CLK is input a plurality of times while the screen switching signal SCS remains constant, the selector 305 selects both analog signals alternately. Further, as the triangular wave waveform used here, it is conceivable to use not only the patterns 1 and 2 but also a triangular wave pattern or a sawtooth wave having a ½ period. In addition, the period of the reference signal such as a triangular wave signal is not limited to the combination of the 200 lines and the 400 lines, and may be a combination of 300 lines and 600 lines, for example.
[0044]
By controlling the dot direction by such waveform control, it is possible to generate a halftone dot image having a smooth shape. FIG. 10 shows this effect. FIG. 10A shows an example of multi-value conversion using a triangular wave pattern 1 having a fixed period and phase. According to this, the output pixel value calculation algorithm described above outputs an intermediate density value, and the density value as a sum is guaranteed, but the output halftone dot shape obtained as a result is satisfied with the occurrence of torsion. It is not a thing. On the other hand, based on the waveform control pattern, waveform control multivalued (b) can generate a smooth halftone dot shape originally assumed.
[0045]
A-4. Edge screen generation pattern generation circuit / output pixel calculation circuit 50
Next, the edge screen generation pattern generation circuit / output pixel calculation circuit 50 will be described. The edge screen generation pattern generation circuit / output pixel calculation circuit 50 may be considered as a combination of the above-described screen generation pattern generation circuit and output pixel value calculation circuit. Parameters such as the gain G and the correction LUT are values suitable for the edge portion. By switching the output of the edge screen generation pattern generation circuit / output pixel calculation circuit 50 and the output of the output pixel value calculation circuit 20 in real time according to a signal supplied from an edge detection circuit 40 to be described later, the edge portion and the non-edge portion It is possible to select a preferable growth method for each edge portion.
[0046]
A portion where resolution is prioritized over gradation, such as characters, can be reproduced with the input resolution as it is by growing it with a minimum pattern such as “edge” shown in FIG. Also, if the signal supplied from the edge detection circuit 40 is multi-stage, a multi-stage growth method is performed from the edge part to the non-edge part by preparing the corresponding halftone dot pattern and waveform control pattern. It becomes possible to make it. As in this embodiment, the 1 × 1 pattern of “edge” shown in FIG. 3 is equivalent to outputting the image signal as it is. In particular, the image signal is not prepared as an edge pattern. You may make it select the output of the output pixel value calculation circuit mentioned later with an edge signal.
[0047]
A-5. Edge detection circuit 40 and switching unit 60
Next, the edge detection circuit 40 will be described. The edge detection circuit 40 is a circuit that generates a signal for dividing an image into edge portions and non-edge portions into K (K> 1) stages based on image edge information. In the present invention, the details are not particularly limited. For example, there is a method in which an edge portion is detected using an edge detection filter and divided by a predetermined threshold value. In addition, a combination of edge detection and other feature amounts may be considered. For example, when K = 2, the SEL signal shown in FIG. 1 becomes 1 bit and is supplied to the switching unit 60. For example, when the SEL signal is “1”, the edge portion is set, and when “0” is set to the non-edge portion, the switching portion 60 outputs the edge screen generation pattern generation circuit / output pixel when the SEL signal is “1”. If the output of the value calculation circuit 50 is selected and “0”, the output (screen switching signal SCS) of the screen angle generation pattern generation circuit 10 and the output pixel value calculation circuit 10 (OD) are output.
[0048]
B. Operation of the embodiment
Next, the operation of this embodiment will be described. When a color image is output using the image processing apparatus of the present embodiment, K color output processing is first performed.
[0049]
First, each memory, register, counter, etc. are reset, and a halftone dot pattern (weight conversion as described above) and a waveform control pattern related to “0 °” shown in FIGS. 3A and 3B are performed. The halftone dot pattern memory 103 and the waveform control pattern memory 111 shown in FIG. 1 are respectively written, and the reset value in the reset circuit 105 is set to “2”.
[0050]
Further, the value “3” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. Next, the pixel clock CLK is supplied to the main scanning direction address counter 104, and the input image signal V related to K color is supplied to the output pixel value calculation circuit 20. The main scanning direction address counter 104 counts the pixel clock CLK. When the count value reaches “3”, the count value is reset by the reset circuit 105. Further, “0” is output from the sub-scanning direction address counter 102.
[0051]
Accordingly, in the halftone dot pattern memory 103, “Y (sub-scanning direction) = 0, X (main scanning direction) from the address“ Y (sub-scanning direction) = 0, X (main scanning direction) = 0 ”. ) = 2 ”is repeatedly accessed, and the corresponding“ 3 ”type dot pattern S is repeatedly supplied to the output pixel value calculation circuit 20. In the output pixel value calculation circuit 20, three intermediate values after the LUT output from the multiplier 202 based on the comparison results of the comparators 203 and 204 and the gradation control pattern, “255” and “0”. Any one of the values is selected, and the selected value is output as the image density signal OD.
[0052]
In the waveform control pattern memory 111, a screen switching signal SCS corresponding to the halftone dot pattern S is output. In this way, when the scan for “1” lines in the main scanning direction is completed, the horizontal synchronization signal H_SYNC is supplied to the screen angle generation pattern generation circuit 10. As a result, the count value of the sub-scanning direction address counter 102 is incremented and the count value of the main scanning direction address counter 104 is reset.
[0053]
Similarly, in the edge screen generation pattern generation circuit / output pixel value calculation circuit 50 shown in FIG. 1, the 1 × 1 dot pattern and the waveform control pattern shown in “Edge” in FIG. “1” is written in the gain register, and a linear table is set in the LUT. In this setting, the image data is output as it is, and the waveform control is always performed from the center of the pixel.
[0054]
Then, scanning for the next line is started. When the horizontal synchronization signal H_SYNC is input to the sub-scanning direction address counter 102 after the scanning for “2” lines is completed, the count value of the sub-scanning direction address counter 102 becomes “2”. When detecting this state, the reset circuit 105 resets the count value of the sub-scanning direction address counter 102 to “0”.
[0055]
Thereafter, similarly, when the input image signal V is supplied to the output pixel value calculation circuit 20 in synchronization with the pixel clock CLK, the halftone dot pattern memory 103 and the waveform control pattern memory 111 are accessed, and the subpixel is set to the output pixel value. While being supplied to the calculation circuit 20, the calculation result OD and the screen switching signal SCS are supplied to the switch 60. If there is an edge portion in the image data, the switch 60 detects this when the edge detection circuit 40 detects this, selects the output of the edge screen generation pattern generation circuit / output pixel value calculation circuit 50, and if it is a non-edge portion. The calculation result OD and the screen switching signal SCS are selected. As a result, the K-color image density signal OD for “1” pages is sequentially supplied to the waveform control multilevel circuit 30. The non-edge portion is reproduced by the staggered line shown in (a1) of FIG. 15, and the edge portion is reproduced as the input image.
[0056]
When the output of the K color is completed, the output process of the Y color is performed next. First, each memory, register, counter, etc. are reset, and the halftone dot pattern (weight converted as described above) and the waveform control pattern relating to “18 °” shown in FIGS. The halftone dot pattern memory 103 and the waveform control pattern memory 111 are respectively written, and the reset value in the reset circuit 105 is set to “10”.
[0057]
Further, the value “10” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. When the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the Y-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the K color is performed. , The Y-color image density signal OD for “1” pages is sequentially supplied to the waveform control multi-value conversion circuit 30.
[0058]
When the output of the Y color is completed, an output process for the M color is performed next. First, each memory, register, counter and the like are reset, and the halftone dot pattern and the waveform control pattern relating to “45 °” shown in FIGS. 3A and 3B are stored in the halftone dot pattern memory 103 and the waveform control pattern memory 111. Each is written, and the reset value in the reset circuit 105 is set to “4”.
[0059]
Further, the value “3” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. When the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the M-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the K color is performed. , “M” image density signals OD for “1” pages are sequentially supplied to the waveform control multi-value conversion circuit 30.
[0060]
When the output of the M color is completed, an output process for the C color is then performed. First, each memory, register, counter, etc. are reset, and the halftone dot pattern and the waveform control pattern relating to “71 °” shown in FIGS. 3A and 3B are stored in the halftone dot pattern memory 103 and the waveform control pattern memory 111. Each is written, and the reset value in the reset circuit 105 is set to “10”.
[0061]
Further, the value “10” is written in the gradation gain register 210 in the output pixel value calculation circuit 20 in accordance with the halftone dot pattern. When the pixel clock CLK is supplied to the screen angle generation pattern generation circuit 10 and the C-color input image signal V is supplied to the output pixel value calculation circuit 20, the same processing as described for the K color is performed. , “C” image density signal OD for “1” pages is sequentially supplied to the waveform control multi-value conversion circuit 30.
[0062]
A dot image having a smooth shape can be generated by controlling the dot by such waveform control. 10A to 10E are conceptual diagrams showing this effect. FIG. 6A shows an example of multi-value conversion using a triangular wave pattern 1 having a fixed period and a fixed phase. According to this, an intermediate density value is output by the above-described output pixel value calculation algorithm, and the density as a sum is obtained. Although the value is guaranteed, the resulting output halftone dot shape is unsatisfactory due to the occurrence of vignetting. On the other hand, based on the waveform control pattern, the smooth halftone dot shape originally assumed can be generated in FIG. This will be specifically described below.
[0063]
Here, an example of the image density signal OD generated based on the density threshold value S and the input image signal V is shown in FIG. In this way, when the image density signal OD relating to each color is supplied to the waveform control multi-value conversion circuit 30, the image density signal OD is converted into an analog signal via the D / A conversion circuit 301. Further, the pattern generation units 302 to 304 output triangular wave signals having different phases and periods. Here, when the image density signal OD is “255”, the digital signal output from the selectors 305 to 307 is always “1”, so the duty ratio of the output pulse modulation signal is “100%”.
[0064]
When the image density signal OD is “0”, the digital signal output from the selectors 305 to 307 is always “0”, so the duty ratio of the output pulse modulation signal is “0%”. When the image density signal OD is an intermediate density, the duty ratio of the output pulse modulation signal becomes a value corresponding to the intermediate density. At that time, the halftone dot shape shown in FIG. 10D or 10E can be considered depending on the triangular wave signal used.
[0065]
For example, as shown in FIG. 10 (d), when multi-value processing is performed using a single triangular wave pattern, a toggling occurs, which is not satisfactory. However, in this embodiment, the selection circuit 308 performs the switching process so that the triangular wave pattern shown in FIG. Therefore, on the other hand, when the waveform control multi-value is made based on the waveform control pattern SCS, a smooth halftone dot shape originally assumed can be generated as shown in FIG.
[0066]
C. Effects of the embodiment
(1) As described above, according to the present embodiment, the condition “input image signal V <density threshold value S” is satisfied, and “value N (N = V−S + D) is not a negative value. The intermediate density corresponding to the value N is set for the sub-pixel satisfying the condition “ That is, there is no conflict between the resolution and the number of reproduced gradations, and a sufficient number of reproduced gradations can be obtained even when the number of subpixels constituting the screen pattern is small.
[0067]
(2) Further, according to the present embodiment, there is a second sub-pixel adjacent to the first sub-pixel having an intermediate density in the main scanning direction and having a lower density threshold than the first sub-pixel. In this case, the triangular wave signal is selected so that the on-state portions of the first and second subpixels are continuous. Thereby, the screen shape can be prevented from being deformed, and a high-quality output image can be stably obtained.
[0068]
(3) Further, according to the present embodiment, the use of staggered lines for the K-color “0 °” halftone dot pattern makes it difficult for pseudo contours to occur even when the analog screen portion changes due to changes over time. Furthermore, by selecting a preferable pixel growth method for each of the edge portion and the non-edge portion in real time, smooth image reproduction can be realized without making the switching boundary conspicuous.
[0069]
D. Modified example
The present invention is not limited to the first or second embodiment described above, and various modifications can be made. For example, in the first or second embodiment, as the first and second triangular wave signals, triangular wave signals having different phases by “180 °” are used. One of these sawtooth signals may be selected as a reference signal based on the switching signal SCS.
[0070]
In the above-described first or second embodiment, the example in which the density pattern method is used has been described. However, the present invention can be similarly applied even when the dither method is used. That is, the “subpixel” in the first or second embodiment is considered as “one pixel” in the dither method, and an image density signal by the dither method may be used as the image density signal OD. Thereby, the thing of the said embodiment converts n input pixel Q1, Q2, ..., Qn into n output pixel R1, R2, ..., Rn corresponding, respectively.
[0071]
Further, in the output pixel value calculation circuit 20, the pixel value is calculated using a subtractor and a multiplier, but a gradation table may be used instead of using a subtractor or a multiplier.
[0072]
【The invention's effect】
As described above, according to the present invention, according to the sub-scanning direction switching unit, the gradation correction unit to be used is selected from among the plurality of gradation correction units according to the position in the sub-scanning direction where the input pixel exists. By switching, the gradation of the density data of the input pixel is corrected, so there is no conflict between the resolution and the number of reproduced gradations, and the degree of freedom of the screen shape can be increased. There is an advantage that a quality output image can be obtained stably.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing a halftone dot pattern conversion method.
FIG. 3 is a conceptual diagram illustrating an example of a halftone dot pattern.
FIG. 4 is a block diagram illustrating a configuration of an output pixel value calculation circuit.
FIG. 5 is a conceptual diagram for explaining the principle of halftoning by a conventional binarization method.
FIG. 6 is a conceptual diagram for explaining the principle of halftoning according to the present embodiment.
FIG. 7 is a conceptual diagram illustrating an example of tone reproduction characteristics and correction tone characteristics.
FIG. 8 is a conceptual diagram showing an example of tone reproduction characteristics and correction tone characteristics of an analog screen generator.
FIG. 9 is a block diagram showing a configuration of a waveform control multilevel circuit.
FIG. 10 is a conceptual diagram illustrating an example of an effect according to the present embodiment.
FIG. 11 is a conceptual diagram showing an example of a staggered line pattern according to the present embodiment.
FIG. 12 is a block diagram illustrating a processing configuration example of a dither method.
FIG. 13 is a conceptual diagram showing a comparison between a dither method and a density pattern method.
FIG. 14 is a conceptual diagram illustrating a binarization example of a density pattern method.
FIG. 15 is a conceptual diagram for explaining a screen angle generation cell (basic pattern).
FIG. 16 is a conceptual diagram for explaining generation of a screen angle.
FIG. 17 is a block diagram illustrating a configuration example of an analog triangular wave comparison method, and a conceptual diagram illustrating an operation example.
FIG. 18 is a conceptual diagram illustrating an example of an analog triangular wave comparison method.
[Explanation of symbols]
20 Output pixel value calculation circuit
30 Waveform control multi-value circuit
103 Halftone dot pattern memory
111 Waveform control pattern memory
112 gradation control pattern memory
201 Subtractor
202 multiplier
203 comparator
204 Comparator
205 LUT
206 LUT
208 decoder
209 Selector
210 gradation gain register

Claims (4)

In an image processing apparatus that corrects gradation of density data of input pixels,
A plurality of gradation correction means having predetermined different correction rules, and correcting the gradations of the input pixels according to the correction rules each has;
A sub-scanning direction switching unit that switches a gradation correction unit to be used among the plurality of gradation correction units according to a position in the sub-scanning direction where the input pixel exists ;
The gradation correction means switched by the sub-scanning direction switching means is means for switching in the main scanning direction in a three-pixel cycle, and an input pixel row arranged in the sub-scanning direction as the first pixel in the three-pixel cycle is represented by “L ”,“ C ”represents an input pixel column arranged in the sub-scanning direction as the second pixel in the three-pixel cycle, and“ R ”represents an input pixel column arranged in the sub-scanning direction as the third pixel in the three-pixel cycle. In this case, the gradation correction is performed so that the pixel growth rate of the input pixel column L and the input pixel column R is corrected to be slow, and the pixel growth rate of the input pixel column C is corrected to be high. An image processing apparatus comprising: main scanning direction switching means for switching means. The sub-scanning direction switching unit switches the gradation correction unit to be used every two line periods in the sub-scanning direction,
The main scanning direction switching means sets the input pixels lined up in the main scanning direction on the first line of the two-line cycle to “E” and the input pixels lined up in the main scanning direction on the second line of the two-line cycle. If “O”,
When correcting the input pixel O of the input pixel column R so that the pixel growth rate is slower than that of the input pixel O of the input pixel column L, the input pixel column E is changed to the input pixel column R. Correction so that the pixel growth rate is faster than the input pixel E of L,
When correcting the input pixel O of the input pixel column R so that the pixel growth rate is faster than that of the input pixel O of the input pixel column L, the input pixel column E is changed to the input pixel column R. The image processing apparatus according to claim 2 , wherein the correction is performed so that the pixel growth rate is slower than the input pixel E of L. In an image processing apparatus having a plurality of gradation correction means for correcting the gradation of an input pixel according to different correction rules, an image processing method for correcting the gradation of density data of an input pixel,
The image processing device
According to the position of the input pixel in the sub-scanning direction, among the plurality of gradation correction means, the gradation correction means to be used is switched,
Among the input pixel columns having a three-pixel cycle in the main scanning direction, the input pixel column aligned in the sub-scanning direction serving as the first pixel is “L”, and is aligned in the sub-scanning direction serving as the second pixel of the three-pixel cycle. When the input pixel column is “C” and the input pixel column arranged in the sub-scanning direction as the third pixel in the three-pixel cycle is “R”, the pixel growth of the input pixel column L and the input pixel column R An image processing method in which the gradation correction unit is switched so that correction is performed so as to reduce the speed and correction is performed so that the pixel growth speed of the input pixel column C is increased. The image processing apparatus is
While switching the gradation correction means to be used every two line periods in the sub-scanning direction,
When the input pixels lined up in the main scanning direction on the first line of the two-line period are “E” and the input pixels lined up in the main scanning direction on the second line of the two-line period are “O”, When correcting the input pixel O of the input pixel column R so that the pixel growth rate is slower than that of the input pixel O of the input pixel column L, the input pixel column L is changed to the input pixel column L. When correcting so that the pixel growth rate is faster than that of the input pixel E, and correcting the input pixel O of the input pixel row R to be faster than the input pixel O of the input pixel row L The image processing method according to claim 3, wherein the input pixel E of the input pixel column R is corrected so that a pixel growth rate is slower than the input pixel E of the input pixel column L.

Images