JP3826784B2 - Integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit in which a main device and a plurality of peripheral devices are connected by a bus, and operating voltages of two or more devices among the main device and the peripheral devices are different from each other.
[0002]
[Prior art]
Conventionally, an integrated circuit in which a main device and a plurality of peripheral devices are provided and connected to each other by a bus is used. FIG. 10 is a block diagram showing a conventional integrated circuit. As shown in FIG. 10, in this conventional integrated circuit, a main device 104 is provided, for example, three peripheral devices 101 to 103 are provided, and the main device 104 and the peripheral devices 101 to 103 are connected to each other, An address data bus 105 for transmitting an address signal and a data signal between these devices is provided.
[0003]
The main device 104 is supplied with a power supply voltage having a voltage of VDD0 (hereinafter referred to as voltage VDD0), and operates with the voltage VDD0. The address data bus 105 is supplied with a power supply voltage having a voltage of VDD (hereinafter referred to as voltage VDD) via the main device 104, and operates based on the voltage VDD. The peripheral device 101 is supplied with a power supply voltage having a voltage of VDD1 (hereinafter referred to as voltage VDD1) and operates by the voltage VDD1, and the peripheral device 102 is supplied with a power supply voltage having a voltage of VDD2 (hereinafter referred to as voltage VDD2). The peripheral device 103 is supplied with a power supply voltage having a voltage of VDD3 (hereinafter referred to as voltage VDD3) and operates with the voltage VDD3.
[0004]
The main device 104 outputs peripheral device control signals EN101 to EN103 to the peripheral devices 101 to 103 without going through the address data bus 105. The peripheral device control signals EN101 to EN103 are signals for enabling the operations of the peripheral devices 101 to 103, respectively. The main device 104 supplies peripheral device control signals EN101 to EN103 according to the operation of each peripheral device.
[0005]
In such an integrated circuit, the main device 104 outputs, for example, the peripheral device control signal EN101, enables the operation of the peripheral device 101, and then addresses with the peripheral device 101 via the address data bus 105. Exchanges signals and data signals. Similarly, the peripheral devices 102 and 103 also exchange address signals and data signals.
[0006]
[Problems to be solved by the invention]
However, the conventional techniques described above have the following problems. In the integrated circuit shown in FIG. 10, since the main device 104 and the peripheral devices 101 to 103 are connected to each other via the address data bus 105, the operating voltages of the peripheral devices 101 to 103 and the main device 104 are Must have the same voltage. For example, when the peripheral devices 101 and 102 are devices that operate in a voltage range of 1.5 to 3.0 V, and the peripheral device 103 is a device that operates in a voltage of 3.0 V, the main device 104 and the address data bus The power supply voltages of 105 and all peripheral devices (peripheral devices 101 to 103), that is, the power supply voltages of VDD0, VDD, VDD1, VDD2, and VDD3 must be unified to 3.0V.
[0007]
As a result, although the peripheral devices 101 and 102 can operate at a low voltage of 1.5V, the operating voltage of the peripheral device 103 is 3.0V, so that it is necessary to operate with a power supply voltage of 3.0V. For this reason, the power consumption of the peripheral devices 101 and 102 increases compared with the case where the voltages VDD1 and VDD2 are set to 1.5V.
[0008]
In addition, for example, when the operating voltage (VDD1) of the peripheral device 101 and the operating voltage (VDD2) of the peripheral device 102 are 1.5V and the operating voltage (VDD3) of the peripheral device 103 is 3.0V, the voltage VDD1 If there is no common voltage range between VDD3 and VDD3, it is necessary to provide voltage adjustment means for signals for passing signals such as a level shift circuit between the peripheral devices 101 to 103 and the main device 104. For example, in the case of the integrated circuit shown in FIG. 10, it is necessary to provide a total of three level shift circuits so as to correspond to the peripheral devices 101 to 103. This increases the cost of the integrated circuit and inhibits the miniaturization of the integrated circuit.
[0009]
The present invention has been made in view of such problems, and in an integrated circuit in which a main device and a plurality of peripheral devices are connected by a bus, the operation voltage of the main device and each peripheral device is made different from each other. An object of the present invention is to provide an integrated circuit that does not require a voltage adjusting means such as a level shift circuit for each peripheral device.
[0010]
[Means for Solving the Problems]
An integrated circuit according to the present invention includes a main device, first to n-th peripheral devices that operate with first to n-th (n is a natural number of 2 or more) voltages, the main device, and the first to first and n peripheral devices connected to each other and a bus for transmitting signals between the main device and the first to n-th peripheral devices, wherein the main device is driven by a main device voltage. A main circuit that operates and generates a signal in which a potential difference between a high level and a low level is equal to the voltage for the main device, and the first to nth voltages are inputted and the main circuit is derived from the first to nth voltages A power switching circuit for selecting and outputting a k-th (k is a natural number from 1 to n) voltage based on a power switching control signal output from the main device voltage and the power switching The k-th voltage output from the circuit is applied, and a signal in which the potential difference between the high level and the low level is equal to the main device voltage is input from the main circuit, and this signal is applied between the high level and the low level. The potential difference is converted into a signal equal to the kth voltage and output to the kth peripheral device among the first to nth peripheral devices via the bus, and from the kth peripheral device to the bus. A signal having a potential difference between the high level and the low level equal to the kth voltage is input via the signal, and the signal is converted into a signal having a potential difference between the high level and the low level equal to the main device voltage. And a bus circuit that outputs to the main circuit.
[0011]
In the present invention, a power supply switching circuit is provided in the main device, and when the main device exchanges signals with the kth peripheral device, the power supply switching circuit changes the kth voltage from the first to nth voltages. The signal is selected and outputted to the bus circuit, and the bus circuit mutually converts a signal whose potential difference between the high level and the low level is the main device voltage and a signal whose potential difference is the kth voltage. As a result, the potential difference of signals exchanged between the main device and each peripheral device becomes equal to the operating voltage of each peripheral device. For this reason, even if the operating voltage of the peripheral device is set to an arbitrary voltage regardless of the operating voltages of other peripheral devices and the main device, it may hinder the exchange of signals between the peripheral device and the main device. Absent. As a result, the operation voltage of the main device and each peripheral device can be made different from each other without providing a level shift circuit or the like for each peripheral device. Power consumption can be minimized.
[0012]
Another integrated circuit according to the present invention includes a main device, first to n-th peripheral devices that operate with first to n-th (n is a natural number of 2 or more) voltages, the main device, and the first device, respectively. An integrated circuit having a data bus and an address bus which are connected to each other to transmit a data signal and an address signal between the main device and the first to n-th peripheral devices, respectively. The main device operates by a main device voltage and generates a data signal and an address signal in which a potential difference between a high level and a low level is equal to the main device voltage, and the first to nth voltages. The kth (k is a natural number from 1 to n) voltage based on the power switching control signal output from the main circuit from the first to nth voltages. A power supply switching circuit to be selected and output, and the main device voltage and the kth voltage output from the power supply switching circuit are applied, and a potential difference between the high level and the low level from the main circuit is the main device. A data signal equal to the operating voltage is input, the data signal is converted into a data signal having a potential difference between the high level and the low level equal to the kth voltage, and the first to n peripheral devices are connected via the data bus. Is output to the kth peripheral device, and a data signal in which the potential difference between the high level and the low level is equal to the kth voltage is input from the kth peripheral device via the data bus. The data signal is converted into a data signal in which the potential difference between the high level and the low level is equal to the voltage for the main device, to the main circuit An address signal is applied to the data bus circuit to be output, and an address signal in which the potential difference between the high level and the low level is equal to the main device voltage is input from the main circuit, and this address signal is set between the high level and the low level. Is converted to an address signal equal to the address voltage, and is output to the kth peripheral device among the first to n peripheral devices via the address bus, and the kth peripheral device outputs the signal. An address signal in which the potential difference between the high level and the low level is equal to the address voltage is input via the address bus, and the address signal is converted into an address signal in which the potential difference between the high level and the low level is equal to the main device voltage. And an address bus circuit for outputting to the main circuit. And
[0013]
The main circuit outputs first to n-th peripheral device control signals that enable the operations of the first to n-th peripheral devices, respectively, and the main device outputs a signal to the k-th peripheral device. When the communication is performed, it is preferable that the main circuit outputs a kth peripheral device control signal to the kth peripheral device to enable the operation of the kth peripheral device.
[0014]
Thereby, only the operation of the peripheral device that exchanges signals with the main device can be validated, and the operation of other peripheral devices can be invalidated. As a result, it is possible to prevent a peripheral device that does not exchange signals with the main device from malfunctioning.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. 1 is a block diagram showing an integrated circuit according to the first embodiment, FIG. 2 is a block diagram showing a main device shown in FIG. 1, and FIG. 3 is a circuit diagram showing a power supply switching circuit shown in FIG. 4 is a block diagram showing the address data bus circuit shown in FIG. 2, FIG. 5 is a circuit diagram showing the output buffer unit shown in FIG. 4, and FIG. 6 is a circuit showing the input buffer unit shown in FIG. FIG. 7 is a circuit diagram showing an inverter of the bus folder shown in FIG.
[0016]
As shown in FIG. 1, in the integrated circuit according to the present embodiment, a main device 4 is provided, for example, three peripheral devices 1 to 3 are provided. In addition, an address data bus 5 for connecting the main device 4 and the peripheral devices 1 to 3 to each other and transmitting an address signal and a data signal between these devices is provided. That is, the main device 4 and the peripheral devices 1 to 3 are connected to the address data bus 5 in parallel.
[0017]
The main device 4 has a power supply voltage having a voltage VDD0 (voltage VDD0), a power supply voltage having a voltage VDD1 (voltage VDD1), a power supply voltage having a voltage VDD2 (voltage VDD2), and a power supply voltage having a voltage VDD3 (voltage VDD3). Have been supplied. The address data bus 5 is supplied with a power supply voltage (voltage VDD) having a voltage VDD from the main device 4 and operates with the voltage VDD. The peripheral device 1 is supplied with the voltage VDD1 and operates with the voltage VDD1. The peripheral device 2 is supplied with the voltage VDD2 and operates with the voltage VDD2. Further, the peripheral device 3 is supplied with the voltage VDD3 and operates with the voltage VDD3. VDD0, VDD1, VDD2, and VDD3 are mutually independent power supply voltages. That is, there are four types of power supply voltages in the integrated circuit of this embodiment.
[0018]
The main device 4 outputs peripheral device control signals EN1 to EN3 to the peripheral devices 1 to 3 without going through the address data bus 5. The peripheral device control signals EN1 to EN3 are signals for enabling the operations of the peripheral devices 1 to 3, respectively. The main device 4 supplies peripheral device control signals EN1 to EN3 according to the operation of each peripheral device.
[0019]
As shown in FIG. 2, the main device 4 includes a main circuit 6, a power supply switching circuit 7, and an address data bus circuit 8. The main circuit 6 is a circuit that performs the original function of the main device 4, operates by being supplied with the voltage VDD 0, receives the input signal IN from the address data bus circuit 8, and outputs it to the address data bus circuit 8. The signal OUT is output. The input signal IN and the output signal OUT are signals whose potential difference between the high level and the low level is the voltage VDD0. The main device 4 outputs a control signal CONT to the address data bus circuit 8. Further, the main device 4 outputs a power supply switching control signal 9 to the power supply switching circuit 7.
[0020]
The power supply switching circuit 7 is supplied with the voltage VDD1, the voltage VDD2, and the voltage VDD3, and also receives the power supply switching control signal 9 output from the main circuit 6. The power supply switching circuit 7 selects one of the supplied voltages VDD1 to VDD3 based on the power supply switching control signal 9 and supplies the selected voltage to the address data bus circuit 8 as the voltage VDD.
[0021]
The address data bus circuit 8 is supplied with the voltage VDD and the voltage VDD0. The address data bus circuit 8 receives an output signal OUT whose voltage difference between the high level and the low level (hereinafter simply referred to as potential difference) is the voltage VDD0 from the main circuit 6, and the potential difference between the output signal OUT and the voltage VDD (voltage VDD1). Or a voltage of any one of VDD3) and output to the address data bus 5. Further, a signal having a potential difference of voltage VDD is input from the address data bus 5, and this signal is converted into an input signal IN having a potential difference of voltage VDD 0 and input to the main circuit 6. The main circuit 6, the power supply switching circuit 7 and the address data bus circuit 8 are all connected to the ground potential GND.
[0022]
As shown in FIG. 3, in the power supply switching circuit 7, the three wirings 11 to 13 are provided so as not to contact each other. Voltages VDD1 to VDD3 are supplied to the wirings 11 to 13, respectively. The power supply switching circuit 7 is provided with three switches SW1 to SW3, and one ends of the switches SW1 to SW3 are connected to the wirings 11 to 13, respectively. The other ends of the switches SW1 to SW3 are connected to the common wiring 14. The operations of the switches SW1 to SW3 are controlled by a power supply switching signal 9, and based on the power supply switching signal 9, only one of the switches is closed and the other two switches are opened. As a result, a voltage of 1 selected from the voltages VDD1 to VDD3 is applied to the wiring 14. The voltage applied to the wiring 14 becomes the voltage VDD.
[0023]
As shown in FIG. 4, the address data bus circuit 8 includes an output buffer unit 16, an input buffer unit 17, and a bus folder unit 18. The address data bus circuit 8 is supplied with the voltage VDD output from the power supply switching circuit 7 and operates with this voltage VDD. In FIG. 4, the power supply voltage circuit is not shown. The output buffer unit 16 receives the output signal OUT and the control signal CONT output from the main circuit 6 (see FIG. 2), and outputs a signal whose level value is the same as the level value of the output signal OUT and whose potential difference is the voltage VDD. This signal is generated and output to the address data bus 5. When the level of the control signal CONT is the same level as the voltage VDD, that is, the high level, the output buffer unit 16 outputs a signal having the same level value as the signal input to the input terminal of the output buffer unit 16 and a potential difference of the voltage VDD. When the control signal CONT is output from the output terminal and the level of the control signal CONT is the same level as the ground potential GND, that is, the low level, the output terminal is brought into a high impedance state. The input buffer unit 17 receives a signal from the address data bus 5, generates an input signal IN having the same level value as this signal and a potential difference of voltage VDD 0, and outputs the input signal IN to the main circuit 6. Is. The bus folder unit 18 is configured by connecting two inverters 19 and 20 in a loop shape, and the output level of the output buffer unit 16 even when the output buffer unit 16 is disabled (unusable). Holds the value.
[0024]
As shown in FIG. 5, in the output buffer unit 16, a wiring 21 to which the voltage VDD is applied and a wiring 22 to which the ground potential GND is applied are provided. CMOSs 23 and 24 are connected in parallel between the wiring 21 and the wiring 22. The input terminal of the CMOS 23 is an input terminal of the output buffer unit 16, and the output signal OUT output from the main circuit 6 is input thereto. The input terminal of the CMOS 24 is a terminal to which a control signal CONT is input. Further, PMOSs 25 and 26 and NMOS 27 are connected in series between the wiring 21 and the wiring 22, the gates of the PMOS 25 and NMOS 27 are connected to the output terminal of the CMOS 23, and the gate of the PMOS 26 is connected to the output terminal of the CMOS 24. Has been. Further, an NMOS 28 is provided, its source is connected to the drain of the PMOS 26 and the source of the NMOS 27, its gate is connected to the output terminal of the CMOS 24, and its drain is connected to the wiring 22. Note that in this specification, when referring to a source or drain of a PMOS or NMOS, the high potential side is called a source, and the low potential side is called a drain.
[0025]
In the output buffer unit 16, a CMOS 29 is provided between the wiring 21 and the wiring 22, and its input terminal is connected to the drain of the PMOS 26 and the source of the NMOS 27. A PMOS 30 and NMOSs 31 and 32 are connected in series between the wiring 21 and the wiring 22, the gates of the PMOS 30 and NMOS 31 are connected to the output terminal of the CMOS 23, and the control signal CONT is input to the gate of the NMOS 32. It has come to be. Further, a PMOS 33 is provided, its source is connected to the wiring 21, its gate is supplied with a control signal CONT, and its drain is connected to the drain of the PMOS 30 and the source of the NMOS 31. Furthermore, a CMOS 34 is provided between the wiring 21 and the wiring 22, and its input terminal is connected to the drain of the PMOS 30 and the source of the NMOS 31. Furthermore, a PMOS 35 and an NMOS 36 are connected in series between the wiring 21 and the wiring 22, the gate of the PMOS 35 is connected to the output terminal of the CMOS 29, and the gate of the NMOS 36 is connected to the output terminal of the CMOS 34. The drain of the PMOS 35 and the source of the NMOS 36 are output terminals of the output buffer unit 16 and are connected to the address data bus 5 (see FIG. 4).
[0026]
As shown in FIG. 6, in the input buffer unit 17, a wiring 41 to which the voltage VDD0 is applied is provided, and CMOSs 42 and 43 are connected in parallel between the wiring 41 and the ground electrode. A signal output from the address data bus 5 (see FIG. 4) is input to the input terminal of the CMOS 42. The output terminal of the CMOS 42 is connected to the input terminal of the CMOS 43. Further, the output terminal of the CMOS 43 is an output terminal of the input buffer unit 17, and the input signal IN is output to the main circuit 6 (see FIG. 2).
[0027]
Further, as shown in FIG. 7, the two inverters 19 and 20 of the output buffer unit 18 are each configured by a CMOS connected between the wiring 51 to which the voltage VDD is applied and the ground electrode. The output terminal of the output buffer unit 16, the input terminal of the input buffer unit 17, and the address data bus 5 shown in FIG. 4 are connected to the CMOS input terminal that constitutes the inverter 19, and this CMOS output terminal constitutes the inverter 20. The CMOS input terminal is connected to the CMOS input terminal, and the CMOS output terminal is connected to the CMOS input terminal constituting the inverter 19.
[0028]
Next, the operation of the integrated circuit of this embodiment will be described. For example, when the main device 4 shown in FIG. 1 exchanges address signals and data signals with the peripheral device 2, the main circuit 6 (see FIG. 2) of the main device 4 outputs the peripheral device control signal EN2. . Thereby, the operation of the peripheral device 2 becomes effective.
[0029]
Next, as shown in FIG. 2, the main circuit 6 outputs a power supply switching control signal 9 to the power supply switching circuit 7. Thereby, as shown in FIG. 3, the power switching circuit 7 closes the switch SW2 and opens the switches SW1 and SW3 based on the power switching control signal 9. As a result, the wiring 12 to which the voltage VDD2 is applied is connected to the wiring 14, and the voltage VDD of the wiring 14 becomes equal to the voltage VDD2. As a result, the power supply switching circuit 7 applies the voltage VDD equal to the voltage VDD2 to the address data bus circuit 8 as its output voltage. As a result, a voltage equal to the voltage VDD2 is applied to the power supply voltage VDD of the output buffer unit 16 and the bus folder unit 18 shown in FIG.
[0030]
On the other hand, the main circuit 6 (see FIG. 2) outputs the output signal OUT and the control signal CONT to the output buffer unit 16 of the address data bus circuit 8. At this time, the control signal CONT is at a high level. Therefore, the output buffer unit 16 receives the output signal OUT at the input terminal, generates a signal whose level value is the same as the output signal OUT, and the potential difference between the high level and the low level is VDD (VDD2), This signal is output from the output terminal. The output signal OUT includes an address signal and a data signal.
[0031]
The operation of the output buffer unit 16 will be described in more detail. As shown in FIG. 5, when a high level (hereinafter referred to as H) signal is input to the output buffer unit 16 as the control signal CONT, the input of the CMOS 24 becomes H and the output is low level (hereinafter referred to as L). become. As a result, the PMOS 26 is turned on and the NMOS 28 is turned off. On the other hand, the NMOS 32 is turned on and the PMOS 33 is turned off.
[0032]
In this state, when H is input to the output buffer unit 16 as the output signal OUT, the input of the CMOS 23 is H and the output is L. As a result, the PMOS 25 is turned on and the NMOS 27 is turned off. For this reason, the input of the CMOS 29 becomes H and its output becomes L. As a result, the PMOS 35 is turned ON. On the other hand, when the output of the CMOS 23 becomes L, the PMOS 30 is turned on and the NMOS 31 is turned off. As a result, the input of the CMOS 34 becomes H, the output thereof becomes L, and the NMOS 36 is turned OFF. Thus, the PMOS 35 is turned on and the NMOS 36 is turned off, so that the output signal of the output buffer unit 16 becomes H.
[0033]
On the other hand, when L is input as the output signal OUT in a state where H is input as the control signal CONT, the input of the CMOS 23 becomes L and the output thereof becomes H. As a result, the PMOS 25 is turned off and the NMOS 27 is turned on. Therefore, the input of the CMOS 29 becomes L and the output becomes H. As a result, the PMOS 35 is turned off. On the other hand, when the output of the CMOS 23 becomes H, the PMOS 30 is turned off and the NMOS 31 is turned on. As a result, the input of the CMOS 34 becomes L, the output thereof becomes H, and the NMOS 36 is turned ON. Thus, the PMOS 35 is turned off and the NMOS 36 is turned on, so that the output signal of the output buffer unit 16 becomes L. Therefore, the output buffer unit 16 outputs a signal having the same level value as the input output signal OUT. Further, since the power supply voltage of the output buffer unit 16 is the voltage VDD (VDD2), the potential difference between the signals is the voltage VDD (VDD2). The output buffer unit 16 outputs this output signal to the bus folder unit 18 (see FIG. 4) and the address data bus 5.
[0034]
In the bus folder unit 18 shown in FIG. 4, when the output signal of the output buffer unit 16 is H, the input of the inverter 19 is H and the output is L. Therefore, the input of the inverter 20 becomes L and the output becomes H. On the other hand, when the output signal of the output buffer unit 16 is L, the input of the inverter 19 is L and its output is H. Therefore, the input of the inverter 20 becomes H and the output becomes L. Therefore, the bus folder unit 18 can hold the level value of the output signal even when the output terminal of the output buffer unit 16 is in a high impedance state.
[0035]
As shown in FIG. 1, the output signal of the output buffer unit 16 is output to the peripheral device 2 via the address data bus 5 as the output signal of the main device 4. At this time, the output signal of the main device 4 is also output to the peripheral devices 1 and 3, but the operation of the peripheral devices 1 and 3 is disabled by the peripheral device control signal.
[0036]
As described above, in the output signal of the main device 4, the potential difference between the high level and the low level is the voltage VDD, and the voltage VDD is equal to the voltage VDD2. On the other hand, the operating voltage of the peripheral device 2 is the voltage VDD2. Therefore, the potential difference of the output signal of the main device 4 is equal to the operating voltage of the peripheral device 2, and no malfunction occurs.
[0037]
Next, the case where the output signal of the peripheral device 2 is input to the main device 4 will be described. As shown in FIG. 1, the output signal of the peripheral device 2 is input to the main device 4 via the address data bus 5. The output signal of the peripheral device 2 is a signal whose potential difference between the high level and the low level is VDD2. This signal is input to the address data bus circuit 8 (see FIG. 2) of the main device 4.
[0038]
At this time, the main circuit 6 outputs a low level signal to the address data bus circuit 8 as the control signal CONT. For this reason, the output terminal of the output buffer unit 16 is in a high impedance state. The operation of the output buffer unit 16 in this case will be described. As shown in FIG. 5, when a low level (L) signal is input to the output buffer unit 16 as the control signal CONT, the input of the CMOS 24 becomes L and its output becomes H. As a result, the PMOS 26 is turned off and the NMOS 28 is turned on. On the other hand, the NMOS 32 is turned off and the PMOS 33 is turned on. Therefore, the input of the CMOS 34 becomes H, the output thereof becomes L, and the NMOS 36 is turned OFF. Further, when the PMOS 26 is turned off and the NMOS 28 is turned on, the input of the CMOS 29 becomes L, the output thereof becomes H, and the PMOS 35 is turned off. As described above, when both the PMOS 35 and the NMOS 36 are turned OFF, the output terminal of the output buffer unit 16 enters a high impedance state.
[0039]
Therefore, a signal input from the peripheral device 2 to the address data bus circuit 8 of the main device 4 is input to the input buffer unit 17 without being input to the output buffer unit 16. As shown in FIG. 6, in the input buffer unit 17, the output signal of the peripheral device 2 is input to the input terminal of the CMOS 42. At this time, for example, if the output signal of the peripheral device 2 is H, the output of the CMOS 42 is L. Note that in the input signal of the CMOS 42, that is, the output signal of the peripheral device 2, the potential difference between the high level and the low level is VDD2, but the potential difference of the output signal of the CMOS 42 is VDD0. Then, the output signal of the CMOS 42 becomes the input signal of the CMOS 43. For example, when the input signal of the CMOS 43 is L, the output signal of the CMOS 43 is H. The output signal of the CMOS 43 becomes the output signal of the input buffer unit 17 and becomes the input signal IN inputted to the main circuit 6. That is, the input buffer unit 17 generates an input signal IN whose level value is the same as the level value of the output signal of the peripheral device 2 and whose potential difference is VDD0. As a result, the main circuit 6 can receive a signal whose content is the same as the output signal of the peripheral device 2 and whose potential difference between the high level and the low level is VDD0.
[0040]
In the above example, the case where the main device 4 exchanges signals with the peripheral device 2 has been described. However, when the main device 4 exchanges signals with the peripheral device 1 or 3, This is the same as the above example. That is, when the main device 4 exchanges signals with the peripheral device 1, the main circuit 6 outputs the peripheral device control signal EN1 to enable the operation of the peripheral device 1, and the operations of the peripheral devices 2 and 3 are performed. Invalid. Further, the main circuit 6 outputs a power switch control signal 9 to the power switch circuit 7, and the power switch circuit 7 closes the switch SW1 and opens the switches SW2 and SW3 based on the power switch control signal 9. The voltage VDD1 is selected as the voltage VDD. On the other hand, the main circuit 6 outputs an output signal OUT, and the address data bus circuit 8 converts the output signal OUT from a signal having a potential difference of VDD0 to a signal having a potential difference of VDD1, and sends it to the peripheral device 1 via the address data bus 5. input. The peripheral device 1 outputs the output signal to the address data bus circuit 8 via the address data bus 5, and the address data bus circuit 8 outputs the output signal from the signal having the potential difference of VDD1 to the signal having the potential difference of VDD0. Into the main circuit 6.
[0041]
Similarly, when the main device 4 exchanges signals with the peripheral device 3, the main circuit 6 outputs the peripheral device control signal EN3, and the power supply switching circuit 7 selects the voltage VDD3 as the voltage VDD. Thereby, the potential difference of signals exchanged between the main device 4 and the peripheral device 3 is set to the voltage VDD3.
[0042]
As described above, the main circuit 6 of the main device 4 outputs the peripheral device control signals EN1 to EN3 in accordance with the timing of exchanging signals with the peripheral devices 1 to 3, thereby enabling the operation of the peripheral devices. At the same time, the operating voltage of the address data bus circuit 8 is switched to the same voltage as the operating voltage of the peripheral device by the power supply switching circuit 7 to adjust the potential difference between the signals input to and output from the main device 4.
[0043]
In this embodiment, in an integrated circuit in which the main device and each peripheral device operate with different power supply voltages, the main device uses the operating voltage of the connection portion (address data bus circuit) as the power supply voltage of each peripheral device. By switching appropriately, it is possible to suppress power consumption and exchange data in an optimal state at all times in the exchange of data between the main device and each peripheral device. Further, there is no need to provide a level shift circuit or the like for each peripheral device, and the integrated circuit can be reduced in size and cost.
[0044]
Also, when the main device outputs a peripheral device control signal, when the main device 4 exchanges data with, for example, the peripheral device 2, only the operation of the peripheral device 2 is validated, and other peripheral devices The operations 1 and 3 can be invalidated. As a result, it is possible to prevent the peripheral devices 1 and 3 from malfunctioning.
[0045]
Next, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing an integrated circuit according to this embodiment, and FIG. 9 is a block diagram showing a main device shown in FIG. As shown in FIG. 8, in the integrated circuit according to the present embodiment, a main device 64 is provided, for example, three peripheral devices 61 to 63 are provided. Further, the main device 64 and the peripheral devices 61 to 63 are connected to each other, and the data bus 65a for transmitting data signals between these devices, and the main device 64 and the peripheral devices 61 to 63 are connected to each other, and these devices are connected. An address bus 65b for transmitting an address signal between them is provided. That is, the main device 64 and the peripheral devices 61 to 63 are connected in parallel to the data bus 65a and the address bus 65b.
[0046]
The main device 64 is supplied with voltage VDD0, voltage VDD1, voltage VDD2, voltage VDD3 and voltage VDD4 as power supply voltages. The data bus 65a is supplied with a voltage VDD, which is one voltage selected from the group consisting of the voltage VDD1, the voltage VDD2, and the voltage VDD3 via the main device 64, and operates based on the voltage VDD. The address bus 65b is supplied with the voltage VDD4 via the main device 64 and operates with the voltage VDD4. The peripheral device 1 is supplied with the voltage VDD1 and the voltage VDD4, handles the data signal by the voltage VDD1, and handles the address signal by the voltage VDD4. The peripheral device 2 is supplied with the voltage VDD2 and the voltage VDD4, handles the data signal by the voltage VDD2, and handles the address signal by the voltage VDD4. Further, the peripheral device 3 is supplied with the voltage VDD3 and the voltage VDD4, handles the data signal by the voltage VDD3, and handles the address signal by the voltage VDD4. VDD0, VDD1, VDD2, VDD3, and VDD4 are mutually independent power supply voltages. That is, there are five types of power supply voltages in the integrated circuit of this embodiment.
[0047]
As described above, in the integrated circuit according to the present embodiment, the peripheral devices 61 to 63 handle the data signal with the voltages VDD1 to VDD3 and the address signal with the voltage VDD4 for the address signal, respectively. Therefore, the main device 64 only needs to switch the power supply voltage when exchanging data signals with the peripheral devices 61 to 63.
[0048]
As shown in FIG. 9, the main device 64 includes a main circuit 66, a power supply switching circuit 7, a data bus circuit 68a, and an address bus circuit 68b. The main circuit 66 is a circuit that performs an original function in the main device 64, operates by being supplied with the voltage VDD0, and receives input signals IN1 and IN2 from the data bus circuit 68a and the address bus circuit 68b, respectively. Output signals OUT1 and OUT2 are output to the circuit 68a and the address bus circuit 68b, respectively. The input signals IN1 and IN2 and the output signals OUT1 and OUT2 are signals whose potential difference between the high level and the low level is the voltage VDD0. The input signal IN1 and output signal OUT1 exchanged with the data bus circuit 68a contain only data signals, and the input signal IN2 and output signal OUT2 exchanged with the address bus circuit 68b have addresses. Only the signal is included. Further, the main device 64 outputs control signals CONT1 and CONT2 to the data bus circuit 68a and the address bus circuit 68b, respectively. Furthermore, the main device 64 outputs a power supply switching control signal 9 to the power supply switching circuit 7.
[0049]
The power supply switching circuit 7 is supplied with the voltage VDD1, the voltage VDD2, and the voltage VDD3, and also receives the power supply switching control signal 9 output from the main circuit 66. The power supply switching circuit 7 selects one of the supplied voltages VDD1 to VDD3 based on the power supply switching control signal 9 and outputs the selected voltage to the data bus circuit 68a.
[0050]
The voltage VDD and the voltage VDD0 are supplied to the data bus circuit 68a. In the data bus circuit 68a, an output signal OUT1 whose potential difference between the high level and the low level is the voltage VDD0 is input from the main circuit 66, and the potential difference of the output signal OUT1 is the voltage VDD (any one of the voltages VDD1 to VDD3). Is output to the data bus 65a. Further, a signal having a potential difference of voltage VDD is input from the data bus 65a, and this signal is converted into an input signal IN1 having a potential difference of voltage VDD0 and output to the main circuit 66.
[0051]
The voltage VDD4 is supplied to the address bus circuit 68b. The address bus circuit 68b receives the output signal OUT2 whose potential difference is the voltage VDD0 from the main circuit 66, converts this output signal OUT2 into a signal whose potential difference is the voltage VDD4, and outputs it to the address bus 65b. Further, a signal having a potential difference of voltage VDD4 is input from the address bus 65b, and this signal is converted into an input signal IN2 having a potential difference of voltage VDD0 and output to the main circuit 66. The main circuit 66, the power supply switching circuit 7, the data bus circuit 68a, and the address bus circuit 68b are all connected to the ground potential GND.
[0052]
In the present embodiment, the power supply switching circuit 7 selects one of the voltages VDD1 to VDD3 based on the power supply switching control signal 9, and outputs the voltage VDD to the data bus circuit 68a. The data bus circuit 68a operates by the voltage VDD and the voltage VDD0, converts the data signal (output signal OUT1) output from the main circuit 66 and having a potential difference of VDD0 into a data signal having a potential difference of VDD, and supplies the data signal to the data bus 65a. Output. Further, the data signal having the potential difference of VDD output from the peripheral devices 61 to 63 is converted into the data signal (input signal IN1) having the potential difference of VDD0 and output to the main circuit 66. As a result, the main circuit 66 exchanges data signals with the peripheral devices 61 to 63 via the data bus circuit 68a and the data bus 65a.
[0053]
The address bus circuit 68b operates with the voltage VDD4, converts an address signal (output signal OUT2) output from the main circuit 66 and having a potential difference of VDD0 into an address signal having a potential difference of VDD4, and outputs the address signal to the address bus 65b. Output. The address signal output from the peripheral devices 61 to 63 having a potential difference of VDD4 is converted into an address signal (input signal IN2) having a potential difference of VDD0 and output to the main circuit 66. As a result, the main circuit 66 exchanges address signals with the peripheral devices 61 to 63 via the address bus circuit 68b and the address bus 65b. Other configurations and operations of the integrated circuit of this embodiment are the same as those of the integrated circuit of the first embodiment described above.
[0054]
In the integrated circuit of this embodiment, since the data bus and the address bus are provided separately, and the data bus circuit and the address bus circuit are provided separately, the data signal and the address are transferred between the main device and the peripheral device. Signals can be exchanged separately. Thereby, the operation of the integrated circuit can be speeded up.
[0055]
In the integrated circuit of the second embodiment, a current may flow between the power supplies via the data bus depending on the potential difference between the voltages VDD1 to VDD3. In such a case, the power supply voltage of the peripheral device whose operation is disabled by the peripheral device control signal is set to the maximum voltage among the voltages VDD1 to VDD3, or the data of the peripheral device whose operation is enabled It may be the same as the operating voltage of the bus circuit. Thereby, it can prevent that an electric current flows between power supplies.
[0056]
In the first and second embodiments described above, the example in which the number of peripheral devices is three has been shown. However, the present invention is not limited to this, and the number of peripheral devices is two or four or more. May be. Furthermore, in the first and second embodiments described above, examples in which the operating voltages of the peripheral devices are different from each other have been shown. However, in the present invention, some of the peripheral devices may operate with the same voltage. . For example, in the first embodiment described above, the voltage VDD2 may be equal to the voltage VDD3. Even in such a case, it is necessary to change the operating voltage range of the peripheral device after manufacturing the integrated circuit if the main device is provided with power terminals for the number of types of necessary voltages in advance. For example, in the above-described example, even when it is necessary to reset the voltage VDD2 to a voltage different from the voltage VDD3, it is possible to cope with expandability.
[0057]
【The invention's effect】
As described above in detail, according to the present invention, in an integrated circuit in which a main device and a plurality of peripheral devices are connected by a bus, it is possible to operate the main device and each peripheral device with different operating voltages. it can. Thereby, the power consumption of the integrated circuit can be reduced without providing voltage adjusting means such as a level shift circuit for each peripheral device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a main device shown in FIG. 1;
FIG. 3 is a circuit diagram showing a power supply switching circuit shown in FIG. 2;
4 is a block diagram showing an address data bus circuit shown in FIG. 2. FIG.
5 is a circuit diagram showing an output buffer unit shown in FIG. 4; FIG.
6 is a circuit diagram showing an input buffer unit shown in FIG. 4; FIG.
7 is a circuit diagram showing an inverter of the bus folder section shown in FIG. 4; FIG.
FIG. 8 is a block diagram showing an integrated circuit according to a second embodiment of the present invention.
9 is a block diagram showing the main device shown in FIG. 8. FIG.
FIG. 10 is a block diagram showing a conventional integrated circuit.
[Explanation of symbols]
1, 2, 3; peripheral devices
4; Main device
5: Address data bus
6: Main circuit
7; Power switching circuit
8: Address data bus circuit
9: Power switch control signal
11, 12, 13, 14; wiring
16: Output buffer section
17: Input buffer section
18: Bus folder section
19; 20; Inverter
21, 22; wiring
23, 24, 29, 34; CMOS
25, 26, 30, 33, 35; PMOS
27, 28, 31, 32, 36; NMOS
41; Wiring
42, 43; CMOS
51: Wiring
61, 62, 63; peripheral devices
64; main device
65a; data bus
65b; address bus
66; main circuit
68a; data bus circuit
68b; address bus circuit
101, 102, 103; peripheral devices
104; main device
105: Address data bus
CONT: Control signal
EN1, EN2, EN3; peripheral device control signals
EN101, EN102, EN103; peripheral device control signal
GND: Ground potential
IN, IN1, IN2; input signals
OUT, OUT1, OUT2; output signals
SW1, SW2, SW3; switch
VDD, VDD0, VDD1, VDD2, VDD3, VDD4; power supply voltage

Claims (6)

The main device, the first to n-th peripheral devices operating with the first to n-th (n is a natural number of 2 or more) voltages, the main device and the first to n-th peripheral devices are mutually connected. In an integrated circuit having a bus connected to transmit a signal between the main device and the first to n-th peripheral devices, the main device operates with a voltage for main device and has a high level and a low level. A main circuit that generates a signal having a potential difference between them equal to the voltage for the main device, and a power supply switching control signal that is input from the first to nth voltages and that is output from the first to nth voltages from the main circuit A power switching circuit that selects and outputs a k-th voltage (k is a natural number from 1 to n) based on the main device voltage and the k-th voltage output from the power switching circuit. A voltage is applied, and a signal from which the potential difference between the high level and the low level is equal to the voltage for the main device is input from the main circuit, and the potential difference between the high level and the low level is changed to the kth voltage. The same signal is converted and output to the kth peripheral device among the first to n peripheral devices via the bus, and the high level and the low level are output from the kth peripheral device via the bus. A signal in which a potential difference between them is equal to the kth voltage is input, and this signal is converted into a signal whose potential difference between a high level and a low level is equal to the voltage for the main device and is output to the main circuit. And an integrated circuit. The integrated circuit of claim 1, wherein the signal comprises a data signal. The integrated circuit according to claim 1, wherein the signal includes an address signal. The bus circuit has an input terminal connected to the main circuit and an output terminal connected to the bus, to which the kth voltage output from the power supply switching circuit is applied. A signal in which the potential difference between the high level and the low level is equal to the voltage for the main device is input, and this signal is converted into a signal in which the potential difference between the high level and the low level is equal to the k-th voltage, and is sent via the bus. Output to the kth peripheral device, and when not operating, the output terminal is in a high impedance state, the input terminal is connected to the bus, and the output terminal is connected to the main circuit. The main device voltage is applied, and the potential difference between the high level and the low level from the kth peripheral device via the bus is a signal equal to the voltage of k is input, and this signal is converted into a signal in which the potential difference between the high level and the low level is equal to the voltage for the main device and input to the main circuit; 4. A bus folder unit connected to an output terminal and the bus and holding an output level value of the output buffer unit when the output buffer unit is not operating. An integrated circuit according to 1. The main device, the first to n-th peripheral devices operating with the first to n-th (n is a natural number of 2 or more) voltages, the main device and the first to n-th peripheral devices are mutually connected. In an integrated circuit having a data bus and an address bus connected to each other and transmitting a data signal and an address signal between the main device and the first to n-th peripheral devices, the main device is a main device voltage. And a main circuit for generating a data signal and an address signal in which a potential difference between a high level and a low level is equal to the main device voltage, and the first to nth voltages are input. A power switching circuit that selects and outputs a k-th voltage (k is a natural number from 1 to n) based on a power switching control signal output from the main circuit. The main device voltage and the kth voltage output from the power supply switching circuit are applied, and a data signal in which the potential difference between the high level and the low level is equal to the main device voltage is input from the main circuit. The data signal is converted into a data signal in which a potential difference between a high level and a low level is equal to the kth voltage, and is transmitted to the kth peripheral device among the first to nth peripheral devices via the data bus. And a data signal in which the potential difference between the high level and the low level is equal to the kth voltage is input from the kth peripheral device via the data bus, and the data signal is set to the high level and the low level. A data bus circuit that converts the potential difference between the data into a data signal equal to the main device voltage and outputs the data signal to the main circuit; An address signal is applied, and an address signal in which the potential difference between the high level and the low level is equal to the voltage for the main device is input from the main circuit, and the potential difference between the high level and the low level is converted into the address voltage. An equal address signal is converted and output to the kth peripheral device among the first to n peripheral devices via the address bus, and the high level is output from the kth peripheral device via the address bus. An address signal whose potential difference between the high level and the low level is equal to the address voltage is input, and the address signal is converted into an address signal whose potential difference between the high level and the low level is equal to the main device voltage. And an address bus circuit for outputting. The main circuit outputs first to n-th peripheral device control signals for enabling operations of the first to n-th peripheral devices, respectively, and the main device exchanges signals with the k-th peripheral device. The main circuit outputs a k-th peripheral device control signal to the k-th peripheral device to enable the operation of the k-th peripheral device. 6. The integrated circuit according to any one of 5 above.

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