JP3826146B2 - Wafer appearance inspection apparatus and wafer appearance inspection method - Google Patents

Description

  The present invention relates to a wafer appearance inspection apparatus and a wafer appearance inspection method for inspecting the appearance of a wafer in order to inspect the state of a chip after dicing.

  A dicing process is performed to divide the wafer on which the electronic circuit is formed into individual chips. In the dicing process, the wafer is attached to the ring frame with an adhesive tape called dicing tape, fixed to a dicing machine, and excavated and divided by a diamond blade. The foreign material in the cleaning water and cooling water used in this process, debris generated by abrasion of the diamond blade, or debris generated by excavation of the wafer and dicing tape cannot be cleaned with the cleaning water, and after drying, the surface of the wafer is dried. May remain and become dirty. In addition, chipping (cracking) may occur at the end of the chip due to various factors.

  Such chipping and contamination can lead to chip defects. Therefore, it is necessary to inspect the state of occurrence of chipping and dirt, and to take some measures if these occur to the extent that they lead to defects as chips.

  The wafer dicing is performed with the wafer attached to a dicing tape. However, the relative position and inclination of each chip cut by dicing may change over time depending on the properties of the tape.

  Such a change in the relative position and inclination of each chip may adversely affect subsequent processes. Therefore, it is necessary to inspect the relative position and inclination change of each chip after dicing, and if this is large, it is necessary to take some measures.

  The inspection of the occurrence of chipping and dirt as described above, and the change over time of the relative position and inclination of each chip after dicing has been conventionally performed visually using a microscope. For this reason, there is a problem that the work to be performed by the inspector is very complicated and the burden on the inspector is large.

  As described above, conventionally, since the inspection of the wafer appearance is performed by visual observation, there is a problem that the burden on the inspector is large.

  The present invention has been made in consideration of such circumstances, and its object is to reduce the burden on the inspector and to accurately inspect the appearance of the wafer and the wafer. It is to provide an appearance inspection method.

  In order to achieve the above object, the first invention provides an inspection stage for moving a ring frame on which a wafer having a plurality of chips formed thereon and a positioning mark is formed at a predetermined position, and the ring frame. Or a microscope for obtaining an enlarged image of a part of the wafer, an imaging means for taking an enlarged image obtained by the microscope and generating a corresponding electrical image signal, and a different part of the ring frame or the wafer. Based on the image indicated by the image signal and means for moving the ring frame by the inspection stage so that the imaging means sequentially captures images, the respective positions of the plurality of chips are detected as relative positions to the positioning marks. A position inspection unit, and a position of each of the plurality of chips detected by the position inspection unit. To constitute a wafer inspection system and means to keep accumulating be examined information.

  According to a second aspect of the present invention, there is provided an inspection stage for moving a ring frame on which a wafer on which a plurality of chips are formed and positioning marks are formed at predetermined positions, and enlargement of the ring frame or a part of the wafer. For inspecting the appearance of the wafer using a wafer appearance inspection apparatus comprising a microscope for obtaining an image and an imaging means for capturing an enlarged image obtained by the microscope and generating a corresponding electrical image signal In the wafer appearance inspection method, the ring frame is moved by the inspection stage so that the imaging unit sequentially images different parts of the ring frame or the wafer, and based on the image indicated by the image signal, the plurality of chips Each position is detected as a relative position with respect to the positioning mark, and the detected Inspection information representing respective positions of the serial plurality of chips so as to accumulate.

  According to the present invention, each position of the plurality of chips formed on the wafer mounted on the ring frame is automatically detected as a relative position with respect to the positioning mark formed on the ring frame. In addition, the wafer appearance can be inspected with high accuracy.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a functional block diagram showing a configuration of a wafer visual inspection apparatus according to the present embodiment.

  As shown in this figure, the wafer appearance inspection apparatus of this embodiment includes an inspection stage 1, a gantry 2, a magnescale 3, a stage controller 4, an operation panel 5, an optical microscope 6, a camera 7, an image processing apparatus 8, and an image monitor 9. , 10, data processing device 11, printer 12, inker 13, inker controller 14, and patrol light 15.

  The inspection stage 1 is placed on the top of the gantry 2. The inspection stage 1 is driven by a stage controller 4 to move a mounted wafer (not shown) freely in the XYZ-θ direction.

  The magnescale 3 is fixed to the gantry 2 and detects the position of the inspection stage 1 with a resolution of 0.1 μm.

  The stage controller 4 drives the inspection stage 1 based on an instruction from the image processing apparatus 8 or an instruction operation on the operation panel 5. The operation panel 5 is for the operator to manually operate the inspection stage 1.

  The optical microscope 6 uses epi-illumination and has a 3.3 times relay lens and five types of objective lenses (1.5 times, 2.5 times, 5 times, 10 times, and 20 times). Yes, and fixed to the gantry 2 by a main body (not shown). A camera 7 is mounted on the eyepiece side of the optical microscope 6, and an enlarged image of the wafer placed on the inspection stage 1 is guided to the camera 7.

  The camera 7 is composed of a CCD camera, takes an image guided by the optical microscope 6, and gives an electric signal (image signal) corresponding to the image to the image processing device 8.

  The image processing device 8 processes the image signal given from the camera 7 to detect chipping and dirt, determine the position of the chip, and the like.

  The image monitors 9 and 10 are made of a CRT, the image monitor 9 is obtained by processing an image (original image) corresponding to an image signal given from the camera 7, and the image monitor 10 is obtained by processing the image processing device 8. Each image (processed image) corresponding to the image signal is displayed.

  The data processing device 11 includes a personal computer, a keyboard, a display, and the like, and performs a totaling process of inspection data obtained by the image processing device 8.

  The printer 12 is a color printer, and prints out the data processed by the data processing device in a table format or a graph format.

  The inker 13 marks the defective chip by spraying ink onto the defective chip among the chips formed on the wafer placed on the inspection stage 1 under the control of the inker controller 14. The inker controller 14 receives information on the defective chip from the image processing device 8 and controls the inker 13 to mark the defective chip.

  The patrol light 15 notifies the operating state under the control of the image processing apparatus 8. Specifically, the lamp has three colors, red, yellow, and green, and the red lamp is lit when an abnormality occurs, the yellow lamp is lit when stopped or stopped, and the green lamp is lit during normal operation.

  Now, dicing is performed with the wafer attached to the ring frame. When inspection is performed, the wafer is mounted on the inspection stage 1 while being attached to the ring frame after the dicing is completed. .

  FIG. 2 is a view showing a state in which the wafer is attached to the ring frame. In this figure, 21 is a wafer, and 22 is a ring frame.

  The wafer 21 is not directly attached to the ring frame 22, but is translucent and adhesively stretched over the ring frame 22 so as to cover an inner region surrounded by the ring frame 22. Is attached to the tape 23 having

  The ring frame 22 is provided with two frame marks 24 a and 24 b formed at different positions so as to have a light reflectance different from that of the main body of the ring frame 22. Further, two notches 22a and 22b are formed at predetermined positions on the outer peripheral edge of the ring frame 22, respectively.

  On the other hand, as shown in FIG. 3, two positioning pins 31a and 31b project from the upper surface (wafer mounting surface) of the inspection stage 1 at predetermined positions. The positioning pins 31a and 31b are provided at positions corresponding to the notches 22a and 22b of the ring frame 22, and the notch 22a abuts on the positioning pin 31a and the notch 22b abuts on the positioning pin 31b. By mounting the ring frame 22 on the inspection stage 1, the wafer 21 is placed in a state of being roughly positioned with respect to the inspection stage 1.

  The inspection stage 1 has an air vacuum function and holds the mounted wafer 21 and ring frame 22 so as not to be displaced due to vibration or the like. The wafer placement surface of the inspection stage 1 is black.

  Next, the operation of the wafer visual inspection apparatus configured as described above will be described.

  Prior to performing the inspection, the image processing apparatus 8 and the data processing apparatus 11 accept settings of parameters such as threshold values and reference values necessary for image processing, wafer test conditions, and various parameters necessary for wafer inspection. After the necessary data has been prepared, the inspection is started.

  Now, the wafer appearance inspection apparatus of the present embodiment has three inspection modes: a dirt inspection mode, a chip inspection mode, and a chip position inspection mode. Further, the dirt inspection mode and the chip inspection mode have two modes of 1 chip / 1 field of view mode and division mode, respectively.

(1) When dirty mode is selected
(1-1) One chip / one field of view mode The one chip / one field of view mode is one chip based on an image obtained by imaging one whole of a large number of chips formed on the wafer 21 on one screen. This is a mode for performing an inspection.

  At this time, the operator sets the inspection stage 1 with the front surface (circuit formation surface) of the wafer 21 facing upward (a state facing the optical microscope 6), and manually operates the inspection stage 1 to complete the entire wafer. θ correction is performed. The operator manually operates the inspection stage 1 and the optical microscope 6 so that the entire start chip indicated by S in FIG. In FIG. 4, “x” indicates a chip formation position.

  When the start of inspection is instructed in this state, the image processing apparatus 8 first captures and digitizes the image signal output from the camera 7, and stores the image data obtained thereby in the built-in memory. Then, the chip range in the image captured by the camera 7 is specified as follows.

  That is, based on the image data stored in the memory, projection data (horizontal projection data and vertical projection data) in the X direction (horizontal direction) and the Y direction (vertical direction) are obtained as shown in FIG. The edge position of the chip is roughly specified by binarizing the data with an appropriate threshold value.

なる演算を行い、
ｙ＝Ａｘ＋Ｂ
なる直線式を求める。 Next, as shown in FIG. 5, n (arbitrary integers, for example, 10) search positions are set for each edge, and a memory search is performed for a predetermined range centered on the edge position for each search position. The actual edge position for each search position is detected, and its coordinates are obtained. Then, using the n coordinates obtained for each edge, a linear equation passing near each of the n coordinate points is obtained by the least square method. That is,

Perform the operation
y = Ax + B
The following linear equation is obtained.

  The four linear expressions thus obtained correspond to each of the four edges, and the range surrounded by the four edges is specified as the chip range. Also, the intersection of each edge is obtained based on the linear expression of each edge.

  When obtaining the edge linear equation as described above, if there is a large chip at the search position, the coordinates obtained for the search position are far away from the original chip edge. If used for calculation, the linear equation cannot be derived correctly. Therefore, such coordinates are set as invalid points as follows, and are not used for calculating a linear expression.

  That is, when the coordinates of 10 points P1 to P10 as shown in FIG. 6 are obtained, the difference d in the x direction from the adjacent points is obtained as follows.

d1 = | P1 (x) −P2 (x) |
d2 = | P2 (x) −P3 (x) |
d3 = | P3 (x) −P4 (x) |
d4 = | P4 (x) −P5 (x) |
d5 = | P5 (x) −P6 (x) |
d6 = | P6 (x) −P7 (x) |
d7 = | P7 (x) −P8 (x) |
d8 = | P8 (x) −P9 (x) |
d9 = | P9 (x) −P10 (x) |
Next, the maximum value of d1 to d9 is max, the minimum value is min,
the = min + max / 2 + 1
The threshold value the is obtained by the following formula.

  When | P1 (x) −P2 (x) | and | P1 (x) −P3 (x) | are both larger than the threshold value the P1 is set as an invalid point. Similarly for other points, if | Pk (x) −Pk + 1 (x) | and | Pk (x) −Pk + 2 (x) | are both larger than the threshold value the Pk is regarded as an invalid point. Set. However, the point of P9 is | P9 (x) −P8 (x) | and | P9 (x) −P10 (x) | are both greater than the threshold value the, and the point of P10 is | P10 (x) − When P8 (x) | and | P10 (x) −P9 (x) | are both larger than the threshold value the, they are set as invalid points.

  The above processing is similarly performed for the other three edges. However, for the edge along the X direction, the value of Pk (y) is used instead of Pk (x).

  Now, the image processing apparatus 8 sets a slightly small labeling inspection range (inside the chip range) as shown in FIG. 7 for the chip range obtained as described above, and then performs a labeling process within this labeling inspection range. Execute.

  In this labeling process, each block of black pixels existing in the labeling inspection range is detected, and the number is counted, the length and width of the circumscribed rectangle of the block are detected, the position of the block is detected, or the area is measured. I do. Specifically, the chip surface appears white on the binarized image, but the dirt appears black, so the dirt is detected as a black pixel block in the binarized image. In many cases, powder stains generated from a wafer or a diamond blade become substantially circular after drying. For this reason, for each black pixel block, it can be inferred from what cause the black pixel block is contaminated from the features such as the length and width (aspect ratio) and area of the circumscribed rectangle. The center of the circumscribed rectangle is set as the position of each black pixel block.

  Thus, in the example of FIG. 7, five black pixel blocks 61 to 65 are detected, and the length, position, area, etc. of the circumscribed rectangle for each are detected, and from the aspect ratio of the circumscribed rectangle, etc. 61 and 65 are classified as dirt originating from the powder, and 62, 63 and 64 are classified as dirt originating from the dicing tape.

  Note that the length and area of the circumscribed rectangle are detected as the number of pixels. And it converts into length or an area based on the relationship of the real visual field and the resolution | decomposability with respect to the magnification set with the optical microscope 6 shown in FIG. The area is finally determined as one of 20 area levels S1 to S20 set as shown in FIG.

  When the inspection related to one chip is completed by the above processing, the image processing apparatus 8 controls the stage controller 4 to move the inspection stage 1 in the x direction (right direction in FIG. 4) by a predetermined pitch, and the next chip is moved by the camera 7. Make sure that the image is captured. If the chip range is specified in the same manner as described above after the inspection stage 1 is moved by a predetermined pitch and it is detected that one chip is off the screen, the image processing apparatus 8 detects the inspection stage 1. Finely adjust 1 to fit one chip in the screen.

  Then, the image processing apparatus 8 performs an inspection on a chip newly imaged by the above-described procedure. Thereafter, each chip is inspected while sequentially changing the chips to be imaged by moving the inspection stage 1.

  When the inspection stage 1 is sequentially moved in the X direction, the wafer 21 eventually protrudes from the imaging position of the camera 7. Here, since the upper surface of the inspection stage 1 has a color (for example, black) having a light reflectance different from that of the wafer, and the dicing tape 23 is translucent, when the wafer 21 protrudes from the imaging position of the camera 7, The chip cannot be detected. Therefore, as shown in FIG. 4, if no chips can be detected for five chips, it is determined that the inspection for one line of chips in the X direction has been completed, and an inspection stage for inspecting the next line of chips. After 1 is moved by a predetermined pitch in the Y direction, it is moved by a predetermined pitch in the X direction (however, opposite to the previous line).

  The inspection information of each chip obtained as described above is given from the image processing device 8 to the data processing device 11 and managed for each chip.

(1-2) Divided Mode The divided mode is a method in which one of a plurality of chips formed on the wafer 21 is divided into a plurality of divided inspection areas and inspected for each divided inspection area. In this mode, the inspection information obtained by the above inspection is totaled to obtain inspection information on one chip. Since this division mode can increase the magnification of the optical microscope 6 as compared with the 1-chip / 1-view mode, it is an effective mode when used when the resolution is insufficient in the 1-chip / 1-view mode.

  More specifically, in this division mode, dirt is detected in the same manner as in the above-described 1 chip / 1 field of view mode, and the length, width, position, area, etc. of the circumscribed rectangle are detected for each. This is performed for each of a plurality of divided inspection areas. The number of divided inspection areas is set by the image processing apparatus 8 to a number that allows efficient inspection based on the magnification, chip size, and overlap amount in the optical microscope 6. The overlap amount indicates the width of the overlap portion when a part of adjacent divided inspection areas overlaps, and can be arbitrarily set by the operator. However, it is also possible to set the overlap amount to “0”, that is, so as not to overlap the divided inspection areas.

  When the number of divided inspection areas is set to 25 (5 × 5), for example, each divided inspection area is set as shown in FIG. 10 with respect to the chip area. FIG. 10 shows the divided inspection area set with the overlap amount “0”.

  Then, the image processing apparatus 8 controls the inspection stage 1 so that each divided inspection area is sequentially imaged by the camera 7 in the order indicated by the broken-line arrows in FIG. The same labeling process is performed as in. Thus, in the example of FIG. 10, the stains 91 to 99 are detected, respectively. The stains 91 and 96 are originally one stain, but are detected by being divided into two. Further, the stains 92, 93, 94, and 95 are originally one stain, but are detected by being divided into four.

  The inspection information of each divided inspection area obtained as described above is given from the image processing device 8 to the data processing device 11 as the inspection information of the corresponding chip. In the data processing device 11, all of the inspection information of the 25 divided inspection areas corresponding to one chip is managed for each chip as inspection information of one chip.

(2) When chip inspection mode is selected
(2-1) 1 chip / 1 field of view mode At this time, the operator sets the inspection stage 1 with the back surface (grind surface) of the wafer 21 facing upward (facing the optical microscope 6), and performs inspection. The stage 1 is manually operated to perform θ correction for the entire wafer. The operator manually operates the inspection stage 1 and the optical microscope 6 so that the entire start chip indicated by S in FIG. In FIG. 4, “x” indicates a chip formation position.

  When the start of inspection is instructed in this state, the image processing apparatus 8 first specifies the chip range and sets the labeling inspection range as shown in FIG. 11 in the same manner as in the dirt inspection mode. Then, a labeling process is performed on the black pixel block on the outer edge of the labeling inspection range. In this labeling process, the upper left corner of the labeling inspection range is used as a reference point to search clockwise along the outer edge of the labeling inspection range, touch the outer edge of the labeling inspection range, and be inside the labeling inspection range. The black pixel block that enters is detected. Then, measure the length of the side perpendicular to the outer edge of the labeling inspection area in the circumscribed rectangle having the outer edge of the labeling inspection area as one side, or use the reference point as the reference point at the intersection of the outer edge of the labeling inspection area and the chip edge. As a result, the position of the odd-numbered one is measured. Specifically, the chip back surface appears white on the binarized image, but the chipping appears black, and the chipping is the part where the chip edge is inward of the original edge position, so the outer edge of the labeling inspection range. The chipping is detected as a block of black pixels that touches the part and enters the inside of the labeling inspection range. In addition, since the side facing the outer edge of the labeling inspection range in the circumscribed rectangle of the black pixel block passes through the tip of the chip, the length of the side orthogonal to the outer edge of the labeling inspection range in the circumscribed rectangle is as follows: The depth of chipping can be detected with reference to the outer edge of the labeling inspection range. Also, when searching clockwise along the outer edge of the labeling inspection range, the position where the black pixel block is first detected, that is, the intersection of the outer edge of the labeling inspection area and the chip edge is used as a reference point. Since the odd-numbered one is the starting point of one chip, this is detected as information indicating the position of the chip.

  Thus, in the example of FIG. 11, 11 black pixel blocks 101 to 111 are detected as missing portions, and the depth and position (starting point) for each missing portion are detected.

  By the way, as shown in FIG. 12, when the chip has a chipped corner, two depths of La and Lb can be taken. Therefore, in such a case, the image processing apparatus 8 employs the smaller one (La in the example of FIG. 12) as the depth.

  Note that the length and area of the circumscribed rectangle are detected as the number of pixels. Then, the length is converted based on the relationship between the real field of view and the resolution with respect to the magnification set by the optical microscope 6 shown in FIG. Further, the length of the side perpendicular to the outer edge of the labeling inspection range in the circumscribed rectangle is finally determined as one of 20 depth levels L1 to L20 set as shown in FIG.

  Thereafter, each chip is inspected while sequentially changing the inspection target chips in the same manner as in the dirt inspection mode.

  Then, the obtained inspection information of each chip is given from the image processing device 8 to the data processing device 11 and managed for each chip.

(2-2) Division Mode At this time, the image processing apparatus 8 divides one chip area into a plurality of division inspection areas in the same manner as the division mode in the dirt search mode. In addition, chipping is detected in the same manner as in the above-described 1 chip / 1 field-of-view mode, and the length of each side perpendicular to the outer edge of the labeling inspection range in the circumscribed rectangle having the outer edge of the labeling inspection range as one side (chip missing). The depth of the labeling inspection range, and the position (defect position) of the odd-numbered detection with respect to the reference point among the intersections between the outer edge of the labeling inspection range and the chip edge is detected. This is performed for each chip located at the outer edge of the chip range.

  When the number of divided inspection areas is set to 25 (5 × 5), for example, each divided inspection area is set as shown in FIG. 14 with respect to the chip area. FIG. 14 shows a divided inspection area set with an overlap amount “0”.

  In this case, there are 16 division inspection regions to be subjected to the labeling inspection, which are located at the outer edge. The image processing apparatus 8 controls the inspection stage 1 so that these divided inspection areas are sequentially imaged by the camera 7 in the order indicated by the broken-line arrows in FIG. The same labeling process is performed as in. Thus, in the example of FIG. 14, twelve black pixel blocks 131 to 142 are detected as missing portions, and the depth and position of each missing portion are detected. Note that the chip 134 and chip 135, the chip 136 and chip 137, and the chip 131 and chip 142 are originally one chip, but are divided into two parts and detected.

  The inspection information of each divided inspection area obtained as described above is given from the image processing device 8 to the data processing device 11 as the inspection information of the corresponding chip. In the data processing apparatus 11, all the inspection information of the 16 divided inspection areas corresponding to one chip is managed for each chip as inspection information for one chip.

(3) Position inspection mode At this time, the image processing apparatus 8 obtains the positions of the two frame marks 24a and 24b provided on the ring frame 22, and passes through the two frame marks 24a and 24b as shown in FIG. A ring frame coordinate system is set with the straight line to be orthogonal to the straight line passing through the two frame marks 24a and 24b and the straight line passing through the frame mark 24a being the Y direction.

  Next, the image processing apparatus 8 obtains the coordinates of the four corners of the chip range for each chip formed on the wafer 21 by the above-described procedure, and develops it in the ring frame coordinate system as shown in FIG. Then, the coordinates of the four corners of each chip in the ring frame coordinate system are obtained and set as the chip position. Further, a straight line passing through the midpoints of the two opposing sides in the chip range is obtained as shown in FIG. 16, and the inclination θ of the straight line with respect to the ring frame coordinate system is obtained, and this is used as the inclination of the chip.

  The inspection information obtained as described above is given from the image processing device 8 to the data processing device 11, and is managed for each chip in the data processing device 11.

  In the data processing apparatus 11, the inspection information obtained from the image processing apparatus 8 by the above-described inspection processing and given from the image processing apparatus 8 is stored in a built-in hard disk or the like. The data processing device 11 performs data processing after the inspection for one wafer is completed, and creates standardized data.

  The standardized data is data obtained by tabulating inspection information of chips belonging to each block obtained by dividing the wafer 21 into appropriate blocks.

  As shown in FIG. 17A, the block may be a lattice block of 5 columns × 5 rows as shown in FIG. 17A, or in the circumferential direction around the center of the wafer 21 as shown in FIG. A total of 24 fan-shaped blocks of 8 and 3 in the radial direction may be used. That is, it is called a virtual block in the sense that a block may be arbitrarily set for convenience of calculation. For example, when paying attention to the cutting direction of the wafer, it may be a lattice block simulating an orthogonal coordinate system, or when paying attention to the shape of the wafer, if the wafer is circular, it may be a fan block simulating a polar coordinate system. good.

  Further, when the wafer is cut for each chip, there is a problem of which block on the boundary of the virtual block belongs to which adjacent block, and this may be processed by providing a rule. For example, a rule for including the chip in a block including the center point of the chip can be set. It is also possible to set a rule that a block is given priority to a chip, and a chip that comes into contact with a high priority block belongs to the block. The size of the chip is often arbitrary. Therefore, even if the wafers are the same size, the number of chips existing on one wafer is different. It is not necessary to change the position and division form of the block, being affected by the number of chips included in the block and its position. However, only the number of chips included in the block changes.

  Even when the wafer size is changed, if the same type of block shape is used, the blocks may be similarly enlarged or reduced at a ratio of the size of the wafer.

  In addition, it is more computationally convenient to assign a number or address to each virtual block.

  Now, as described above, there are cases where a chip is present in the block, but there are cases where a chip of the same size as the block is virtually present in the block in an uncut wafer. Since it can be considered, the normalized data will be described below assuming that at least one or more chips exist in the block.

  The normalized data is schematically represented in a state as shown in FIG. 18, for example.

As items in FIG. 18, for example, for a chip inspection, when a set of maximum depth values of chips belonging to one block is {lm}, the set {lm} and the maximum value are lm _max. , Average value is lm _av , minimum value is lm _min , variance is Lmσ, processed wafer number (wafer No.), date, total number of inspection chips on wafer (inspection chip number G.totol), multiple wafers (For example, 10 wafers) Number of wafers indicating processing, number of inspection chips as a whole, tape configuration indicating conditions such as tape product name and adhesive as common conditions, processing the tape and the wafer to be inspected The device name, the mounter condition as the condition of the apparatus, the dicing condition, the expanding condition of the tape after dicing, and the like are displayed.

The inspected results for each wafer are calculated for lm _max , lm _av , lm _min , and lm σ for each block as described above, and each block number (in FIG. 18, since it is a 25 block, Block 1, Block 2 to Block 25) It is displayed in each column corresponding to.

The total of all wafers is obtained by calculating the respective average values for {lm _max }, (lm _av }, {lm _min }, and {lmσ}, which are a set of the above lm _max , lm _av , lm _min , and lmσ. Is displayed in the column No Block subtotal 1 to Block subtotal 25 of the Block subtotal of the lot total term, and the G.total term of the same term includes {lm _max } of each of the Block subtotal 1 to Block subtotal 25, The average value of {lm _av }... {Lmσ} is displayed.

In the above, the average value is used for all, but only the maximum value may be used for {lm _max }. In addition, lm _max , lm _av , lm _min , and lmσ are always lm _max , lm _max , average value lm _av , minimum value lm _min , and variance for {lm _max }, which are always subject to aggregation. It may be set to lmσ. Alternatively, various statistical methods may be introduced.

Values and calculation methods that can be commonly calculated from each chip to lot lotal, such as lm _max and ln _max , are referred to as normalized data.

  For position inspection, the gap between adjacent chips is calculated for each chip in the block, and the following standardized data is obtained for each wafer and lot total as in the case of chip inspection. Do.

When a set of measured values of the X direction gap between the left and right chips of a certain block in a block is {Gx} and a set of measured values of the upper and lower Y direction gaps is {Gy),
The maximum values of {Gx} and {Gy} are set to Gx _max and Gy _max
The minimum values of {Gx} and {Gy} are set to Gx _min and Gy _min
The average value of {Gx} and {Gy} is expressed as Gx _av and Gy _av
The variance of {Gx} and {Gy} is expressed as Gxσ and Gyσ
As in the case of the chip inspection, the same processing is performed.

For the dirt inspection, a set of the total values of the dirt areas on the chip in a certain block is set as {S},
The maximum value of {S} is set to S _max
Set the minimum value of {S} to S _min
The average value of {S} is S _av
The variance of {S} is expressed as Sσ
Are processed in the same manner as the chip inspection.

  In this way, by adding the inspection information on the wafer 21 to the standardized data, it is possible to grasp the tendency of the defect to occur at similar coordinates by changing the block size in accordance with this even with wafers of different sizes.

  Further, defect information based on standardized data using grid blocks is more easily correlated with conditions of a dicing machine or the like than non-standardized data. Furthermore, the defect information based on the standardized data of the fan-shaped block is more likely to correlate with various factors generated from a substantially circular wafer, dicing tape, or the like than non-standardized data or other standardized data.

  Also, the standardized data is not simply dividing a single wafer, but all chips on the wafer are blocked in a grid pattern as shown in FIG. May be standardized by summing them into one block. According to this method, one wafer can be evaluated as if it were one chip. Information on defects in the standardized data is not related to the position of the wafer, and is easily correlated with defects generated at specific positions on the chip.

  In FIG. 18, “Block Detail” indicates a virtual block of each chip. The standardized data and the blocking method are exactly the same as described above.

  In addition, the shaded part in FIG. 18 is given to a part that seems unnecessary. For example, in the position inspection, making a virtual block of a chip is meaningless.

  By the way, the chip located on the peripheral edge of the wafer 21 may not be rectangular as shown in FIG. Further, as shown in FIG. 19B, the chip adjacent to the chip located on the peripheral edge of the wafer 21 may not be rectangular. Since these chips are not normal defects but normal chips, they become invalid chips. Therefore, if the length of the side along the Y direction in the chip located at the peripheral edge of the wafer 21 is less than or equal to the original half, the data processing apparatus 11 sees the chip in the imaging order including the chip 3 Each of the chip and the first three chips in the next line (chips marked with “x” in FIG. 20) are standardized exclusion chips, and inspection information relating to these standardized exclusion chips is not used to create standardized data.

  The data processing device 11 edits the contents of the standardized data into a table format or a graph format in accordance with an instruction from the operator, and displays this on the display or causes the printer 12 to print out.

  Thus, according to the present embodiment, the following effects can be obtained.

  (1) Contamination and chipping are automatically detected for each of the chips formed on the wafer 21. Further, the position, area and number of dirt, or the position and depth of the chip are automatically obtained. Therefore, the inspector can easily and accurately know the state of the wafer 21 based on various information automatically obtained, and it is not necessary to perform the inspection by a complicated visual inspection using a microscope.

  Further, for each chip formed on the wafer 21, the position in the ring frame coordinate system determined by the frame marks 24a and 24b, that is, the relative position of each chip with respect to the ring frame 21 is automatically detected. Therefore, if the change in the position of each chip obtained by a plurality of inspections carried out at a certain time is verified, it is possible to easily and accurately recognize the extent of expansion of the dicing tape 23, and a microscope is used. There is no need for inspection by complicated visual inspection.

  (2) Chips are chipped at the corners of the chip. When two depths in the X and Y directions are obtained for the chip, the smaller value is used as the depth measurement value. It is possible to appropriately measure the depth of the chip at the corner.

  (3) Since the labeling inspection range is set slightly smaller than the actual chip range, dirt and chips are not detected within a predetermined range of the outer edge of the chip range. Is not erroneously detected as dirt and chipping.

  (4) Since the coordinates are determined based on the position of the inspection stage 1 detected with high accuracy using the magnescale 3, it is possible to prevent a measurement error from occurring due to an error in the amount of movement of the inspection stage 1 and improve the accuracy. be able to.

  (5) Since the upper surface of the inspection stage 1 is black and the reflectance of light is different from that of the chip portion which is a mirror surface, the level of the image signal is greatly different between the chip portion and the other portions. In the image processing apparatus 8, the chip portion and other portions can be reliably identified. From this, it is possible to accurately specify the chip range and chip edge in the image, and it is possible to accurately detect dirt and chipping or chip position.

  (6) If a chip cannot be detected even if the inspection stage 1 is moved over a predetermined number of chips, it is determined that the inspection up to the peripheral edge of the wafer 21 has been completed, and therefore exists on one line. Even if the number of chips is indefinite, the peripheral portion of the wafer 21 can be reliably determined without receiving designation of the position of the peripheral portion.

  (7) In the divided inspection mode, a part of adjacent divided inspection regions can be overlapped, so that it is possible to reliably inspect even dirt and chips present at the boundary portion of the divided inspection regions.

  (8) Since the image processing apparatus 8 sets the number of divided inspection areas to a number that can be efficiently inspected based on the magnification, chip size, and overlap amount in the optical microscope 6, it is not necessary for the operator to set it. It is possible to prevent the processing efficiency from being deteriorated due to setting of a division inspection area more than necessary.

  (9) The entire wafer 21 is divided into 25 uniform blocks regardless of their diameters, and standardized data is created by collecting inspection information relating to chips contained in each block. By doing so, it is possible to compare and deal with contamination, chipping, and chip position at the same level between wafers of different sizes.

  (10) The chips formed on the wafer 21 are uniformly divided into 25 blocks, and the inspection data relating to the chips on the wafer 21 is tabulated for each block to create standardized data. The standardized data is evaluated. As a result, a block obtained by dividing the entire wafer or the entire wafer 21 into 25 can be evaluated as if it were a single chip.

  (11) In the case where the length of the side along the Y direction in the chip located at the peripheral edge of the wafer 21 is less than or equal to the original half, the front three chips including the chip in the order of imaging and the next Since each of the first three chips in the line is not used as a standardized exclusion chip for creating standardized data, it is possible to obtain reasonable data regarding the regular chip.

  In addition, this invention is not limited to the said embodiment, The following deformation | transformation implementation is possible.

  (1) The imaging order of each chip by the camera 7 is not limited to that described in the above embodiment, and may be arbitrary.

  (2) It is not necessary to have a function of inspecting all of dirt, chips, and chip positions, and it is also possible to have a function of inspecting only a part of these.

  (3) The number of block divisions is not limited to 25, and may be arbitrary.

  (4) Although the stain on the binarized image is a black pixel block, if the chip surface appears black on the binarized image, the stain appears white, so it is dirty as a white pixel block in the binarized image. It is possible to carry out a modified implementation of detecting.

  (5) In addition, various modifications can be made without departing from the scope of the present invention.

1 is a functional block diagram showing a configuration of a wafer visual inspection apparatus according to an embodiment of the present invention. The figure which shows a mode that the wafer is attached to the ring frame. The figure which shows the installation condition of the positioning pin in the upper surface (wafer mounting surface) of the inspection stage 1. FIG. The figure which shows typically the chip formation condition in a wafer form, and the imaging order of each chip | tip. The chip range determination process will be described. The figure explaining the setting process of the invalid point in the determination process of a chip | tip range. The figure which shows an example in the process image at the time of dirt mode selection and 1 chip | tip / 1 visual field mode. The figure which shows the relationship of the real visual field and the resolution with respect to the magnification set in the optical microscope. The figure which shows each representative value of area level S1-S20. The figure which shows an example in the process image at the time of dirt mode selection and division mode. The figure which shows an example in the process image at the time of chip | tip inspection mode selection and 1 chip | tip / 1 visual field mode. The figure explaining the determination process of the depth in case a chip | corner has arisen in the corner part of a chip | tip. The figure which shows each representative value of depth level L1-L20. The figure which shows an example in the process image at the time of chip | tip inspection mode selection and a division mode. The figure explaining the setting process of a ring frame coordinate system. The figure explaining the detection process of a chip | tip position and a chip | tip inclination. The figure which shows the block and subblock for producing normalized data. The figure which shows the form of normalization data typically. The figure explaining an invalid chip. The figure explaining the setting process of a standardization exclusion chip.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Inspection stage, 2 ... Stand, 3 ... Magnescale, 4 ... Stage controller, 5 ... Operation panel, 6 ... Microscope, 7 ... Camera, 8 ... Image processing device, 11 ... Data processing device, 21 ... Wafer, 22 ... Ring frame, 23 ... dicing tape, 24a, 24b ... frame mark, 22a, 22b ... notch, 31a, 31b ... positioning pin.

Claims (6)

An inspection stage for moving a ring frame on which a wafer on which a positioning mark is formed at a predetermined position and a plurality of chips are formed is mounted;
A microscope for obtaining an enlarged image of a part of the ring frame or the wafer;
Imaging means for capturing an enlarged image obtained by the microscope and generating a corresponding electrical image signal;
Means for moving the ring frame by the inspection stage so that the imaging means sequentially images different portions of the ring frame or the wafer;
Position inspection means for detecting each position of the plurality of chips as a relative position with respect to the positioning mark based on an image indicated by the image signal;
A wafer visual inspection apparatus comprising: means for storing inspection information representing the positions of the plurality of chips detected by the position inspection means.   2. The wafer appearance inspection apparatus according to claim 1, wherein the position inspection unit detects the position of the chip as coordinates in a coordinate system determined with a plurality of the positioning marks formed on the ring frame as a reference.   The wafer appearance inspection apparatus according to claim 1, wherein the inspection stage includes a positioning pin that engages a notch formed in the ring frame. An inspection stage for moving a ring frame on which a wafer on which a plurality of chips are formed and positioning marks are formed at predetermined positions, respectively,
A microscope for obtaining an enlarged image of a part of the ring frame or the wafer;
In the wafer appearance inspection method for inspecting the appearance of the wafer using a wafer appearance inspection apparatus comprising an imaging means for capturing an enlarged image obtained by the microscope and generating a corresponding electrical image signal,
Moving the ring frame by the inspection stage to cause the imaging means to sequentially image different portions of the ring frame or the wafer;
Based on the image indicated by the image signal, each position of the plurality of chips is detected as a relative position with respect to the positioning mark,
A wafer appearance inspection method, wherein inspection information representing each position of the detected plurality of chips is accumulated.   2. The wafer appearance inspection apparatus according to claim 1, further comprising means for displaying or printing contents of standardized data obtained by collecting the inspection information.   5. The wafer appearance inspection method according to claim 4, further comprising displaying or printing contents of standardized data obtained by collecting the inspection information.

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