JP3825743B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device, for example.
[0002]
[Prior art]
This type of nonvolatile memory stores data by controlling a threshold voltage of a memory cell transistor (hereinafter abbreviated as a memory cell). A memory cell constituting a non-volatile memory has a two-layer gate structure in which a charge storage layer (floating gate) and a control gate are stacked on a semiconductor substrate via an insulating film. Data is stored in a state where the injected threshold voltage is high as a write state (“0” data), and a state where the threshold voltage is low as electrons in the floating gate are discharged into the channel is an erase state (“1” data).
[0003]
The NAND type nonvolatile memory is composed of NAND cells in which a plurality of the memory cells are connected in series, and when reading data of a selected memory cell, a voltage higher than a threshold voltage is applied to the control gate of the non-selected memory cell. Must be applied. For this reason, the threshold voltage of the memory cell in the written state must be a certain value or less, and it is necessary to reduce the variation in the threshold voltage in the written state. Furthermore, recently, a multi-value storage method for storing a plurality of data in one memory cell by further subdividing the threshold voltage distribution has been performed, and it is important to control the threshold voltage distribution width to be small. It has become.
[0004]
When data is written to the NAND type nonvolatile memory, the data of a plurality of NAND cells in the block are erased at once. Thereafter, data is written to a plurality of memory cells along control gate lines (word lines) selected in order from the source line side. When “0” data is written, the channel potential is kept low (eg, 0 V), and when “1” data is written, the channel potential is kept high, and the boosted positive write voltage Vpgm is applied to the selected word line. When “0” data is written, electrons are injected from the channel to the floating gate, and the threshold voltage of the memory cell increases. In addition, when “1” data is written, electrons are not injected into the floating gate, and the threshold voltage of the memory cell does not change. After applying the write voltage once, the threshold voltage is verified in units of word lines. As a result, when there is a memory cell in which the threshold voltage has not reached the predetermined value, the write voltage value is increased by a step-up width ΔVpgm from the first value, and the threshold voltage is set to a predetermined value by using this write voltage. “0” is written to a memory cell that has not reached the threshold value, and “1” is written to a memory cell whose threshold voltage has reached a predetermined value.
[0005]
Various write methods for stepping up the write voltage have been developed. For example, there is a method of writing data with a constant step-up width (step-up voltage width) of the write voltage and a constant write time (see, for example, Patent Document 1). In addition, there is a method in which the step-up voltage width is gradually reduced with a constant writing time (see, for example, Patent Document 2).
[0006]
FIG. 16 shows the write voltage and the number of writes related to the conventional write method similar to the invention described in FIG. This example shows a case where writing is completed by four writing operations. The second and subsequent step-up voltage widths have the same value as the step-up voltage width ΔVpgm from the first write voltage Vpgm1 to the second write voltage Vpgm2. The horizontal width of the bar graph represents the writing time, and the writing time tpgm is constant regardless of the number of writings. In this way, ΔVpgm is kept constant, the write voltage is applied and the threshold voltage is repeatedly verified while increasing the write voltage, and the threshold voltages of all the memory cells connected to the same word line reach a predetermined value. Then, the writing of the memory cell connected to the word line is finished. By sequentially performing this operation in units of word lines, writing to all memory cells is performed.
[0007]
Next, a change in the threshold voltage distribution of the memory cell due to the above four conventional write operations will be described with reference to FIGS.
[0008]
FIG. 17 shows the threshold voltage distribution of the memory cell after writing with the first write voltage Vpgm1. The solid line A in the figure indicates a predetermined threshold voltage Vth0 after writing, and the dotted lines B, C, and D indicate the threshold voltages of the memory cells whose threshold voltage becomes Vth0 by the second, third, and fourth writing operations, respectively. Show. Further, the number of memory cells having the highest threshold voltage among the cells written by the second write operation is n0. It is known that after all the write operations, the threshold voltage distribution width of the memory cell changes due to the influence of data stored in the surrounding memory cells, and thus becomes larger than the step-up voltage. Therefore, the step-up voltage width is made smaller than a value obtained by equally dividing the threshold voltage width by one writing by the number of writing. That is, when the width of the threshold voltage distribution is 4ΔVpgm + α (α> 0), the step-up voltage width is set to ΔVpgm. At this time, the threshold voltage distribution width of the memory cell having a threshold voltage higher than the predetermined threshold voltage Vth0 in the first write operation is ΔVpgm + α.
[0009]
FIG. 18 shows the threshold voltage distribution of the memory cell after the second write operation. The threshold voltage variation of the n0 memory cells having the highest threshold voltage in the second write operation is indicated by a dotted line in FIG. If half of the variation width is ΔVth (n0), ΔVpgm is stepped up. Therefore, the threshold voltage distribution width of the memory cell in which the threshold voltage is higher than Vth0 by the second write operation is ΔVpgm + ΔVth (n0). Here, α is half of the variation width when writing to a larger number of memory cells than n0, and therefore α> ΔVth (n0).
[0010]
19 and 20 show threshold voltage distributions after the third and fourth write operations, respectively. Among the memory cells written by the third and fourth write operations, the number of memory cells having the highest threshold voltage is n1 and n2, respectively, and the variation in the third and fourth write operations of these memory cells. Are ΔVth (n1) and ΔVth (n2), respectively. Since α is half the variation width when writing to a larger number of memory cells than n1 and n2, α> ΔVth (n1) and α> ΔVth (n2).
[0011]
By four write operations, the threshold voltages of all the memory cells become higher than the predetermined threshold voltage Vth0, and the write operation is completed. As shown in FIG. 20, the threshold voltage distribution width after completion of all the write operations is ΔVpgm + α.
[0012]
Variations in threshold voltage of memory cells connected to one word line are normally distributed due to variations in manufacturing. Therefore, when the total number of memory cells increases, variation in threshold voltage when writing is performed at the same voltage. growing. At this time, the writing is completed without increasing the writing time. That is, ΔVpgm needs to be increased in order to perform a write operation with a fixed number of writes.
[0013]
[Patent Document 1]
JP 07-169284 A
[0014]
[Patent Document 2]
Japanese Patent Application Laid-Open No. 11-31391
[0015]
[Problems to be solved by the invention]
However, as shown in FIG. 16, when ΔVpgm is simply increased to increase the step voltage width in each writing operation, the threshold distribution width (ΔVpgm + α) after the writing is increased, and the controllability of the threshold distribution width is poor. There is a problem of becoming.
[0016]
In addition, in order to prevent the threshold voltage from exceeding the maximum allowable value, if the first write voltage is lowered and the number of times of writing is increased without changing ΔVpgm, the writing time increases and high-speed writing is difficult. Become.
[0017]
Further, in the case of the method of gradually reducing the step-up voltage width ΔVpgm as in the invention described in Patent Document 2, the step-up voltage width ΔVpgm becomes smaller as the number of times of writing increases. For this reason, compared with the case where ΔVpgm is constant, there is a problem that the number of times of writing required for setting the threshold voltage of a memory cell with slow writing to a predetermined value increases and the writing time increases.
[0018]
The present invention has been made to solve the above-described problems, and the object of the present invention is to set a predetermined threshold voltage in a memory cell at high speed without increasing the number of times of writing and the writing time. A non-volatile semiconductor memory device is to be provided.
[0019]
[Means for Solving the Problems]
In order to solve the above problems, a nonvolatile semiconductor memory device of the present invention includes a memory cell array configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells having a control gate and a charge storage layer in a matrix. A write circuit for writing data by applying a write voltage to a control gate of a selected memory cell in the memory cell array a plurality of times, and a memory cell connected to the selected memory cell, each time the write voltage is generated And a verification circuit that verifies whether or not the threshold voltage has reached a predetermined value, and the write voltage output from the write circuit is increased for each write count. The first write voltage increase from the second write operation to the second write operation is the third write from the second write operation. Greater than the second write voltage increase on the operation, and the write voltage increase of the second and subsequent characterized in that it is a constant.
[0020]
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device including a memory cell array configured by arranging a plurality of electrically rewritable non-volatile semiconductor memory cells having a control gate and a charge storage layer in a matrix, and the memory cell array A write circuit for writing data by applying a write voltage to the control gate of the selected memory cell multiple times, and a threshold voltage of the memory cell connected to the selected memory cell and detecting the write voltage And a verification circuit that verifies whether or not the threshold voltage has reached a predetermined value, and the write voltage output from the write circuit has a first write time that is greater than a second write time. Short, the writing time after the second time is the same, and the writing voltage after the second time increases by a certain amount for every number of writings. To.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
FIG. 1 schematically shows a configuration of a NAND nonvolatile memory according to the present invention, and FIG. 2 schematically shows a configuration of a memory cell array. As shown in FIG. 2, the memory cell array 1 includes a plurality of (16 in the illustrated example) memory cells MC (MC0 to MC15) sharing their source and drain diffusion layers adjacent to each other and connected in series. The plurality of NAND cell units. The memory cell MC is a MOSFET having a stack gate structure in which a floating gate and a control gate are stacked. One end of the NAND cell is connected to the bit line BL via the selection gate SG1, and the other end is connected to the common source line SL via the selection gate SG2.
[0023]
The control gates of the memory cells MC arranged in the row direction are commonly connected to control gate lines (word lines) CG (CG0 to CG15). The gates of the selection gates SG1 arranged in the row direction are connected to the selection gate line SGD, and the gates of the selection gate SG2 are connected to the selection gate line SGS, respectively.
[0024]
A range of memory cells connected to one control gate line CG is a range in which data is written collectively, and this constitutes one page. In addition, a plurality of NAND cell units arranged in the row direction form a block, and data is collectively erased in units of the block.
[0025]
The bit line BL of the memory cell array 1 is connected to the sense amplifier / data latch circuit 2. This sense amplifier / data latch circuit 2 is connected to an I / O buffer 9 via a column gate 3 driven by a column decoder 5 shown in FIG. The sense amplifier / data latch circuit 2 senses data read from the memory cell and latches data to be written to the memory cell. Further, the sense amplifier / data latch circuit 2 latches the voltage read from the memory cell in order to verify the threshold voltage of the data written at the time of data writing.
[0026]
A row decoder / word line driving circuit 4 is further connected to the memory cell array 1. The row decoder / word line drive circuit 4 selects and drives the control gate line of the memory cell array 1. An address latch circuit 6 is further connected to the I / O buffer 9. The address latch circuit 6 holds the external address supplied from the I / O buffer 9 and supplies it to the column decoder 5 and the row decoder / word line driving circuit 4.
[0027]
The control circuit 7 controls the sense amplifier / data latch circuit 2, the address latch circuit 6, and the internal voltage generation circuit 8 based on the command supplied from the I / O buffer 9. That is, the control circuit 7 controls data writing and subsequent verification operations, data erasing and subsequent verification operations, and the like. The internal voltage generation circuit 8 includes, for example, a booster circuit and the like, and generates various levels of voltages corresponding to various operation modes for a necessary time based on the control of the control circuit 7. That is, the internal voltage generation circuit 8 generates the write voltage Vpgm supplied to, for example, the control gate line selected at the time of writing. Further, an erase voltage Vera supplied to the well at the time of data erase is generated. Further, each time a write voltage is generated, a verification voltage for verifying the threshold voltage of the memory cell after writing is generated, and a verification voltage for verifying erasure after erasing is generated. In addition, a voltage necessary for a data read operation is generated.
[0028]
The write operation is performed by applying Vpgm to the control gate line for a predetermined time tpgm while the substrate (well) is held at a reference potential (for example, ground potential GND), and injecting electrons from the substrate to the floating gate, thereby The threshold voltage of the cell is changed. After the first write operation, the threshold voltage of the memory cell is verified for each control gate line. The memory cell that has reached the predetermined threshold voltage is set in the write prohibited state, and the second write operation is performed with the write voltage increased. Thereafter, the threshold voltage is verified. Thereafter, similarly, when the threshold voltages of all the memory cells connected to the control gate line reach a predetermined value, the write operation to the memory cells connected to the control gate line is finished. By performing this operation sequentially for all the other control gate lines, the write operation for all the memory cells is completed.
[0029]
A specific embodiment of the write operation will be described below.
[0030]
(First embodiment)
FIG. 3 shows the write frequency dependency of the write voltage in the first embodiment of the present invention. In this embodiment, the case where writing is completed by four writing operations is shown. The number of times of writing is not limited to four, and may be four or more.
[0031]
In the present embodiment, the first write voltage Vpgm1 is set smaller than the conventional one, and the step-up voltage width ΔVpgm1 from Vpgm1 to the second write voltage Vpgm2 is larger than the second and subsequent step-up voltage widths ΔVpgm2 and ΔVpgm3. To be. At this time, the step-up voltage widths ΔVpgm2 and ΔVpgm3 for the second and subsequent times are set to constant values regardless of the number of times. The horizontal width of the bar graph represents the writing time, and the writing time tpgm is constant regardless of the number of writings.
[0032]
Next, changes in the threshold voltage distribution of the memory cell using the write method according to the present embodiment will be described with reference to FIGS.
[0033]
FIG. 4 shows the threshold voltage distribution of the memory cell after writing with the first write voltage Vpgm1. In the drawing, a solid line A indicates a predetermined write voltage Vth0, and dotted lines B, C, and D indicate threshold voltages of the memory cells that have a threshold voltage Vth0 by the second, third, and fourth write operations, respectively. By the first write operation, the threshold voltage of at least two or more memory cells becomes Vth0 or more. Further, the number of memory cells having the highest threshold voltage among the memory cells written by the second writing operation is n0. When the threshold voltage distribution width is 4ΔVpgm + α, if ΔVpgm1 = ΔVpgm + β (β> 0) and ΔVpgm2 = ΔVpgm3 = ΔVpgm, the threshold voltage distribution width of the memory cell having the threshold voltage higher than Vth0 (the writing is completed) is as shown in FIG. As shown, ΔVpgm + α−β.
[0034]
FIG. 5 shows the threshold voltage distribution of the memory cell after the second write operation. The threshold voltage variation of the n0 memory cells having the highest threshold voltage in the second write operation is indicated by a dotted line in FIG. If ΔVth (n0) is half of the variation width, step-up of ΔVpgm + β is performed by the second write operation, and thus the threshold voltage distribution width of the memory cell whose threshold voltage is higher than Vth0 is ΔVpgm + β + ΔVth (n0). . The conditions under which the threshold voltage distribution width ΔVpgm + α−β of the memory cell that has been written in the first write operation and the threshold voltage distribution width ΔVpgm + β + ΔVth (n0) of the memory cell that has been written in the second write operation are both minimum. , Β = (α−ΔVth (n0)) / 2. At this time, the threshold distribution width of the memory cell for which writing has been completed is ΔVpgm + (α + ΔVth (n0)) / 2.
[0035]
On the other hand, in the conventional writing method that does not change the step-up voltage width, the threshold voltage distribution width of the memory cell that has been written in the second writing operation is ΔVpgm + α, and the threshold distribution width ΔVpgm + ( There is a difference of (α−ΔVth (n0)) / 2 from α + ΔVth (n0)) / 2.
[0036]
Here, α is half of the variation width when writing to a larger number of memory cells than n0, and therefore α> ΔVth (n0). Therefore, (α−ΔVth (n0)) / 2> 0, and the threshold voltage of the memory cell in which writing has been completed in the second writing operation is better when the writing method according to the present embodiment is used than with the conventional writing method. The distribution width can be reduced.
[0037]
6 and 7 show threshold voltage distributions after the third and fourth write operations, respectively. The third and fourth write operations are the same as the conventional write operation. For this reason, the threshold voltage distribution generated by the third and fourth write operations is the same as the conventional one. Therefore, in the write operation according to the present embodiment, the threshold voltage distribution width after completion of all the write operations can be reduced by the smaller threshold voltage distribution generated by the second write operation.
[0038]
8A and 8B show threshold voltage distributions after writing between the conventional technique and this embodiment. FIG. 8A shows a case where the conventional step-up voltage width is constant, and FIG. 8B shows a threshold voltage distribution after writing according to the present embodiment. In this embodiment, as shown in FIG. 8B, the threshold voltage distribution width is ΔVpgm + (α + ΔVth (n0)) / 2 in the second write operation. On the other hand, in the conventional case shown in FIG. 8A, the threshold voltage distribution width is ΔVpgm + α. For this reason, in the present embodiment, the threshold voltage distribution width becomes narrower by (α−ΔVth (n0)) / 2 than in the conventional case.
[0039]
Next, the effect of the first embodiment over the conventional writing method in which the step-up voltage is gradually reduced will be described with reference to FIGS.
[0040]
FIG. 9 shows the threshold voltage distribution of the memory cell after writing with the first write voltage Vpgm1 by the write method in which the step-up voltage is gradually reduced. A solid line A in the figure indicates a predetermined write voltage Vth0, and dotted lines B, C, and D indicate the threshold voltages of the memory cells in which the threshold voltage becomes Vth0 by the second, third, and fourth write operations, respectively. Further, the number of memory cells having the highest threshold voltage among the cells written by the second write operation is n0. The width of the threshold distribution is 4ΔVpgm + α. Assuming that ΔVpgm1 = ΔVpgm + β (β> 0), when β is larger than the value determined by the write method according to the first embodiment, the threshold voltage distribution width ΔVpgm + β of the memory cell written by the second write operation is the first. It becomes larger than the case of the embodiment. For this reason, the threshold voltage distribution width after completion of all the write operations is increased.
[0041]
FIG. 10 shows the threshold voltage of the memory cell after the second writing operation when β is made equal to the value determined by the writing method according to the first embodiment, or when the value of β is made smaller than the above value. Distribution is shown. However, the first write voltage Vpgm1 is smaller than the first write voltage Vpgm1 in the first embodiment.
[0042]
If the step-up width ΔVpgm2 from the first write voltage to the second write voltage is ΔVpgm + γ (β>γ> 0), the voltage required to write the slowest memory cell is equal regardless of the write method. Therefore, when the number of times of writing is equal, the step-up voltage width ΔVpgm3 from the second writing voltage to the third writing voltage is ΔVpgm−δ (δ> 0).
[0043]
FIG. 11 shows the threshold voltage distribution of the memory cell after the third write operation. Since ΔVpgm2 is larger than ΔVpgm, the threshold voltage distribution width of the memory cell written by the third write operation becomes larger than that of the write method according to the first embodiment. Further, if the number of memory cells having the highest threshold voltage among the cells written by the third write operation is n1, the threshold voltage distribution width of the memory cell written by the third write operation is ΔVpgm + γ + ΔVth (n1). It becomes.
[0044]
Since the threshold voltage distribution of the memory cells is a normal distribution, among the memory cells written by the third write operation, the number n1 of the memory cells having the highest threshold voltage is the memory cell written by the second write operation. Of these, the number n0 of memory cells having the highest threshold voltage is very large. For this reason, as shown in FIG. 11, ΔVth (n1), which is half of the variation in threshold voltage when n1 memory cells are written, becomes very large. Therefore, the threshold voltage distribution width ΔVpgm + γ + ΔVth (n1) of the memory cell written by the third writing operation is larger than the threshold voltage distribution width ΔVpgm + β + ΔVth (n0) of the memory cell in which writing has been completed by the second writing operation. . That is, the threshold voltage distribution width ΔVth (c) of the memory cell written by the third write operation is larger than ΔVth (c) of FIG. 6 in the first embodiment. Therefore, the threshold voltage distribution width ΔVth after completion of the fourth write operation shown in FIG. 12 is larger than the threshold voltage distribution width ΔVth of FIG. 7 in the first embodiment. Therefore, by using the writing method of the first embodiment, the threshold voltage distribution width ΔVth after completion of all writing operations can be made smaller than that of the conventional writing method.
[0045]
In the first embodiment, the first write voltage Vpgm1 is set smaller than the conventional voltage, and the step-up voltage width ΔVpgm1 from Vpgm1 to the second write voltage Vpgm2 is larger than the second and subsequent step-up voltage widths ΔVpgm. In this writing method, the step-up voltage width ΔVpgm for the second and subsequent times is set to a constant value regardless of the number of times. That is, the number of cells exceeding a predetermined threshold voltage is reduced by the first write operation. For this reason, it is possible to reduce the threshold voltage distribution width of the memory cells after completion of all writing.
[0046]
In addition, since the threshold voltage distribution width of the memory cell after writing can be reduced without increasing the step-up voltage width and the number of writing times, high-speed writing is possible.
[0047]
(Second Embodiment)
FIG. 13 shows a write method according to the second embodiment of the present invention, and shows the write voltage dependency of the write voltage. In the second embodiment, the write time can be shortened by making the first write time shorter than the second and subsequent write times, and the threshold voltage distribution width of the memory cells after all the write operations are reduced. Is shown.
[0048]
This embodiment shows a case where writing is completed by four writing operations. As shown in FIG. 13, in the present embodiment, the first write time tpgm1 is shorter than the second and subsequent write times tpgm. Further, the write voltage is increased with a constant step-up voltage width ΔVpgm.
[0049]
When the first write is performed under the above conditions, the write voltage is the same as in the conventional case, but the write time is shorter than in the conventional case. Become. That is, the number of memory cells exceeding the predetermined threshold voltage Vth0 is smaller than in the prior art, and a threshold voltage distribution similar to that of the first embodiment shown in FIG. 4 can be obtained. At this time, by optimizing the write time tpgm1, β in FIG. 4 can be made the value obtained in the first embodiment.
[0050]
The second writing is the same as the condition described in the first embodiment. Therefore, the threshold voltage distribution after the second writing operation is as shown in FIG. Therefore, the threshold voltage distribution width of the memory cell exceeding Vth0 can be made smaller than before by optimizing the value of β by setting the write time tpgm1 to a short time.
[0051]
Thereafter, similarly to the first embodiment, the threshold voltage distributions shown in FIGS. 6 and 7 can be obtained by performing the third and fourth write operations.
[0052]
Therefore, according to the second embodiment, as in the first embodiment, the threshold voltage distribution width after completion of all the write operations can be made smaller than that of the conventional one, and high-speed writing can be performed.
[0053]
(Third embodiment)
FIG. 14 shows a write method according to the third embodiment of the present invention, and shows the write voltage dependency of the write voltage. The horizontal width of the bar graph indicates the writing time.
[0054]
The third embodiment is a method combining the first embodiment and the second embodiment. That is, the first write time tpgm1 is longer than the value of the second embodiment and shorter than the second and subsequent write times tpgm2, tpgm3, and tpgm4, and the first write voltage Vpgm1 is the same as that of the first embodiment. It is set larger than the value and smaller than the value of the second embodiment.
[0055]
The first write time tpgm1 is longer than the value of the second embodiment and shorter than the second write time tpgm, and the first write voltage Vpgm1 is larger than the value of the first embodiment. It is set smaller than the value of the second embodiment. For this reason, the writing voltage is smaller than that of the prior art and the writing time is shorter than that of the prior art. Therefore, the change in the threshold voltage of the memory cell in which the first writing is performed can be reduced compared to the conventional case. That is, the number of memory cells exceeding the predetermined threshold voltage Vth0 by the first writing is smaller than in the prior art, and the threshold voltage distribution similar to that of FIG. 4 shown in the first embodiment can be obtained. At this time, by optimizing the write voltage Vpgm1 and the write time tpgm1, the value of β shown in FIG. 4 can be made the value obtained in the first embodiment.
[0056]
Since the second writing is the same as the condition described in the first embodiment, the threshold voltage distribution after the second writing operation is as shown in FIG. Therefore, the threshold voltage distribution width of the memory cell exceeding Vth0 can be made smaller than before by optimizing the value of β by shortening the write voltage Vpgm1 and the write time tpgm1. Thereafter, similarly to the first embodiment, the third and fourth write operations are performed, so that the threshold voltage distribution shown in FIGS. 6 and 7 is obtained.
[0057]
Therefore, as described in the first embodiment, the threshold voltage distribution width after completion of all the write operations can be made smaller than that in the prior art. In addition, the writing time can be shortened and a high-speed writing operation can be realized.
[0058]
(Fourth embodiment)
FIG. 15 shows a write method according to the fourth embodiment of the present invention, and shows the write voltage dependency of the write voltage. The horizontal width of the bar graph indicates the writing time.
[0059]
The fourth embodiment is a modification of the second embodiment. The first write time tpgm1 is shorter than the value of the second embodiment, and the first write voltage Vpgm1 is set to the second value. A value larger than the value of the embodiment, for example, a value equal to the second write voltage Vpgm2 is set. Although the first write voltage is higher than the conventional one, the change in the threshold voltage of the memory cell in which the first write is performed can be made smaller than before by sufficiently shortening the write time. That is, the number of memory cells exceeding the predetermined threshold voltage Vth0 can be reduced as compared with the conventional case. Therefore, according to the fourth embodiment, a threshold voltage distribution similar to the threshold voltage distribution shown in FIG. 4 of the first embodiment can be obtained. At this time, the value of β shown in FIG. 4 can be made the value obtained in the first embodiment by optimizing the write time tpgm1.
[0060]
Since the second write operation is the same as the first embodiment, the threshold voltage distribution after the second write operation is as shown in FIG. Therefore, the threshold voltage distribution width of the memory cell exceeding Vth0 can be made smaller than before by optimizing the value of β by shortening the write time tpgm. Thereafter, similarly to the first embodiment, the third and fourth write operations are performed, so that the threshold voltage distribution shown in FIGS. 6 and 7 is obtained.
[0061]
Therefore, as described in the first embodiment, the threshold voltage distribution width after completion of all the write operations can be made smaller than that in the prior art. In addition, the writing time can be shortened and a high-speed writing operation can be realized.
[0062]
In the fourth embodiment, the first write voltage Vpgm1 is set equal to the second write voltage Vpgm2. However, the first write voltage Vpgm1 is not limited to the second write voltage Vpgm2. However, in order to reduce the change in the threshold voltage of the memory cell written by the first write operation compared to the conventional case, the first write voltage Vpgm1 in the fourth embodiment is the same as the first write voltage in the second embodiment. It is desirable that it is larger than the write voltage Vpgm1 and not more than the second write voltage Vpgm2.
[0063]
The first to fourth embodiments are not limited to the case of storing binary (1 bit) data in one memory cell, but are the first in the case of storing data of 4 values (2 bits) or more. It is also possible to apply to each writing operation of page data, second page data,.
[0064]
Of course, various modifications can be made without departing from the scope of the present invention.
[0065]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of setting a predetermined threshold voltage in a memory cell at high speed without increasing the number of times of writing and the writing time.
[Brief description of the drawings]
FIG. 1 is a configuration diagram schematically showing a semiconductor nonvolatile memory device of the present invention.
FIG. 2 is a circuit diagram schematically showing a configuration of a memory cell array shown in FIG. 1;
FIG. 3 is a view showing the relationship between the number of writes and a write voltage according to the first embodiment of the present invention.
FIG. 4 is a diagram showing a threshold voltage distribution of a memory cell after a first write operation according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a threshold voltage distribution of a memory cell after a second write operation according to the first embodiment of the present invention.
FIG. 6 is a diagram showing a threshold voltage distribution of a memory cell after a third write operation according to the first embodiment of the present invention.
FIG. 7 is a diagram showing a threshold voltage distribution of a memory cell after a fourth write operation according to the first embodiment of the present invention.
FIG. 8 is a diagram showing the relationship between the threshold voltage distribution width after writing and the number of bits in the prior art and the first embodiment of the present invention;
FIG. 9 is a diagram showing a threshold voltage distribution of a memory cell after a first write operation in another conventional example.
FIG. 10 is a diagram showing a threshold voltage distribution of a memory cell after a second write operation in another conventional example.
FIG. 11 is a diagram showing a threshold voltage distribution of a memory cell after a third write operation in another conventional example.
FIG. 12 is a diagram showing a threshold voltage distribution of a memory cell after a fourth write operation in another conventional example.
FIG. 13 is a diagram showing a relationship between the number of writings and a writing voltage according to the second embodiment of the present invention.
FIG. 14 is a diagram showing a relationship between the number of writings and a writing voltage according to the third embodiment of the present invention.
FIG. 15 is a diagram showing a relationship between the number of writings and a writing voltage according to the fourth embodiment of the present invention.
FIG. 16 is a diagram showing a relationship between the number of times of writing and a writing voltage in the related art.
FIG. 17 is a diagram showing a threshold voltage distribution of a memory cell after a conventional first write operation.
FIG. 18 is a diagram showing a threshold voltage distribution of a memory cell after a conventional second write operation.
FIG. 19 is a diagram showing a threshold voltage distribution of a memory cell after a conventional third write operation.
FIG. 20 is a diagram showing a threshold voltage distribution of a memory cell after a conventional fourth write operation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Sense amplifier / data latch circuit, 3 ... Column gate, 4 ... Row decoder / word line drive circuit, 5 ... Column decoder, 6 ... Address latch circuit, 7 ... Control circuit, 8 ... Internal voltage generation Circuit, 9 ... I / O buffer, MC0 to MC15 ... Memory cell, SG1, SG2 ... Select gate transistor, BL0-BL4223 ... Bit line, SL ... Common source line, CG0-CG15 ... Control gate line (word line), SGD , SGS... Selection gate line.

Claims (9)

A memory cell array configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells having a control gate and a charge storage layer in a matrix;
A write circuit for writing data by applying a write voltage multiple times to the control gate of a selected memory cell in the memory cell array;
A verification circuit connected to the selected memory cell, detecting a threshold voltage of the memory cell each time the write voltage is generated, and verifying whether the threshold voltage has reached a predetermined value;
The write voltage output from the write circuit is increased for each write count, and the first write voltage increase from the first write operation to the second write operation is the third write operation from the second write operation. A non-volatile semiconductor memory device, characterized in that it is larger than a second write voltage increase amount for a write operation, and a second and subsequent write voltage increase amount is constant. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a write time is constant in the plurality of write operations. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of write operations are performed at least four times. 2. The nonvolatile semiconductor memory device according to claim 1, wherein, in the plurality of write operations, the first write time is shorter than the second and subsequent write times, and the second and subsequent write times are constant. A memory cell array configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells having a control gate and a charge storage layer in a matrix;
A write circuit for writing data by applying a write voltage multiple times to the control gate of a selected memory cell in the memory cell array;
A verification circuit connected to the selected memory cell, detecting a threshold voltage of the memory cell each time the write voltage is generated, and verifying whether the threshold voltage has reached a predetermined value;
The write voltage output from the write circuit is shorter than the first write time after the second write time, the second write time is the same, and the second and subsequent write voltages are constant for each write count. A non-volatile semiconductor memory device characterized in that the amount increases. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the first write voltage is the same as the second write voltage. 6. The nonvolatile semiconductor memory device according to claim 5, wherein the first write voltage is smaller than the second write voltage. 6. The nonvolatile semiconductor memory device according to claim 1, wherein a threshold voltage of at least two memory cells reaches the predetermined value by the first write voltage. 6. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the memory cells are arranged in series to constitute a NAND type cell.

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