JP3819120B2 - Encoding circuit applied to associative memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention is applied to a large-capacity associative memory device (associative memory) divided into a plurality of associative memory sub-blocks, and an address corresponding to a hit flag, which is a match search result between the search data and the contents of each memory word, Alternatively, the present invention relates to an encoding circuit for efficiently encoding an address corresponding to an empty flag indicating whether or not the content of each memory word is a valid match search target in order according to a predetermined priority order. Is.
[0002]
[Prior art]
Conventionally, an associative memory, that is, a fully parallel type CAM (Content Addressable Memory), is used as a semiconductor memory device having a function of detecting coincidence between search data and stored data in parallel in all bits and outputting the storage address or data of the matched data. Address type memory) is well known (see Takuo Ishino, edited by Tetsuya Iizuka, “Design of CMOS VLSI”, Baifukan, P176-P177).
[0003]
The content addressable memory (CAM) is searched by content, not by physical memory address. Accordingly, the basic function of the CAM is to input search data contrary to a normal memory, for example, and output the address of a word in which data matching the search data is stored. However, the number of matching words is not limited to one, and a plurality of words may match. Thus, when a match is obtained in a plurality of words, a normal encoded circuit (encoder) cannot obtain a correct encoded output. For this reason, a priority-order encoding circuit (priority encoder) that encodes and outputs a plurality of coincidence signals (hit signals) according to a predetermined priority is used for the CAM.
[0004]
By the way, in a large-capacity CAM, the number of words is generally very large with respect to the word length. For this reason, although the cell array is divided into a plurality of blocks, the arrangement of priority encoders is an important problem. That is, if priority encoders are attached to all the blocks of the CAM, the area occupied by the priority encoder circuit is increased, and the power consumption is also increased. When the number of blocks to be divided increases, the occupied area and power consumption further increase in proportion to this.
[0005]
Therefore, an associative memory device is proposed in which one main priority encoder is provided for a plurality of blocks, and blocks that are encoded (encoded) by the priority encoder are performed by a separately provided block priority encoder. Has been.
[0006]
This associative memory (CAM) is shown in FIG. As shown in FIG. 30, the associative memory 200 is divided into four associative memory blocks 202, and the associative memory block 202 is further divided into eight associative memory sub-blocks 204. Then, the priority encoder 210 corresponds to the main priority encoder 212 provided for each of the eight associative memory blocks 202 including the eight associative memory sub-blocks 204, that is, a total of four associative memory blocks 202 and four associative memory blocks 202. A hierarchical priority encoder having a single sub-block priority encoder 214 is employed. Here, as shown in FIG. 31, the associative memory sub-block 204 includes a CAM sub-array 206 in which a predetermined number of associative memory words having a predetermined word length are arranged and its control unit. The control unit includes search data, associative memory words, A hit signal register 208 for holding the hit signals is included.
[0007]
In the associative memory block 202, when searching for a match, first, the hit signals of all the words in this sub block are held in the hit signal register 208 for each associative memory sub block 204 and at the same time, the control of each associative memory sub block 204 is performed. A sub-block hit signal indicating the presence of a matching word in this sub-block 204 is generated by an OR circuit (not shown). Subsequently, the sub-block priority encoder 214 receives the signal and generates a sub-block select signal indicating the highest priority associative memory sub-block 204. At the same time, the sub-block priority encoder 214 is encoded (coded). Generate sub-block addresses.
[0008]
Next, the switch circuit (not shown) of the selected sub-block receives and activates the block select signal, and the data (hit signal) held in the hit signal register 208 is output to the main priority encoder 212 as an output signal. Forward. Thereafter, the main priority encoder 212 encodes the transferred hit signal in accordance with a predetermined priority order, and generates a hit memory word address in the associative memory sub-block 204. The priority encoder 210 outputs the encoded logical address of the hit memory word of the CAM memory 200 by combining the hit memory word address and the sub-block address.
[0009]
In the conventional CAM memory 200 shown in FIGS. 30 and 31, a priority encoder (encoding circuit) 210 performs encoding with a main priority encoder (priority-encoding circuit) 212 that handles a plurality of associative memory sub-blocks 204. A sub-block priority encoder 214 for assigning priorities to the associative memory sub-block 204. The sub-block priority encoder 214 first determines a priority among the plurality of sub-blocks 204, and outputs an output signal of the prioritized sub-block 204 to the main priority encoder. By inputting into 212 and encoding (encoding), the entire encoding circuit configuration can be made relatively small, the circuit area with respect to the circuit scale of the entire CAM memory 200 can be reduced, and high integration can be achieved. Yes.
[0010]
However, all the output signals (hit signal data) from the prioritized associative memory sub-block 204 are encoded by the main priority encoder 212, the encoding is completed, and the encoded data is output. It takes time to switch the hit signal between the sub-blocks until encoding of the output signal (hit signal data (hereinafter also referred to as flag data)) from the priority sub-block 204 is started. That is, after the encoded address is output by the main priority encoder 212, it takes time for the hit signal data to be transferred from the hit signal register 208 of the next priority sub-block 204 to the main priority encoder. was there.
[0011]
On the other hand, in an apparatus using an associative memory, in order to maximize the use efficiency of each memory word of the associative memory, for example, as a result of a match search, the contents of a plurality of memory words that match the search data are retained and stored. After erasing the contents of the memory word that has not been performed, the operation of updating the contents of the memory word is frequently performed by sequentially writing new data to the location of the erased memory word.
[0012]
For example, in a device such as a switching hub that connects a plurality of computers and constructs an integrated network environment, an associative memory is used, and attached data such as a port number corresponding to the MAC address existing in the header portion of the packet data. Based on this, the packet data transferred from the transmission source computer is output from the port corresponding to the acquired port number, so that it is correctly transferred to the reception destination computer.
[0013]
Here, when the port for connecting a computer is changed from port 1 to port 3, the port number stored in the attached data of the memory word storing the data of the MAC address corresponding to this computer is changed from port 1 to port 3. If not updated, the packet data transferred to this computer will be output from port 1 to which this computer was previously connected, not to port 3 to which it is actually connected. In order to prevent this, it is necessary to constantly update the port number to which each computer is connected to the latest information.
[0014]
The number of memory words in the associative memory is generally smaller than the total number of computers on the network, and only information on a specific computer is selectively stored in each memory word. For example, in order to improve the use efficiency of the associative memory device, time stamp information for managing the use time is stored as attached data, and this time stamp information is constantly updated so that only information on a computer that is frequently used is stored. Registered in memory word. Therefore, it is necessary to always update the time stamp information of each memory word to the latest information.
[0015]
Thus, in an apparatus using an associative memory, an operation of updating the contents of each memory word in the associative memory is frequently performed.
[0016]
However, in order to update the contents of each memory word of the associative memory, it is necessary to manage the address of the memory word from which the contents are erased. However, since the address of the memory word from which the contents are erased is randomly generated, The associative memory device cannot manage the address of an invalid memory word whose contents are erased. For example, the address of a memory word whose contents are erased must be managed outside the associative memory.
[0017]
[Problems to be solved by the invention]
  The object of the present invention is applicable to a large-capacity associative memory device composed of associative memory blocks composed of a plurality of associative memory sub-blocks, which solves the above-mentioned problems of the prior art and requires high-speed processing for large-capacity data. An object of the present invention is to provide an encoding circuit capable of managing invalid memory words whose contents have been erased and encoding their addresses efficiently.
  In addition to the above object, another object of the present invention is that there is no time delay (waiting time) in switching between a plurality of associative memory sub-blocks, and output signals from a plurality of associative memory sub-blocks are transmitted in a predetermined cycle. It is an object of the present invention to provide an encoding circuit capable of encoding continuously and efficiently.
[0018]
[Means for Solving the Problems]
  To achieve the above object, the present invention provides a plurality of associative memory sub-blocks.HaveEach said associative memory sub-blockButA first register holding a hit flag which is a match search result between the search data and the contents of each of the memory words in a one-to-one correspondence with each of the plurality of memory words; and A second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid ones to be matched.An encoding circuit applied to an associative memory device,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit And an end detection means for detecting that the conversion is complete.
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Coding circuit characterized by being inputted to circuit and codingIs to provide.
[0019]
  The present invention also provides:A plurality of associative memory sub-blocks, each of the associative memory sub-blocks corresponding to each of the plurality of memory words, one to one for each of the memory words, search data, contents of each of the memory words, A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets HaveAn encoding circuit applied to an associative memory device,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, and each hit flag or empty flag output from the associative memory sub-block selected by the selection circuit is output to a corresponding detection line.switchCircuit, a sense circuit for detecting the hit flag or the empty flag output on each of the detection lines, and an address of the memory word corresponding to each of the hit flag or the empty flag detected by the sense circuit A main priority encoder that sequentially encodesHave
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed Has a disable bit flag circuit, and an end detection means for encoding the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit detects that it has completed showing,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Input to the circuit and encodeAn encoding circuit is provided.
[0020]
  AlsoThe present inventionA plurality of associative memory sub-blocks, each of the associative memory sub-blocks corresponding to each of the plurality of memory words, one to one for each of the memory words, search data, contents of each of the memory words, A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets HaveAn encoding circuit applied to an associative memory device,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, and each hit flag or empty flag output from the associative memory sub-block selected by the selection circuit is output to a corresponding detection line.switchCircuit,A sense circuit for detecting the hit flag or the empty flag output on each of the detection lines, and a sense circuit detected by the sense circuit;A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or the empty flags in accordance with the priority order;Have
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit Timing control means for detecting in advance the timing at which all the conversion ends, and holding the hit flag or the empty flag of the next priority detected by the sense circuit in the flag register circuit,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Input to the circuit and encodeAn encoding circuit is provided.
[0021]
  The present invention further includes a plurality of associative memory sub-blocks, each of the associative memory sub-blocks corresponding to each of the plurality of memory words, the search data, and each of the memory words. A first register that holds a hit flag that is a match search result with the contents of the memory word, and an empty flag that indicates whether the contents of each memory word are valid search targets An encoding circuit applied to an associative memory device having a second register,
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed The timing of the end of the encoding of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit is detected in advance and detected by the sense circuit. Timing control means for holding the hit flag or the empty flag of the next priority in the flag register circuit,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Provided is an encoding circuit which is characterized by being input to a circuit for encoding.
[0022]
  Also,The present invention has a plurality of associative memory sub-blocks, and each of the associative memory sub-blocks corresponds to a plurality of memory words and a one-to-one correspondence with each of the memory words. A first register holding a hit flag which is a result of a match search with the content of a word, and a first register holding an empty flag indicating whether or not the content of each memory word is a valid search target An encoding circuit applied to an associative memory device having two registers,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit that holds the hit flag or the empty flag of the next priority output on the detection line in advance while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities;
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit An end detection means for detecting that the conversion is complete.Have
  The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Provided is an encoding circuit which is characterized by being input to a circuit for encoding.
[0023]
  Also,The present invention has a plurality of associative memory sub-blocks, and each of the associative memory sub-blocks corresponds to a plurality of memory words and a one-to-one correspondence with each of the memory words. A first register holding a hit flag which is a result of a match search with the content of a word, and a first register holding an empty flag indicating whether or not the content of each memory word is a valid search target An encoding circuit applied to an associative memory device having two registers,
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit that holds the hit flag or the empty flag of the next priority output on the detection line in advance while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities;
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed And disabling bit flag circuit shown, the end detection means for encoding the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit detects that it has completedHave
  The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Provided is an encoding circuit which is characterized by being input to a circuit for encoding.
[0024]
  Also,The present invention has a plurality of associative memory sub-blocks, and each of the associative memory sub-blocks corresponds to a plurality of memory words and a one-to-one correspondence with each of the memory words. A first register holding a hit flag which is a result of a match search with the content of a word, and a first register holding an empty flag indicating whether or not the content of each memory word is a valid search target An encoding circuit applied to an associative memory device having two registers,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit that holds the hit flag or the empty flag of the next priority output on the detection line in advance while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities;
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit Timing control means for detecting in advance the timing at which all the digitization ends, and for causing the flag register circuit to hold the hit flag or the empty flag of the next priority detected by the sense circuitHave
  The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Provided is an encoding circuit which is characterized by being input to a circuit for encoding.
[0025]
  Also,The present invention has a plurality of associative memory sub-blocks, and each of the associative memory sub-blocks corresponds to a plurality of memory words and a one-to-one correspondence with each of the memory words. A first register holding a hit flag which is a result of a match search with the content of a word, and a first register holding an empty flag indicating whether or not the content of each memory word is a valid search target An encoding circuit applied to an associative memory device having two registers,
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit that holds the hit flag or the empty flag of the next priority output on the detection line in advance while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities;
  The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed The timing of the end of the encoding of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit is detected in advance and detected by the sense circuit. Timing control means for holding the hit flag or the empty flag of the next priority in the flag register circuit;Have
  The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. Provided is an encoding circuit which is characterized by being input to a circuit for encoding.
[0026]
  Here, the detection line is shared by the hit flag and the empty flag.Is preferred.
[0027]
  In addition, the aboveIn any ofAn encoding circuit comprising:
  The main priority encoder further encodes the hit flag by directly inputting the hit flag from the flag register circuit to the main encode circuit without passing through the main priority circuit, or the hit flag is input to the flag register. Selection means for determining whether to input and encode from the circuit to the main encoding circuit via the main priority circuitthingIs preferred.
[0029]
The sub-priority encoder includes a data latch circuit that holds the sub-block hit signal or the sub-block empty signal that is output from each of the content addressable memory sub-blocks, and each of the sub-holds that is held in the data latch circuit. A sub-priority circuit that sequentially outputs only one sub-block hit signal or the sub-block empty signal as an active state according to the priority order among the block hit signal or the sub-block empty signal, and the sub-priority circuit sequentially And a sub-encoding circuit that sequentially encodes the addresses of the associative memory sub-blocks corresponding to the sub-block hit signal or the sub-block empty signal that is output in an active state.
[0030]
The sub-priority encoder outputs only one sub-block hit signal which is output from each of the associative memory sub-blocks, and outputs from the data latch circuit. It is also preferable to have a sub-encoding circuit that encodes the address of the associative memory sub-block corresponding to the sub-block hit signal in one active state.
[0031]
  Also,Any of the aboveAssociative memory deviceEncoding circuit applied toBecause
  A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, the associative memory sub-block is selected, the sub-encoder for encoding the address, and the detection flag corresponding to each of the hit flag or the empty flag output from the selected associative memory sub-block And a main encoder that encodes the address of the memory word corresponding to each hit flag or empty flag output to the detection line.Is preferred.
[0032]
  The main encoder encodes an address of a memory word corresponding to one active hit flag, and sequentially sets only one empty flag in an active state in accordance with the priority among the active state empty flags, It is preferable to sequentially encode the addresses of the memory words corresponding to the active state empty flag..
[0033]
  The main encoder preferably has a priority circuit that sequentially outputs only one empty flag as an active state among empty flags in an active state according to priority..
[0034]
  The associative memory device includes:
Further, each of the associative memory sub-blocks is provided corresponding to the same memory word, and either the hit flag or the empty flag corresponding to the memory word is output in common. Detection line
Preferably, each of the hit flags or each of the empty flags has a switch circuit that outputs each of the hit flags to the corresponding detection line..
[0035]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, based on a preferred embodiment shown in the accompanying drawings, first, an encoding circuit as a premise for understanding an encoding circuit applied to an associative memory device of the present invention and an associative memory device to which the same is applied The encoding circuit applied to the content addressable memory device of the present invention will be described in detail.
[0036]
  First, an example of an encoding circuit that is a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention will be described in detail with reference to FIGS.
[0037]
In the associative memory device of the illustrated example, when search data is input to the associative memory block constituting the associative memory device at the time of matching search, matching search is sequentially performed from the first of the plurality of associative memory sub-blocks. At this time, as a result of each associative memory sub-block, that is, a match signal (hit signal) matching the search data is held in a plurality of associative memory words, and the highest priority is assigned by the sub-block coding circuit with priority. The associative memory sub-block having a higher value is selected, the hit signal is transferred to the priority order encoding circuit, the hit order encoding circuit encodes the hit signal, and the hit address is output. On the other hand, during the encoding of the hit signal, the hit signal of the next priority content addressable memory sub-block selected by the prioritized sub-block encoding circuit is input to the prefetch circuit. Then, after the encoding of the hit signal of the prioritized associative memory sub-block is completed in the prioritized encoding circuit, the hit of the next priority associative memory sub-block input to the prefetch circuit is immediately performed. Start encoding the signal. After that, the hit signal of the associative memory sub-block having the next priority is prefetched to the prefetch circuit in the prefetch circuit in which the empty space is generated. These procedures are sequentially repeated to encode the hit signal of the entire associative memory block, that is, to output an address.
[0038]
According to this encoding circuit, as described above, the hit signal of the associative memory sub-block to be encoded next is input to the prefetch circuit during the encoding of the hit signal of the previous associative memory sub-block. Since it is not necessary to take the time for transferring the hit signal from the associative memory sub-block to the prioritized encoding circuit in addition to the encoding time, the encoding time of the entire associative memory block and the entire associative memory can be shortened. The associative memory match search operation can be speeded up.
[0039]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an encoding circuit which is a premise of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0040]
FIG. 1 is a schematic diagram of an embodiment of an associative memory block to which an encoding circuit as a premise of the present invention is applied. The encoding circuit 10 of the illustrated example includes a pre-order buffered circuit with priority order (hereinafter referred to as a main priority encoder or main encoder) 12 and a priority-attached sub-block encoding circuit 14 (hereinafter referred to as sub-block priority encoder or The main encoder 12 includes a prefetch buffer circuit 16, a data latch circuit 18, a priority circuit 20, and an encoding circuit 22. The sub block encoder 14 includes a latch circuit 24, , A priority circuit 26 and an encoding circuit 28.
[0041]
The main encoder 12 is provided for an associative memory block (hereinafter referred to as a memory block) 30. The associative memory block 30 includes a plurality (n in the illustrated example) of associative memory sub-blocks (hereinafter referred to as sub-blocks) 32 (B₁, B₂... B_nThe sub-block 32 includes a plurality of (m + 1 in the illustrated example) associative memory words (hereinafter referred to as words) having a predetermined number of CAM memory cells arranged in an array, that is, having a continuous logical address of a predetermined word length. 34) (W₀, W₁... W_m) And the sub-array (CAM cell sub-array) unit configured with the search data in each word 34, for example, a match “1” signal (hit signal) and a mismatch “0” signal are held for each word 34. Register 36 (R₀, R₁, R₂... R_mAnd an OR circuit that takes an OR (logical sum) of the match search results (hereinafter referred to as hit signal data) of each word 34, and the output of this OR circuit is a sub-block encoder 14 described later. The latch circuit 24 holds each sub-block.
[0042]
FIG. 2 shows a configuration diagram of an embodiment of the main encoder 12. In the figure, the look-ahead buffer circuit 16 of the main encoder 12 is such that the priority circuit 20 and the encoding circuit 22 of the main encoder 12 match the hit signal of the sub-block 32 with a higher priority according to a predetermined priority (word). The hit signal data held in the register 36 of the next priority sub-block 32 is stored in each word 34 (W₀, W₁... W_m), And any data can be used as long as it can temporarily hold m + 1 '0' or '1' 1-bit data, such as a data latch circuit or a data register. . The prefetch buffer circuit 16 outputs the hit signal data of each word 34 latched and held in parallel to the data latch circuit 18 by the encode output (encode address output) of the main encoder 12, and then the hit signal data is sent to the main encoder 12. The hit signal data of the next priority sub-block 32 selected by the sub-block encoder 14 during the encoding by the sub-block encoder 14 is fetched for each word 34.
[0043]
The data latch circuit 18 latches and holds m + 1 1-bit data as in the prefetch buffer circuit 16, and each word 34 (W₀, W₁... W_m), Particularly hit signal data having a plurality of hit signals, the priority circuit 20 selects data having a hit signal ('1') only in one word address in accordance with a predetermined priority order, and encodes the data. This is for holding the hit signal data until all the hit signals ('1') are encoded by repeating the encoding of 22. The data latch circuit 18 is configured to reset the word address hit signal ('1') every time a high priority word address hit signal ('1') is encoded.
[0044]
As shown in FIG. 2, the priority circuit 20 receives only m + 1 input signals of all words 34 having a plurality of coincidence signals when hit signal data having a plurality of hit signals is input. Output signals including hit signals with predetermined priorities (priorities) are sequentially output according to predetermined priorities, and m + 1 priority circuit elements 40 (40₀, 40₁..., 40_m)including. Here, one priority circuit element (hereinafter referred to as a circuit element) 40 is a second circuit element 40.₁As a representative example, the input terminal I₁The inverter 42 for inverting the input signal inputted to the N-channel MOS transistor 44, and the output of the inverter 42 and its gate electrode are connected to each other, and the N-channel MOS transistor 44 (N₁) And P-channel MOS transistor 46 (P₁) And the source and drain electrodes of the NMOS transistor 44 as inputs, and an output terminal O₁And a logical operation circuit 48 that outputs.
[0045]
Here, NMOS transistor N₁One electrode (for example, source electrode) of the₀In the upper circuit element 40₀NMOS transistor N₀Connected to the other electrode (for example, drain electrode) of the NMOS transistor N₁The other electrode (for example, drain electrode) of the₁In the lower circuit element 40₂MOS transistor N₂Are connected to one of the electrodes (for example, the source electrode). Thus, the NMOS transistor N₀, N₁, N₂..., N_mIs node Q₀, Q₁, Q₂... Q_m-1Is connected serially. NMOS transistor N_mNode Q below_mIs connected to an OR output terminal or, which is connected to each circuit of the data latch circuit 18 via an inverter 49. In addition, the uppermost NMOS transistor N₀The upper electrode (for example, the source electrode) is fixed at a potential (signal state) indicating “0” or grounded. On the other hand, PMOS transistor P₀, P₁, P₂... P_mOne of the electrodes (for example, the source electrode) is fixed to a potential (signal state) indicating ‘1’ or the power source V_ddThe other electrode (for example, drain electrode) is connected to the node Q, respectively.₀, Q₁, Q₂... Q_mConnected to. Here, the connection direction of the electrodes (source electrode and drain electrode) between the NMOS transistors is determined by the NMOS transistor N₀, N₁, N₂..., N_mAs long as serial connection is possible, the direction may be reversed. PMOS transistor P₀~ P_mThe same applies to. In this way, the priority circuit 20 with m + 1 inputs and m + 1 outputs is configured.
[0046]
Next, a priority (priority order) assigning operation of the priority circuit 20, that is, a plurality of hit signals (match signals) '1' is I₀~ I_mThe output operation of the priority-added output signal in which only the address with the highest priority is the coincidence signal ‘1’ even if input from the above will be described. Circuit element 40 of this unit circuit 20₁Paying attention to I₁N if the input is '1'₁Transistor 44 turns off and P₁The transistor 46 is turned on. Therefore, this P₁Transistor 46 allows Q₁The node is set to '1'. I₁N if the input is '0'₁Transistor 44 is turned on and P₁The transistor 46 is turned off. Therefore, Q₁The node is one Q above₀The same as the logical value of the node. If I_kIf the input is '1', Q_kBecomes ‘1’, so Q after that_n(J ≧ k + 1) is I_jWhether it is ‘1’ or ‘0’, it cannot be set to ‘1’. That is, I_{k + 1}= '1', node Q_{k + 1}(Signal state) is ‘1’ while I_{k + 1}= Q if '0'_{k + 1}= Q_kQ_k= Q from ‘1’_{k + 1}= 1
[0047]
As a result, in FIG. 2, when the plurality of I inputs are “1” and the corresponding serial connection NMOS transistor 44 (N) is OFF, it propagates to the uppermost NMOS transistor 44. The control signal “0” is transmitted, but the propagation control signal “0” is not transmitted to each Q node below the control signal, and becomes “1”. Therefore, it is only necessary to detect to what extent the control signal ‘0’ is transmitted by the logic operation circuit 48. I of this priority circuit 20₀~ I_mIf all the m + 1 inputs become “0”, the control signal “0” is transmitted to the OR output terminal or, and there is no “1” in all m + 1 input signals. Is notified that the hit signal data of the next priority level latched and held in the look-ahead buffer circuit 16 can be input to the data latch circuit 18, and then selected by the sub-block encoder 14. It is notified that the hit signal data of the next next priority can be read into the prefetch buffer circuit 16.
[0048]
Here, the logical operation circuit 48 shown in FIG. 2 includes an NMOS transistor 44 (N₁) Signal state between the drain and the source, that is, the node Q₀And node Q₁And an exclusive OR gate (Exclusive OR gate: anti-matching circuit) 48a that takes an exclusive OR of the logical values between them. In this logical operation circuit 48, the node Q₀And node Q₁Does not match, ie, the circuit element 40₁NMOS transistor 44 (N₁) Node Q₀Until the propagation control signal ‘0’ is propagated, the node Q₁Until the propagation control signal '0' is not propagated, the exclusive OR gate 48a outputs '1'. Node Q₀And node Q₁Output terminal O if they match ('0')₁The output of “0” is “0”. The logic operation circuit 48 is not limited to the example shown in FIG. 2, and may be configured to perform a desired logic operation by combining various gates. The input of the logic operation circuit 48 is connected to the node Q.₀And node Q₁The input signal or an inverted value thereof may be used, and the content of the logical operation may be appropriately selected according to the signal value.
[0049]
Next, when the output signal (O) having the highest priority and having one hit signal is output from the input signal (I) having a plurality of hit signals, the hit signal having the next highest priority is output. If the addresses are in the same sub-block 32, the input side may be reset using the highest priority output signal. That is, for example, in the priority circuit 20 shown in FIG.₁= '1', I₂= If it was '1', node Q₀= '0', node Q₁= Q₂= ... = Q_m= “1”, so output O₁= ‘1’ and output O₀= O₂= ... = O_m= 0. This O₁The output value is input to the data latch circuit 18 (18₁) Input to the reset terminal to reset I₁= '0', therefore, N transistor 44 (N₁) Is on, P transistor 46 (P₁) Is off and node Q₁= Q₀= '0', where N transistor N₂Is off so node Q₀= Q₁= '0', node Q₂= ... = Q_m= ‘1’ and the next priority is I₂= '1' is selected as the next output signal.
[0050]
Thus, a plurality of hit signals in the hit signal data of the same sub-block 32 input to the main encoder 12 at a time are output by the priority circuit 20 as output signals having only one hit signal according to a predetermined priority order. The hit signal (') that is sequentially output to the encode circuit 22 and' 1 'output is input to the reset terminal of the data latch circuit 18 of the word address corresponding to the' 1 'output. 1 ') is reset sequentially. Thus, when the last hit signal is prioritized and output to the encoding circuit 22 and reset, the lowest node Q in the figure is displayed._mIs transmitted from the OR output terminal or, inverted by the inverter 49, and the inverted value “1” is input to all the circuits of the data latch circuit 18 and latched and held in the prefetch buffer circuit 16. After the hit signal data of the next sub-block 32 of the next priority level is inputted (shifted) to each corresponding circuit of the data latch circuit 18 and held, the empty pre-read buffer circuit 16 is preliminarily stored in the sub-block encoder 14. The hit signal data of the next sub-block 32 of the next priority selected by is read from the register 36 and latched and held. Thus, after the priority circuit 20 finishes processing the hit signal data of the sub-block of the previous priority, the hit signal data of the sub-block of the next priority is transferred from the register 36 of the sub-block 32. Since there is no need to wait for a while, encoding can be performed efficiently.
[0051]
The encoding circuit 22 is for encoding the address of the coincidence signal that exists only in the output signal sequentially output from the priority circuit 20, and each word 34 (W₀, W₁, W₂... W_m) Corresponding to the output terminal O₀, O₁, O₂... O_mFor encoding each word address, m + 1 ≦ 2^LL + 1 address lines 50 (50) for encoding L + 1 bits for the smallest natural number L₀, 50₁, 50₂..., 50_L) And the gate electrode of each output line O.₀, O₁, O₂... O_mFrom a ground transistor 52 connected to the output line from Here, all L + 1 address lines 50₀, 50₁, 50₂..., 50_LEach has resistance r on one end side₀, R₁, R₂... r_LConnected to the power supply via (or fixed at the '1' potential)_L... A₂A₁A₀The transistor 52 is attached so that the L + 1 bit code output can be obtained.
[0052]
That is, the output terminal O₀Output lines from all L + 1 address lines 50₀~ 50_LAre connected to all the gate electrodes of L + 1 ground transistors 52 connected to each other. Here, for example, the output terminal O₀Output is ‘1’ (coincidence signal) and the rest are all ‘0’, A_L= ... = A₂= A₁= A₀= 0 and (A_L... A₂A₁A₀) = (0... 000). Next, the second and third word addresses W₁Output terminal O corresponding to₁And O₂Output lines are address lines 50, respectively.₀And 50₁L address lines 50 excluding₁~ 50_LAnd 50₀, 50₂~ 50_LConnected to the gate electrodes of the L ground transistors 52 connected to the output terminal O.₁And O₂When only becomes ‘1’, (A_L... A₂A₁A₀) = (0... 001) and (0... 010). Similarly, the ground transistor 52 is connected to each address line 50 so as to represent each code address. For example, m + 1 = 2^LThe last output terminal O_mOutput line is the address line 50_LOnly to the ground transistor 52 attached only to the output terminal O_mOnly when ‘1’, (A_L... A₂A₁A₀) = (01... 111) (the first L + 1 digit is “0” and the remaining L digits are all “1”). And all output terminals O₀, O₁, O₂... O_mWhen ‘0’, (A_L... A₂A₁A₀) = (1... 111) (all 1). The encoding circuit 22 is basically configured as described above. Here, the encoding circuit 22 is not particularly limited to the one shown in the figure, and receives an input signal having a “1” output for only one word address, and encodes (encodes) an address of the “1” output. If it can do, there will be no limitation in particular, A conventionally well-known thing can also be used. The main encoder 12 is basically configured as described above.
[0053]
Next, FIG. 3 shows a block diagram of an embodiment of the sub-block encoder 14. The data latch circuit 24, the priority circuit 26, and the encoding circuit 28 shown in FIG. 2 are basically the data latch circuit shown in FIG. 2 except that the number of units constituting each is n with respect to m + 1. 18, since the configuration similar to that of the priority circuit 20 and the encoding circuit 22 is shown, a detailed circuit configuration is omitted. Here, in the sub-block encoder 14, the associative memory sub-block 32 (B₁, B₂... B_n) When a match search is performed every time, a match search result in each memory sub-block 32, that is, hit signal data is held in the register 36 and is searched in the sub-block 32 by an OR circuit (not shown) in the sub-block 32. A sub-block hit signal indicating whether or not there is a word 34 (hit word or match word) indicating coincidence with data is generated and held in the data latch circuit 24 of the corresponding sub-block 32. Thus, the subblock 32 is successively searched for coincidence, and the hit signal data is held in the register 36 of the subblock 32, and the block hit signal is latched and held in the data latch circuit 24.
[0054]
On the other hand, in the sub-priority circuit 26 of the sub-block encoder 14, the block hit signal latched and held in the data latch circuit 24 from the left side to the right side in the illustrated example is a hit signal ('1') according to a predetermined priority order. The sub-block 32 is selected and an output signal with priority having “1” only in the block address is output. This output signal is encoded and output by the sub-encoding circuit 28 in the subsequent stage, and is returned to the control unit of the sub-block 32, and the gate circuit 54 in the control unit is turned on to obtain the hit signal data in the register 36. Input after the prefetch circuit 16 of the main encoder 12 becomes empty. In this way, the sub-block encoder 14 selects the sub-block 32 having the priority to be encoded next in accordance with the predetermined priority, and the main encoder 12 selects the hit signal from the hit signal data of the sub-block 32 having the previous priority. While the first word address is being encoded, the hit signal data of the sub-block 32 of the next priority is transferred to the prefetch circuit 16 which has become empty and latched and held.
[0055]
Here, the encoding circuit 10 in the illustrated example outputs the encoded block address output from the sub-encoding circuit 28 of the sub-block encoder 14 and the encoded word address output from the main encoding circuit 22 of the main encoder 12. Both are sequentially output as encoded logical addresses. Then, when the last sub-block 32 or the sub-block 32 with the lowest priority is selected, the processing of the sub-block encoder 14 ends, and when the encoding of all hit signals by the main encoder is completed, the encoding circuit 10 The hit signals of all the memory words 34 in the associative memory sub-block 30 are output as logical addresses, and the match search operation is terminated. The encoding circuit 10 in the illustrated example shows an example in which one main encoder 12 and one sub-block encoder 14 are provided for the associative memory block 30 having a plurality of associative memory sub-blocks 32. The present invention is not limited to this, and a configuration in which one sub-block encoder 14 is provided for a plurality of associative memory blocks 30 as in the conventional encoding circuit 210 applied to the associative memory 200 shown in FIG.
[0056]
Next, FIG. 4 shows a specific circuit configuration of the prefetch circuit 16 used in the illustrated encoding circuit 10 and a switch circuit 160 and a precharge circuit 162 for controlling each sub-block 32 necessary for the operation thereof.
[0057]
As shown in the figure, the switch circuit 160 includes the sub-block 32 (B₁) Register 36 (R₀) Connected to one (S₀) As a representative example, two NMOS transistors 163 and 164 are connected in series. Each switch circuit 160 (S₀, S₁, ..., S_m) Of one of the transistors 163 (for example, the drain electrode) corresponds to the corresponding detection line 165 (L₀, L₁, ..., L_m) In each sub-block 32 (B₁, B₂, ..., B_n) And the detection line L is connected to the prefetch circuit 16. Each switch circuit 160 (S₀, S₁, ..., S_mThe gate electrode of the transistor 163 is connected to the AND circuit 166 in parallel with the block selection line 167 in each sub-block 32. Each switch circuit 160 (S₀, S_i, ..., S_m) Of the other transistor 164 is connected to the corresponding register 36 (R₀, R₁, ..., R_m) And the other electrode (for example, the source electrode) of the transistor 164 is grounded. The precharge circuit 162 is connected to each detection line 165 (L₀, L₁, ..., L_m) PMOS transistor 168 (PC) which is a precharge transistor for precharging the potential to a predetermined potential (for example, power supply potential).₀, PC₁, ..., PC_m) And each PMOS 168 (PC₀, PC₁, ..., PC_m) One electrode to a predetermined potential source (power source) and the other electrode to each detection line 165 (L₀, L₁, ..., L_m), The gate electrode is connected to the precharge signal line 169.
[0058]
Prefetch circuit 16 includes two inverters 170 and 172 connected in parallel in opposite directions, and latch signal lines 174 and 175 for inputting a control signal for controlling the output state of inverters 170 and 172. (M + 1) data latch circuits. The input side ends of the parallel connection inverters 170 and 172 are connected to the corresponding input line 165 (L_iThe output side end is connected to a corresponding circuit element of the data latch circuit 18. The latch signal line 174 is connected to the control signal terminal of the inverter 170 and the inverted control signal terminal of the inverter 172, and the latch signal line 175 is connected to the control signal terminal of the inverter 172 and the inverted control signal terminal of the inverter 170.
[0059]
One input terminal of the AND circuit 166 is connected to a corresponding circuit element of the data latch circuit 24 (or the sub priority circuit 26) of the sub block encoder 14, and the other input terminal is used to select the selection timing of the block selection line 167. It is connected to a control signal line 176 to be controlled. The control signal line 176, the precharge signal line 169, and the latch signal lines 174 and 175 are connected to a timing control circuit 178 that controls the operation timing of each circuit.
[0060]
Next, the prefetch (prefetch) operation of the prefetch circuit 16 will be described.
First, the precharge signal line 169 is set to L and the PMOS 168 (PC₀, PC₁, ..., PC_m) Are turned on, and (m + 1) detection lines 165 (L₀, L₁, ..., L_m) To a predetermined potential.
[0061]
Next, the timing control circuit 178 sets the precharge signal line 169 to H, turns off (m + 1) PMOSs 168, and sets the control line 176 to '1' (H) to block the data latch circuit 24 of the sub-block encoder 14. Sub-block 32 (B) of the next priority (the next priority of the sub-block encoded by the main encoder 12) in which the hit signal “1” is latched and held_i) Block hit signal ‘1’ is input to the AND circuit 166, and the sub-block 32 (B_i) Block selection line 167 is turned on.
[0062]
Subblock 32 (B_i) Is selected, and the block selection line 167 is set to H (high level) by the corresponding AND circuit 166, the register 36 (R) that holds the hit signal ('1') in the register 36._i) And the transistor 163 connected to the gate electrode thereof are turned on, and the detection line 165 (L_i) Is grounded, and this detection line 165 (L_i) To remove the precharged charge and lower its potential. On the other hand, the register 36 (R_jThe transistor 164 whose gate is connected to the transistor 164 is not turned on but remains off. Therefore, even if the block selection line becomes H, the corresponding detection line 165 (L_j) Does not change, and the precharge potential is maintained.
[0063]
Thus, the selected sub-block 32 (B_i) Storage register 36 (R₀, R₁, ..., R_m) In accordance with the stored value ('1': hit signal, '0': miss hit signal), the detection line 165 (L₀, L₁, ..., L_m) Changes, and the polarity is reversed.
[0064]
Here, a latch signal is applied to the latch signal lines 174 and 175 of the prefetch circuit 16 to cause the parallel connection inverters 170 and 172 of the prefetch circuit 16 to latch. Here, the detection lines on the input side of the inverters 170 and 172 have a polarity opposite to that of the register 36, but the output side is inverted and thus has the same polarity. Therefore, at the same time as the encoding of the subblock 32 with the highest priority of the main encoder 12 is completed, the hit signal data of the subblock 32 with the next priority that has been latched in the prefetch circuit 16 is input to the data latch circuit 18. Thereafter, the prefetch circuit 16 repeats the above-described operation to prefetch hit signal data in the storage register 36 of the next next priority sub-block 32.
The encoding circuit 10 is basically configured as described above.
[0065]
The prioritized encoding circuit 10 is not limited to the priority circuits 20 and 26 and the encoding circuits 22 and 28 shown in FIG. 2 and FIG. 3, and a conventionally known priority circuit and encoding circuit may be used. In order to increase the speed of the prioritization and encoding itself, the priority circuit 180 and the encoding circuit 190 shown in FIGS. 4, 5 and 6 may be used. Of course, the priority circuit 180 may be combined with the main encoding circuit 22 shown in FIG.
[0066]
The priority circuit 180 shown in FIG. 5 is composed of three layers, the lowest layer is composed of 16 4-input small unit priority circuits (hereinafter referred to as unit circuits) 182, and the intermediate layer is composed of four similar layers. It consists of a 4-input small unit priority circuit 184, and the highest hierarchy consists of one similar 4-input small unit priority circuit 186. Therefore, the priority circuit 180 can have 64 inputs by the 16 unit circuits 182 in the lowest hierarchy. That is, the 64 inputs of the priority circuit 180 are grouped into 16 groups, 4 groups. A small unit priority circuit 182 having 4 inputs of one group as a unit is configured and 16 pieces are used. The 16 small unit priority circuits 182 are grouped into four groups, and one group is composed of four unit circuits 182. The four unit circuits 182 constituting the one group constitute an intermediate layer 1 Are connected to two small unit priority circuits 184. The four unit circuits 184 are connected to the small unit priority circuit 186 in the highest hierarchy as a group.
[0067]
The priority circuit 180 shown in FIG. 5 has a three-layer structure having 64 inputs and four-input unit circuits 182, 184, and 186 as a structural unit, but is not limited to this. The number of elements and the number of layers can be appropriately selected as necessary, but the hierarchical structure may be appropriately selected according to the total number of inputs and the number of inputs of the unit circuit to be used. The unit circuits 182, 184, and 186 constituting each layer use the same number of inputs, but are not limited to this and may be different. It is convenient to increase the speed of priority change if the number of inputs to the unit circuit is small. However, if the number is too small, the number of necessary unit circuits increases and the number of necessary layers increases. Is not preferable because it increases. Therefore, if the total number of inputs and the number of unit circuit inputs that can be used for each layer (either one type or multiple types) are selected, the number of layers is determined so as to conform to this, and a multi-layer configuration is obtained. Good.
[0068]
As shown in FIG. 6A, the small unit priority circuit 182 is configured such that the upper side, that is, the upper side has a higher priority, and has four input terminals I.₀, I₁, I₂And I_ThreeAnd four output terminals O₀, O₁, O₂And O_ThreeAn enable signal input terminal e, a logical sum (OR) output terminal or, and four priority circuit elements 188 (188)₀188₁188₂And 188_Three). The circuit element 188 shown in FIG. 2 is the same as that shown in FIG. 2 except that the logical operation circuit 48 used has an enable signal input terminal e and is activated by an enable signal input therefrom. Since the circuit element 40 has the same configuration as that of the circuit element 40 shown, the same components are denoted by the same reference numerals and description thereof is omitted.
[0069]
FIG. 7 shows a specific configuration example of the logical operation circuit 48 shown in FIG. The logical operation circuit 48 shown in FIG. 7 includes an exclusive OR gate 48a and an AND gate 48b that takes the logical product of the output of the exclusive OR gate 48a and the enable signal e. This logical operation circuit 48 has a mismatch in input signals, that is, a node Q₀And node Q₁Is not coincident, the exclusive OR gate 48a outputs "1", and at the same time, if the enable signal e is "1" (active), the AND gate 48b outputs the output terminal O₁If the input signal matches or the enable signal e is ‘0’, the output terminal O₁The output of “0” is “0”.
[0070]
FIGS. 6B and 6C are schematic diagrams of unit circuits 184 and 186 respectively constituting the intermediate hierarchy and the highest hierarchy. The unit circuits 184 and 186 shown in the figure have the same configuration as the unit circuit 182 in the lowest hierarchy shown in FIG. 6A except for signals input to and output from the input / output signal terminals. The illustration of the configuration is omitted. The input terminal or of the unit circuit 184 shown in FIG.₀, Or₁, Or₂, Or_ThreeIs the OR output or of each of the four unit circuits 182 constituting the lowest layer shown in FIG. Output Ot of this unit circuit 184_k(K = 0, 1, 2, 3) to each input signal or_kUnit circuit 182 corresponding to_kEnable terminal e_kConnect to Ot_k= K'th circuit 182 only when '1'_kCan be selectively activated. Therefore, it can be seen from the OR output whether or not there is a “1” in the or input of this unit circuit 184, and this OR output is eventually controlled by all the I's of the plurality of unit circuits 182 under the control of the unit circuit 184. This indicates whether there is an input signal that is '1'.
[0071]
Furthermore, another upper layer unit circuit 186 that receives the OR output of the unit circuit 184 is shown in FIG. 6C. The configuration of the unit circuit 186 is shown in FIGS. 6A and 6B, respectively. As described above, the unit circuits 182 and 184 may have exactly the same configuration. The unit circuit 186 shown in FIG. 6C receives the OR outputs of all four unit circuits 184 constituting the intermediate hierarchy as an OR input OR._k(K = 0, 1, 2, 3) input, this OR input OR_kOutput OUT corresponding to₀, OUT₁, OUT₂, OUT_ThreeAre input to the respective enable signal inputs E as enable signals of all four unit circuits 184 in the intermediate layer. Thus, the OR input OR of this unit circuit 186_kIt can be seen from the OR output GOR of this unit circuit 186 whether or not there is '1'. The enable signal ENB of the unit circuit 186 itself is OUT_kA predetermined clock signal is separately input until all output signals are "0", that is, until the OR output GOR becomes "0". Conversely, the output OUT of the unit circuit 186_kWhile “1” is being output, an output of a signal having a unique “1” at the highest priority address (hereinafter referred to as an output signal with priority) selected from the input signal of the priority circuit 180. Indicates that a small unit priority circuit having “1” (match signal) exists in a lower group corresponding to an address that outputs “1”.
[0072]
Using the priority units 182, 184, and 186 of the small unit configured as described above, when the circuit configuration of the priority circuit 180 that performs hierarchical selection in this way is realized, a priority circuit 20 shown in FIG. 2 is obtained. Compared with the case where all the N transistors 44 are serially connected in a single layer, the speed can be greatly increased. Here, as the or output and the OR output, as shown in FIG. 6, the lowest-order (lower) circuit element 188 of the priority circuit 182_ThreeNode Q of_ThreeThe signal state (logical value) can be used. Thus, node Q_ThreeHowever, the present invention is not limited to this, and it is not limited to this, and the input is required to further increase the speed. In order to obtain an OR output directly from the signal, a normal OR gate or the like may be used.
[0073]
By using such an or output or an OR output, even if there are consecutive hit signals with different priority levels in different small unit priority circuits 182, a hit signal with a higher priority level is output as an output signal with priority. Until the input signal is reset by this output signal and the OR output becomes “0”, “1” output is possible from the unit circuit 182 having the hit signal of the low priority word address. However, the output signal of the upper layer unit circuit 184 does not become “1” output. Therefore, the enable signal of the unit circuit 182 does not become “1” (ie, active), and the unit circuit 182 has “1”. Cannot output. However, if the OR output of the unit circuit 182 of the previous priority level becomes “0”, the OR output of the unit circuit 182 of the next priority level is “1” output, so that the unit circuit 184 of the upper layer is also “1”. 'Output. Therefore, the enable signal of the next priority unit circuit 182 is “1”, and this unit circuit 182 can output “1”. Thus, even if hit signals are straddling between different unit circuits 182, quick switching is possible.
[0074]
Since the priority circuit 180 shown in FIG. 5 has 64 inputs, 6 bits are required for address code conversion, and 6 address lines are required. When a conventional address encoder such as the main encoding circuit 22 shown in FIG. 2 is used, the six address lines and the four output lines of the sixteen priority circuits 182 in the lowest hierarchy, that is, a total of 64 lines are used. A 6-bit address encoder can be configured by connecting the output lines to each other via the ground transistor 52 in accordance with the predetermined method described above. As described above, a conventional encoding circuit can be applied to the priority circuit 180 shown in FIG. 5, but the number of ground transistors connecting the output line and the address line increases as the input increases.
[0075]
For this reason, the encoding circuit 190 shown in FIG. 5 has an address encoder configuration that encodes 2 bits for each layer of the above-described priority circuit 180 having the three-layer structure. When a coincidence output (hit signal) is included, an output signal with a priority is output. At this time, the priority circuit 180 selects each hierarchical level among the small unit priority circuits 182, 184, and 186 constituting each hierarchical level. There is one output terminal that outputs' 1'H (high). Accordingly, the 16 small unit priority circuits 182 in the lowest hierarchy are divided into the lower 2 bits A₁, A₀Two address lines 192 for determining₁192₀Connected to. The middle layer four priority circuits 184 are intermediate two bits A_Three, A₂Two address lines 192 for determining_Three192₂Connected to. The priority circuit 186 of the highest hierarchy is composed of the upper 2 bits A_Five, A_FourTwo address lines 192 for determining_Five192_FourConnected to.
[0076]
Here, since the connection between one priority circuit and two address lines is the same in each hierarchy, the priority circuit 182 in the lowest hierarchy is representative.₀And address line 192₁192₀As a representative example, the connection to the terminal will be described. Priority circuit 182₀First output line O₀Is the address line 192₁192₀Are respectively connected to the gate electrodes of the two ground transistors 52 that are grounded (or fixed to the “0” potential). Therefore, the first output line O₀Only the output of ‘1’ [(O₀, O₁, O₂, O_Three) = (1, 0, 0, 0)], the two ground transistors 52 are turned on, and A₀= A₁= 0. Next, the priority circuit 182₀Second output line O₁Is the address line 192₁Is connected to the gate electrode of the grounding transistor 52 that grounds (or is fixed to the “0” potential). For this reason, the second output line O₁Only “1” [(O₀, O₁, O₂, O_Three) = (0, 1, 0, 0)], the ground transistor 52 is turned on and (A₁, A₀) = (0, 1). Furthermore, the priority circuit 182₀Third output line O₂Address line 192₀Is connected to the gate electrode of the grounding transistor 52 that grounds (or is fixed to the “0” potential). Therefore, the third output line O₂Only “1” [(O₀, O₁, O₂, O_Three) = (0, 0, 1, 0)], the ground transistor 52 is turned on and (A₁, A₀) = (1, 0). Here, the fourth output line O_ThreeOnly “1” [(O₀, O₁, O₂, O_Three) = (0, 0, 0, 1)] (A₁, A₀) = (1, 1).
[0077]
The encoding circuit 190 can be configured by performing such a connection for each priority circuit with respect to two address lines for each layer. Here, in the encoding circuit 190, the address line 192₀~ 192_FiveThe number of ground transistors 52 used to connect each of the priority circuits 182, 184 and 186 is 4 for one priority circuit, so that 64 are the lowest hierarchy, 16 are the middle hierarchy, and the highest hierarchy is The total number is 84, and the total number may be 84. On the other hand, in the case of connecting all six address lines to the 16 main priority circuits 20 in the lowest hierarchy as in the address encoder shown in FIG. Is required. Therefore, the encoding circuit 190 shown in FIG. 5 can achieve the effect of speeding up the encoding operation.
[0078]
As a priority example of the priority circuit constituting the main encoder and sub-block encoder of the encoding circuit which is the premise of the present invention, a configuration in which N channel transistors are serially connected as shown in FIG. 2 and FIG. 6A is given as a representative example. However, the present invention is not limited to this, and a priority circuit configured to serially connect P-channel transistors may be used, or a configuration capable of bidirectional priority may be used. As long as the prefetch circuit is provided in the main encoder and the sub-block encoder, conventionally known ones can be used.
[0079]
  As mentioned above, although the encoding circuit used as the premise for understanding the encoding circuit applied to the content addressable memory device of the present invention has been described with various examples, it is not limited to the illustrated examples. It goes without saying that the design can be changed and various improvements can be made, such as the number of inputs and the configuration of the prefetch circuit, data latch circuit, priority circuit, and encoding circuit constituting the sub-block encoder.
[0080]
As described above in detail, in the encoding circuit of the illustrated example, when performing a match search with the search data of the associative memory block of the associative memory device, of the plurality of associative memory sub-blocks constituting the associative memory block. A match search result of the first associative memory sub-block, for example, a match signal (hit signal) that matches the search data in a plurality of associative memory words is held in holding means such as a register and the associative memory sub-block. A block hit signal indicating the presence of an associative memory word matching the search data is generated. Subsequently, the prioritized sub-block encoding circuit receives the block hit signal, selects the associative memory sub-block having the highest priority, and generates a sub-block address. Then, the hit signal of the selected highest priority sub-block (simultaneously for all words) is transferred to the coding circuit with priority. Thereafter, the coding circuit with priority order codes the hit signal with a predetermined priority order and outputs a word address. During this encoding, the associative memory sub-block having the next priority is selected by the sub-block encoding circuit with priority, and the hit signal data held in the holding means such as a register of this sub-block is selected as the priority. The data is input to a prefetch circuit provided in the encoding circuit. Thus, after the encoding of the hit signal is completed, the encoding circuit with priority order immediately starts to encode the hit signal data of the next priority sub-block input to the prefetch circuit immediately before, Encode and output word address. The word address output and the sub-block address output are combined to output a logical address.
[0081]
Therefore, according to this encoding circuit, even in an associative memory block composed of a plurality of associative memory sub-blocks, there is no time delay (waiting time) in switching between the plurality of associative memory sub-blocks, and a large number of associative memory The output signal from the memory sub-block can be efficiently encoded. As a result, the present invention can also be applied to a large-capacity associative memory device including an associative memory block composed of a plurality of associative memory sub-blocks that require high-speed processing for large-capacity data.
[0082]
  Next, referring to FIG. 8 to FIG. 11, there are another encoding circuit as a premise for understanding the encoding circuit applied to the associative memory device of the present invention and a number detection circuit applicable thereto. The semiconductor integrated circuit will be described in detail.
[0083]
In the associative memory device of the illustrated example, when search data is input to the associative memory block constituting the associative memory device at the time of matching search, matching search is performed across a plurality of associative memory sub-blocks. At this time, as a result of each associative memory sub-block, that is, flag data including a match signal (hit signal) that matches the search data is held in a plurality of associative memory words, and a priority sub-block encoding circuit As a result, the associative memory sub-block having the highest priority is selected, and the flag data is transferred to and held in the flag register of the main coding circuit with priority. The priority-added main encoding circuit encodes the hit signal in the flag data stored in the flag register according to a predetermined priority, and outputs a hit address. On the other hand, during the encoding of the flag data, the flag data of the associative memory sub-block of the next priority selected by the prioritized sub-block encoding circuit is input to the prefetch circuit. In the prioritized main encoding circuit, hit signals in the flag data of the prioritized associative memory sub-block are sequentially encoded, and the hit signal in the flag register is sequentially output as the hit address is output. It will be reset.
[0084]
At this time, the number of hit signals held in the flag register is detected by timing detection control circuit means for detecting the end of the hit signal of the flag register in advance. For example, when the number of the remaining hit signals becomes the last one, the flag data of the associative memory sub-block of the next priority inputted to the prefetch circuit immediately after the end of the encoding of the hit signal Is moved to the flag register, and encoding of the hit signal in the flag data is started. Thereafter, the flag data of the associative memory sub-block of the next priority is prefetched to the prefetch circuit in the prefetch circuit in which a space is generated. These procedures are sequentially repeated to encode the hit signal of the entire associative memory block, that is, to output an address.
[0085]
According to the encoding circuit of the illustrated example, as described above, the hit signal in the flag data of the associative memory sub-block to be encoded next is being encoded during the encoding of the hit signal of the flag data of the previous associative memory sub-block. Since it is input to the prefetch circuit, it is possible to eliminate the time for transferring the hit signal from the associative memory sub-block to the flag register of the main coding circuit with priority, and the last hit signal of the flag data in the flag register can be eliminated. Immediately after the start of encoding, it is detected that the hit signal has become the last one, and the flag data held in the prefetch circuit is transferred to the flag register. In the next encoding cycle, the flag data in the transferred flag data is transferred. Since the hit signal can be encoded, there is no loss in the encoding cycle. It is possible to shorten the coding time for the entire entire triblock therefore associative memory can speed up the match search operation of the CAM device.
[0086]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an encoding circuit which is a premise of the present invention and a semiconductor integrated circuit applicable thereto will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0087]
FIG. 8 is a schematic diagram of an embodiment of an associative memory block to which the encoding circuit as the premise of the present invention is applied. The encoding circuit 11 shown in the figure has a timing control circuit 60 to which a semiconductor integrated circuit as a premise of the present invention is applied in a main encoder 12, and an initial value of a flag register (data latch circuit) 18 is output from the timing control circuit 60. Since the configuration is basically the same as that of the encoding circuit shown in FIG. 1 except that the setting is performed, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0088]
The encoding circuit 11 shown in FIG. 1 includes a priority-added encoding circuit with a prefetch circuit (hereinafter referred to as a main priority encoder or a main encoder) 12 and a priority-added sub-block encoding circuit (hereinafter referred to as a sub-block priority encoder or a sub-encoder). The main encoder 12 includes a prefetch circuit (prefetch circuit) 16, a flag register circuit 18, a main priority circuit 20, a main encode circuit 22, and a timing control circuit 60. The sub block encoder 14 includes a data latch circuit 24, a sub priority circuit 26, and a sub encode circuit 28.
[0089]
FIG. 9 shows a configuration diagram of an embodiment of the main encoder 12 of the encoding circuit 11. In the figure, the prefetch circuit 16 of the main encoder 12 is configured so that the main priority circuit 20 and the main encode circuit 22 of the main encoder 12 receive the hit signal in the flag data of the sub-block 32 having a higher priority with a predetermined priority (word ), The flag data held in the register 36 of the next priority sub-block 32 is stored in each memory word 34 (W₀, W₁... W_m), And any data can be used as long as it can temporarily hold (m + 1) 1-bit data of “0” or “1”, such as a data latch circuit or a data register. It's okay. The flag data from the prefetch circuit 16 is input in parallel to the flag register 18 by the switching timing output (detection output) of the timing control circuit 60. In addition, while the flag data is encoded by the main encoder 12, the flag data of the sub-block 32 of the next priority selected by the sub-block encoder 14 is taken into the prefetch circuit 16 for each memory word 34. .
[0090]
That is, in the main encoder 12 shown in FIG. 9, the timing control circuit 60 detects the number of flag data (hit signals) held in the flag register 18, for example, the last one, and stores it in the flag register 18. A switching timing signal (initial value setting signal) is output, and the flag data of the prefetch circuit 16 is input to the flag register 18. In contrast, in the main encoder 12 shown in FIG. 2, after resetting the last hit signal of the flag data held in the flag register 18, the node Q of the priority circuit is reset._mProposed to switch the flag data of the flag register 18 to the flag data of the next priority sub-block 32 latched and held in the prefetch circuit 16 using the end data '0' which is the OR output output from Yes. That is, this node Q_mThe output “0” is inverted by the inverter, the inverted value “1” is input to all the circuits of the prefetch circuit 16, and the flag data of the subblock 32 of the next priority level latched and held here is used as the flag register circuit 18. Each is input (shifted) to a corresponding circuit and held. After that, the main encoder 12 shown in FIG. 2 also has the next pre-priority sub-block 32 previously selected by the sub-block encoder 14 in the free prefetch circuit 16 as in the main encoder 12 shown in FIG. Are read from the register 36 and latched and held. In this way, in the method of the main encoder 12 of FIG. 2, as with the main encoder 12 of FIG. 9, the main priority circuit 20 ends the processing of the flag data of the previous priority sub-block and then the next priority sub-block. Since it is not necessary to wait while the flag data of the block is transferred from the register 36 of the sub-block 32, encoding can be performed efficiently. However, in the main encoder 12 of FIG. 2, the contents of the flag register 18 are held in the prefetch circuit after the last hit signal of the flag data of the previous priority sub-block held in the flag register is reset. Therefore, in the priority encoding cycle started by reset, a cycle in which encoding cannot be performed at the time of switching of flag data in the sub-block occurs, and time in which encoding output cannot be performed occurs.
[0091]
Therefore, in the main encoder 12 of FIG. 9, the number of flag data hit signals in the flag register 18 is detected by the timing control circuit 60 as will be described later, and it is detected that it has become the last one. Thus, instead of resetting the last hit signal in the main priority circuit 20 by using this detection result as an input signal, the flag data of the sub-block 32 of the next priority stored in the prefetch circuit 16 is shifted to the flag register 18. (Input). Therefore, in the main encoder 12 of FIG. 9, priority encoding can be performed in the same cycle even when the flag data of the same sub-block or the flag data of the sub-block is switched. Of course, in the main encoder 12 of FIG. 9, the next pre-priority sub-block previously selected by the sub-block encoder 14 is preliminarily selected in the pre-fetch circuit 16 which has become empty due to the switching of the flag data of the sub-block in the flag register 18. 32 flag data is read first from the register 36 and latched and held, so that this read time (time for transferring flag data from each sub-block 32 to the main encoder 12) is irrelevant to the encoding process. Efficiency can be increased. In the main encoder 12 of FIG. 9, the last hit signal of the flag data in the flag register 18 does not need to be reset.
[0092]
FIG. 10 shows a specific circuit diagram of an embodiment of the timing control circuit 60 to which the semiconductor integrated circuit as the premise of the present invention, which is the most characteristic part of the encoding circuit 11 of the illustrated example, is applied.
[0093]
The timing control circuit 60 shown in FIG. 10 includes m + 1 flag registers 18 in parallel with the first signal line (signal current detection line) 62, the second signal line (reference current drive line) 64, and the first signal line 62, respectively. Data latch circuit 18₀, 18₁, ..., 18_mM + 1 current drive circuits (current drive means) 66 provided for each of₀, 66₁, ..., 66_mAnd a reference current driving circuit (reference current driving means) 68 provided on the second signal line 64, and a difference between currents flowing in the first signal line 62 and the second signal line 64, that is, a difference current for detecting the difference current. The operation timing of the detection circuit (difference current detection means) 70 and the timing control circuit is controlled, that is, the current drive circuit 66 (66₀, 66₁, ..., 66_m), And a precharge control signal line 72 for controlling the reference current drive circuit 68, the difference current detection circuit 70, and the like.
[0094]
Further, in the timing control circuit 60 of the illustrated example, in order to balance the electric characteristics such as the electric capacity of the circuit, the second signal line 64 includes a current driving circuit 66 (66) provided in the first signal line 62.₀, 66₁, ..., 66_m) Corresponding to the dummy circuit 74 (74₀74₁, ..., 74_m) And a dummy circuit 76 corresponding to the reference current driving circuit 68 provided on the second signal line 64 is provided on the first signal line 62. One end of each of the first signal line 62 and the second signal line 64 is connected to the differential current detection circuit 70. Further, the first signal line 62 and the second signal line 64 are connected to a precharge transistor 78 and an equipotential transistor 79, and function to initialize the two signal lines to 5V, for example. Here, the transistors 78 and 79 are both P-channel MOS transistors, and their gate electrodes are connected to the precharge control signal line 72. Here, the dummy circuit 74 (74₀74₁, ..., 74_m) May be used as the reference current driving circuit 68. At this time, the dummy circuit 76 becomes unnecessary.
[0095]
The current driving circuit 66 will be described as one representative example. The current driving circuit 66 includes a control transistor 67a and a signal voltage applying transistor 67b, both of which are connected in series and composed of N-channel MOS transistors. The transistor 67a is a first signal line 62. The transistor 67b is grounded, the gate electrode of the transistor 67a is connected to the control signal line 72, and the gate electrode of the transistor 67b is connected to the corresponding data latch circuit of the flag register 18 and the output terminal Q.
[0096]
In the current driving circuit 66, the transistor 67a is turned on at the time of detection, and when the hit signal “1” is input from the flag register 18 to the gate electrode of the transistor 67b, the transistor 67b is turned on, and a predetermined current i₀Is configured to flow. This drive current i₀Are all current drive circuits 66₀, 66₁, ..., 66_mHowever, there are variations in the transistors 67a and 67b used, such as variations due to process variations. The dummy circuit 74 has a configuration similar to that of the current drive circuit 66, and includes two series-connected N-channel MOS transistors 75a and 75b, one of which is connected to the second signal line 64 and the other of which is grounded. Similarly, the gate electrode of the transistor 75b is connected to the control signal line 72, but the gate electrode of the transistor 75b is grounded and is not always turned on.
[0097]
On the other hand, the reference current drive circuit 68 supplies a predetermined reference current (reference current) i to the second signal line 64._rThe N-channel transistors 69a and 69b are connected in series. The transistor 69a is connected to the second signal line 64, the gate electrode is connected to the control signal line 72, and the transistor 69b is grounded. The gate electrode is connected to a power supply having a predetermined H (high) potential, and is configured to always turn on the transistor 69b. On the other hand, the dummy circuit 76 includes N-channel MOS transistors 77a and 77b having the same configuration as that of the dummy circuit 74 except that the dummy circuit 76 is connected to the first signal line 62. Reference current i_rThe value of the current drive circuit 66 (66₀, 66₁, ..., 66_m) Can be passed through the current value i₀Can be appropriately determined according to the number of hit signals to be detected, but in order to detect the last hit signal, i₀Super 2i₀The difference current detection circuit 70 to be described later may be set to a current value that can detect the difference current. This current value i_rMay be determined in consideration of variations in circuit elements such as the transistors 67a, 67b, 69a, and 69b._r= 1.2i₀~ 1.8i₀Is preferable.
[0098]
The difference current detection circuit 70 detects the magnitude of the current flowing through the signal lines 62 and 64, and latches and holds the larger current side in the L (low) state and the smaller side in the H (high) state. P-channel MOS transistors (PMOS) 80a and 80b connected to the same potential as the power supply on the other end of both signal lines 62 and 64, for example, 5V power supply, N channel MOS transistors (NMOS) 82a and 82b connected in series and two precharge transistors 83 made of PMOS are included. The gate electrodes of the transistors 82a and 80a connected to the first signal line 62 are connected to each other and are connected at a contact point B between the transistors 80b and 82b. Further, the gate electrodes of the transistors 82b and 80b connected to the second signal line 64 are connected to each other and are connected at a contact A between the transistors 80a and 82a. An output line extends from the contact B and is connected to the output terminal 85 via the inverter 84.
[0099]
Next, the detection operation of the timing control circuit 60 will be described as a representative example of the action of detecting the last hit signal of the flag data in the flag register 18, that is, the last hit signal. Here, flag data having a plurality of hit signals ('1') is held in the flag register 18, and the reference current i_rIs the drive current i of one current drive circuit 66₀1.5 times that is 1.5i₀It is assumed that it is set to.
[0100]
First, prior to the detection, the precharge control signal line 72 is set to L (low: '0'), both the precharge transistors 78 and 79 are turned on, and the first and second signal lines 62 and 64, and hence the contact points. a and b are also precharged to the same H (high) potential (for example, 5 V), both precharge transistors 83 are turned on, and the contacts A and B in the differential current detection circuit 70 are similarly set to the H (high) potential. (For example, 5V) is precharged. Note that the transistors 82a and 82b of the differential current detection circuit 70, the transistors 67a of all the current drive circuits 66, and the transistor 68a of the reference current drive circuit 68 are off.
[0101]
Next, the precharge control signal line 72 is set to H (high: '1'), the PMOS transistors 78, 79, 83 are turned off, and the NMOS transistors 67a, 69a, 75a, 77a are turned on. Accordingly, the two transistors 69a and 69b of the reference current driving circuit 68 are both turned on, and the reference current i is supplied to the second signal line 64._r(= 1.5i₀) Flows to lower the potential of the contact b. On the other hand, m + 1 current driving circuits 66 (66₀, 66₁, ..., 66_m) Of the data latch circuit 18 in which the flag data of the flag register 18 is the hit signal ‘1’._jSince the transistor 67b having the gate electrode connected to is turned on and the transistor 67a is turned on, the current driving circuit 66_jIncludes a driving current i from the first signal line 62.₀Flows. By the way, the flag data of the flag register 18 includes a plurality of, for example, k (k ≧ 2) hit signals “1”, so that the first signal line 62 has ki.₀Current flows, and the potential of the contact a also decreases accordingly.
[0102]
Here, when k is larger than 2, the current ki flowing in the first signal line 62₀Is the reference current i flowing through the second signal line 64_r(= 1.5i₀) Is larger than the potential of the contact b, the potential of the contact a is lowered more quickly. Here, the difference between the gate potential of the NMOS 82a (the potential of the contact B) and the source potential (the potential of the contact a) becomes larger than the substrate biased threshold voltage (for example, 1.4V) of the NMOS 82a. When the voltage is 3.6 V or less, the NMOS 82a is turned on, and the potential of the contact A is lowered. On the other hand, at this time, the potential of the contact b is not lowered enough to turn on the NMOS 82a, and the off state is maintained as it is. Thereafter, further current flows through both signal lines 62 and 64, and the potentials of the contacts A and a further decrease. However, since the decrease in the potential of the contact A is larger than the decrease in the potential of the contact b, the NMOS 82b is turned off. keep. Thus, the contact A becomes ‘0’, but the contact B remains ‘1’, and the output of the inverter 84 remains ‘0’.
[0103]
Next, as the plurality of hit signals “1” in the flag register 18 are encoded, each of them is reset to “0” one by one, and when the number of remaining hit signals becomes one, the detection operation of the timing control circuit 60 In other words, when “0” is first input to the precharge control signal line 72 and then precharged and then “1” is input, the first signal line 62 is connected to the first signal line 62 in the same manner as described above. Current i₀However, the second signal line 64 has a reference current i._r(= 1.5i₀) Will flow. At this time, since the current flowing through the second signal line 64 is larger, the potential at the contact b drops earlier than the potential at the contact a. It becomes. Accordingly, the potential of the contact B is lowered and inverted by the inverter 84, and “1” is output from the output terminal 85. Note that precharging both the signal lines 62 and 64 to the power supply potential (5 V) in advance is extremely important for the stable operation of the differential current detection circuit 70. That is, by precharging up to 5V and creating a timing margin until any one of the signal lines 62 and 64 drops to 3.6V which is the operating potential of the difference current detection circuit 70, a latch-type difference current is generated. This is because a margin is given to the operation timing of the detection circuit, and the influence of control line switching noise and the like can be eliminated.
[0104]
From the above, if the output signal output from the output terminal 85 of the timing control circuit 60 is “0”, two or more hit signals “1” are held in the flag register 18 and the output signal is “1”. If there is, it can be seen that the number of hit signals is one or less. Therefore, when the output signal changes from “0” to “1”, the flag data in the flag register 18 can be switched to the flag data in the prefetch circuit 16 by using this detection result, for example, a “1” signal or a change in signal. That's fine. Of course, the output signal may be taken out from the contact A here.
[0105]
FIG. 11 shows a time chart of encoding timing using the timing control circuit 60 of the illustrated example.
FIG. 4A shows the encoding timing of the main encoder 12. (B) shows the reset timing of the hit signal ‘1’ of the flag register 18. (C) shows the detection timing of the timing control circuit 60. (D) shows the change of the output signal of the timing control circuit 60, and (e) shows the timing of shifting the flag data of the prefetch circuit 16 to the flag register 18.
[0106]
In this way, while the hit signal in the same flag data held in the flag register 18 is encoded with a predetermined priority, the encoding cycle is started at a predetermined time from the rising timing of the reset pulse of the hit signal. It is configured to stand up. However, when the timing control circuit 60 detects the last hit signal at the detection timing activated by the encode pulse and the output signal (d) changes from “0” to “1”, the reset pulse is originally generated. A pulse for replacing the flag data of the prefetch circuit 16 into the flag register 18 is generated by the pulse circuit 87 shown in FIG. 10, and the flag data of the flag register 18 is switched. Then, in successive encoding cycles, the flag circuit is used to perform an encoding operation by the priority circuit 20 and the encoding circuit 22, and an encode address is output. In this way, the main encoder performs an encode operation in a predetermined continuous cycle and outputs an encode. The main encoder 12 is basically configured as described above.
[0107]
As described above in detail, in the coding circuit of the illustrated example, in addition to the effect of the coding circuit of FIG. 1, the coding circuit with priority order has finished coding the hit signal by the data switching timing control circuit. The encoding of the flag signal data of the next priority sub-block which has been input to the prefetch circuit immediately before in a continuous cycle can be started, encoded, and a word address can be output.
[0108]
Therefore, according to the encoding circuit of the illustrated example, even in an associative memory block composed of a plurality of associative memory sub-blocks, there is no time delay (waiting time) in switching between the plurality of associative memory sub-blocks, and there are many The output signal from the associative memory sub-block can be efficiently encoded in successive cycles. As a result, the present invention can also be applied to a large-capacity associative memory device including an associative memory block composed of a plurality of associative memory sub-blocks that require high-speed processing for large-capacity data.
In addition, according to the semiconductor integrated circuit which is the premise of the present invention, it is possible to accurately and quickly detect that the number of data “0” or “1” input to the current driving means has become a preset number. Can do.
[0109]
  Next, with reference to FIGS. 12 to 14, another semiconductor integrated circuit which is a premise for understanding the encoding circuit applied to the associative memory device of the present invention will be described in detail. This semiconductor integrated circuit is applicable to the encoding circuit shown in FIG. 8 as a number detection circuit for timing control.
[0110]
In the semiconductor integrated circuit of the illustrated example, first, data input to data input lines for controlling M (M ≧ 1) current driving means provided in parallel with the first signal line, that is, the signal current detection line, respectively. Number of data to be detected out of '1' or '0' k₀(M> k₀Reference current (reference current) value i to be supplied to the reference current drive means provided in the reference current drive line as the second signal line in response to ≧ 0)_rThat is, the current value i flowing through one current driving means₀K₀Greater than double k₀Current value smaller than +1 times (k₀i₀<I_r<(K₀+1) i₀) Is set in advance. Here, each current driving means of this semiconductor integrated circuit has a signal voltage application transistor having a data input line connected to its gate electrode, and a control transistor for controlling the operation timing of this semiconductor integrated circuit. The application transistor is provided on the signal current detection line side.
[0111]
For this reason, in the semiconductor integrated circuit of the illustrated example, the control transistor of the all current driving means and the control transistor of the reference current driving means are controlled according to the operation timing, and when these are turned on, the required data is input to the data input line. Since the signal voltage application transistors of all the current driving means are turned on, each of these current driving means has a current i₀Current i (i = ki) corresponding to the number k (M> k ≧ 0).₀) Flows in the signal current detection line, while the reference current drive line has a reference current value i by the reference current drive means._rFlows. The current values i and i flowing in both signal lines_rIs detected by the difference current detecting means, and the sign of the difference current is reversed, that is, both current values i and i_rOutputs the reversal (timing) of the magnitude relationship with. In this way, the number k of required data among the data input to each data input line is preset, and the number k of data to be detected is preset.₀It detects that it became. Thus, the semiconductor integrated circuit of the illustrated example can detect the number of required data input to the data input line.
[0112]
At this time, if the control transistor of the current driving means is provided on the current signal detection line side from the signal voltage application transistor, even if the data input to the data input line is not the required data, the signal voltage application transistor remains off. However, when this semiconductor integrated circuit is at the operation timing and the control transistor of the all current driving means is turned on, a temporary current flows from the signal current detection line to the control transistor. A current also flows through the signal current detection line. For this reason, the difference current between the current flowing in the detection line and the reference current flowing in the reference current drive line at the time of reversal that requires detection becomes small, and it is difficult to quickly detect the reversal of the difference current by the difference current detection means. Yes, it is easily affected by noise or the like, and stable and accurate detection may not be performed quickly.
[0113]
In contrast, in the semiconductor integrated circuit of the illustrated example, since the signal voltage application transistor is provided on the signal current detection line side of the control transistor, even if the control transistor of all current driving means is turned on, the signal voltage The current from the signal current detection line does not flow unless the application transistor is turned on. Therefore, when the voltage application transistor is turned on, the difference current between the current flowing through the signal current detection line and the reference current can be made relatively large even during reverse rotation that requires detection. As a result, the detection of the reversal of the difference current by the difference current detection means can be performed stably and accurately and quickly.
[0114]
FIG. 12 shows a specific circuit diagram of another embodiment of the timing control circuit 61 to which the semiconductor integrated circuit as the premise of the present invention is applied. Here, the timing control circuit 61 shown in the figure is applied to the encoding circuit 11 shown in FIG. 8, and controls the timing control circuit 60 shown in FIG. 10 and the signal application transistor 67c of the current drive circuit 66. Since the transistors 67d and the transistors 69c and 69d of the reference current drive circuit 68 are exactly the same except for the differences, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0115]
In the timing control circuit 61 shown in FIG. 12, the current drive circuit 66, which is the most characteristic part, will be described as one representative example. A signal voltage application composed of two N-channel MOS transistors connected in series is described. The signal voltage application transistor 67c is connected to the first signal line 62, the control transistor 67d is grounded, and the gate electrode of the signal voltage application transistor 67c is a data latch circuit corresponding to each of the flag registers 18. The gate electrode of the control transistor 67 d is connected to the control signal line 72.
[0116]
In the current driving circuit 66, the control transistor 67d is turned on at the time of detection, and the signal voltage application transistor 67c is turned on when the hit signal “1” is input from the flag register 18 to the gate electrode of the signal voltage application transistor 67c. , A predetermined current i from the first signal line 62₀Is configured to flow. This drive current i₀Are all current drive circuits 66₀, 66₁, ..., 66_mHowever, there are variations in the transistors 67c and 67d used, such as variations due to process variations. The dummy circuit 74 has the same configuration as that of the current drive circuit 66, and includes two series-connected N-channel MOS transistors 75c and 75d, one of which is connected to the second signal line 64 and the other of which is grounded. Similarly, the gate electrode of the transistor 75d is connected to the control signal line 72, but the gate electrode of the transistor 75c on the second signal line 64 side is grounded and is not always turned on.
[0117]
On the other hand, the reference current drive circuit 68 applies a predetermined reference current (reference current) i to the second signal line._rThe N-channel transistors 69c and 69d are connected in series. The transistor 69c is connected to the second signal line, and the gate electrode thereof is set to a predetermined H (high) so that the transistor 69c is always turned on. The transistor 69 d is connected to a potential power source, and its gate electrode is connected to the control signal line 72. The dummy circuit 76 of the reference current driving circuit 68 is connected to the first signal line 62. Reference current i_rThe value of the current drive circuit 66 (66₀, 66₁, ..., 66_m) Can be passed through the current value i₀Can be appropriately determined according to the number of hit signals to be detected, but in order to detect the last hit signal, i₀Super 2i₀The difference current detection circuit 70 to be described later may be set to a current value that can detect the difference current. This current value i_rMay be determined in consideration of variations in circuit elements such as the transistors 67c, 67d, 69c, and 69d._r= 1.2i₀~ 1.8i₀Is preferable.
[0118]
An output line extends from the contact B of the differential current detection circuit 70 and is connected to the AND circuit 88 through the inverter 84. The other input of the AND circuit 88 receives the reset signal of the flag register 18 described above. The output of the AND circuit 88 is connected to the clock terminal of the flag register 18 described above.
[0119]
Next, the detection operation of the timing control circuit 61 in the illustrated example will be described by taking the action of detecting the last hit signal of the flag data of the flag register 18, that is, the action of detecting the last hit signal as a representative example. To do. Here, flag data having a plurality of hit signals ('1') is held in the flag register 18, and the reference current i_rIs the drive current i of one current drive circuit 66₀1.5 times that is 1.5i₀It is assumed that it is set to.
[0120]
First, prior to the detection, the precharge control signal line 72 is set to L (low: '0'), both the precharge transistors 78 and 79 are turned on, and the first and second signal lines 62 and 64, and hence the contact points. (Nodes) a and b are also precharged to the same H (high) potential (for example, 5 V), both precharge transistors 83 are turned on, and the contacts A and B in the differential current detection circuit 70 are similarly set to H ( High) Precharged to a potential (for example, 5 V). Note that the transistors 82a and 82b of the difference current detection circuit 70, the transistors 67d of all the current drive circuits 66, and the transistor 69d of the reference current drive circuit 68 are off.
[0121]
Next, the precharge control signal line 72 is set to H (high: '1'), the PMOS transistors 78, 79, 83 are turned off, and the NMOS transistors 67d, 69d, 75d, 77d are turned on. Accordingly, the two transistors 69c and 69d of the reference current driving circuit 68 are both turned on, and the second signal line 64 has a reference current i._r(= 1.5i₀) Flows to lower the potential of the contact b. On the other hand, (m + 1) current drive circuits 66 (66₀, 66₁, ..., 66_m) Of the data latch circuit 18 in which the flag data of the flag register 18 is the hit signal ‘1’._jSince the signal voltage application transistor 67c having the gate electrode connected to is turned on and the control transistor 67d is turned on, the current drive circuit 66_jIncludes a driving current i from the first signal line 62.₀Flows. By the way, the flag data of the flag register 18 includes a plurality of, for example, k (k ≧ 2) hit signals “1”, so that the first signal line 62 has ki.₀Current flows, and the potential of the contact a also decreases accordingly.
[0122]
Here, when k is larger than 2, the current ki flowing in the first signal line 62₀Is the reference current i flowing through the second signal line 64_r(= 1.5i₀) Is larger than the potential of the contact b, the potential of the contact a is lowered more quickly. Here, when the difference between the gate potential of the NMOS 82a (the potential of the contact B) and the source potential (the potential of the contact a) is larger than the substrate biased threshold voltage (eg, 1.4V) of the NMOS 82a (for example, the contact). When the potential of the contact a drops to 3.6 V when the potential of B is 5 V), the NMOS 82a is turned on, and the potential of the contact A is lowered. On the other hand, at this time, the potential of the contact b is not lowered enough to turn on the NMOS 82b, and the off state is maintained as it is. Thereafter, a further current flows through both signal lines 62 and 64, and the potentials of the contacts A and a further decrease. However, the decrease in the potential of the contact a, that is, the decrease in the potential of the contact A is lower than the potential decrease of the contact b. Since it is large, the NMOS 82b is kept off. In this way, the contact B maintains “1”, and “0” is output to the AND circuit 88 by the inverter 84 connected thereto. On the other hand, the contact A is “0”.
[0123]
Next, as the plurality of hit signals “1” in the flag register 18 are encoded, each of them is reset to “0” one by one, and when the number of remaining hit signals becomes one, the timing control circuit 61 of the illustrated example. In other words, when “0” is first input to the precharge control signal line 72 to perform precharge and then “1” is input, the first signal line is the same as described above. 62 has a current i₀However, the second signal line 64 has a reference current i._r(= 1.5i₀) Will flow. At this time, since the current flowing through the second signal line 64 is larger, the potential at the contact b drops earlier than the potential at the contact a. It becomes. Accordingly, the potential of the contact B is lowered to the low level, inverted by the inverter 84, and "1" is output to the AND circuit 88 described above. The potential of the contact A is maintained at the H (high) potential.
[0124]
From the above, if the output signal output from the inverter 84 of the timing control circuit 61 in the illustrated example is “0”, there are two or more hit signals “1” held in the flag register 18, and this output signal is “ If it is 1 ', it turns out that the hit signal is one or less. Accordingly, when this output signal changes from “0” to “1”, the AND circuit 88 obtains the switching control signal from the detection result, that is, the “1” signal and the reset signal of the flag register 18 described above. The flag data in the flag register 18 may be switched to the flag data in the prefetch circuit 16 using a signal. Of course, the output signal here may be taken out from only the contact A or from both the contacts A and B.
[0125]
Here, as described above, the timing control circuit 60 shown in FIG. 10 includes the timing circuit 61 shown in FIG. 12 and the current drive circuit 66 (66₀, 66₁, ..., 66_m) Of the control transistor 67a and the signal voltage applying transistor 67b and the dummy circuit 74 (74).₀74₁, ..., 74_mThe data latch circuit of the flag register 18 is exactly the same except that the arrangement of the control transistor 75a and the grounded gate transistor 75b in FIG. It is possible to detect that the number of hit signals '1' held by a predetermined number is, for example, the last one.
[0126]
In both the timing control circuits 60 and 61, when the timing detection operation is started as described above, the signal current detection line (first signal line) 62 has a hit signal ('1') of the flag register 18. A current corresponding to the number of currents flows, and a predetermined reference current flows through the reference current drive line (second signal line) 64. Therefore, the difference current detection circuit 70 has a small potential difference between the contacts a and b caused by the difference between the currents flowing through the signal lines 62 and 64, and one (the high potential side of the contacts a and b) is a precharge voltage (for example, Vdd). And the other (low potential side) is detected as a large potential difference between the contacts A and B which decreases to the ground level (for example, approximately OV).
[0127]
Here, the subsequent change in the potentials of the contacts A and B, which are precharged to the same potential (for example, Vdd = 5V) first, is determined by which of the transistors 82a and 82b is turned on. That is, as described above, during the timing detection operation, a current flows through the first and second signal lines 62 and 64, the potentials of the contacts a and b of both signal lines 62 and 64 are lowered, and the contact B and When either the potential difference of the contact a or the potential difference between the contact A and the contact b becomes larger than the substrate biased threshold value (for example, 1.4 V), that is, the potentials of both the signal lines 62 and 64 (the contact points of the contact points a and b). When any of the potentials exceeds the threshold value (for example, 1.4V) and drops (below 3.6V), one of the transistors 82a and 82b is turned on. As a result, one of the contacts A or B on the transistor 82a or 82b side that is turned on immediately becomes equal to the potential of the lowered contact a or b, respectively, and then drops together to the ground level (OV). On the other hand, each contact A or B on the side of the transistor 82a or 82b that has not been turned on is kept at the precharged potential (5V).
[0128]
Thus, by detecting the potential of the contact B as a detection signal and taking it out as an output signal via the inverter 84, it is possible to detect that a predetermined number (for example, the last one) of hit signals has been obtained. That is, since the inverter 84 is connected to the tip of the contact B, the transistor 82b is turned on, and when the potential of the contact B decreases and falls below the threshold value of the inverter 84 (for example, about 2.5V). The output signal “1” is obtained.
[0129]
As can be seen from the above, in the above-described differential current detection circuit 70, if the potential difference between the contacts a and b when the contacts A and B start to separate is too small, the on-operation of the transistors 82a and 82b causes the potential difference between the contacts a and b. The possibility of malfunction occurring, that is, malfunction is increased. Therefore, the larger the potential difference between the two contacts a and b, the less susceptible to noise, and always accurate and stable timing detection can be performed.
[0130]
However, in the timing control circuit 60 shown in FIG. 10, the control transistor 67a of the current drive circuit 66 is connected to the first signal line 62 which is a signal current detection line, and the signal voltage application transistor 67b connected in series to the control transistor 67a. The other electrode of the dummy circuit 74 is grounded, the control transistor 75a of the dummy circuit 74 is connected to the second signal line which is a reference current drive line, and the other electrode of the gate grounded transistor 75b connected in series to the control transistor 75a is grounded. Is done. Therefore, when the precharge control signal line 72 is changed from the low (L: “0”) level of the precharge operation to the high (H: “1”) level of the timing detection operation, each data latch circuit of the flag register 18 is changed. 18_jRegardless of the retained data of (j = 0,..., M), the control transistor 67a of the current drive circuit 66 is turned on, and a temporary charge flows between the control transistor 67a and the signal voltage application transistor 67b. Similarly, the control transistor 75a of the dummy circuit 74 is turned on, and a temporary charge flows between the control transistor 75a and the grounded gate transistor 75b.
[0131]
As a result, as shown in FIG. 14B, current flows from the first and second signal lines 62 and 64 to the control transistors 67a and 75a of the current drive circuit 66 and the dummy circuit 74 at the beginning of the timing detection operation. The potentials of the contacts a and b of the signal lines 62 and 64 are simultaneously reduced. In particular, if the number of data latch circuits in the flag register 18 is large and the corresponding number of current driving circuits 66 and dummy circuits 74 are large, the currents flowing in the first and second signal lines 62 and 64 at the initial stage of detection increase. The potentials of the contacts a and b are greatly reduced at the same time. For this reason, the difference between the potentials of the contacts a and b due to the turning on of the signal voltage applying transistor 67b is delayed, and the potentials of both of them are lowered. That is, when either of the potentials of the signal lines 62 and 64 (the potentials of the contacts a and b) drops below a predetermined value (for example, 3.6 V), the contact when turning on one of the transistors 82a and 82b. The potential difference between a and b becomes small.
[0132]
On the other hand, in the timing control circuit 61 of FIG. 12, the signal voltage application transistor 67c of the current drive circuit 66 is provided on the first signal line 62 side, and the control transistor 67d is provided on the ground side. 75c is provided on the second signal line side, and the control transistor 75d is provided on the ground side. Therefore, even if the timing detection operation is started, all the control transistors 67d of the current drive circuit 66 in which the signal voltage application transistor 67c is not turned on are not turned on, and all the control transistors 75d of the dummy circuit 74 are not turned on. The current for charging the control transistors 67d and 75d does not flow through the signal lines 62 and 64. As a result, only the signal voltage application transistors 67c and the control transistors 67d of all the current drive circuits 66 corresponding to the data latch circuits of the flag register 18 in which the hit signal “1” is held are turned on, and the current corresponding to the number thereof Only flows to the first signal line 62, only the transistors 69c and 69d of the reference current drive circuit 68 are turned on to the second signal line, and only the reference current flows to the second signal line. Therefore, as shown in FIG. 14 (a), the potential difference between the contacts a and b occurs immediately after the detection operation, that is, from the time when the potentials of both the contacts a and b slightly decrease. The potential difference between the two contacts when the power cuts a predetermined value (for example, 3.6 V) can be made large.
[0133]
As described above, in the timing control circuits 60 and 61 shown in FIGS. 10 and 12, the potential difference between the contacts a and b when either one of the contacts a or b cuts a predetermined value (for example, 3.6 V) is different. For example, the examples shown in FIGS. 14A and 14B (examples of the timing control circuits 61 and 60 shown in FIGS. 12 and 10 respectively) will be described. When b is less than 3.6V, the potential difference between the contacts a and b is about 0.3V in FIG. 14 (a), whereas it is about 0.1V in FIG. 14 (b). is there. Therefore, the timing control circuit 61 shown in FIG. 14A has a larger noise margin, and as a result, even if it is affected by noise, the possibility that the differential current detection circuit 70 malfunctions is small and always accurate and stable. Timing detection can be performed.
[0134]
Further, in FIGS. 14A and 14B, the potential difference between the two contacts at the time when the contacts a and b cut 3.6 V is increased by precharging both signal lines 62 and 64 in advance. . However, if the signal lines 62 and 64 are operated without being precharged, there is no potential difference between the contacts a and b, and normal operation cannot be expected. Therefore, in both cases (a) and (b) of the figure, it is significant to operate after being precharged.
[0135]
14 (a) and 14 (b) show the power supply voltage (V) in the timing control circuits 61 and 60 shown in FIGS. 12 and 10, respectively._dd) Is 5V, the number (m + 1) of current driving circuits 66 and dummy circuits 74 is 256, and the reference current i_r1.5i₀At this time, the detection timing (change in the voltage of the precharge control signal line 72), the detection timing when the last hit signal '1' held in the flag register 18 is one, the contacts a, b, and the contact A , B and the output signal (out put) of the inverter 84 are shown.
The timing control circuit 61 is basically configured as described above.
[0136]
A time chart of the encoding timing of the main encoder 12 of the encoding circuit 11 shown in FIG. 8 using the timing control circuit 61 is shown in FIG.
[0137]
In the figure, (a) represents an encode signal indicating the encode timing of the main encoder 12. (B) represents a reset pulse indicating the reset timing of the hit signal ‘1’ of the flag register 18. (C) represents a detection operation signal (voltage applied to the precharge control signal line 72) indicating the detection operation timing of the timing control circuit 61 of FIG. (D) represents a detection output signal indicating a change in potential of the contact B of the timing control circuit 61, (e) represents an output signal obtained by inverting the detection output signal of (d) by the inverter 84, and (f) represents A flag data switching control signal indicating timing for shifting the flag data of the prefetch circuit 16 to the flag register 18 is represented.
[0138]
As described above, while the hit signal in the same flag data held in the flag register 18 is encoded with a predetermined priority, that is, if the detection output signal (d) is at a high level (H), the hit signal is hit. The encoding cycle is started (rises) at a predetermined time from the rising timing of the signal reset pulse (b). However, the timing control circuit 61 in the illustrated example detects the last hit signal at the detection timing activated by the encode pulse (a), and the detection output signal (d) changes from the high level (H) '1' to the low level (L ) When it changes to “0”, its inverted output signal (e) changes from “0” to “1”. Here, the AND circuit 88 shown in FIG. 12 calculates the logical product of the inverted output signal (e) of the detection output signal (d) and the reset pulse (b), and replaces the flag data of the prefetch circuit 16 with the flag register 18. The switching control pulse (f) is generated. Thus, the flag data of the flag register 18 is switched by the switching control pulse (f).
[0139]
As described in detail above, according to the semiconductor integrated circuit of the illustrated example, the signal voltage application transistor of the current driving means is provided on the signal current detection line side, and the control transistor is provided on the ground side. Since the control transistor is not turned on unless the voltage application transistor is turned on, there is no outflow of charge for charging all the control transistors from the signal current detection line, and detection of the difference current detection means and malfunction do not occur. Therefore, the difference current between the reference current drive line and the signal current detection line can be stably and accurately detected quickly, and is suitable as a timing control circuit for predicting the end of encoding of an encoding circuit such as an associative memory. Can be used.
[0140]
  Next, with reference to FIGS. 15 to 17, another semiconductor integrated circuit which is a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention will be described in detail. The semiconductor integrated circuit of the illustrated example can be applied to the encoding circuit shown in FIG. 8 as a number control circuit for timing control, similarly to the semiconductor integrated circuit shown in FIGS.
[0141]
In the semiconductor integrated circuit of the illustrated example, first, data input to data input lines for controlling M (M ≧ 1) current driving means provided in parallel with the first signal line, that is, the signal current detection line, respectively. Number of data to be detected out of '1' or '0' k₀(M> k₀Reference current (reference current) value i to be supplied to the reference current drive means provided in the reference current drive line as the second signal line in response to ≧ 0)_rThat is, the current value i flowing through one current driving means₀K₀Greater than double k₀Current value smaller than +1 times (k₀i₀<I_r<(K₀+1) i₀) Is set in advance. Here, each current driving means of this semiconductor integrated circuit has a signal voltage application transistor having a data input line connected to its gate electrode, and a control transistor for controlling the operation timing of this semiconductor integrated circuit.
[0142]
For this reason, in the semiconductor integrated circuit of the illustrated example, when all the current driving means in which required data is input to the reference current driving means and the data input line are turned on according to the operation timing, the reference current driving line has a reference current. Reference current value i by the driving means_rFlows. On the other hand, each current driving means has a current i.₀As a result, the current i corresponding to the number k (M> k ≧ 0) is applied to the signal current detection line (i = ki).₀) Flows. The current values i and i flowing in both signal lines_rIs detected by the difference current detection means, and the sign of the difference current is reversed, that is, both current values i and i_rOutputs the reversal (timing) of the magnitude relationship with. In this way, the number k of required data among the data input to each data input line is preset, and the number k of data to be detected is preset.₀It detects that it became. Thus, the semiconductor integrated circuit of the illustrated example can detect the number of required data input to the data input line.
[0143]
At this time, both signal lines of the reference current drive line (reference current line) and the signal current detection line (detection line) have a predetermined voltage level (V₀) Is set. Therefore, the reference current i flowing through the reference current line_rAnd the total signal current i (ki₀The difference between the voltage levels of both signal lines (voltage difference) caused by the current difference from the signal line) at the start of the detection operation, that is, the constant voltage level (V₀), When a predetermined time has elapsed after the start of the detection operation, that is, the set voltage level (V₀) At a predetermined voltage drop or increased voltage level. This is because the difference between the accumulated currents that flowed becomes larger. Therefore, the detection start voltage level of the difference current detection means (circuit) is set to the set voltage level (V₀This setting level (V₀), It is possible to accurately and stably detect the current difference between the two signal lines, that is, the voltage difference, by setting the voltage level to a predetermined voltage drop or increased voltage level that is relatively different. The result is less susceptible to noise and other disturbances.
[0144]
By the way, in the semiconductor integrated circuit of the illustrated example, the differential current detection means has the detection start level setting means, so that the detection start voltage level is the same for both the signal current detection line and the reference current line. Can be set to a voltage level having a large difference (separated from a predetermined voltage level) from a preset voltage level (for example, a precharge voltage level). The difference can be made relatively large. Therefore, detection of the difference current between the current flowing through the signal current detection line and the reference current is most important, and the voltage difference between the two signal lines is relatively large even when the difference current is reversed so that the difference current between the two signal lines becomes the smallest. be able to. As a result, the detection of the difference current by the difference current detection means and the detection of the reverse timing (timing) can be stably and accurately performed.
[0145]
FIG. 15 shows a specific circuit diagram of still another embodiment of the timing control circuit 90 to which the semiconductor integrated circuit as the premise of the present invention is applied. Here, the timing control circuit 90 shown in the figure is applied to the encoding circuit 11 shown in FIG. 8, and includes a timing control circuit 60 shown in FIG. 10 and a transistor 86 serving as detection circuit level setting means. A precharge transistor 78 for precharging the contacts a and b on one end side of the signal lines 62 and 64 and a transistor 79 for setting the signal lines 62 and 64 to the same potential on the other end side are provided. The number of hit signals '1' held by the data latch circuit of the flag register 18 input to the gate electrode of the signal voltage application transistor 67b is exactly the same, except for Since it can be detected that the number is one, the same number is assigned to the same component, and the detailed description thereof is omitted.
[0146]
In the timing control circuit 90 shown in FIG. 15, the difference current detection circuit 70, which is the most characteristic part, is connected to the same predetermined potential as the power supply on the other end side of both signal lines 62 and 64, for example, a 5 V power supply. A P-channel MOS transistor (PMOS) 86, 80a and 80b connected to the PMOS transistor 86, N-channel MOS transistors (NMOS) 82a and 82b connected in series to the PMOS transistor 86, and two precharges comprising PMOS A transistor 83 is provided. Here, the PMOS transistor 86 connected to the power supply constitutes a detection start level setting means, and its source electrode is connected to the power supply, and its gate electrode is connected to its own drain electrode. The gate electrodes of the transistors 82a and 80a connected to the first signal line are connected to each other and are connected at a contact point B between the transistors 80b and 82b. Further, the gate electrodes of the transistors 82b and 80b connected to the second signal line are connected to each other and are connected at a contact A between the transistors 80a and 82a. An output line extends from the contact B and is connected to the AND circuit 88 via the inverter 84. The other input of the AND circuit 88 receives the reset signal of the flag register 18 described above. The output of the AND circuit 88 is connected to the clock terminal of the flag register 18 described above.
[0147]
Here, the power supply voltage V to which the source electrode of the PMOS transistor 86 is connected._ddIs a predetermined potential, for example, 5V, and the threshold voltage V_THIs a predetermined voltage, for example, about 0.7 V, the PMOS transistor 86 has a gate voltage obtained by subtracting a threshold voltage from the power supply voltage (V_dd-V_THFor example, it is turned on while lower than 5-0.7 = 4.3 V), but it is turned off when higher than this. Therefore, the voltage of the drain electrode connected to the gate electrode is the power supply voltage minus the threshold voltage (V_dd-V_THFor example, 4.3V). That is, the PMOS transistor 86 sets the precharge voltage at the contacts A and B when precharging through the precharge transistor 83 to the above-described V_dd-V_THAnd supply voltage V_ddFunctions as a means to lower As will be described in detail later, since the precharge potential at the contacts A and B is lowered, the precharged gate voltage of the transistors 82a and 82b is lowered, and one of the transistors 82a and 82b is turned on during the timing detection operation. The potential of the contacts a and b at the time, that is, the detection start voltage level is lowered. That is, the PMOS transistor 86 functions as detection start level setting means.
[0148]
Next, the detection operation of the timing control circuit 90 in the illustrated example will be described with reference to a representative example of the action when the last hit signal of the flag data in the flag register 18 is detected, that is, the last hit signal. To do. Here, the power supply potential used for precharging is the same, for example, 5 V, and flag data having a plurality of hit signals ('1') is held in the flag register 18, and the reference current i_rIs the drive current i of one current drive circuit 66₀1.5 times that is 1.5i₀It is assumed that it is set to.
[0149]
First, prior to detection, the precharge control signal line 72 is set to L (low: '0'), the precharge transistors 78 and 79 at both ends of both signal lines 62 and 64 are turned on, and the first and second signals are turned on. The lines 62 and 64, and hence the contacts a and b, are also precharged to the same predetermined potential, for example, a power supply potential (for example, 5V), and both precharge transistors 83 of the difference current detection circuit 70 are turned on to detect the difference current. The contacts A and B in the circuit 70 are precharged to a precharge voltage, that is, a predetermined H (high) potential (for example, 4.3 V). Note that the transistors 82a and 82b of the differential current detection circuit 70, the transistors 67a of all the current drive circuits 66, and the transistor 68a of the reference current drive circuit 68 are off. Here, in the state where the transistor 86 connected to the power source is first turned off, the drain potential is set to the power source potential-threshold potential (V_dd-V_TH, For example, 4.3 V), but as a result of the precharge transistor 83 being turned on, the drain potential V of the transistor 86 is_dd-V_THWhen it is further lowered, the transistor 86 is turned on to precharge the contacts A and B. In this way, the potential of the contacts A and B, that is, the gate potential (drain potential) of the transistor 86 becomes the precharge voltage, that is, V_dd-V_THThe transistor 86 is turned on until reaching (for example, 4.3 V), and the precharge of the contacts A and B is continued. After reaching the precharge voltage, the transistor 86 is turned off.
[0150]
Next, the precharge control signal line 72 is set to H (high: '1'), the PMOS transistors 78, 79, 83 are turned off, and the NMOS transistors 67a, 69a, 75a, 77a are turned on. Accordingly, the two transistors 69a and 69b of the reference current driving circuit 68 are both turned on, and the reference current i is supplied to the second signal line 64._r(= 1.5i₀) Flows to lower the potential of the contact b. On the other hand, (m + 1) current drive circuits 66 (66₀, 66₁, ..., 66_m) Of the data latch circuit 18 in which the flag data of the flag register 18 is the hit signal ‘1’._jSince the transistor 67b having the gate electrode connected to is turned on and the transistor 67a is turned on, the current driving circuit 66_jIncludes a driving current i from the first signal line 62.₀Flows. By the way, the flag data of the flag register 18 includes a plurality of, for example, k (k ≧ 2) hit signals “1”, so that the first signal line 62 has ki.₀Current flows, and the potential of the contact a also decreases accordingly.
[0151]
Here, when k is larger than 2, the current ki flowing in the first signal line 62₀Is the reference current i flowing through the second signal line 64_r(= 1.5i₀) Is larger than the potential of the contact b, the potential of the contact a is lowered more quickly. Here, the difference (gate-source voltage) between the gate potential of the NMOS 82a (the potential at the contact point B) and the source potential (the potential at the contact point a) is larger than the substrate biased threshold voltage (for example, 1.4 V) of the NMOS 82a. That is, that is, the potential of the contact a is the detection start voltage V_ONWhen the voltage drops beyond (the voltage obtained by subtracting the above threshold voltage from the precharge voltage) (for example, when the potential at the contact B drops to 2.9 V when the potential at the contact B is 4.3 V), the NMOS 82a is turned on. As a result, the potential of the contact A decreases. On the other hand, at this time, the potential of the contact b is not lowered enough to turn on the NMOS 82b, and the off state is maintained as it is. Thereafter, a further current flows through both signal lines 62 and 64, and the potentials of the contacts A and a further decrease. However, the potential of the contact a decreases, that is, the potential of the contact A decreases. Since it is larger, the NMOS 82b remains off. In this way, the contact B maintains “1”, and “0” is output to the AND circuit 88 by the inverter 84 connected thereto. On the other hand, the contact A is “0”.
[0152]
Next, as the plurality of hit signals “1” in the flag register 18 are encoded, each of them is reset to “0” one by one, and when the remaining hit signals become one, the timing control circuit 90 in the illustrated example is shown. In other words, when “0” is first input to the precharge control signal line 72 to perform precharge and then “1” is input, the first signal line is the same as described above. 62 has a current i₀However, the second signal line 64 has a reference current i._r(= 1.5i₀) Will flow. At this time, since the current flowing through the second signal line 64 is larger, the potential at the contact b drops earlier than the potential at the contact a. It becomes. Accordingly, the potential of the contact B is lowered to the low level, inverted by the inverter 84, and "1" is output to the AND circuit 88 described above. On the other hand, the potential of the contact A is maintained at the H (high) potential.
[0153]
From the above, if the output signal output from the inverter 84 of the timing control circuit 90 in the illustrated example is “0”, two or more hit signals “1” are held in the flag register 18 and the output signal is “1”. If it is', it turns out that the hit signal is 1 or less. Therefore, when this output signal changes from “0” to “1”, the AND circuit 88 obtains a switching control signal from the detection result, that is, the “1” signal and the reset signal of the flag register, and this switching control. The flag data in the flag register 18 may be switched to the flag data in the prefetch circuit 16 using a signal. Of course, the output signal here may be taken out from only the contact A or from both the contacts A and B.
[0154]
By the way, in the timing control circuit 90 in the illustrated example, when the timing detection operation is started as described above, the hit signal ('1') of the flag register 18 is applied to the signal current detection line (first signal line) 62. A current corresponding to the number of currents flows, and a predetermined reference current flows through the reference current drive line (second signal line) 64. Therefore, the difference current detection circuit 70 has a small potential difference between the contacts a and b caused by the difference between the currents flowing through the signal lines 62 and 64, and one (the high potential side of the contacts a and b) is a precharge voltage (for example, Vdd). And the other (low potential side) is detected as a large potential difference between the contacts A and B which decreases to the ground level (for example, approximately 0 V).
[0155]
Here, the subsequent change in the potentials of the contacts A and B that were initially precharged to the same precharge potential (for example, 4.3 V) is determined by which of the transistors 82a and 82b is turned on. That is, as described above, during the timing detection operation, a current flows through the first and second signal lines 62 and 64, the potentials of the contacts a and b of both signal lines 62 and 64 are lowered, and the contact B and When either the potential difference of the contact a or the potential difference between the contact A and the contact b becomes larger than the substrate biased threshold value (for example, 1.4 V), that is, the potentials of both the signal lines 62 and 64 (the contact points of the contact points a and b). Any of the potentials) is a detection start voltage (a potential obtained by subtracting the aforementioned threshold voltage from the precharge potential) V_ONWhen the voltage exceeds (for example, 2.9 V), one of the transistors 82a and 82b is turned on. As a result, one of the contacts A or B on the side of the transistor 82a or 82b that is turned on immediately becomes equal to the potential of the contact a or b that has dropped, and then drops together to the ground level (0 V). On the other hand, each contact A or B on the side of the transistor 82a or 82b that is not turned on is kept at the precharge potential (4.3 V).
[0156]
Thus, by detecting the potential of the contact B as a detection signal and taking it out as an output signal via the inverter 84, it is possible to detect that a predetermined number (for example, the last one) of hit signals has been obtained. That is, since the inverter 84 is connected to the tip of the contact B, the transistor 82b is turned on, and when the potential of the contact B decreases and falls below the threshold value of the inverter 84 (for example, about 2.5V). The output signal “1” is obtained.
[0157]
As can be seen from the above, in the above-described differential current detection circuit 70, if the potential difference between the contacts a and b when the contacts A and B start to separate is too small, the on-operation of the transistors 82a and 82b causes the potential difference between the contacts a and b. The possibility of malfunction occurring, that is, malfunction is increased. Therefore, the larger the potential difference between the two contacts a and b, the less susceptible to noise, and always accurate and stable timing detection can be performed.
[0158]
Here, the equally precharged potentials of the contacts a and b of the signal lines 62 and 64 are the initial values of the timing detection operation (when the precharge control signal line 72 is at the high level (H: '1')). In this case, a temporary inflow of charge to the control transistors 67a, 69a, 75a, and 77a that are turned on, such as the current drive circuit 66, the reference current drive circuit 68, and the dummy circuits 74 and 76, occurs. However, the total signal current i flowing through the first signal line 62 through the current driving circuit 66 in which the signal voltage applying transistor 67b is turned on according to the number of hit signals ('1') held in the flag register 18 and the transistor 69b. The reference current i flowing through the second signal line 64 through the reference current driving circuit 68 turned on_rTherefore, when a predetermined time elapses after the start of detection, a potential difference occurs between the contacts a and b due to this current difference. This potential difference increases as the difference between the integrated currents flowing down the signal lines 62 and 64 increases, and therefore increases until a predetermined time after the start of detection. However, as the current flows, the potentials of the two signal lines 62 and 64 that have been precharged in advance decrease, and the retained charges decrease. Therefore, the retained charges decrease, and the potential is reduced. Since the current hardly flows when it approaches the ground level and eventually stops flowing, the potentials of both signal lines 62 and 64, that is, the potentials of both contacts a and b, are substantially equal to the ground level after a sufficient time has elapsed. Become.
[0159]
Therefore, in the semiconductor integrated circuit of the illustrated example, the potential difference between the contacts a and b increases as the potential decreases from the precharged potential unless the potentials at both contacts a and b decrease to near the ground level. . Therefore, when the potential between the contacts a and b is further lowered and a larger potential difference is generated between the contacts a and b, the lower potential of the contacts a and b is one of the transistors 82a and 82b. The difference between the precharge voltage of both contacts a and b, that is, both signal lines 62 and 64, and the detection start voltage level at which the transistors 82a and 82b are turned on can be made as large as possible so that the detection start voltage for turning on one of them is obtained. It is preferable to keep it. For this purpose, there is a method of either increasing the precharge voltage of both signal lines 62 and 64 or decreasing the detection start voltage level. In order to increase the precharge voltage of both signal lines 62 and 64, a booster circuit may be used. However, since the booster circuit increases the circuit area and costs, it is necessary to provide means for lowering the detection start voltage level. preferable. The detection start voltage is the source voltage when the transistor 82a or 82b is turned on, that is, the potential of the contact a or b, and the threshold value between the gate and source of the transistors 82a and 82b (for example, about 1.4 V) is determined. Therefore, the detection start voltage level can be lowered by lowering the potentials of the gate electrodes of the transistors 82a and 82b.
[0160]
In the timing control circuit 90 shown in FIG. 15, the precharge potential of the contacts A and B connected to the gate electrodes of both transistors 82a and 82b by the detection start level setting transistor 86 using a PMOS transistor is predetermined from the power supply potential (for example, 5V). Although the voltage is reduced to the potential (for example, 4.3 V) by the threshold voltage of the PMOS transistor, the present invention is not limited to this. For example, the detection start level setting transistor 86 is set to NMOS like the timing control circuit 92 shown in FIG. A transistor can also be used. NMOS transistor substrate biased gate-source threshold voltage V_THIs about 1.4V, for example, the power supply voltage V_ddIs 5 V, the drain electrode and the gate electrode of the NMOS transistor 86 are connected and connected to the power source, so that the increase in the potential of the source electrode is V_dd-V_THThat is, up to about 3.6V. Therefore, the precharge voltage at the contacts A and B is about 3.6 V, and the threshold voltage V between the gate and source of the NMOS transistors 82a and 82b._THIs about 1.4V, so that the detection start voltage V at which these transistors 82a and 82b are turned on is_ONCan be about 2.2V (3.6-1.4V).
[0161]
By the way, when the semiconductor integrated circuit of the illustrated example is applied as a timing control circuit of an encoding circuit, the potential difference between the contacts a and b of both signal lines 62 and 64 is increased early after the timing detection operation is started, that is, the contacts a and In order to increase the potential of the potential b even if it is small, the signal voltage application transistor 67c of the current drive circuit 66 is changed to a first one like a timing control circuit 92 shown in FIG. 16 in contrast to the timing control circuit 90 shown in FIG. The control transistor 67d is provided on the ground side on the 1 signal line (signal current detection line) 62 side, the gate ground transistor 75c of the dummy circuit 74 is provided on the second signal line (reference current drive line) side, and the control transistor 75d is grounded. It may be provided on the side. By doing this, only the control transistor 67d of the current drive circuit 66 in which the signal voltage application transistor 67c is turned on is turned on, and all the control transistors 67d in which the transistor 67c is not turned on and the control transistors 75d of all the dummy circuits 74 are turned on. Therefore, it is possible to eliminate charges flowing into the control transistors 67d and 75d at the initial stage of the timing detection operation, and to prevent simultaneous deterioration at the beginning of the timing detection operation of both the signal lines 62 and 64, that is, both the contacts a and b. In addition, the potential difference between the contacts a and b can be increased.
[0162]
However, in the timing control circuit 60 shown in FIG. 10, since the precharge transistor 83 is directly connected to the power supply, the contacts A and B are connected to the power supply potential V_dd(For example, 5 V). The precharge voltage at contacts A and B is the power supply potential V_ddTherefore, the threshold voltage between the gate and the source is V_THDetection start voltage V at which the transistors 82a and 82b (for example, 1.4V) are turned on_ONIs V_dd-V_TH(For example, 3.6V). In contrast, the detection start level (voltage) V of the timing control circuits 90 and 92 shown in FIGS._ONAre about 2.9 V and 2.2 V, respectively, for the same power supply potential (5 V), so that the detection start voltage level V is higher than that of the timing control circuit 60 shown in FIG._ONThe transistor 82a or 82b can be accurately and stably performed at a lower potential at which the potential difference between the signal lines 62 and 64, that is, the contact points a and b becomes larger. As a result, even if the timing control circuits 90 and 92 shown in FIGS. 15 and 16 are affected by noise compared to that shown in FIG. 3, the difference current detection circuit 70 is less likely to malfunction and is always accurate and stable. The detected timing can be performed with a high noise margin.
[0163]
FIGS. 17A and 17B show the circuit operation simulation waveform of the timing control circuit 92 shown in FIG. 16 and the circuit operation simulation waveform of the timing control circuit 60 shown in FIG.
[0164]
It can be seen that the voltage difference between the node a and the node b at the operating point where the node A point and the node B point respectively are 0.6 V and 0.1 V, and the margin of FIG.
Note that the encoding operation of the main encoder 12 of the encoding circuit 11 shown in FIG. 8 to which the timing control circuit 90 is applied is the same as that in the timing chart shown in FIG.
The timing control circuits 90 and 92 applied to the encoding circuit 11 shown in FIG. 8 are basically configured as described above.
[0165]
Further, according to the semiconductor integrated circuit of the illustrated example, the difference current detecting means can detect the difference between the detection start voltage and the voltage set in advance in the first and second signal lines relatively large. Since the start level setting means is provided, even in the detection operation timing, the potential of both signal lines of the signal current detection line and the reference current drive line is sufficiently lowered and the potential difference is sufficiently increased. It can be detected dynamically. For this reason, there is no possibility that the differential current detection means cannot be detected or malfunctions. Therefore, the difference current between the reference current drive line and the signal current detection line can be stably detected with low power consumption, accurately and quickly with a high noise margin, and a compact circuit configuration can be achieved. It can be suitably used as a timing control circuit that predicts the end of encoding of an encoding circuit such as an associative memory.
[0166]
  Next, with reference to FIG. 18 to FIG. 22, another semiconductor integrated circuit which is a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention will be described in detail. The semiconductor integrated circuit of the illustrated example can be applied to the encoding circuit shown in FIG. 8 as a timing control number detection circuit.
[0167]
In the semiconductor integrated circuit of the illustrated example, first, data input to data input lines for controlling M (M ≧ 1) current driving means provided in parallel with the first signal line, that is, the signal current detection line, respectively. Number of data to be detected out of '1' or '0' k₀(M> k₀Reference current (reference current) value i to be supplied to the reference current drive means provided in the reference current drive line as the second signal line in response to ≧ 0)_rThat is, the current value i flowing through one current driving means₀K₀Greater than double k₀Current value smaller than +1 times (k₀i₀<I_r<(K₀+1) i₀) Is set in advance. Prior to detection, both the first and second signal lines are precharged to a predetermined same potential. Accordingly, both the input and the inverted output of the first and second inverters connected in series or in parallel to these signal lines are the same, and both the inputs to the differential current detecting means are also the same.
[0168]
For this reason, in the semiconductor integrated circuit of the illustrated example, when predetermined data is input to the data input line in accordance with the operation timing and all the current driving units are activated, each of these current driving units has a current i.₀Current i (i = ki) corresponding to the number k (M> k ≧ 0).₀) Flows in the signal current detection line. On the other hand, the reference current drive line is supplied with the reference current value i by the reference current drive means._rFlows. As a result, the potentials of the signal current detection line and the reference current drive line that have been precharged to a predetermined potential start to drop, and the number k of current drive units that are active becomes k.₀When the value is larger, the potential of the signal current detection line decreases earlier, while k₀In the following cases, the potential of the reference current drive line decreases more quickly.
[0169]
By the way, in the semiconductor integrated circuit of the illustrated example, when the potential of either one of the signal lines decreases beyond the threshold value of the inverter connected to the signal line, the output of the inverter is inverted. Here, in the semiconductor integrated circuit of the illustrated example, the inversion of the inversion output of the inverter connected in series to the signal line can be directly detected by the differential current detection means. In the semiconductor integrated circuit of the illustrated example, only the transistor connected in series with the signal line (connected in parallel with the inverter) is turned on by inverting the inverted output of the inverter connected in parallel with the signal line. Thus, the current can flow down to the signal line and the potential can be lowered, and the drop in the input potential can be detected by the differential current detecting means. Therefore, the current values i and i flowing through both the first and second signal lines are as follows._rIs detected by the difference current detecting means, and the sign of the difference current is reversed, that is, both current values i and i_rOutputs the reversal (timing) of the magnitude relationship with. In this way, the number k of required data among the data input to each data input line is preset, and the number k of data to be detected is preset.₀It detects that it became. Thus, the semiconductor integrated circuit of the illustrated example can detect the number of required data input to the data input line.
[0170]
Here, by adjusting the threshold value of the inverter connected to both signal lines, the difference in potential between the two signal lines can be made relatively large when detecting the difference current between the two signal lines. Therefore, at this time, the inverted output of only one inverter can be inverted stably and accurately. Further, since the inverter has its own drive capability, in the semiconductor integrated circuit of the illustrated example, the voltage level of the initial value of the input signal to the differential current detecting means can be increased by inversion of one of the inverters. In addition, the voltage difference between the two input signals due to the difference current between the two signal lines at the start of detection can be increased, and the detection operation can be performed reliably and stably. Furthermore, in the semiconductor integrated circuit of the illustrated example, the transistor is turned on by inversion of the inverter, so that one of the signal lines can be reliably connected to the input of the difference current detection means first, so that the detection operation is stabilized. Can be done accurately. As a result, the detection of the reversal of the difference current between the two signal lines by the difference current detecting means can be stably and accurately performed.
[0171]
FIG. 18 shows a specific circuit diagram of still another embodiment of the timing control circuit 100 to which the semiconductor integrated circuit as a premise of the present invention is applied. Here, the timing control circuit 100 shown in the figure is applied to the encoding circuit 11 shown in FIG. 8, and includes the timing control circuit 61 shown in FIG. 12, the inverter trains 102a, 104a and 102b, 104b, and Since the transistors 103a and 103b are exactly the same except that the transistors 103a and 103b are provided, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0172]
The timing control circuit 100 shown in FIG. 18 includes the first signal line (signal current detection line) 62, the second signal line (reference current drive line) 64, and the (m + 1) of the flag register 18 in parallel with the first signal line 62. Data latch circuit 18₀, 18₁, ..., 18_m(M + 1) current drive circuits (current drive means) 66 provided for each of₀, 66₁, ..., 66_mAnd a reference current driving circuit (reference current driving means) 68 provided on the second signal line 64, and a difference between currents flowing in the first signal line 62 and the second signal line 64, that is, a difference current for detecting the difference current. Detection circuit (difference current detection means) 70, inverters 102a, 104a and 102b, 104b provided between first signal line 62 and second signal line 64 and difference current detection circuit 70, and operation of this timing control circuit The timing is controlled, that is, the current driving circuit 66 (66₀, 66₁, ..., 66_m), And a precharge control signal line 72 for controlling the reference current drive circuit 68, the difference current detection circuit 70, and the like.
[0173]
Furthermore, in this timing control circuit 100, one end contact p and contact q of the first signal line 62 and the second signal line 64 are connected to the inverters 102a and 102b, respectively, and further via the inverters 104a and 104b, The contacts a and b are connected to the differential current detection circuit 70, and the other end is connected to a predetermined potential, for example, a 5V power source via the precharge transistor 78. The reference current i flowing in the reference current drive circuit 68_rThe value of the current drive circuit 66 (66₀, 66₁, ..., 66_m) Can be passed through the current value i₀Can be appropriately determined according to the number of hit signals to be detected, but in order to detect the last hit signal, i₀Super 2i₀The inversion timings of the inverters 102a and 102b can be clearly distinguished and the difference current detection circuit 70 may have a current value that can detect the difference current by this inversion.
[0174]
Inverters 102a and 104a are connected between first signal line 62 and difference current detection circuit 70, while inverters 102b and 104b are connected between second signal line and difference current detection circuit 70. Further, NMOS transistors 103a and 103b connected to a predetermined low potential (for example, ground potential) are connected between inverters 102a and 104a and between inverters 102b and 104b, respectively, and their gate electrodes are connected to contact a (inverter 104a and contact point of difference current detection circuit 70) and contact point b (contact point of inverter 104b and difference current detection circuit 70). Here, the threshold voltage causing the output inversion of the inverters 102a and 102b is adjusted by the transistor width or threshold voltage of the PMOS and NMOS constituting the inverter. By adjusting the threshold voltage of the inverted output, the potential difference due to the difference current between the contacts p and q at the time of output inversion of only one inverter can be made relatively large, and the operation margin can be increased.
[0175]
Next, the detection operation of the timing control circuit 100 in the illustrated example will be described with reference to a representative example of the action when the last hit signal of the flag data in the flag register 18 is detected, that is, the last hit signal. To do. Here, flag data having a plurality of hit signals ('1') is held in the flag register 18, and the reference current i_rIs the drive current i of one current drive circuit 66₀1.5 times that is 1.5i₀It is assumed that it is set to.
[0176]
First, prior to detection, the precharge control signal line 72 is set to L (low: '0'), both the precharge transistors 78 and 79 are turned on, and the first and second signal lines 62 and 64, and hence the contact points. (Nodes) p and q are also precharged to the same H (high) potential (for example, 5 V), both precharge transistors 83 are turned on, and the contacts A and B in the differential current detection circuit 70 are similarly set to H ( High) Precharged to a potential (for example, 5 V). Therefore, both the connection points of the inverters 102a and 104a and 102b and 104b are L (low) potential by the inverters 102a and 102b, and the contacts a and b are both H (high) potential by the inverters 104a and 104b. Accordingly, the transistors 103a and 103b are turned on, and both node potentials of the inverters 102a and 104a and 102b and 104b are reliably fixed to the L (low) potential. Note that the transistors 82a and 82b of the difference current detection circuit 70, the transistors 67d of all the current drive circuits 66, and the transistor 69d of the reference current drive circuit 68 are off.
[0177]
Next, the precharge control signal line 72 is set to H (high: '1'), the PMOS transistors 78, 79, 83 are turned off, and the NMOS transistors 67d, 69d, 75d, 77d are turned on. Accordingly, the two transistors 69c and 69d of the reference current driving circuit 68 are both turned on, and the second signal line 64 has a reference current i._r(= 1.5i₀) Flows to lower the potential of the contact q. On the other hand, (m + 1) current drive circuits 66 (66₀, 66₁, ..., 66_m) Of the data latch circuit 18 in which the flag data of the flag register 18 is the hit signal ‘1’._jSince the signal voltage application transistor 67c having the gate electrode connected to is turned on and the control transistor 67d is turned on, the current drive circuit 66_jIncludes a driving current i from the first signal line 62.₀Flows. By the way, the flag data of the flag register 18 includes a plurality of, for example, k (k ≧ 2) hit signals “1”, so that the first signal line 62 has ki.₀Current flows, and the potential of the contact point p also decreases accordingly.
[0178]
Here, when k is larger than 2, the current ki flowing in the first signal line 62₀Is the reference current i flowing through the second signal line 64_r(= 1.5i₀), The potential at the contact point p decreases more quickly than the potential at the contact point q. For this reason, the contact p reaches the inverter output inversion potential (threshold value) earlier than the contact q, the output inversion of the inverter 102a occurs earlier than the output inversion of the inverter 102b, and the inverter 104a inverts the output earlier. That is, only the inverters 102a and 104a invert the output first, the potential drop of the contact a occurs, and the difference between the gate potential of the NMOS 82a (potential of the contact B) and the source potential (potential of the contact a) of the differential current detection circuit 70. Becomes larger than the substrate biased threshold voltage (eg, 1.4V) of the NMOS 82a (eg, the potential of the contact a drops below 3.6V when the potential of the contact B is 5V), and the NMOS 82a is turned on. The potential of A is lowered to enter the L (low) state. Note that the NMOS 103a is turned off by the potential drop of the contact a, and the connection point between the inverters 102a and 102b is kept in the H (high) state. On the other hand, the contact q (second signal line 64) does not reach the output inversion potential (threshold value) of the inverter 102b, the output inversion of both the inverters 102b and 104b does not occur, and the potential of the contact b is H The NMOS 82b is maintained in the OFF state, and the contact B is maintained in the H (high) state.
[0179]
Thereafter, a further current flows through both signal lines 62 and 64, the potentials of the contacts p and q are lowered, the potential of the contact q is lowered beyond the threshold value of the inverter 102b, and the output inversion occurs. Even if the output inversion of 104b is caused and the potential of the contact b is lowered, the gate potential of the NMOS 82b (potential of the contact A) is maintained in the L (low) state, so that the NMOS 82b is maintained in the off state. The potential of B is maintained in the H (high) state. In this way, the setting is maintained at H (high) '1' by the latch operation of the difference current detection circuit 70 and is inverted by the inverter 84 connected thereto, and L (low) '0' is output to the AND circuit 88. It will be. On the other hand, the contact A maintains L (low) ‘0’.
[0180]
Next, as the plurality of hit signals “1” in the flag register 18 are encoded, each of them is reset to “0” one by one, and when the number of remaining hit signals becomes one, the timing control circuit 100 in the illustrated example. In other words, when “0” is first input to the precharge control signal line 72 to perform precharge and then “1” is input, the first signal line is the same as described above. 62 has a current i₀However, the second signal line 64 has a reference current i._r(= 1.5i₀) Will flow. At this time, since the current flowing through the second signal line 64 is larger, the potential of the contact q drops earlier than the potential of the contact p, and the output inversion of the inverters 102b and 104b occurs, contrary to the above, Only b decreases first, and the NMOS 82b is turned on, but the NMOS 82a is kept off. Accordingly, the potential of the contact B is lowered to L (low) level, inverted by the inverter 84, and H (high) ‘1’ is output to the AND circuit 88 described above. On the other hand, the potential of the contact A is maintained at the H (high) “1” potential.
[0181]
From the above, if the output signal output from the inverter 84 of the timing control circuit 100 is “0”, the number of hit signals “1” held in the flag register 18 is two or more, and this output signal is “1”. If there is, it can be seen that the number of hit signals is one or less. Accordingly, when this output signal changes from “0” to “1”, the AND circuit 88 obtains the switching control signal from the detection result, that is, the “1” signal and the reset signal of the flag register 18 described above. The flag data in the flag register 18 may be switched to the flag data in the prefetch circuit 16 using a signal. Of course, the output signal here may be taken out from only the contact A or from both the contacts A and B.
[0182]
As described above, by appropriately adjusting the threshold voltages of the inverters 102a and 102b connected to the two signal lines 62 and 64, the potentials of the two contacts p and q generated by the difference current between the two signal lines 62 and 64 are obtained. Even if the difference in decrease is small, it can be reliably detected, and the output of only one inverter can be inverted first. Since the inverter has driving capability, the potential between the contacts a and b can be increased by output inversion, and the potential difference between the contacts a and b at the start of detection by the differential current detection circuit 70 can be increased. Only one of the NMOSs 82a and 82b can be reliably turned on. Therefore, the detection operation of the differential current detection circuit 70 can be performed stably and reliably. That is, the potential difference between the contacts a and b at the start of detection of the differential current detection circuit 70 can be made larger than the potential difference between the contacts p and q of both signal lines, so that either one of the transistors 82a and 82b is turned on. Will not malfunction. Therefore, since the timing circuit 100 in the illustrated example has a large noise margin and is not easily affected by noise, the timing circuit 100 can always perform accurate and stable timing detection. Of course, by adjusting the input threshold voltage for the output change of the inverters 102a and 102b to a low value, the voltage difference between the contacts p and q when one inverter starts to work can be increased, and a more stable operation can be achieved. Needless to say.
[0183]
The timing circuit 100 in the illustrated example uses two stages of inverters 102a, 104a, 102b, and 104b between the signal lines 62 and 64 and the difference current detection circuit 70, respectively, and contacts A and B of the NMOSs 82a and 82b. This is detected by dropping one of the potentials. However, the present invention is not limited to this, and is configured by a differential current detection circuit that has one inverter and raises the potential of one of the contacts A and B by a PMOS transistor. Also good.
The timing control circuit 100 is basically configured as described above.
[0184]
  Next, another semiconductor integrated circuit which is a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention will be described.
  FIG. 19 shows still another embodiment of the timing control circuit to which the semiconductor integrated circuit as the premise of the present invention is applied. The timing control circuit 106 shown in FIG. 19 is different from the timing control circuit 100 shown in FIG. 18 except that inverters 108a and 108b and transistors 109a and 109b are provided instead of the two-stage inverters 102a, 104a and 102b and 104b. Since they have exactly the same configuration, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.
[0185]
In the timing control circuit 106 shown in FIG. 19, an NMOS transistor 109a is connected between one end contact p of the first signal line 62 and the source electrode side contact a of the NMOS 82a of the differential current detection circuit 70. An inverter 108a is connected between the gate electrode and the contact p, an NMOS transistor 109b is connected between the end contact q of the second signal line and the source electrode side contact b of the NMOS 82b, and the gate electrode of the NMOS 109b An inverter 108b is connected between the contact q. Here, the threshold values of inverters 108a and 108b are adjusted similarly to inverters 102a and 102b.
[0186]
Similarly to the timing control circuit 100 shown in FIG. 18, in the timing control circuit 106 shown in FIG. 19, all the contacts A, B, a, b, p, q are first set to H by the L signal of the precharge control signal line 72. (E.g., contacts A, B, p, q are power supply voltage (Vdd, e.g., 5V), and contacts a, b are driven by substrate biased thresholds (e.g., 1.4V) of NMOSs 82a, 82b). Precharged to 3.6V). Next, by setting the signal line 72 to H, the first signal line 62 has a ki corresponding to the number k of hit signals by the current drive circuit 66 activated by the hit signal ‘1’ of the flag register 18.₀Current draw occurs, the voltage drops accordingly, and the second signal line 64 is connected to i by the reference current drive circuit 68._r(1.5i₀) Current draw occurs, and the voltage drops accordingly.
[0187]
At this time, when the number k of active current driving circuits 66 is 2 or more, the voltage drop of the first signal line 62 is faster than that of the second signal line 64. Therefore, the contact point b reaches the inverter threshold voltage earlier than the contact point q, and the output inversion of the inverter 108a occurs earlier than the output inversion of the inverter 108b. Therefore, the NMOS 109a is turned on before the NMOS 109b. For this reason, the potential drop of the contact a occurs, the NMOS 82a of the differential current detection circuit 70 is turned on, and the potential of the contact A becomes L (low) level. As a result, after that, even if the potential at the contact q further decreases, the output of the inverter 108b is inverted, the transistor 109b is turned on, and the potential drop at the contact b occurs, the gate potential of the NMOS 82b (the potential at the contact A) Is already L, the NMOS 82b is not turned on and remains off, and the potential at the contact B remains H. Therefore, the output of the contact B is inverted by the inverter 84, and the output of the inverter 84, which is the output of the timing control circuit 106, becomes L (low) hold.
[0188]
Conversely, when the number k of active current driving circuits 66 is 1 or less, the flowing current i of the second signal line 64 is reversed._rIs larger than the flowing current i of the first signal line 62, and the potential drop of the contact q is larger than that of the contact p. As a result, the output of the inverter 108b is inverted, the transistor 109b is turned on, the potential drop of the contact b occurs, the NMOS 82b is subsequently turned on, and the potential of the contact B becomes L level. On the other hand, since the potential of the gate electrode (contact B) of the NMOS 82a is L level, regardless of the potential of the contact a, that is, the potential drop of the contact p occurs, the inverter 108a inverts the output, and the transistor 109a is turned on. Even if the potential at the contact a drops, the NMOS 82a does not turn on. Therefore, the potential of the contact A is maintained at the H level. As a result, the potential of the contact B is inverted by the inverter 84, and the output of the timing control circuit 106 changes to H level. Thus, it can be detected that the hit signal “1” in the flag register 18 is the remaining one.
[0189]
In the timing control circuit 106 in the illustrated example, by adjusting the threshold values of the inverters 108a and 108b, the detection operation of the differential current detection circuit 70 is started, that is, at the time when one of the NMOSs 82a and 82b is turned on. The potential difference between the contacts a and b can be set, and stable and accurate timing detection with a large noise margin can always be performed.
[0190]
FIG. 20 shows a timing control circuit to which still another semiconductor integrated circuit as a premise of the present invention is applied. The timing control circuit 110 shown in the figure further adds to the timing control circuit 106 shown in FIG. 19 precharge PMOS transistors 78 and 78 for precharging the potentials of the contacts a and b to a predetermined potential, for example, a power supply potential Vdd (for example, 5 V). In order to obtain the same potential, a PMOS 79 for connecting both contacts a and b is added. The gate electrodes of these PMOSs 78, 78 and 79 are connected to the precharge control line 72.
[0191]
Here, in the timing control circuit 106 shown in FIG. 19, when the contacts A, B, p, q are first precharged to the H state of the power supply potential 5V, the potentials of the contacts a and b are set to the H state of 3.6V. In contrast, in the timing control circuit 110 shown in FIG. 20, the potentials of the contacts a and b can be raised to 5V. Therefore, the potential difference between the contacts p and q at the time when the detection operation of the difference current detection circuit 70 is started and when one of the NMOSs 82a and 82b is turned on can be made larger than that of the timing control circuit 106 shown in FIG. it can. Therefore, the timing control circuit 110 shown in FIG. 20 has a larger noise margin and can always perform accurate and stable timing detection.
[0192]
Further, like the timing control circuit 112 shown in FIG. 21, the control transistors 67e and 77e obtained by merging the control transistors 67d, 69d, 75d, and 77d of the current drive circuit 66 and the reference current drive circuit 68 may be used. It goes without saying that it is good.
[0193]
In order to set the initial value of the flag register 18, an OR logic circuit 114 that has received the initial value setting signal shown in FIG. 22 is inserted between the AND circuit 88 and the flag register 18.
The encoding operation of the main encoder 12 of the encoding circuit 11 shown in FIG. 8 to which the timing control circuits 100, 106, 110, and 112 are applied is the same as the timing chart shown in FIG.
The timing control circuit to which the semiconductor integrated circuit as the premise of the present invention is applied is basically configured as described above.
[0194]
As described in detail above, according to the semiconductor integrated circuit of the illustrated example, an inverter is provided in series or in parallel between the first and second signal lines and the differential current detecting means, respectively, and the inverter output inversion threshold is set. By adjusting the value voltage, the potential difference between the two input signals to the difference current detection means at the start of detection of the difference current detection means can be set relatively arbitrarily, so that the difference current detection means cannot be detected or malfunctions. Will not occur. Therefore, according to this semiconductor integrated circuit, it is possible to always accurately and stably detect the magnitude of the difference current between the two signal lines and the reverse timing. That is, the semiconductor integrated circuit of the illustrated example is a stable circuit that is not easily affected by noise and has a large operation margin, and is preferably used as a timing control circuit that predicts the end of encoding of an encoding circuit such as an associative memory. it can.
[0195]
Here, according to the semiconductor integrated circuit of FIG. 18, after the output of the inverter is inverted, the detection operation of the difference current detecting means can be performed regardless of the change in the potential of the first and second signal lines. Further, according to the semiconductor integrated circuit of FIG. 20, the operation margin can be further increased as compared with the semiconductor integrated circuit of FIG.
[0196]
  Next, with reference to FIG. 23, another semiconductor integrated circuit which is a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention will be described in detail. The semiconductor integrated circuit of the illustrated example can be applied to the encoding circuit shown in FIG. 8 as a timing control circuit number detection circuit.
[0197]
In this semiconductor integrated circuit, first, the desired number k of data “0” or “1” held in the data register is to be detected.₀(M> k₀≧ 0: The number of data equal to M (M ≧ 1) is the number of data that can be held in the data register) is held in the reference current control register. For example, data ‘1’ held in the data register is k₀If it is detected that the number has become, the reference current control register has k₀Pieces of data ‘1’ are held.
[0198]
Here, there are M signal unit current driving means and a second signal line which are provided in parallel to the first signal line, that is, the signal current detection line, and are controlled by data held in the data register. The currents flowing in each of the N reference unit current driving means provided in parallel to the reference current driving lines and controlled by the data held in the reference current control register are the same unit current i.₀And the offset current i flowing in the reference offset current drive means provided in the reference current drive line_osThe unit current i₀Smaller current value (i₀> I_os> 0) in advance. Therefore, k₀Reference current i flowing in the reference current drive line via the reference unit current drive means and the reference offset current drive means_r(= K₀i₀+ I_os) Is k₀i₀Larger (k₀+1) i₀Smaller current value (k₀i₀<I_r<(K₀+1) i₀)
[0199]
For this reason, in the semiconductor integrated circuit of the illustrated example, the unit current i is supplied to all the signal unit current driving means corresponding to the data registers holding the required data according to the operation timing.₀Current i (i = ki) corresponding to the number k (M> k ≧ 0).₀) Flows in the signal current detection line, whereas the reference current drive line has the reference current value i as described above._rFlows. The current values i and i flowing in both signal lines_rIs detected by the difference current detecting means, and the sign of the difference current is reversed, that is, both current values i and i_rOutputs the reversal (timing) of the magnitude relationship with. In this way, the number k of required data among the data input to each data input line is preset, and the number k of data to be detected is preset.₀It detects that it became. In this way, the semiconductor integrated circuit of the illustrated example can detect the number of required data held in the data register. The number of detected data can be arbitrarily set by changing the number of required data to be set and held in the reference current control register.
[0200]
FIG. 23 shows a specific circuit diagram of still another embodiment of the timing control circuit 116 to which the semiconductor integrated circuit as a premise of the present invention is applied. Here, the timing control circuit 116 shown in the figure is applied to the encoding circuit shown in FIG. 8, and includes a timing control circuit 61, a reference current control register 118, and an OR circuit shown in FIG. Since it is exactly the same except that 114 is provided, the same components are denoted by the same reference numerals, and detailed description thereof is omitted. The serially connected transistors 75c and 75d are used as the dummy circuit 74 in the timing control circuit 61 shown in FIG. 12, but the gate of the NMOS transistor 75c is connected to the reference current control register 118 in the timing control circuit 116 shown in FIG. The reference unit current drive circuit 74 is made to function.
[0201]
The timing control circuit 116 shown in the figure includes (m + 1) data latch circuits 118.₀, 118₁, ..., 118_mA reference current control register 118, a first signal line (signal current detection line) 62, a second signal line (reference current drive line) 64, and (m + 1) of the flag register 18 in parallel with the first signal line 62, respectively. Data latch circuits 18₀, 18₁, ..., 18_m(M + 1) signal unit current drive circuits (signal unit current drive means) 66 provided for each of₀, 66₁, ..., 66_mAnd (m + 1) data latch circuits 118 of the reference current control register 118 in parallel with the second signal line, respectively.₀, 118₁, ..., 118_m(M + 1) reference unit current drive circuits (reference unit current drive means) 74 provided for each of₀74₁, ..., 74_mAnd a reference offset current drive circuit (reference offset current drive means) 68 provided in the second signal line 64, and a difference between currents flowing in the first signal line 62 and the second signal line 64, that is, a difference current is detected. The differential current detection circuit (differential current detection means) 70 and the operation timing of this timing control circuit are controlled, that is, the unit current drive circuit 66 (66₀, 66₁, ..., 66_m) And 74 (74₀74₁, ..., 74_m), And a precharge control signal line 72 for controlling the reference offset current drive circuit 68, the difference current detection circuit 70, and the like.
[0202]
The reference current control register 118 has the same configuration as the flag register 18 and (m + 1) data latch circuits 118.₀, 118₁, ..., 118_mEach data latch circuit 18 of the flag register 18.₀, 18₁, ..., 18_mThe number of flag data (hit signal ‘1’) to be detected individually stored in₀((M + 1)> k₀≧ 0) depending on k₀Pieces of data (hit signal) ‘1’ to k₀Data latch circuits 118_jIt is for making it hold. Data latch circuit 118 of register 118_jThe number of data (hit signal) '1' to be stored in can be arbitrarily set from the outside, and the detected number k₀Can also be set arbitrarily as required. In addition, the data latch circuit 118 of the register 118₀, 118₁, ..., 118_mWhich k₀Data latch circuits 118_jIt is also optional to hold data ‘1’.
[0203]
The reference unit current drive circuit 74 has the same configuration as the unit current drive circuit 66, and is composed of two series-connected N-channel MOS transistors, one of which is connected to the second signal line 64 and the other is grounded. The signal application transistor 75c and the control transistor 75d are connected to each other._jThe gate electrode of the ground-side control transistor 75 d is connected to the control signal line 72. The unit current drive circuit 74 is exactly the same as the unit current drive circuit 66, and the control transistor 75d is turned on at the time of detection, and the signal application transistor 75c has a hit signal '1 Unit current i from the second signal line 64 when turned on when '₀Is configured to flow. Therefore, the detected number is k₀The reference current control register 118 has k₀Since the number of hit signals ‘1’ are held, k₀Unit current drive circuits 74 for reference are turned on and k₀i₀Current flows in the second signal line. This unit current i₀Are all unit current drive circuits 66₀, 66₁, ..., 66_mAnd 74₀74₁, ..., 74_mHowever, there may be variations in the transistors 67c and 67d and 75c and 75d used, for example, variations of variations due to processes.
[0204]
On the other hand, the reference offset current drive circuit 68 supplies a predetermined reference offset current i to the second signal line._OSIt is for flowing. Reference offset current i_OSIs the unit current i₀Smaller current value (i₀> I_OS> 0), and a current value that can be detected by the differential current detection circuit 70 described later may be used. This current value i_OSIs the unit current i₀It may be determined in consideration of variations in circuit elements such as the transistors 67c, 67d, 75c, 75d constituting the unit current drive circuits 66 and 74 and the transistors 69c, 69d constituting the reference offset current drive circuit 68. i_os= 0.2i₀~ 0.8i₀Is preferable.
[0205]
As a result, the reference current i flowing in the second signal line at the time of detection_rThe value of is the number of detections (number of hit signals to be detected) k₀Turn on according to₀Current value k flowing through each unit current drive circuit 74₀i₀And reference offset current value i flowing through the reference offset current drive circuit 68_osAnd sum (k₀i₀+ I_os) And unit current value i₀K₀Greater than double k₀Current value smaller than +1 times (k₀i₀<I_r<(K₀+1) i₀) For example, in order to detect the last one hit signal, the reference current value i_rIs i₀Super 2i₀However, as described above, i is considered in consideration of the variation of the constituent circuit elements and the margin of the difference current detection circuit 70._r= 1.2i₀~ 1.8i₀It is good to do.
[0206]
The output of the AND circuit 88 of the differential current detection circuit 70 is connected to the clock terminal of the flag register 18 described above. Further, the output of the AND circuit is connected to one input of the OR circuit 114, and the other of the OR circuit 114 is connected to the initial value setting signal.
[0207]
Next, the detection operation of the timing control circuit 116 in the illustrated example will be described with reference to a representative example of the action when the last hit signal of the flag data in the flag register 18 is detected, that is, the last hit signal. To do. Here, the flag register 18 includes a plurality of data latch circuits 18._jFlag data having a hit signal ('1') is held in the reference current control register 118, and one data latch circuit 118 is stored in the reference current control register 118._jHolds the data having the hit signal ('1'), and the unit current values of the unit current drive circuits 66 and 74 are i.₀Reference offset current value i of the reference offset current drive circuit 68_osIs 0.5i₀Therefore, the reference current i_rIs the unit current i₀1.5 times that is 1.5i₀It is assumed that it is set to.
[0208]
First, prior to detection, one data latch circuit 118 of the reference current control register 118 is used._jThe hit signal “1” is latched and held. Further, the precharge control signal line 72 is set to L (low: '0'), the first and second signal lines 62 and 64, and therefore the contacts (nodes) a and b, and the contacts A and B in the difference current detection circuit 70 Similarly, B is precharged to an H (high) potential (for example, 5 V).
[0209]
Next, the precharge control signal line 72 is set to H (high: '1'), the PMOS transistors 78, 79, 83 are turned off, and the control transistors 67d, 69d, 75d, 77d are turned on. Therefore, one data latch circuit 118 holding the hit signal “1” of the reference current control register 118._jUnit current drive circuit 74 corresponding to_jThe two NMOS transistors 75c and 75d and the two NMOS transistors 69c and 69d of the reference offset current driving circuit 68 are both turned on, and the second signal line 64 has a reference current i._r(= 1.5i₀) Flows to lower the potential of the contact b. On the other hand, (m + 1) unit current drive circuits 66 (66₀, 66₁, ..., 66_m) Of the data latch circuit 18 in which the flag data of the flag register 18 is the hit signal ‘1’._jUnit current drive circuit 66 connected to_jIncludes a unit current i from the first signal line 62.₀Flows. By the way, the flag data of the flag register 18 includes a plurality of, for example, k (k ≧ 2) hit signals “1”, so that the first signal line 62 has ki.₀Current flows, and the potential of the contact a also decreases accordingly.
[0210]
Here, when k is larger than 2, the current ki flowing in the first signal line 62₀Is the reference current i flowing through the second signal line 64_r(= 1.5i₀), The potential of the contact A drops to “0”. On the other hand, at this time, the contact B keeps “1”, and the AND circuit 88 is connected to the AND circuit 88 by the inverter 84 connected thereto. Will be output.
[0211]
Next, when the detection operation of the timing control circuit 116 is performed when the number of remaining hit signals in the flag register 18 is 1, the potential at the contact B is lowered to the low level and inverted to the inverter 84, and the above AND operation is performed. “1” is output to the circuit 88. On the other hand, the potential of the contact A is maintained at the H (high) potential.
[0212]
From the above, when the output signal output from the inverter 84 of the timing control circuit 116 changes from “0” to “1”, the AND circuit 88 resets the detection result, that is, the “1” signal and the flag register 18 described above. The switching control signal may be obtained from the signal, and the flag data in the flag register 18 may be switched to the flag data in the prefetch circuit 16 using this switching control signal.
[0213]
In the timing control circuit 116 shown in FIG. 23, in the unit current drive circuits 66 and 74 and the reference offset current drive circuit 68 and the dummy circuit 76, the signal application transistor 67c and the normally-off transistor 77c are connected to the first signal line 62 side and the signal. The application transistor 75c and the normally-on transistor 69c are provided on the second signal line 64 side, and the control transistors 67d, 75d, 69d, and 77d are provided on the ground side. However, the arrangement of the illustrated example is preferable, and by doing so, at the start of the detection operation, the first signal line 62 and the second signal line 64 are not turned on (the hit signal “1” is input to the gate electrode). No) The ON currents to the control transistors 67d, 77d and 75d connected to the transistors 67c, 77c and 75c respectively prevent the voltage drop of the first and second signal lines 62 and 64, and the separation of the contacts A and B The potential difference between the contact a and the contact b at the start, that is, when the potential of the contact a or b drops below 3.6 V can be increased, and the operation of the differential current detection circuit 70 can be made stable and reliable.
[0214]
In the above example, the unit currents flowing through both unit current drive circuits 66 and 74 are the same unit current i.₀However, it is not limited to this and may be different. At this time, the reference offset current i_osDepending on the value of the reference current i_rCan be determined. Reference offset current value i_osThe unit current i₀The value is smaller, but the present invention is not limited to this. The number of data latch circuits that hold the hit signal “1” in the reference current control register 118 and the value of the reference unit current that flows to one reference unit current drive circuit 74 It may be determined appropriately depending on the situation.
The timing control circuit 116 is basically configured as described above.
[0215]
The timing control circuit 116 in the illustrated example can be applied to the encoding circuit 11 illustrated in FIG. 8, but is not limited thereto, and can be applied to a circuit that requires detection of an arbitrary number of a plurality of detection nodes. .
[0216]
As described above in detail, according to the semiconductor integrated circuit of the illustrated example, a predetermined number of predetermined data, for example, data '1' for controlling the reference unit current driving means provided in the second signal line is referred to. By holding the current control register, it is possible to detect the number of predetermined data in the data register for controlling the signal unit current driving means provided in the first signal line. Therefore, the semiconductor integrated circuit of the illustrated example can be suitably used as a timing control circuit that predicts the end of encoding of an encoding circuit such as an associative memory.
[0217]
  Next, with reference to FIGS. 24 to 27, another encoding circuit which is a premise for understanding the encoding circuit applied to the associative memory device of the present invention will be described.
[0218]
In the associative memory of the illustrated example, when search data is input to the associative memory block constituting the associative memory device at the time of matching search, matching search is performed across a plurality of associative memory sub-blocks. At this time, as a result of each associative memory sub-block, that is, flag data including a match signal (hit signal) that matches the search data is held in a plurality of associative memory words, and a priority sub-block encoding circuit As a result, the associative memory sub-block having the highest priority is selected, and the flag data is transferred to and held in the flag register of the main coding circuit with priority. The priority-added main encoding circuit encodes the hit signal in the flag data stored in the flag register according to a predetermined priority, and outputs a hit address. In the prioritized main encoding circuit, hit signals in the flag register are sequentially reset with the output of the hit address.
[0219]
On the other hand, during the encoding of the flag data, the flag data of the next priority associative memory sub-block selected by the prioritized sub-block encoding circuit is changed to the flag data of the previous priority associative memory sub-block. In order to prepare for input to the flag register prior to the end of all hit signals, the number of hit signals held in the flag register is detected by a timing detection control circuit that detects the end of the hit signal of the flag register in advance. . For example, when the number of remaining hit signals becomes the last one, the flag data of the next priority associative memory sub-block is generated by the flag data sense circuit provided for each associative memory word according to the detection signal. The flag data of the next associative memory sub-block is input to the flag register immediately after the completion of encoding of all hit signals of this flag data, and the hit signal in this flag data is encoded. Start. These procedures are sequentially repeated to encode the hit signal of the entire associative memory block, that is, to output an address.
[0220]
According to the encoding circuit of the illustrated example, as described above, the hit signal in the flag data of the associative memory sub-block to be encoded next is being encoded during the encoding of the hit signal of the flag data of the previous associative memory sub-block. Since the flag data sense (detection) circuit is prepared for input to the flag register, time for transferring the hit signal from the associative memory sub-block to the flag register of the prioritized main encoding circuit can be eliminated. The flag data of the associative memory sub-block of the next priority is detected by the flag data sense circuit after detecting that the last hit signal has become one immediately before the start of encoding of the last hit signal of the flag data in the flag register Is detected in the next encoding cycle, and the sign of the hit signal in the input flag data It is possible to perform, since no loss in coding cycle occurs, it is possible to reduce the encoding time of the entire associative memory block whole turn associative memory can speed up the match search operation of the CAM device.
[0221]
That is, when the number of hit signals of the flag data to be encoded becomes the last one when the flag data of one associative memory sub-block is encoded, the encoding circuit of the illustrated example has the next associative memory to be encoded. The sub-block flag data is taken out to the detection line, and taken into the flag register at the end of encoding. For this reason, the flag data can be efficiently and quickly encoded, and a prefetch circuit or the like is not required, and the occupied area on the chip can be reduced.
[0222]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an encoding circuit which is a premise of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0223]
24 to 27 show an encoding circuit according to still another embodiment as a premise of the present invention. FIG. 24 is a configuration diagram including an associative memory portion of the encoding circuit as a premise of the present invention. FIG. FIG. 26 is a partial circuit diagram, FIG. 26 is a circuit diagram of the main circuit, and FIG. 27 is a timing chart. The difference between the encoding circuit 120 shown in these drawings and the encoding circuit 11 shown in FIGS. 8 to 10 is that there is basically no difference between the prefetch circuit 16 and the same configuration. Elements are given the same numbers and their explanation is omitted. In FIG. 24, the flag data sense circuit 126 is described in some detail, but this configuration is not different from the encoding circuit 10. Also shown in the figure are a switch circuit 124 and an AND circuit 128 for selecting the register 36 of the required sub-block 32.
[0224]
FIG. 24 is a schematic diagram of still another embodiment of an associative memory block to which the encoding circuit as the premise of the present invention is applied. As shown in the figure, the encoding circuit 120 includes a priority order encoding circuit (hereinafter referred to as a main priority encoder or main encoder) 122 and a priority order sub block encoding circuit (hereinafter referred to as a sub block priority encoder or sub encoder). 14), a switch circuit 124 for detecting flag data, a flag data sense circuit 126, and an AND circuit 128. The main encoder 122 includes a flag register circuit 18, a main priority circuit 20, The sub-block encoder 14 includes a data latch circuit 24, a sub-priority circuit 26, and a sub-encode circuit 28.
[0225]
In FIG. 24, reference numeral 30 denotes an associative memory block (hereinafter referred to as a memory block). As described above, a plurality of memory blocks 30 (n in this embodiment, B₁, B₂, ..., B_n) Associative memory sub-block (hereinafter referred to as sub-block) 32. The memory block 30 includes n (A₁, A₂, ..., A_n) AND circuit 128 and (m + 1) (C + 1) (C₀, C₂, ..., C_m) Flag data sense circuit 126 is provided.
[0226]
First, the switch circuit 124 for detecting flag data, the flag data sense circuit 126, and the AND circuit 128, which are the most characteristic parts in the encoding circuit 120 shown in the drawing, will be described.
[0227]
The switch circuit 124 includes the sub-block 32 (B₁) Register 36 (R₀) Connected to one (S₀) As a representative example, two NMOS transistors 124a and 124b are connected in series. Each switch circuit 124 has a detection line L (L (L) corresponding to an electrode (for example, drain electrode) of one transistor 124a).₀, L₁, ..., L_mAnd the gate electrode of the transistor 124a is connected in parallel to the AND circuit 128 in each sub-block 32. The other transistor 124b has a gate electrode connected to the output terminal of the corresponding register 36, and an electrode (for example, a source electrode) of the transistor 124b is grounded. In the switch circuit 124, when the register 36 outputs a hit signal ('1') and the high level signal '1' is input from the AND circuit 128, both the transistors 124a and 124b are turned on, and the detection line. L is grounded to release the charge, and the potential of the detection line L is lowered. On the other hand, when the data held in the register 36 is “0”, even if the high level signal “1” is input from the AND circuit 128, the transistor 124 b of the switch circuit 124 remains OFF. The potential is not changed by the switch circuit 124.
[0228]
The flag data sense circuit 126 is configured by a self-driven sense amplifier, precharges the detection line L to a predetermined potential in advance, and detects the potential (fluctuation in potential) of the precharged detection line, This is to detect the data (hit signal “1” or mismatch signal “0”) held in 36. Each flag data sense circuit 126 (C₀) Is provided on the detection line L so as to be denoted by a representative example, and includes two PMOS transistors 126a and 126b and an inverter 126c. In the flag data sense circuit 126, one electrode (for example, drain) of each of the PMOS transistors 126a and 126b is connected to the power source, the other electrode (for example, source) is connected to the detection line L, and the gate of one transistor 126a is connected in parallel. In the timing circuit 60 shown in FIG. 26 of the main encoder 122, the gate of the other transistor 126b is connected to the detection line L on the output side of the inverter 126c. The inverter 126 c is interposed in the detection line L and outputs an inverted signal to the flag register circuit 18 of the main encoder 122. The flag data sense circuit 126 precharges the detection line L by turning on the PMOS transistors 126a and 126b when an output level (CS1) of a timing circuit 60 described later is at a low level (L: '0').
[0229]
After this, the timing circuit 60 signals that the end of the encoding of the flag data of one sub-block 32, such as a signal indicating that the hit signal in the flag data of the sub-block 32 currently being encoded is the last one. When the output level (CS1) becomes high level (H: '1'), the flag data sense circuit 126 turns off the transistor 126a and holds the search line L in the precharged high (H) state. To do. At this time, the transistor 126b is in an ON state. On the other hand, at this time, since the output level (CS1) is at the high level, the data latch circuit 24 of the sub-block encoder 14 is provided corresponding to the sub-block 32 of the next priority in which “1” is latched. The AND circuit 128 outputs a high level signal (H: '1'). As a result, both transistors 124a and 124b of the switch circuit 124 of the word whose data in the register 36 of the selected sub-block 32 is the hit signal “1” are turned on, and the precharged charge is discharged from the search line L. As a result, the potential of the search line L decreases and changes from a high (H) state to a low (L) state. The flag data sense circuit 126 detects a decrease (change) in the potential of the search line L and outputs a hit signal from the register 36 to the flag register circuit 18. That is, the inverter 126c inverts the low (L) potential of the search line L, turns off the PMOS transistor 126b, and inputs the high (H) potential hit signal “1” to the input signal line of the flag register 18 of the main encoder 122. To do. On the other hand, when the data in the register 36 of the selected sub-block 32 is the mismatch signal “0” while the output level (CS1) of the timing circuit 60 is high (H) level, the switch circuit 124 is used. Does not turn on, the potential of the search line L does not change, and the PMOS transistors 126a and 126b of the flag data sense circuit 126 remain on. Therefore, the flag data sense circuit 126 is inverted by the inverter 126c. ) The state mismatch signal “0” is input to the input signal line of the flag register 18 of the main encoder 122.
[0230]
In this way, the flag data sense circuit 126 is used until the last hit signal is encoded after the last hit signal encoded in the flag data of the sub-block 32 of the previous priority level becomes one. Next, the flag data of the sub-block 32 of the next priority is detected. Thereafter, when the encoding of the last hit signal is completed and the signal is input to the clock terminal of the flag register 18, the detected flag data is immediately input to the flag register 18 and latched.
[0231]
The AND circuit 128 calculates the logical product of the encoding end timing notice signal (CS1) from the timing circuit 60 and the latch data (or reset output) of the data latch circuit of the sub-block encoder 14, and outputs the corresponding sub-block 32. This is for controlling all the switch circuits 124. Only when the warning signal (CS1) and the latch data are both high (H) level '1', the output of the AND circuit 128 is also high (H) level '1'. The transistor 124a of each switch circuit 124 is turned on. At this time, if the data held in the register 36 of the sub-block 32 is a hit signal ('1'), the transistor 124b is also turned on, the switch circuit 124 is turned on, the search line L is grounded, and the potential is lowered. Then, the level changes from the high level to the low level. On the other hand, if it is a mismatch signal ('0'), the transistor 124b remains off, the switch circuit 124 does not turn on, and the potential of the search line L does not change.
[0232]
The main encoder 122 includes a flag register circuit 18, a main priority circuit 20, a main encoding circuit 22, and a timing circuit 60 as shown in FIGS. The flag register 18 has (m + 1) data latch portions corresponding to the detection lines L (for convenience, subscripts corresponding to the detection lines L are attached). These latch portions are respectively determined in accordance with timing signals from the timing circuit 60. The data of the detection line L that is input in the order of priority is held, and is reset by a signal input from the main priority circuit 20. The flag register circuit 18 holds flag data until the main encoding circuit 22 encodes all hit signals, and each time a high priority word address hit signal is encoded, Reset.
[0233]
In this embodiment, the flag register 18 uses a D latch, but can be arbitrarily selected as long as it can temporarily hold 1 bit.
[0234]
By the way, the main encoder 122 shown in FIG. 25 and the main encoder 12 shown in FIG. 2 used in the encoding circuit 120 shown in FIG. And the node Q of the priority circuit 20_mThe difference is that (OR output) is not connected to the flag register 18 via the inverter 49.
[0235]
That is, the priority circuit 20 of the main encoder shown in FIG. 2 resets the last hit signal of the flag data held in the flag register 18 and then resets the node Q_mIs used to switch the flag data of the flag register 18 to the flag data of the next priority sub-block 32 latched and held in the prefetch circuit 16 in advance. That is, in the main encoder 12 shown in FIG._mThe output “0” is inverted by the inverter 49, the inverted value “1” is input to the flag register 18, and the flag data of the next priority sub-block 32 latched and held in the prefetch circuit 16 is stored in the flag register circuit 18. Each is input to and held in a corresponding circuit. Thereafter, the vacant prefetch circuit 16 reads the flag data of the next priority sub-block 32 previously selected by the sub-block encoder 14 from the register 36 and latches and holds it. Thus, after the priority circuit 20 finishes processing the flag data of the sub-block of the previous priority, the flag data of the sub-block of the next priority is transferred from the register 36 of the sub-block 32. Since there is no need to wait, encoding can be performed efficiently. However, in this method, the content of the flag register 18 is held in the prefetch circuit 16 after the last hit signal of the flag data of the sub-block 32 of the previous priority level held in the flag register 18 is reset. Since it is switched to the flag data of the next priority order, in the priority encoding cycle started by reset, a cycle in which encoding cannot be performed at the time of switching the flag data of the sub-block may occur, and there may be a time during which encoding output cannot be performed.
[0236]
On the other hand, in the illustrated encoding circuit 120, the number of hit signals of flag data in the flag register 18 is detected by the timing control circuit 60 shown in FIG. Instead of resetting the last hit signal in the main priority circuit 20 using this detection result (encoding end notice signal) as an input signal, the flag data is encoded during the encoding of the last one hit signal. The sense circuit 126 detects the flag data of the sub-block 32 of the next priority, and inputs it to the flag register 18 simultaneously with the end of encoding. Therefore, the encoding circuit 120 of the illustrated example can perform priority encoding in the same cycle even when the flag data of the same sub-block is switched even when the flag data of the sub-block is switched. Of course, in the encoding circuit 120 of the illustrated example, the next one previously selected by the subblock encoder 14 by the flag data sense circuit 126 during the encoding of the last one hit signal of the flag data of the subblock in the flag register 18. Since the contents of the flag data in the register 36 of the sub-block 32 of the priority order are detected and can be input to the flag register 18 at the end of encoding, the prefetch circuit is not necessary, and the time for reading the flag data ( The time for transferring the flag data from each sub-block 32 to the main encoder 12 is eliminated, and the processing is unrelated to the encoding process, so that the encoding efficiency can be improved. In the illustrated encoding circuit 120, the last hit signal of the flag data in the flag register 18 need not be reset.
[0237]
FIG. 26 shows a timing control circuit 60 that is one of the characteristic parts of the encoding circuit 120 in the illustrated example.
[0238]
The timing control circuit 60 shown in the figure has the same configuration as the timing control circuit 60 shown in FIG. In the timing control circuit 60, an output line extends from the contact B and is input to the AND circuit 88 through the inverter 84, and this output is supplied to each data latch circuit 18 of the flag register 18 through the OR circuit 114.₀, 18₁, ..., 18_mConnected to the clock. An initial value setting signal for setting the initial value of the flag register 18 is input to the other input of each OR circuit 114. The output of the inverter 84 is connected to each AND circuit 128 via the OR circuit 130. Note that the reset signal of the flag register 18 described above is input to the other input of the AND circuit 88.
[0239]
As described above, the number of flag data hit signals “1” held in the flag register 18 by the timing control circuit 60 is detected, but the output signal output from the inverter 84 of the timing control circuit 60 is “0”. If it is "2", it can be seen that there are two or more hit signals "1" held in the flag register 18, and if the output signal is "1", there are one or less hit signals "1". In the illustrated example, the CS1 signal output from the OR circuit 130 is guided to the AND circuit 128 and the flag data sense circuit 126. When the CS1 signal is “1”, that is, the last one hit signal remaining ” In order to detect the flag data of the next memory sub-block 32 by the switch circuit 124, the AND circuit 128 and the flag data sense circuit 126 when encoding 1 ', the flag data of the memory sub-block 32 is read and switched. It can be done quickly.
[0240]
On the other hand, in the sub-block encoder 14, the associative memory sub-block 32 (B₁, B₂, ..., B_nAt the time of a match search performed every time, the match search result in each memory sub-block 32, that is, flag data is held in the register 36, and the search data and A subblock hit signal indicating whether or not there is a memory word 34 (hit word or match word) indicating a match is generated and held in the data latch circuit 24 of the corresponding subblock 32.
[0241]
On the other hand, in the sub-priority circuit 26 of the sub-block encoder 14, the block hit signal latched and held in the data latch circuit 24 from the left side to the right side in the illustrated example is a hit signal ('1') according to a predetermined priority order. The sub-block 32 is selected and an output signal with priority having “1” only in the block address is output. This output signal is encoded and encoded by the subsequent sub-encoding circuit 28 and also output to the AND circuit 128 corresponding to the sub-block 32. As described above, the AND circuit 128 outputs a high level signal to the switch circuit 124 only when the block hit signal is “1” and a high level signal is input from the timing circuit 60. As a result, the switch circuit 124 corresponding to the memory word 34 of the hit signal “1” grounds the detection line L. Thus, the charge previously charged to the detection line L by the flag data sense circuit 126 is discharged, and the flag data sense circuit 126 detects a decrease in the potential of the detection line L, that is, a change from the high potential to the low potential, and the inverter 126c. The high potential hit signal inverted by the above is input to the flag register 18. Thereafter, these hit signals (flag data) are input to the flag register 18 by the end signal of the last one hit signal of the main encoder 122.
[0242]
Next, FIG. 27 shows an example of a timing chart of the encoding timing of the main encoder 112 using the timing control circuit 60 of the illustrated example, and the encoding operation of the encoding circuit 120 will be described with reference to this.
[0243]
In the figure, (a) is an encode signal indicating the encode timing of the main encoder 12, (b) is a reset signal indicating the reset timing of the hit signal '1' of the flag register 18, and (c) is a timing detection circuit 60. (D) is a detection output signal (end notice signal) of the timing detection circuit 60, and (e) is an AND circuit 128 from the timing detection circuit 60 via the OR circuit 130. The signals (CS1) and (f) input to the flag data sense circuit 126 are the flag sense output signals (output data signals of the flag data sense circuit 126) of the next priority sub-block 32, and (g) is the next flag. A flag data switching control signal indicating the timing of shifting the data to the flag register 18 (end It represents the signal).
[0244]
As can be seen from the figure, while the hit signal in the same flag data held in the flag register 18 is encoded with a predetermined priority, a predetermined time has elapsed from the rising timing of the reset pulse (b) of the hit signal. Thus, the encoding cycle (a) and the detection cycle (c) are configured to start (rise). However, the timing control circuit 60 detects the last hit signal at the detection timing (c) activated by the encode pulse (a) or the reset pulse (b) and the input pulse (g), and from the contact B which is the end notice signal. When the detection output signal (d) of FIG. 27 changes to the low level as shown in FIG. 27 (d), the CS1 shown in FIG. 27 (e) is an inverted signal of the detection output signal (d) to the AND circuit 128 and the flag data sense circuit 126. A signal (e) is input. For this reason, after the flag data sense circuit 126 precharges the detection line L in advance, the switch circuit 124 to which the high level signal is input from the AND circuit 128 corresponds to the word in which the register 36 holds the hit signal. The detection line L is grounded to discharge the precharged charge, while the potential of the detection line L corresponding to the word that does not hold the hit signal does not change, the precharged charge does not change, and the detection line L changes its potential opposite to the flag data in the register 36, and the output signal is determined as shown in FIG. In the flag sense output (f) shown in FIG. 27 (f), flag data having a hit signal “1” and flag data not having a hit signal are shown together.
[0245]
Then, the output signal of the flag data sense circuit 126 is taken into the flag register 18 in synchronization with the switching control signal (g), and the main priority circuit 20 and the main encode circuit 22 are used by using the flag data in successive encode cycles. Performs encoding operation according to, and outputs the encoding address. In this way, the main encoder 122 performs an encode operation in a predetermined continuous cycle and outputs an encode. Here, the switching control signal (g) is output by AND (logical product) of the inverted data of the detection output (d) and the reset (b).
[0246]
Thereafter, both the encoded block address output from the sub-encoding circuit 28 of the sub-block encoder 14 and the encoded word address from the main encoding circuit 22 of the main encoder 122 are combined as an encoded logical address. Output sequentially. When the last sub-block 32 or the sub-block 32 with the lowest priority is selected, the processing of the sub-block encoder 14 is finished, and when all the hit signals are encoded by the main encoder 122, all associative memory sub-blocks are processed. The hit signals of all 30 memory words 34 are output as logical addresses, and the match search operation is terminated.
[0247]
As described in detail above, according to the encoding circuit of the illustrated example, when performing a match search with the search data of the associative memory block of the associative memory device, among the plurality of associative memory sub-blocks constituting the associative memory block A match search result of the first associative memory sub-block, for example, a match signal (hit signal) that matches the search data in a plurality of associative memory words is held in holding means such as a register and the associative memory sub-block A block hit signal indicating the presence of an associative memory word matching the search data is generated in the block. Subsequently, the prioritized sub-block encoding circuit receives the block hit signal, selects the associative memory sub-block having the highest priority, and generates a sub-block address. Then, the hit signal of the selected highest priority sub-block (simultaneously for all words) is transferred to the coding circuit with priority. Thereafter, the coding circuit with priority order codes the hit signal with a predetermined priority order and outputs a word address. During this encoding, the associative memory sub-block of the next priority is selected by the prioritized sub-block encoding circuit, detected by the data switching timing control circuit, and the flag data of the previous priority sub-block is stored. Before the end of encoding, for example, after the hit signal to be encoded becomes the last one, the hit signal data held in the holding means such as the register of this sub-block is detected immediately after the end of encoding, and the encoding ends. At the same time, the data is input to the data holding circuit of the coding circuit with priority. Thus, after the encoding of the hit signal is completed, the encoding circuit with priority order immediately starts encoding the flag signal data of the next priority sub-block in a continuous cycle, encodes the word address Is output. The word address output and the sub-block address output are combined to output a logical address.
[0248]
Therefore, according to the encoding circuit of the illustrated example, even in an associative memory block composed of a plurality of associative memory sub-blocks, there is no time delay (waiting time) in switching between the plurality of associative memory sub-blocks. Processing becomes possible, and output signals from a large number of associative memory sub-blocks can be efficiently encoded in successive cycles. Further, according to the encoding circuit of the illustrated example, a buffer such as a prefetch circuit is not required, the area occupied on the chip can be reduced, and power consumption can be reduced.
[0249]
  As described above, the coding circuit with a prefetch circuit, which is a premise for understanding the coding circuit applied to the content addressable memory device of the present invention, and the premise for understanding the coding circuit applied to the content addressable memory device of the present invention. The semiconductor integrated circuit and the encoding circuit with the prefetch circuit and the flag data sense circuit using this as a timing control circuit are basically configured as described above, but these are not limited to the above-described embodiments. Absent. In other words, the timing circuit is applied to an encoding circuit of a content addressable memory (CAM) and is not limited to the one that detects the last one hit signal in advance, and any number of hit signals may be detected. The applied circuit may also be a memory encoding circuit such as SRAM or DRAM. The timing control circuit includes dummy circuits, but these dummy circuits are not necessarily provided. Further, the timing control circuit detects the number of hit signals ‘1’ held in the flag register 18, but may detect the number of signals ‘0’. Further, the timing control circuit detects the discharge of the signal line by the current driving unit to which the hit signal “1” is input, but conversely, the charge control by the current driving unit may be detected at the detection timing. . In this case, the difference current detection means can be configured to detect the difference current not by lowering the potentials of the two signal lines but by raising them.
[0250]
In addition, various semiconductor integrated circuits in the illustrated example may be used in combination, and these may be combined with various encoding circuits in the illustrated example.
Further, the semiconductor integrated circuit which is a premise of the present invention is not limited to the one used as the timing control circuit of the encoding circuit, but simply the signal current detection line and the reference current driving means to which at least one current driving means is connected. May be used as a sense amplifier that detects a difference current flowing in a reference current drive line to which the is connected and detects the change timing. Further, it may be used as a sense amplifier for reading a memory such as a DRAM or SRAM.
[0251]
  Next, referring to FIG. 28 and FIG. 29 with reference to the encoding circuit and the semiconductor integrated circuit, which are prerequisites for understanding the encoding circuit applied to the content addressable memory device of the present invention shown in FIGS. The encoding circuit applied to the associative memory device of the present invention will be described in detail.
[0252]
  In the associative memory device to which the encoding circuit of the present invention is applied, when the search for matching between the search data and the contents of each memory word is completed, a hit flag as a result of the match search is stored in a register corresponding to each memory word. . The hit flag stored in the register is logically ORed with all hit flags in each sub-block for each sub-block, and is held in the sub-encoder as a sub-block hit signal for each sub-block.
[0253]
In the sub-encoder, only one sub-block hit signal in the active state is sequentially output as the active state according to the priority among the sub-block hit signals of each sub-block, and the sub-block hit flag corresponding to the priority is set. While being input to the AND circuit for selection, subblock addresses corresponding to the active subblock hit signal are sequentially encoded.
[0254]
Here, under the control of the timing control circuit of the main encoder, the output signal of the AND circuit corresponding to the sub-block hit signal output as only one active state becomes active, and each register of the sub-block corresponding to this AND circuit A switch circuit corresponding to is selected. The hit flag corresponding to the selected switch circuit is output to the detection line, the hit flag output on the detection line is detected by the sense circuit, and detected by the sense circuit by the timing control signal output from the timing control circuit A hit flag is held in the main encoder.
[0255]
In the main encoder, only one hit flag in the active state is sequentially output as the active state in accordance with the priority order among the held hit flags, and the addresses of the memory words corresponding to the hit flag in the active state are sequentially encoded. It becomes.
In this way, in the encoding circuit of the present invention, the address of the memory word corresponding to the hit flag is sequentially output by combining the address of the sub block and the address of the memory word.
[0256]
  The associative memory device to which the encoding circuit of the present invention is applied has a register for storing an empty flag indicating whether the contents of the memory word are valid or invalid to be searched for coincidence. The address of the memory word corresponding to the empty flag can be sequentially output in the same manner as in the case of outputting the address of the memory word corresponding to the hit flag.
[0257]
  Hereinafter, an encoding circuit applied to an associative memory device of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0258]
  FIG. 28 is a schematic diagram of an embodiment of an associative memory block to which the encoding circuit of the present invention is applied.
  In the figure, first, an associative memory block (hereinafter referred to as a memory block) 30 includes a plurality of associative memory sub-blocks (hereinafter referred to as sub-blocks) 32 (B₁ , B₂ , ..., B_n ). Each sub-block 32 includes a plurality of associative memory words (hereinafter referred to as memory words) 34 (W₀, W₁ , ..., W_m ) And a register 36a (R for holding the hit flag of each memory word 34 for each memory word 34)_0a, R_1a, ..., R_ma), And a register 36b (R for holding the empty flag of each memory word 34 for each memory word 34)_0b, R_1b, ..., R_mb).
[0259]
Here, the hit flag indicates the result of the match search between the contents of each memory word 34 and the search data, and is held in the register 36a corresponding to each memory word 34 after the match search. In this embodiment, it is assumed that the hit flag is, for example, “1” (active state) when they match and “0” (inactive state) when they do not match.
[0260]
The empty flag indicates whether the content of the memory word 34 is valid to be searched or invalid that is not to be searched. For example, the content of the memory word 34 is erased. Sometimes, or when new data is written to the memory word 34, it is held in the register 36b corresponding to each memory word 34. Here, for example, the empty flag is “0” (inactive state) when valid data is held in the memory word 34, for example, “1” when the content of the memory word 34 is erased. (Active state).
[0261]
Although not shown, each sub-block 32 takes an OR of hit flags of all memory words 34 in each sub-block 32 and outputs this as a sub-block hit signal, and An OR circuit that takes the logical sum of the empty flags of all the memory words 34 in each sub-block 32 and outputs it as a sub-block empty signal is provided. The block empty signal is held in data latch circuits of two sub-encoders described later.
The memory block 30 is basically as described above.
[0262]
Next, the encoding circuit 10a includes a main priority encoder (hereinafter referred to as main encoder) 12a that encodes the address of the memory word 34, and two sub priority encoders (hereinafter referred to as sub encoders) that encode the address of the sub block 32. 14a and 14b, and a switch circuit (switching circuit) 124 (S) for selectively outputting hit flags or empty flags (hereinafter collectively referred to as flag data) of the sub-block 32 having the highest priority._0a, S_1a, ..., S_na), 125 (S_0b, S_1b, ..., S_nb), Sense circuit 126 (C₀, C₁, ..., C_m), OR circuit 127 and AND circuit (selection circuit) 128 (A_1a, A_2a, ..., A_na), 129 (A_1b, A_2b, ..., A_nb).
[0263]
In the encoding circuit 10a, the main encoder 12a includes a flag register circuit 18, a main priority circuit 20, a main encoding circuit 22, and a timing control circuit 60a.
[0264]
Here, the flag register circuit 18 holds (m + 1) pieces of flag data output from the sub-block 32 having the highest priority. Of the flag data held in the flag register circuit 18, the address of the memory word 34 corresponding to the flag data in the active state is sequentially encoded. After completion of encoding, the flag data is reset to the inactive state, and after the addresses of the memory word 34 corresponding to all the flag data in the active state are encoded, the flag register circuit 18 stores the next priority sub-data. (M + 1) pieces of flag data of the block 32 are held. The flag register circuit 18 may be anything as long as it can temporarily hold (m + 1) 1-bit data and reset the data for each bit. For example, a latch or a register may be used. it can.
[0265]
The main priority circuit 20 receives (m + 1) pieces of flag data held in the flag register circuit 18 and outputs, for example, only the flag data in the active state having the highest priority as the active state. After only the flag data in the active state having the highest priority is output as the active state, the flag data of the flag register circuit 18 output as the active state is reset to the inactive state, and thereafter held in the flag register circuit 18 in the same manner. For all the flag data in the active state, only one flag data is sequentially output as the active state. The main priority circuit 20 may have a configuration in which priority circuit elements are arranged in a line as shown in FIG. 2, for example. Alternatively, as shown in FIGS. It may be a configuration with a specific arrangement.
[0266]
For example, as shown in FIG. 2, the main encoding circuit 22 is a memory word corresponding to the flag data of the highest priority order in which only one of the flag data output from the main priority circuit 20 is active. 34 addresses are encoded. The main encoding circuit 22 is not particularly limited as long as it can encode the address of the memory word 34 corresponding to only one flag data in the active state, and a conventionally known one is used. be able to.
[0267]
The timing control circuit 60a stores the number of flag data in the active state that has not yet been encoded among the flag data held in the flag register circuit 18, for example, flag data in the active state that has not yet been encoded. Detecting that it is the last one, outputting the output signals CS1 and CS2 and the timing control signal, and causing the flag register circuit 18 to hold (m + 1) flag data of the next priority sub-block It is. The timing control circuit 60a may have any configuration illustrated in FIGS. 10, 12, 15, 16, 18, 18, 19, 20, 23, or 26.
[0268]
In the main encoder 12a, of the (m + 1) flag data held in the flag register circuit 18 by the main priority circuit 20, for example, only the flag data in the active state having the highest priority is made active and outputted. The main encode circuit 22 encodes the address of the memory word 34 corresponding to the flag data with the highest priority, which is only in the active state. The encoded flag data of the highest priority active state is reset to the inactive state by the main priority circuit 20, and the flag data of the next priority active state becomes the flag data of the highest priority active state. Similarly, the addresses of the memory words corresponding to the (m + 1) pieces of flag data in the active state held in the flag register circuit 18 are sequentially encoded. The timing control circuit 60a detects that the flag data in the active state that has not been encoded yet is the last one of the (m + 1) flag data held in the flag register circuit 18. Then, the output signals CS1 and CS2 and the timing control signal are output, and (m + 1) pieces of flag data of the next priority sub-block 32 are held in the flag register circuit 18, and the above operation is repeated in the same manner. .
The main encoder 12a is basically as described above.
[0269]
Subsequently, the sub-encoder 14a encodes the address of the sub-block 32 corresponding to the hit flag, and includes a data latch circuit 24a, a sub-priority circuit 26a, and a sub-encoding circuit 28a. Similarly, the sub encoder 14b encodes the address of the sub block 32 corresponding to the empty flag, and includes a data latch circuit 24b, a sub priority circuit 26b, and a sub encode circuit 28b. Since the sub-encoders 14a and 14b have the same configuration and operation except for the difference in sub-block signals held in the data latch circuits 24a and 24b, the sub-encoder 14a is a representative example unless otherwise mentioned. explain.
[0270]
First, the data latch circuit 24a holds a total of n sub-block hit signals output from each sub-block 32.
[0271]
Here, the sub-block hit signal is a result of matching search between the search data and the contents of each memory word 34 of each sub-block 32, and the contents matching the search data are stored in the memory word 34 in each sub-block 32. In this embodiment, for example, when there is a memory word 34 in which the content matched with the search data is stored in the sub-block 32, “1” (active State), “0” (inactive state) when not present. The sub block hit signal is generated by ORing hit flags of all memory words 34 in each sub block 32 by an OR circuit (not shown) in each sub block 32.
[0272]
Of the sub-block hit signals held in the data latch circuit 24a, the addresses of the sub-blocks 32 corresponding to the active sub-block hit signals are sequentially encoded. Of the sub-block hit signals held in the data latch circuit 24a, the address of the sub-block 32 corresponding to the sub-block hit signal in the active state is sequentially encoded, and the sub-block hit signal that has been encoded is set to the inactive state. Reset.
[0273]
The data latch circuit 24b holds a total of n sub-block empty signals output from each sub-block 32.
[0274]
Here, the sub-block empty signal indicates whether or not there is an invalid memory word 34 that is not a search target in the memory word 34 in each sub-block 32. In this embodiment, for example, a sub-block empty signal is used. It is assumed that “1” (active state) is set when there is an invalid memory word 34 not to be searched in the block 32, and “0” (inactive state) when there is no invalid memory word 34. The sub-block empty signal is generated by ORing the empty flags of all the memory words 34 in each sub-block 32 by an OR circuit (not shown) in each sub-block 32.
[0275]
Of the sub-block empty signals held in the data latch circuit 24b, the addresses of the sub-blocks 32 corresponding to the active sub-block empty signals are sequentially encoded. Of the sub-block empty signals held in the data latch circuit 24b, the address of the sub-block 32 corresponding to the sub-block empty signal in the active state is sequentially encoded, and the sub-block empty signal that has been encoded is set to the inactive state. Reset.
[0276]
The data latch circuits 24a and 24b may be anything as long as they can temporarily hold n pieces of 1-bit data and can reset each bit. For example, a latch or a register can be used.
[0277]
The sub-priority circuits 26a and 26b and the encoding circuits 28a and 28b basically have the main priority circuit 20 and the main encoder 12a of the main encoder 12a except that the number of units constituting each is n instead of (m + 1). Since it has the same configuration and operation as the encoding circuit 22, detailed description thereof is omitted here.
[0278]
In the sub-encoder 14a, of the n sub-block hit signals held in the data latch circuit 24a by the sub-priority circuit 26a, for example, only the sub-block hit signal in the active state with the highest priority is made active and output. Then, the sub-encoding circuit 28a encodes the address of the sub-block 32 corresponding to the highest-priority sub-block hit signal in which only one is activated. The encoded highest priority active sub-block hit signal is reset to the inactive state by the sub-priority circuit 26a, and the next highest priority active sub-block signal becomes the highest priority active sub-block signal. In the same manner, the addresses of the sub-blocks 32 corresponding to the n active sub-block hit signals held in the data latch circuit 24a are sequentially encoded.
The sub-encoders 14a and 14b are basically as described above.
[0279]
Next, switch circuits 124 and 125, a sense circuit 126, an OR circuit 127, and AND circuits 128 and 129 for selectively outputting flag data of the highest priority sub-block 32, which is the most characteristic part of the present invention. Will be described.
[0280]
First, the switch circuit 124 has (m + 1) hit flags output from the registers 36a of the sub-block 32 with the highest priority in the detection line provided in common for the same memory word 34 of each sub-block 32. L (L₀, L₁, ..., L_m) For outputting to the detection line L corresponding to the memory word 34. Each switch circuit 124 is provided in a one-to-one correspondence with each register 36a of each sub-block 32, and has two N-type MOS transistors (hereinafter referred to as NMOS) 124a and 124b connected in series. A hit flag, which is an output of the register 36a, is input to the gate of the NMOS 124b, and its source is connected to the ground. The output signal of the AND circuit 128 is input to the gate of the NMOS 124a, and the drain thereof is connected to the detection line L corresponding to each memory word 34.
[0281]
In the switch circuit 124, when the hit flag is “1” and the output signal of the AND circuit 128 is “1”, both the NMOSs 124a and 124b are turned on, and the charge precharged to the detection line L is The output signal of the AND circuit 128 is discharged through the NMOSs 124a and 124b of the (m + 1) switch circuits 124 input to the gate of the NMOS 124a. On the other hand, when at least one of the hit flag and the output signal of the AND circuit 128 is “0”, at least one of the NMOS 124a and the NMOS 124b is turned off, so that the level of the detection line L remains in a precharged state. The That is, the detection line L is set to the inversion level of the hit flag input to the (m + 1) switch circuits 124 by the (m + 1) switch circuits 124 selected by the AND circuit 128 whose output signal is “1”. Become.
[0282]
The switch circuit 125 is for outputting (m + 1) empty flags output from the registers 36b of the highest priority sub-block 32 to the detection line L corresponding to the memory word 34. Note that since the configuration and operation of the switch circuit 125 are the same as those of the switch circuit 124, detailed description thereof is omitted here.
[0283]
Subsequently, the sense circuit 126 detects the level of the hit flag output to the detection line L by the switch circuit 124 or the level of the empty flag output to the detection line L by the switch circuit 125. Each sense circuit 126 is provided in a one-to-one correspondence with the detection line L, and two P-type MOS transistors (hereinafter referred to as PMOS) 126a, connected in parallel between the power source and the detection line L, 126b and an inverter 126c. The output signal of the OR circuit 127 is input to the gate of the PMOS 126a, and the output signal of the inverter 126c is input to the gate of the PMOS 126b. Further, the detection line L is input to the inverter 126c, and the output of the inverter 126c is input to the flag register circuit 18 of the main encoder 12a.
[0284]
In the sense circuit 126, when the output signal of the OR circuit 127 is “0”, the PMOS 126a is turned on, and all the detection lines L are precharged via the PMOS 126a. The level of the detection line L is inverted by the inverter 126c. When the output signal of the inverter 126c becomes “0”, the PMOS 126b is turned on, and the level of the detection line L is charged up via the PMOS 126b, and even after the output signal of the OR circuit 127 becomes “1”. It is held at “1”. If the detection line L is discharged by either the switch circuit 124 or the switch circuit 125 after the output signal of the OR circuit 127 becomes “1”, the output signal of the inverter 126c becomes “1” and the PMOS 126b is turned off. The charge-up to the detection line L is stopped. As a result, the charge precharged to the detection line L is discharged through either the switch circuit 124 or the switch circuit 125, and the output signal of the inverter 126c becomes ‘1’. On the other hand, when the detection line L is not discharged and remains in the precharged state, the output signal of the inverter 126c maintains the state of “0”. That is, the output signal of the inverter 126c, which is the output signal of the sense circuit 126, is the flag data input to the (m + 1) switch circuits 124 or the switch circuit 125 selected by the AND circuit 128 whose output signal is “1”. Equal level.
[0285]
The OR circuit 127 calculates a logical sum of the output signals CS1 and CS2 of the timing control circuit 60a of the main encoder 12a. The output signal of the OR circuit 127 becomes “0” when the output signals CS1 and CS2 of the timing control circuit 60a are both “0”, and the on / off of the PMOS 126a of all the sense circuits 126 is controlled.
[0286]
The AND circuit 128 calculates a logical product of the output signal CS1 of the timing control circuit 60a of the main encoder 12a and the output signal of the sub-priority circuit 26a of the sub-encoder 14a, and corresponds to each sub-block 32 on a one-to-one basis. Is provided. The output signal of the AND circuit 128 becomes “1” when the output signal CS1 of the timing control circuit 60a is “1” and the output signal of the sub-priority circuit 26a is “1”. (M + 1) switch circuits 124 are selected.
[0287]
The AND circuit 129 calculates a logical product of the output signal CS2 of the timing control circuit 60a of the main encoder 12a and the output signal of the sub priority circuit 26b of the sub encoder 14b. Since the configuration and operation of the AND circuit 129 are the same as those of the AND circuit 128, a detailed description thereof is omitted here.
[0288]
  Next, the operation of the encoding circuit applied to the associative memory device of the present invention will be described.
[0289]
When the match search between the search data and the contents of each memory word 34 of each sub-block 32 is completed, a hit flag is stored in each register 36 a corresponding to each memory word 34. The hit flag stored in the register 36a is logically ORed with the hit flag corresponding to all the memory words 34 for each subblock 32 by an OR circuit (not shown) in each subblock 32. A total of n sub-block hit signals output from 32 are held in the data latch circuit 24a of the sub-encoder 14a.
[0290]
In the sub-encoder 14a, of the n sub-block hit signals held in the data latch circuit 24a, only one sub-block hit signal is sequentially output as '1' in the active state according to the priority order. While being input to the AND circuit 128, the addresses of the sub blocks 32 corresponding to the sub block hit signals in the active state are sequentially encoded.
[0291]
Here, the output signal CS1 of the timing control circuit 60a of the main encoder 12a becomes “1”, and the output signal of the AND circuit 128 corresponding to the sub-block hit signal outputted as only one active state becomes “1”. The (m + 1) switch circuits 124 of the sub-block 32 corresponding to the AND circuit 128 are selected. By the selected switch circuit 124, the inversion level of the hit flag is output to the detection line L, inverted by the sense circuit 126 to be equal to the hit flag, and then the timing control signal output from the timing control circuit 60a. The (m + 1) hit flags on the detection line L are stored in the flag register circuit 18 of the main encoder 10a.
[0292]
In the main encoder 12a, only one hit flag is sequentially output as “1” in an active state according to the priority order, and the addresses of the memory words 34 corresponding to the hit flag in the active state are sequentially encoded. .
[0293]
  In the encoding circuit applied to the content addressable memory device of the present invention, the hit flag is set by combining the address of the sub block 32 output from the sub encoder 14a and the address of the memory word 34 output from the main encoder 12a. Are sequentially output as addresses of memory words corresponding to.
  The encoding circuit applied to the content addressable memory device of the present invention basically operates as described above.
[0294]
In the above embodiment, the case where the address of the memory word 34 corresponding to the hit flag is output has been described as an example. However, in the system using the associative memory, the use efficiency of the memory word 34 is improved to the maximum. Therefore, as a result of the match search, the contents of the plurality of memory words 34 that match the search data are retained, and the contents of the memory words 34 that did not match are erased, and new ones are sequentially added to the locations of the erased memory words 34. The operation of updating the contents of the memory word 34 is frequently performed by writing data.
[0295]
However, the problem at this time is that the address of the memory word 34 from which the contents are erased is randomly generated as described in the section of the prior art, so that the address of the invalid memory word 34 from which the contents are erased is managed. It is difficult.
[0296]
  In order to solve this problem, in the encoding circuit applied to the associative memory device of the present invention, first, a register 36b for storing an empty flag having the same configuration as the register 36a for storing a hit flag is provided. ing. As a result, in the same manner as when the address of the memory word 34 corresponding to the hit flag is output, the address of the invalid memory word 34 corresponding to the empty flag can be sequentially output according to the priority order. There is an advantage that the management of the memory word 34 is easy. Whether to encode the address corresponding to the hit flag or the address corresponding to the empty flag is determined by the output signals CS1 and CS2 of the timing control circuit 60a. That is, an address corresponding to the hit flag is encoded by the output signal CS1, and an address corresponding to the empty flag is encoded by the output signal CS2.
[0297]
  Further, as a result of the match search, it is necessary to output the address of the memory word 34 in which data matching the search data is stored, and to write an invalid memory word 34 address in order to write new data. Sometimes it is generally different. Based on this, in the encoding circuit applied to the associative memory device of the present invention, the detection line L to which the hit flag and empty flag are output is shared. Thereby, the layout area of the associative memory is reduced, and there is an advantage that a high-density associative memory can be formed.
[0298]
In addition, regarding the encoding of the address corresponding to the hit flag, there is a further demand for higher output. On the other hand, the main priority circuit 20 and the sub-priority circuit 26a are unnecessary under the limitation (use condition) that only the hit flag corresponding to only one memory word 34 becomes active as a result of the match search, for example. When encoding the address corresponding to the hit flag, it is expected that the operation speed of the main priority circuit 20 and the sub-priority circuit 26a is not functioned so that the operation speed is improved by about twice as compared with the conventional one. Can do.
[0299]
Here, FIG. 29 shows a code of the present invention adapted to increase the operation speed under the limitation that only the hit flag corresponding to only one memory word becomes active as a result of the match search. FIG. 3 shows a schematic diagram of another embodiment of a circuit.
The encoding circuit 10b in the illustrated example is different from the encoding circuit 10a shown in FIG. 28 in that the main encoder 12b has a select circuit 21, the timing control circuit 60b outputs an output signal CS3, and , Except that the OR circuit 130 is provided between the sub-encoder 14a and the AND circuit 128, the same components other than these three points are denoted by the same reference numerals, and detailed description thereof will be given here. Is omitted.
[0300]
That is, the encoding circuit 10b includes a main encoder 12b, sub-encoders 14a and 14b, switch circuits 124 and 125, a sense circuit 126, an OR circuit 127, an AND circuit 128, and an OR circuit 130 (O₁, O₂, ..., O_n).
[0301]
In the encoding circuit 10b, first, the main encoder 12b includes a flag register circuit 18, a main priority circuit 20, a select circuit 21, a main encode circuit 22, and a timing control circuit 60b.
[0302]
Here, the select circuit 21 selectively outputs either the flag data held in the flag register circuit 18 or the flag data output from the main priority circuit 20 under the control of the output signal CS3 of the timing control circuit 60b. Is. In the illustrated example, the select circuit 21 selectively outputs flag data output from the main priority circuit 20 when the output signal CS3 is “0”, and the main priority circuit 20 when the output signal CS3 is “1”. And the flag data held in the flag register circuit 18 is selectively output. That is, when the output signal CS3 of the timing control circuit 60b is ‘1’, the main priority circuit 20 is bypassed, and the flag data held in the flag register circuit 18 is directly input to the main encoding circuit 22.
[0303]
The timing control circuit 60b basically has the same function as the timing control circuit 60a shown in FIG. 28 except that the output signal CS3 is generated.
[0304]
Here, for example, in a network environment in which a plurality of computers are connected, each computer is uniquely identified by being given a unique network address. In a device such as a switching hub, for example, the network address of each computer and the port number of the switching hub to which the computer is connected are stored in each memory word of the associative memory, and the packet output from the transmission source computer A match search is performed using the network address of the receiving computer present in the header of the data, and the port number of the switching hub to which the receiving computer is connected is obtained. In this way, for example, when managing network addresses, the network address unique to each computer is stored in the memory word of the associative memory. Therefore, as a result of matching search, only the hit flag corresponding to one memory word is stored. A usage condition occurs that becomes active.
[0305]
As described above, the output signal CS3 output from the timing control circuit 60b is subject to the limitation (usage condition) that only the hit flag corresponding to one memory word becomes active as a result of the match search, and “1” is output only when an address corresponding to only one hit flag in the active state is encoded, and “0” is output in other cases.
[0306]
As described above, the address corresponding to only one hit flag in the active state is encoded under the limitation that only the hit flag corresponding to only one memory word is in the active state as a result of the match search. Sometimes, by setting the output signal CS3 output from the timing control circuit 60b to “1”, the hit flag held in the flag register circuit 18 of the main encoder 12b bypasses the main priority circuit 20 and the main encoding circuit 22 The address of the memory word 34 corresponding to the hit flag is encoded. For this reason, the delay due to the signal processing of the main priority circuit 20 can be eliminated, and the encoding of the address corresponding to the hit flag can be speeded up. The operation when the output signal CS3 is "0" is exactly the same as the operation of the encoding circuit 10a of the present invention shown in FIG.
[0307]
Subsequently, the OR circuit 130 calculates a logical sum of the output signal CS3 of the timing control circuit 60b of the main encoder 12b and the output signal of the sub priority circuit 26a of the sub encoder 14a, and corresponds to each sub block 32. Is provided. The output signal of the OR circuit 130 becomes ‘1’ when at least one of the output signal CS3 of the timing control circuit 60b or the output signal of the sub-priority circuit 26a is ‘1’. That is, by setting the output signal CS3 of the timing control circuit 60b to “1”, the output signal of the OR circuit 130 can be set to “1” regardless of the output signal of the sub-priority circuit 26a.
[0308]
By adding the OR circuit 130, the AND circuit 128 calculates the logical product of the output signal CS1 of the timing control circuit 60b and the output signal of the OR circuit 130. The output signals of the AND circuits 128 are all output signals of the AND circuits 128 regardless of the output signal of the sub-priority circuit 26a when both the output signal CS1 and the output signal CS3 of the timing control circuit 60b are “1”. 1 'and all switch circuits 124 of all sub-blocks 32 are selected simultaneously. The operation of the AND circuit 128 when the output signal CS3 is “0” is exactly the same as the operation of the AND circuit 128 in the encoding circuit 10a shown in FIG.
[0309]
As described above, the address corresponding to only one hit flag in the active state is encoded under the limitation that only the hit flag corresponding to only one memory word is in the active state as a result of the match search. Sometimes, by setting both the output signal CS1 and the output signal CS3 of the timing control circuit 60b to "1", the output signal of the sub-priority circuit 26a is invalidated and the output signals of all the AND circuits 128 are set to "1". be able to. As a result, the hit flag in only one active state is immediately output to the detection line L, and the address of the memory word 34 corresponding to this hit flag is encoded. For this reason, an internal delay due to signal processing in the sub-encoder 14a can be eliminated, and the encoding of the address corresponding to the hit flag can be speeded up.
[0310]
Hereinafter, the operation of the encoding circuit 10b will be briefly described.
In the encoding circuit 10b, as a result of the match search, the hit flag is stored in each register 36a corresponding to each memory word 34.
[0311]
The hit flags stored in the respective registers 36a are logically ORed with all hit flags for each sub-block 32, and used as a sub-block hit signal for each sub-block 32. Here, as a result of the match search, only one sub-block hit signal is in an active state under the limitation that only a hit flag corresponding to one memory word is in an active state. The address of the sub-block 32 corresponding to the sub-block hit signal which is only one active state is encoded.
[0312]
On the other hand, after the hit flag is stored in each register 36a, both the output signal CS1 and the output signal CS3 of the timing control circuit 60b of the main encoder 12b are set to “1”, and the output of the sub priority circuit 26a of the sub encoder 14a. Regardless of the signal, the output signals of all the AND circuits 128 become “1”, and all the switch circuits 124 are simultaneously selected. Thus, regardless of the internal operation of the sub-encoder 14a, the hit flag is immediately output to the detection line L, and the address of the memory word 34 corresponding to the hit flag which is only one active state is encoded in the main encoder 12b. The
[0313]
From the encoding circuit 10b, the memory word corresponding to the hit flag which is only one active state is obtained by combining the address of the sub block output from the sub encoder 14a and the address of the memory word output from the main encoder 12b. Is output.
[0314]
In the above embodiment, as a result of the matching search, only the hit flag corresponding to only one memory word becomes active, and the address corresponding to only one hit flag is encoded. The operation of the encoding circuit 10b of the present invention has been described by taking as an example the case of the encoding, but other operations are the same as those of the encoding circuit 10a of the present invention shown in FIG.
[0315]
As described above, according to the encoding circuit 10b of the present invention, the main priority circuit 20 of the main encoder 12b is limited under the limitation that only the hit flag corresponding to only one memory word is activated as a result of the match search. Since both the internal processing in FIG. 5 and the internal processing in the sub-priority circuit 26a of the sub-encoder 14a can be omitted, the encoding of the address of the memory word 34 corresponding to the hit flag can be speeded up. As described above, the limitation that only the hit flag corresponding to only one memory word becomes active as a result of the matching search is quite natural, for example, when managing a network address using an associative memory. Under this limitation, the speed of encoding of the address of the memory word 34 corresponding to the hit flag is very high for a user who wants to speed up the encoding of the address of the memory word 34 corresponding to the hit flag. This is desirable.
[0316]
However, with respect to the encoding of the address corresponding to the empty flag, the presence of a plurality of invalid memory words 34 in the same device of the associative memory is very likely to occur. Needless to say, 20 and the sub-priority circuit 26b cannot be omitted, and it is necessary to perform encoding after the processing by the main priority circuit 20 and the sub-priority circuit 26b.
[0317]
Although the encoding circuit of the present invention has been described in detail above, the present invention is not limited to the above embodiment.
[0318]
For example, the encoding circuits 10a and 10b of the present invention shown in FIGS. 28 and 29 are obtained by applying the present invention to the encoding circuit 120 shown in FIG. 24. Of course, the encoding circuits shown in FIGS. 10 and 11 are also applicable.
[0319]
In the above embodiment, when encoding the hit flag of the memory word, an example in which only one memory word hits and a case where a plurality of memory words hit is switched by the output signal CS3 and controlled. showed that. That is, the sub-priority circuit 26a is provided in the sub-encoder 14a in order to support the both functions and encode the hit flag. However, the present invention is not limited to this, and only one hit flag is always active. If it is limited to the case where it does not become a state, this subpriority circuit 26a becomes unnecessary, and a semiconductor chip with higher area efficiency can be designed.
[0320]
In the encoding circuits 10a and 10b of the present invention shown in FIGS. 28 and 29, the sub-encoder 14a encodes the address of the sub-block 32 corresponding to the sub-block hit signal, and the sub-encoder 14b generates the sub-block empty. Although an example in the case of encoding the address of the sub-block 32 corresponding to the signal has been shown, the present invention is not limited to this. For example, the sub-block hit signal or the sub-block empty signal is shared by sharing one sub-encoder. The address of the sub-block 32 corresponding to either one may be selectively encoded, or one data latch circuit is shared by the sub-block hit signal and the sub-block empty signal in the sub-encoders 14a and 14b. Or one sub-encoding It may be or share the circuit.
[0321]
Also, in applications where only one hit flag is always active, the select circuit 21 is omitted and a main encoder dedicated to the empty flag and a main encoder dedicated to the hit flag are provided separately for faster encoding. Is also possible. In this case, the main priority circuit 20 is not required for a main encoder dedicated to hit flags, in which only one hit flag is always active.
[0322]
In the above embodiment, the case where the address of the memory word corresponding to the hit flag in the active state is encoded has been described as an example. However, the present invention is not limited to this, for example, the hit flag in the inactive state It is also possible to encode the address of the memory word corresponding to, and similarly, the address of the memory word corresponding to the empty flag in the active state and inactive state can be encoded.
[0323]
In the above embodiment, the case where the two registers 36a and 36b for holding flag data are provided has been described as an example. However, the present invention is not limited to this. For example, the address of the memory word 34 corresponding to the hit flag. Is not necessarily provided, the register 36a for holding the hit flag is not necessarily provided, and only the register 36b for holding the empty flag may be provided. Thereby, the layout area of the associative memory can be further reduced.
[0324]
The associative memory device to which the encoding circuit of the present invention is applied may have a static circuit configuration having a register 36a for holding a hit flag and a register 36b for holding an empty flag, or a register It may have a dynamic circuit configuration without 36a and 36b.
[0325]
Also, the number and configuration of inputs of the prefetch circuit, data latch circuit, priority circuit, and encoding circuit that constitute the main encoder and sub encoder, and various combinations of circuit elements including PchMOS transistors and NchMOS transistors can be combined. Alternatively, flag data that has been encoded by the priority circuit is not reset to be in an inactive state. For example, an invalidation bit flag circuit corresponding to the flag register circuit is provided so that the priority circuit can encode the flag data. By setting the bit of the invalidation bit flag circuit corresponding to the completed flag data, it is possible to inactivate the flag data that has been encoded by the priority circuit, so that it does not depart from the gist of the present invention. To range There are, of course possible to make various improvements and modifications.
[0326]
【The invention's effect】
  As described in detail above, according to the encoding circuit applied to the associative memory device of the present invention, it is possible to sequentially output the addresses of invalid memory words corresponding to the empty flag according to the priority order. Easy management of invalid memory words. In the encoding circuit applied to the associative memory device of the present invention, since the detection lines for outputting the hit flag and the empty flag are shared, the layout area of the associative memory device is reduced, and a high-density associative memory is configured. can do.
  Further, according to the encoding circuit applied to the associative memory device of the present invention, under the limitation (usage condition) that only the hit flag corresponding to only one memory word becomes active as a result of matching search, Since the internal processing of the main priority circuit of the main encoder and the sub priority circuit of the sub encoder can be omitted, the encoding of the address of the memory word corresponding to the hit flag can be speeded up.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of an encoding circuit as a premise for understanding an encoding circuit applied to an associative memory device of the present invention and an associative memory block to which the encoding circuit is applied.
FIG. 2 is a configuration diagram of an embodiment of a priority-added encoding circuit with a prefetch circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the associative memory device of the present invention.
FIG. 3 is a configuration diagram of an embodiment of a priority sub-block encoding circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention;
FIG. 4 is a configuration diagram of an embodiment of a prefetch circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention.
FIG. 5 is a configuration diagram of another embodiment of a priority circuit and an encoding circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention.
6A, 6B, and 6C are schematic configuration diagrams of an embodiment of a small unit priority circuit used in the priority circuit shown in FIG.
7 is a configuration diagram of one embodiment of a logical operation circuit used in the small unit priority circuit shown in FIG. 5; FIG.
FIG. 8 is a configuration diagram of another embodiment of an encoding circuit as a premise for understanding an encoding circuit applied to an associative memory device of the present invention and an associative memory block to which the encoding circuit is applied;
FIG. 9 is a configuration diagram of another embodiment of a prioritized encoding circuit with a prefetch circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention. .
FIG. 10 is a configuration diagram of an embodiment of a timing control circuit used in an encoding circuit which is a premise for understanding the encoding circuit applied to the associative memory device of the present invention.
FIG. 11 is a time chart showing timings of respective parts of a priority-added encoding circuit with a prefetch circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention. .
FIG. 12 is a configuration diagram of another embodiment of a timing control circuit which is a semiconductor integrated circuit which is a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention.
FIG. 13 shows the timing of each part of a coding circuit with priority with a prefetch circuit of a coding circuit to which a semiconductor integrated circuit as a premise for understanding the coding circuit applied to the content addressable memory device of the present invention is applied. It is a time chart which shows.
14A and 14B are graphs showing detection results of the timing circuits shown in FIGS. 12 and 10, respectively.
FIG. 15 is a configuration diagram of another embodiment of a timing control circuit which is a semiconductor integrated circuit which is a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention.
FIG. 16 is a configuration diagram of another embodiment of a timing control circuit which is a semiconductor integrated circuit which is a premise for understanding an encoding circuit applied to an associative memory device of the present invention.
FIGS. 17A and 17B are graphs showing detection results of the timing circuits shown in FIGS. 15 and 10, respectively.
FIG. 18 is a configuration diagram of another embodiment of a timing control circuit to which a semiconductor integrated circuit as a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention is applied.
FIG. 19 is a configuration diagram of another embodiment of a timing control circuit to which a semiconductor integrated circuit as a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention is applied.
FIG. 20 is a configuration diagram of another embodiment of a timing control circuit to which a semiconductor integrated circuit as a premise for understanding an encoding circuit applied to the associative memory device of the present invention is applied.
FIG. 21 is a configuration diagram of another embodiment of a timing control circuit to which a semiconductor integrated circuit as a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention is applied;
FIG. 22 shows a configuration of an embodiment of a sub-block encoding circuit component with priorities of an encoding circuit to which a semiconductor integrated circuit as a premise for understanding the encoding circuit applied to the associative memory device of the present invention is applied. FIG.
FIG. 23 is a configuration diagram of another embodiment of a timing control circuit which is a semiconductor integrated circuit which is a premise for understanding an encoding circuit applied to the content addressable memory device of the present invention.
FIG. 24 is a configuration diagram of an embodiment of an encoding circuit as a premise for understanding an encoding circuit applied to an associative memory device of the present invention and an associative memory block to which the encoding circuit is applied.
FIG. 25 is a configuration diagram of an embodiment of a prioritized encoding circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention.
FIG. 26 is a configuration diagram of an embodiment of a timing control circuit used in an encoding circuit as a premise for understanding the encoding circuit applied to the associative memory device of the present invention.
FIG. 27 is a timing chart for explaining the operation of the encoding circuit as a premise for understanding the encoding circuit applied to the content addressable memory device of the present invention;
FIG. 28 is a block diagram of an embodiment of an encoding circuit of the present invention and an associative memory block to which the encoding circuit is applied.
FIG. 29 is a configuration diagram of another embodiment of the encoding circuit of the present invention and an associative memory block to which the encoding circuit is applied.
FIG. 30 is an overall configuration diagram of an associative memory device to which a conventional encoding circuit is applied.
FIG. 31 is an overall configuration diagram of an associative memory block to which a conventional encoding circuit is applied.
[Explanation of symbols]
  10, 10a, 10b, 11, 120 Coding circuit
  12, 12a, 12b, 122, 212 Main priority encoder
  14, 14a, 14b, 214 Sub-block priority encoder
  16 Prefetch circuit
  18, 24, 24a, 24b Data latch circuit
  20 Main priority circuit
  21 Select circuit
  22 Main encoding circuit
  26, 26a, 26b Sub-priority circuit
  28, 28a, 28b Sub-encoding circuit
  30,202 associative memory block
  32,204 associative memory sub-block
  34 associative memory words
  36, 36a, 36b registers
  40,188 priority circuit elements
  42, 49, 84, 102a, 102b, 104a, 104b, 108a, 108b, 126c, 170, 172 Inverter
  44, 52, 69a, 69b, 69c, 69d, 75a, 75b, 75c, 75d, 77a, 77b, 77c, 77d, 82a, 82b, 103a, 103b, 109a, 109b, 124a, 124b, 163, 164 N-channel MOS Transistor
  46, 80a, 80b, 86, 126a, 126b, 168 P-channel MOS transistor
  48 logic operation circuit
  48b, 88, 128, 129, 166 AND circuit
  48a EXOR gate
  50,192 Address line
  54 Gate circuit
  60, 60a, 60b, 61, 90, 92, 100, 106, 110, 112, 116, 178 Timing control circuit
  62 Signal current detection line
  64 Reference current drive line
  66 Current drive circuit
  67a, 67d control transistor
  67b, 67c Signal voltage application transistor
  68 Reference current drive circuit
  70 Differential current detection circuit
  72 Precharge control signal line
  74,76 Dummy circuit
  78,83 Precharge transistor
  79 Equipotential transistor
  85 Output terminal
  87 Pulse circuit
  114, 127, 130 OR circuit
  118 Reference current control register
  124, 125, 160 switch circuit
  126 sense circuit
  162 Precharge circuit
  165 detection line
  167 Block selection line
  169 Precharge signal line
  174, 175 Latch signal line
  176 Control signal line
  180 priority circuit
  182, 184, 186 Small unit priority circuit
  190 Encoding circuit
  200 associative memory
  206 CAM subarray
  208 Hit signal register
  210 priority encoder

Claims (16)

A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder ,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit And an end detection means for detecting that the conversion is complete .
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder ,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed Has a disable bit flag circuit, and an end detection means for encoding the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit detects that it has completed showing,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder ,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit Timing control means for detecting in advance the timing at which all the conversion ends, and holding the hit flag or the empty flag of the next priority detected by the sense circuit in the flag register circuit ,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block; a switch circuit for outputting each of the hit flag or empty flag output from the associative memory sub-block selected by the selection circuit to a corresponding detection line; and each of the detections Output on line A sense circuit for detecting the hit flag or the empty flag, and the addresses of the memory words corresponding to the hit flag or the empty flag detected by the sense circuit are sequentially encoded according to the priority order. A main priority encoder ,
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed The timing of the end of the encoding of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit is detected in advance and detected by the sense circuit. Timing control means for causing the flag register circuit to hold the hit flag or the empty flag of the next priority ,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit for pre-holding the hit flag or the empty flag of the next priority output on the detection line while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities ;
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit And an end detection means for detecting that the conversion is complete .
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit for pre-holding the hit flag or the empty flag of the next priority output on the detection line while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities ;
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed Has a disable bit flag circuit, and an end detection means for encoding the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit detects that it has completed showing,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit for pre-holding the hit flag or the empty flag of the next priority output on the detection line while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities ;
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit; Reset means for sequentially resetting the hit flag or the empty flag after encoding in the flag register circuit, and the sign of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit Timing control means for detecting in advance the timing at which all the conversion ends, and holding the hit flag or the empty flag of the next priority detected by the sense circuit in the flag register circuit ,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. A plurality of CAM subblock, each of said content addressable memory subblocks, and a plurality of memory words, in one-to-one correspondence to each said memory words, and the contents of the memory words of the search data and each A first register that holds a hit flag that is a match search result, and a second register that holds an empty flag indicating whether or not the contents of each of the memory words are valid search targets An encoding circuit applied to an associative memory device having
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, a sub-priority encoder that determines the priority of the associative memory sub-block, and the associative memory sub-corresponding to the sub-block hit signal of the priority determined by the sub-priority encoder or the sub-block empty signal A selection circuit for selecting a block, a switch circuit for outputting each hit flag or empty flag output from the content addressable memory sub-block selected by the selection circuit to a corresponding detection line, and a previous priority The hit of A prefetch circuit for pre-holding the hit flag or the empty flag of the next priority output on the detection line while encoding the address of the memory word corresponding to the lag or the empty flag; A main priority encoder that sequentially encodes the addresses of the memory words corresponding to the hit flags or empty flags of each of the previous priorities held in the prefetch circuit according to the priorities ;
The main priority encoder has a flag register circuit for holding each hit flag or the empty flag, and one of the hit flags or the empty flags held in the flag register circuit according to the priority order. A main priority circuit that sequentially outputs only the hit flag or the empty flag as an active state, and an address of the memory word corresponding to the hit flag or the empty flag that is sequentially output from the main priority circuit. A main encoding circuit that sequentially encodes whether or not the encoding of the address of the memory word corresponding to each of the hit flag or the empty flag held in the flag register circuit is completed The timing of the end of the encoding of the address of the memory word corresponding to the hit flag or the empty flag held in the flag register circuit is detected in advance and detected by the sense circuit. Timing control means for causing the flag register circuit to hold the hit flag or the empty flag of the next priority ,
The main priority encoder further includes a select circuit that selectively outputs either the hit flag held in the flag register circuit or the hit flag output from the main priority circuit to the main encode circuit. Have
The hit flag is directly input from the flag register circuit to the main encoding circuit and encoded without passing through the main priority circuit, and the empty flag is encoded from the flag register circuit through the main priority circuit. An encoding circuit which inputs into a circuit and encodes. Encoding circuit according to claim 1, characterized in that sharing the detecting lines and the empty flag and the hit flag. An encoding circuit according to any one of claims 1 to 9 ,
The main priority encoder further encodes the hit flag by directly inputting the hit flag from the flag register circuit to the main encode circuit without passing through the main priority circuit, or the hit flag is input to the flag register. An encoding circuit comprising: selection means for determining whether to input and encode from the circuit to the main encoding circuit via the main priority circuit. The sub-priority encoder includes a data latch circuit that holds the sub-block hit signal or the sub-block empty signal output from each of the content addressable memory sub-blocks, and each of the sub-block hits held in the data latch circuit. Of the signal or the sub-block empty signal, the sub-priority circuit that sequentially outputs only the one sub-block hit signal or the sub-block empty signal as an active state according to the priority order and the sub-priority circuit sequentially And a sub-encoding circuit that sequentially encodes the addresses of the associative memory sub-blocks corresponding to the sub-block hit signal or the sub-block empty signal in the active state. Encoding circuit as claimed in any one of claim 1 to 10. The sub-priority encoder has a data latch circuit that outputs only one active state of the sub-block hit signal that is output from each of the associative memory sub-blocks, and only one output that is output from the data latch circuit. encoding circuit according to claim 1, characterized in that it comprises a sub-encoder circuit to encode the address of the content addressable memory sub block corresponding to the sub-block hit signal is active. An encoding circuit applied to the associative memory device according to any one of claims 1 to 12 ,
A sub-block hit signal that is a logical sum of all the hit flags in each of the associative memory sub-blocks, or a sub-block empty signal that is a logical sum of all the empty flags in each of the associative memory sub-blocks. Correspondingly, the associative memory sub-block is selected, the sub-encoder for encoding the address, and the detection flag corresponding to each of the hit flag or the empty flag output from the selected associative memory sub-block And a main encoder for encoding an address of the memory word corresponding to each of the hit flag or the empty flag output to the detection line. The main encoder encodes the address of a memory word corresponding to one active hit flag, and sequentially sets only one empty flag in the active state according to the priority order. 14. The encoding circuit according to claim 13 , wherein the address of the memory word corresponding to the empty flag of the state is sequentially encoded. The encoding circuit according to claim 13 , wherein the main encoder has a priority circuit that sequentially outputs only one empty flag as an active state among empty flags in an active state according to priority. The associative memory device includes :
Further, each of the associative memory sub-blocks is provided corresponding to the same memory word, and either the hit flag or the empty flag corresponding to the memory word is output in common. Detection line
16. The encoding circuit according to claim 1, further comprising: a switch circuit that outputs each of the hit flags or each of the empty flags to the corresponding detection line.

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