JP3818807B2 - Signal converter having a dynamically adjustable reference voltage and chipset including the signal converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal converter, and more particularly to a signal converter having a dynamically adjustable reference voltage capable of receiving a foreign digital signal.
[0002]
[Prior art]
In a typical digital circuit, two digital signals having 0V and 5V usually represent two different logic levels. Devices used for digital circuits include TTL devices and CMOS devices. In a digital circuit including a TTL device, the switch speed is fast, but the DC power consumption is large. On the other hand, in a digital circuit including a CMOS device, the DC power consumption is small, but the switch speed is slow and there is a lot of noise. Furthermore, when the operating frequency of the digital circuit is as high as several tens of MHz, electromagnetic interference (EMI: Electro Magnetic Interference) may occur if devices are not properly arranged or separated from each other in the digital circuit.
[0003]
Recently, another electronic signal specification called the Gunning Transceiver Logic (GTL +) specification has been introduced. The magnitude of the GTL + signal is in the range of 0 to 1.5V. In addition, one end of the signal transmission line is electrically connected to a 1.5V power source via a terminator with a resistance of 56Ω, which prevents signal reflection and impedance matching on the printed circuit board (PCB). Used for. Since the size range of the GTL + signal is only 1.5V, a circuit adopting the GTL + signal specification has the advantages of low power consumption, high speed, and the ability to solve the EMI problem.
[0004]
Generally, in a computer system with an operating frequency of several hundred MHz, a central processing unit (CPU) communicates with other devices using a GTL + bus. With reference to FIG. The GTL + bus 130 is used for communication between the two devices 110 and 120. In FIG. 1, the devices 110 and 120 may be a chip set and a CPU on a printed circuit board, respectively. The CPU 120 communicates with the chipset 110 via the GTL + bus 130, which allows the chipset 110 to control other devices (not shown) on the printed circuit board.
[0005]
As shown in FIG. 1, the devices 110 and 120 are electrically connected to each other by a GTL + bus 130 that functions as a transmission line. The device 110 includes an input buffer 114 and an output buffer 112. Using this input buffer 114, a first digital signal such as a GTL + signal received from the GTL + bus 130 is converted into a second digital signal such as a TTL signal that conforms to the signal specifications for the device 110. Using the output buffer 112, a second digital signal such as a TTL signal from the device 110 is converted into a first digital signal such as a GTL + signal, and the first digital signal is further transmitted to the device 120 via the GTL + bus 130. To do. Similarly, the device 120 also includes an input buffer 124 and an output buffer 122, which are used to generate a first digital signal such as a GTL + signal that conforms to the signal specifications of the device 120 and a second digital signal such as a GTL + signal. Signal conversion between.
[0006]
As shown in FIG. 1, each of the devices 110 and 120 is electrically connected to one end of a transmission line 130, and both ends are electrically connected to a power source Vtt via two terminators Rt1 and Rt2. It is connected. The terminators Rt1 and Rt2 not only improve the signal quality, but also can pull the signal potential by an open drain connection employed in the output buffer. However, the state of impedance matching affects the signal quality on the transmission line. In particular, when the transmission rate is fast, ringback occurs on the GTL + signal. Referring to FIG. 2, the waveform in the case of the GTL + bus is shown. The waveform (A) is an ideal waveform, but the waveform (B) is a waveform distorted by the ringback P. If the terminator does not match the impedance of the input / output circuit well, the ringback P becomes even stronger.
[0007]
A conventional input buffer converts a GTL + signal into another logic signal based on a fixed reference voltage. When the potential of the GTL + signal is higher than the reference voltage, the output logic signal is set to the logic level “1”. Conversely, when the potential of the GTL + signal is lower than the reference voltage, the output logic signal is set to the logic level “0”. In general, the reference voltage is set to 1.0V ± 200 mV, but the Vtt is set to 1.5V. If the received ringback is so strong that it exceeds a predetermined reference voltage, a conversion error will occur.
[0008]
Further, since the GTL + bus 130 connected to the chipset 110 has a large number of transmission lines, a plurality of terminators are incorporated in the chipset 110 to reduce the complexity of external circuit design. Thus, the terminator not only affects signal quality, but also increases power consumption. Taking a CPU such as PENTIUM II made by INTEL as an example, when the resistance of each terminator used is 56Ω, the number of transmission lines is 100, and Vtt is set to 1.5V. The additional power consumption is estimated at 47.8 mW. That is, the greater the number of transmission paths, the greater the additional power consumption. Furthermore, as the power consumption increases, the power consumption generates heat directly on the CPU, causing a temperature rise on the CPU. On the other hand, when another control chip set related to the CPU adopts the same terminator as the CPU, each chip set consumes substantially the same amount of power. As a result, the heat generated by the terminator may affect the stability of the CPU and chipset. Originally, the power consumption of the CPU and chip set becomes very large as the operating frequency of the CPU increases. Considering the additional power consumption due to the installation of the terminator, it is necessary to use more heat radiation fins for the CPU and chipset. Furthermore, it is necessary to take into account heat dissipation when manufacturing the chip. For example, a multilayer chip substrate having 2 to 4 layers is manufactured in consideration of heat dissipation. However, this leads to an increase in manufacturing costs.
[0009]
[Problems to be solved by the invention]
The resistance of the terminator can also be increased to prevent the generation of heat further generated by the terminator. However, when the resistances of the terminators at both ends of the transmission line cannot be maintained at the same value, the ringback of the GTL + signal becomes even stronger. Actually, since the CPU and the chipset are usually manufactured by different manufacturers, it is difficult to maintain the resistances of the terminators at both ends of the transmission line at the same value. Therefore, it is necessary to adopt another method for solving the ringback problem. For example, the ringback problem can be solved by replacing the fixed reference voltage for detecting the input GTL + signal employed in the conventional input buffer with an adjustable reference voltage.
[0010]
That is, an input buffer that employs a fixed reference voltage for converting an input GTL + signal has the following drawbacks.
(1) When the resistance of the terminator is lowered to increase the number of transmission lines, the power consumption is further increased and a large amount of heat is generated. As a result, it is necessary to consider to further improve the heat dissipation during chip manufacture. This further increases the manufacturing cost.
(2) With the generation of a large amount of heat, the temperature of the chip rises and the stability deteriorates.
[0011]
[Means for Solving the Problems]
It is an object of the present invention to provide a signal converter with a dynamically adjustable reference voltage that allows excessively strong ringback, reduces additional power consumption, and reduces the heat generated by a high resistance terminator. It is to provide.
[0012]
To achieve the above object, the signal converter according to the present invention has a dynamically adjustable reference voltage, and is electrically connected between the control circuit and the bus, and has an input circuit and a reference voltage generator. Including a bowl.
[0013]
The input circuit has an input end connected to the bus and an output end connected to the control circuit. A first digital signal coming from the bus is converted into a second digital signal including a first logic level and a second logic level, and the second signal is output to the control circuit based on an adjustable reference voltage. Has been. If the potential of the first digital signal is higher than the adjustable reference voltage, the second digital signal is set to the first logic level. Conversely, if the potential of the first digital signal is lower than the adjustable reference voltage, the second digital signal is set to the second logic level.
[0014]
The reference voltage generator is controlled by a control circuit and outputs an adjustable reference voltage including a first potential and a second potential used for the input circuit. When the control circuit sends a second digital signal towards the bus, the adjustable reference voltage is changed to the first potential by controlling the reference voltage generator. On the other hand, when the bus sends the first digital signal towards the control circuit, the adjustable reference voltage is changed to the second potential by controlling the reference voltage generator.
[0015]
The signal converter has an input connected to the control circuit based on an adjustable reference voltage and an output connected to a bus for converting the second digital signal into the first digital signal. A circuit is further included.
[0016]
In the present invention, the bus is a GTL + bus. The second potential (for example, 1.2V) is higher than the first potential (for example, 1.0V).
[0017]
The present invention will be more fully understood from the following detailed description and the accompanying drawings, which are given by way of illustration only and not by way of limitation. In the accompanying drawings,
FIG. 1 is a schematic diagram showing two devices electrically connected to each other via a GTL + bus;
FIG. 2 is a schematic diagram showing waveforms for the GTL + bus,
FIG. 3 is a circuit block diagram illustrating a signal converter having a dynamically adjustable reference voltage according to the present invention.
FIG. 4 is a circuit block diagram illustrating a chipset including a signal converter having a dynamically adjustable reference voltage according to the present invention.
FIG. 5 is a circuit block diagram showing a chip set including a signal converter having a reference voltage supplied from the outside according to the present invention.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 shows a signal converter with a dynamically adjustable reference voltage according to a preferred embodiment of the present invention. In FIG. 3, a signal converter 300 is electrically connected between a control circuit 310 and a bus 130 such as a GTL + bus for signal conversion.
[0019]
As shown in FIG. 3, the signal converter 300 includes an input circuit 314, an output circuit 312, and a reference voltage generator 320. The input circuit 314 and the output circuit 312 are electrically connected between the control circuit 310 and the signal conversion bus 130. Furthermore, one end of the bus 130 is electrically connected to the power source Vtt via the terminator Rt. The reference voltage generator 320 generates a reference voltage Vr to the input circuit 314 and the output circuit 312.
[0020]
The input circuit 314 converts a first digital signal such as a GTL + signal input from the bus 130 into a second digital signal such as a TTL signal or a CMOS signal that can be received by the control circuit 310. During signal conversion, if the potential of the first digital signal is higher than the reference voltage Vr from the first adjustable potential output from the reference voltage generator 320, the second digital signal is set to logic level “1”. Is done. Conversely, when the potential of the first digital signal is lower than the first adjustable potential Vr, the second digital signal is set to the logic level “0”. Further, when the control circuit 310 needs to receive the first digital signal coming from the bus 130 via the input circuit 314, the first potential Vr can be adjusted according to the quality of the first digital signal. Therefore, the allowable range of ringback that occurs on the first digital signal can be greatly expanded.
In other words, the first potential of the reference voltage Vr represents the signal transmission direction from the bus 130 such as a GTL + bus to the control circuit 310 in the example of FIG. On the other hand, the second potential of the reference voltage Vr represents the signal transmission direction from the control circuit 310 to the bus 130 such as a GTL + bus in the example of FIG.
When the first digital signal enters the input circuit 314 from the bus 130 side such as the GTL + bus, the reference voltage Vr is set to 1.2 V, for example. On the other hand, when the second digital signal enters the output circuit 312 from the control circuit 310, the reference voltage Vr is set to 1.0 V, for example.
The actual potential of the reference voltage Vr corresponding to the first potential and the second potential can be adjusted according to the quality of the first digital signal, for example.
[0021]
Further, the first potential Vr is adjusted by a control signal S from the control circuit 310. In general, the first potential Vr supplied to the input circuit 314 is determined according to the actual circuit design. For example, when Vtt is 1.5V, the first potential Vr is set to 1.0V. If only the resistance of the terminator Rt causes more significant ringback, the first potential Vr can be adjusted to increase to a potential of 1.2V or higher to allow stronger ringback.
[0022]
On the other hand, when the control circuit 310 needs to transmit a second digital signal such as a TTL signal or a CMOS signal to the bus 130 via the output circuit 312, the control circuit 310 causes the reference voltage generator 320 to control the signal conversion control signal. In S, the output circuit 312 outputs the reference voltage Vr of the second potential (for example, 1 V). After the control circuit 310 has completely transmitted the second digital signal, the control circuit 310 uses the reference voltage generator 320 to generate the reference voltage of the first adjustable potential (eg, 1.2V) with the signal conversion control signal S. Vr is output to the input circuit 314 so that a first digital signal such as a GTL + signal from the bus 130 can be received.
[0023]
As can be understood from the above description, the first potential Vr can be adjusted (or increased) to allow stronger ringback caused by impedance mismatch of the terminator Rt.
[0024]
Similarly, if the bus 130 has completely transmitted the first digital signal to the control circuit 310 and the control circuit 310 needs to retransmit a digital signal such as a TTL signal or a CMOS signal toward the bus 130, the control circuit In 310, the reference voltage generator 320 causes the output circuit 312 to output the reference voltage Vr of the second potential.
[0025]
The signal converter with a dynamically adjustable reference voltage according to the present invention is suitable for a chipset on a printed circuit board that cooperates with a CPU adopting the GTL + signal specification. FIG. 4 shows a chipset including a signal converter according to the invention. The chip set 400 includes a control circuit 410, an input circuit 414, an output circuit 412, and a reference voltage generator 420. The control circuit 410 controls the operation of the entire chip set 400 and the reference voltage generator 420 to generate an adjustable reference voltage Vr. The control circuit 410 and an external circuit (not shown) connected to the GTL + bus 130 communicate with each other via the input circuit 414 and the output circuit 412. The input circuit 414, the output circuit 412 and the reference voltage generator 420 constitute a signal converter 430 having the same operation as described above.
[0026]
As described above, the signal converter according to the present invention may be incorporated into a chip set on a printed circuit board that cooperates with a CPU adopting the GTL + signal specification. Further, the reference voltage may be supplied externally for use by a signal converter inside the chipset. FIG. 5 shows a chipset including a signal converter with an external reference voltage generator. In FIG. 5, the chip set 500 includes a control circuit 510, an input circuit 514, and an output circuit 512. An adjustable reference voltage Vr used for input circuit 514 and output circuit 512 during signal conversion is supplied from an external reference voltage generator 520. The control circuit 510 controls the operation of the entire chip set 500 and the external reference voltage generator 520 to generate an adjustable reference voltage Vr. Further, the control circuit 510 and a circuit (not shown) outside the chipset 500 communicate with each other via the input circuit 514 and the output circuit 512. The operation of the chip set 500 is the same as that described above.
[0027]
In the signal converter according to the present invention, even when the transmitted first digital signal such as the external GTL + signal has a more serious ringback problem, the impedance mismatch of the terminator is adjusted (increased) by adjusting the reference voltage Vr. By avoiding the abnormal operation caused by the above, the above problem can be solved. When a second digital signal such as a TTL signal or a CMOS signal is transmitted therefrom, the reference voltage Vr changes to the second potential for the output circuit.
[0028]
【The invention's effect】
Compared to the signal converter with a fixed reference voltage of the prior art, the signal converter with a dynamically adjustable reference voltage according to the present invention has the following advantages. Even if the corresponding terminator that causes more severe ringback cannot be further changed to a matching resistor, the reference voltage can be dynamically adjusted upon receipt of the GTL + digital signal to solve the ringback problem. Thus, additional power loss and heat generation can be reduced using a high resistance terminator. This reduces costs and eliminates the need for heat dissipation issues during manufacturing.
[0029]
Although the present invention has been described by way of examples and preferred embodiments, the present invention is not limited to the above embodiments. On the contrary, it is intended to protect various modifications and similar arrangements that will be apparent to those skilled in the art. Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing two devices electrically connected to each other via a GTL + bus.
FIG. 2 is a schematic diagram showing waveforms for a GTL + bus.
FIG. 3 is a circuit block diagram illustrating a signal converter having a dynamically adjustable reference voltage according to the present invention.
FIG. 4 is a circuit block diagram illustrating a chipset including a signal converter having a dynamically adjustable reference voltage according to the present invention.
FIG. 5 is a circuit block diagram illustrating a chipset including a signal converter having an externally supplied reference voltage according to the present invention.

Claims (4)

A signal converter electrically connected between the control circuit and the GTL + bus and having a dynamically adjustable reference voltage,
Based on an input terminal coupled to the GTL + bus and an adjustable reference voltage, a first digital signal that is a GTL + signal from the GTL + bus can be received by a control circuit into a TTL signal or a second digital signal that is a CMOS signal. An input circuit having an output connected to a control circuit for conversion;
An output circuit having an input coupled to the control circuit and an output coupled to the GTL + bus for converting the second digital signal from the control circuit into the first digital signal to the GTL + bus;
It is controlled by the control circuit, a reference voltage generator for outputting an adjustable reference voltage including a first potential and a second potential used in the input circuit and the output circuit, the control circuit of the second digital signal When the control circuit sends the GTL + bus to the GTL + bus, the adjustable reference voltage is changed to the first potential by controlling the reference voltage generator, and the GTL + bus sends the first digital signal to the GTL + bus. A reference voltage generator configured to change the adjustable reference voltage to the second potential by controlling the reference voltage generator when being sent to the control circuit ;
Including
The signal converter, wherein the adjustable reference voltage is switched between the first potential and the second potential according to a signal transmission direction . A signal converter electrically connected between the control circuit and the bus and having a dynamically adjustable reference voltage,
An input connected to the bus and an output connected to a control circuit for converting a first digital signal coming from the bus into a second digital signal receivable by the control circuit based on an adjustable reference voltage. An input circuit;
A concatenated input to the control circuit, and an output circuit having a second digital signal the concatenated output to said bus for converting said first digital signal to said bus from said control circuit,
A reference voltage generator controlled by the control circuit and outputting an adjustable reference voltage including a first potential and a second potential used for the input circuit and the output circuit, wherein the second potential is the first potential. The adjustable reference voltage is changed to the first potential by controlling the reference voltage generator when the control circuit sends the second digital signal from the control circuit to the bus. A reference voltage adapted to change the adjustable reference voltage to a second potential by controlling the reference voltage generator when the bus sends the first digital signal from the bus to the control circuit; A generator ,
Including
The signal converter, wherein the adjustable reference voltage is switched between the first potential and the second potential according to a signal transmission direction .   The signal converter according to claim 2, wherein the first potential is 1.0V.   The signal converter according to claim 3, wherein the second potential is 1.2V.

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