JP3812815B2 - Printed circuit board for DVD player - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board used in a DVD playback apparatus, and more particularly to a printed circuit board with reduced unwanted radiation.
[0002]
[Prior art]
The printed circuit board of the DVD playback apparatus is equipped with an MPEG decoder IC that demodulates the video signal by performing MPEG decoding on the signal output from the pickup. In addition, a synchronous DRAM (hereinafter referred to as SDRAM) serving as a work area for the MPEG decoder is mounted. The MPEG decoder IC receives operation power from a first power supply path that supplies operation power to the SDRAM, and supplies operation power from a second power supply path having a voltage different from the voltage of the first power supply path. Have come to receive. A relatively large capacity, such as 0.1 μF, is provided between the appropriate position of the first power supply path and the ground level and between the appropriate position of the second power supply path and the ground level. By connecting a bypass capacitor, the level of unnecessary radiation from the first and second power supply paths is reduced (first conventional technique).
[0003]
Further, as one of conventional techniques using a bypass capacitor, there is a technique proposed as Japanese Patent Laid-Open No. 10-98313. That is, in this technique, in each of the resonators, four short-circuit rods having the same inductance are arranged radially at an equal distance from the short-circuit surface. Then, the shorting bar is bent into an L shape at an appropriate position, and the extending direction is made parallel to the internal conductor, and then connected to the shorting surface via a pin diode and a bypass capacitor. Then, the tuning frequency is finely adjusted by controlling the circuit constant of a series circuit composed of a short bar, a pin diode, and a bypass capacitor (referred to as the second prior art).
[0004]
[Problems to be solved by the invention]
However, when the first prior art is used, the following problems occur. That is, a high-frequency clock signal such as 121.5 MHz is given to the SDRAM which is the work area of the MPEG decoder. On the other hand, in the SDRAM, a current flows in a spike shape in a period corresponding to the clock signal. In addition, the power supply path has a pattern of being pulled for a long time because power is supplied to other ICs. For this reason, spike-like noise generated by the SDRAM is emitted as unnecessary radiation to the outside of the printed circuit board with the pattern of the power supply path serving as an antenna.
[0005]
In addition to the 121.5 MHz component that is the frequency of the clock signal, the frequency component of 364.5 MHz that is the triple harmonic is included in the frequency component of the unwanted radiation emitted from the printed circuit board due to spike-like noise. included. On the other hand, in a capacitor having a relatively large capacity such as 0.1 μF, the self-resonance frequency is often lower than 100 MHz due to the parasitic inductance component (the parasitic inductance component is extremely small, and is special and expensive). Excluding element). As a result, for the frequency of 364.5 MHz, which is a triple harmonic, the impedance does not become a sufficiently small value, and the effect as a bypass capacitor is reduced. The level of higher harmonics increased, and the level of unwanted radiation that leaked outside the casing increased.
[0006]
In the second prior art, the bypass capacitor is a feedthrough type bypass capacitor. Therefore, it can be applied when the printed circuit board is built in the shield case, but in this case, the manufacturing cost is extremely increased. For this reason, it is a technique that is difficult to apply in a DVD playback apparatus in which a printed board is simply provided inside a housing without being built in a shield case.
[0007]
The present invention has been devised to solve the above-described problems. The object of the present invention is to provide a self-resonant frequency of an unnecessary radiation signal whose level is to be reduced in a bypass capacitor of a power supply path for supplying operating power to an SDRAM. By using a capacitor having a self-resonance frequency lower than the frequency of an unnecessary radiation signal whose level is to be reduced, a SDRAM having a higher frequency than the frequency and having a self-resonant frequency lower than the frequency of the unwanted radiation signal whose level is to be reduced is used. An object of the present invention is to provide a printed circuit board of a DVD reproducing apparatus capable of efficiently reducing unnecessary radiation having a frequency three times that of a supplied clock signal.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a printed circuit board of a DVD playback apparatus according to the present invention includes a first power supply path and a second power supply path having a voltage different from the voltage of the first power supply path. ground and SDRAM which operates a direct current supplied from the power supply path as an operating power supply supplies a clock signal to the S DRAM, a SDRAM as a work area, and the MPEG decoder IC for decoding the MPEG system, the first power supply path In a printed circuit board of a DVD playback apparatus, on which a first bypass capacitor connected between the first power supply level and a second bypass capacitor connected between the second power supply path and the ground level is mounted. And a second bypass capacitor having a self-resonance frequency higher than three times the frequency of the clock signal. The self-resonant frequency is lower than three times the frequency of the clock signal, and the stray capacitance component generated between the first power supply path and the second power supply path and the second power supply path are formed. The resonance frequency of the series resonance circuit in which the inductance component due to the pattern to be connected and the second bypass capacitor are connected in series is set to a frequency in the vicinity of three times the frequency of the clock signal .
[0009]
That is, when the vicinity position of the SDRAM on the first power supply path is viewed from the ground level via the first bypass capacitor and the first power supply path, from the vicinity position to the connection position of the first bypass capacitor. The inductance component generated by this pattern is connected in series to the first bypass capacitor. Therefore, the resonance frequency of the series circuit from the vicinity position to the ground level is lower than the self-resonance frequency of the first bypass capacitor. For this reason, when the self-resonance frequency of the first bypass capacitor is higher than the target frequency for reduction, the resonance frequency of the series circuit from the vicinity position to the ground level is set to a frequency that is about three times the clock signal. can do.
[0010]
Further, when the vicinity position of the SDRAM on the first power supply path is viewed from the ground level through the second bypass capacitor and the second power supply path, the second power supply path and the first power supply path The stray capacitance component generated between them and the inductance component generated by the pattern of the second power supply path are connected in series to the second bypass capacitor. In addition, the stray capacitance component remains small. Accordingly, the resonance frequency of the series circuit from the vicinity position to the ground level is higher than the self-resonance frequency of the second bypass capacitor. For this reason, when the self-resonance frequency of the second bypass capacitor is set to a frequency lower than the target frequency for reduction, the resonance frequency of the series circuit from the vicinity position to the ground level is set to a frequency that is about three times the clock signal. can do.
[0011]
In addition to the above configuration, the MPEG decoder IC uses the direct current supplied from the first power supply path and the direct current supplied from the second power supply path as operation power supplies.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is an explanatory view schematically showing an outline of an IC mounting position and a shape of a power supply path in an embodiment of a printed circuit board of a DVD playback apparatus according to the present invention.
[0013]
In the figure, an MPEG decoder IC 12 is an IC for demodulating a video signal and an audio signal by performing MPEG decoding on a signal reproduced by a pickup (not shown). The SDRAMs 14 to 16 are connected to the MPEG decoder IC 12 via the bus 31, and receive a clock signal of 121.5 MHz from the MPEG decoder IC 12 via the path 32, whereby the work of the MPEG decoder IC 12 is received. It is a memory that operates as an area.
[0014]
The OSC 11 is an IC for generating a 27 MHz clock signal to be supplied to the MPEG decoder IC 12. The DAC 13 is an IC for converting the video signal (digital signal) restored by the MPEG decoder IC 12 into an analog signal.
[0015]
The SDRAMs 14 to 16 are mounted so as to have a positional relationship close to each other. Further, the MPEG decoder IC 12 is mounted at a position close to the SDRAMs 14 to 16 on the surface opposite to the mounting surface of the SDRAMs 14 to 16. The OSC 11 is mounted at a position where the path to the MPEG decoder IC 12 is shortened.
[0016]
The first power supply path 21 is a 3.3V power supply line, and supplies operating power to the OSC 11, the MPEG decoder IC 12, and the SDRAMs 14 to 16. Further, operation power is supplied to other ICs (not shown). The first power supply path 21 is also connected to a connector 17 used for connection to a block outside the printed circuit board. For this reason, the first power supply path 21 has a pattern routed over a wide range of the printed circuit board.
[0017]
The second power supply path 22 is a 2.5 V power supply line and supplies operation power to the MPEG decoder IC 12. In addition, operation power is supplied to other ICs (not shown). For this reason, the 2nd power supply path 22 is also a pattern drawn over the wide range of the printed circuit board.
[0018]
In the following description, the frequency of the unwanted radiation signal that is desired to be reduced is referred to as a reduction target frequency. Note that this reduction target frequency is specifically three times the frequency of the clock signal and is 364.5 MHz.
[0019]
The first bypass capacitor C11 reduces unnecessary radiation from the printed circuit board. Therefore, in the positional relationship on the printed circuit board, the first bypass capacitor C11 is located between the first power supply path 21 and the ground level at a point A close to the OSC 11. It is a bypass capacitor connected to. In addition, a chip-type ceramic capacitor whose self-resonant frequency is higher than the frequency to be reduced is adopted for the element.
[0020]
The second bypass capacitor C12 is a bypass capacitor connected between the second power supply path 22 and the ground level at a point C near the MPEG decoder IC 12 in the positional relationship on the printed circuit board. Yes. Further, a chip-type ceramic capacitor whose self-resonant frequency is lower than the frequency to be reduced is adopted for the element.
[0021]
The effect | action of embodiment which consists of the said structure is demonstrated below.
[0022]
The main cause of unnecessary radiation is a change in the current of the SDRAMs 14 to 16 in which the current changes in a spike shape corresponding to the period of the clock signal. Therefore, the signal source can be regarded as the respective power supply terminals of the SDRAMs 14 to 16. For this reason, the position B on the first power supply path 21 and close to the power supply terminals of the three SDRAMs 14 to 16 is regarded as an equivalent signal source position. This means that the level of unnecessary radiation to the outside is reduced as the impedance between the point B and the ground level is reduced at the reduction target frequency.
[0023]
If the DC resistance is ignored, the point B is connected to the ground level via the inductance component L21 generated by the pattern from the point B to the point A and the first bypass capacitor C11 as shown in FIG. Will be. On the other hand, the first bypass capacitor C11 is equivalently shown as a series circuit of a parasitic inductance component L1 and a capacitance component C1. Therefore, the point B is grounded via a series circuit of the inductance component L21, the parasitic inductance component L1, and the capacitance component C1.
[0024]
41 in FIG. 4 indicates the relationship between the impedance and the frequency of the first bypass capacitor C11, and the self-resonant frequency f1 at which the impedance is minimum is higher than the reduction target frequency f0. However, since the inductance component L21 is connected in series to the parasitic inductance component L1 of the first bypass capacitor C11, the resonance frequency of the series circuit when the ground level is viewed from the point B is self-resonant. The frequency f1 is shifted to the lower side.
[0025]
Therefore, when selecting an appropriate element based on the experimental results from the elements in the first bypass capacitor C11 whose self-resonant frequency is higher than the reduction target frequency f0, when the ground level is viewed from the point B Can be set to a frequency near the reduction target frequency f0. When this is done, point B becomes the end of the series resonance circuit at a frequency near the reduction target frequency f0, so that the ground impedance at point B is minimum near the reduction target frequency f0.
[0026]
The same applies to the second power supply path 22, which means that the level of unnecessary radiation to the outside is reduced as the impedance between the point B and the ground level can be reduced. On the other hand, when the ground level is viewed from the point B via the second power supply path 22, the equivalent circuit is provided between the first power supply path 21 and the second power supply path 22 as shown in FIG. The stray capacitance component C22 formed, the inductance component L22 generated by the pattern of the second power supply path 22, and the parasitic inductance component L2 constituting the second bypass capacitor C12 and the capacitance component C2 are shown as a series circuit.
[0027]
42 in FIG. 4 indicates the relationship between the impedance and the frequency of the second bypass capacitor C12, and the self-resonant frequency f2 at which the impedance is minimum is lower than the reduction target frequency f0. However, the inductance component L22 and the stray capacitance component C22 are connected in series to the parasitic inductance component L2 of the second bypass capacitor C12. On the other hand, the stray capacitance component C22 has a small capacity.
[0028]
Therefore, when the ground level is viewed from the point B via the second power supply path 22, the stray capacitance component C22 has a smaller capacity than the effect that the inductance component L22 is connected in series. large. For this reason, the resonance frequency of the series circuit changes from the self-resonance frequency f2 of the second bypass capacitor C12 to the higher side.
[0029]
Therefore, when an appropriate element is experimentally selected from the elements in the self-resonance frequency lower than the reduction target frequency f0 for the second bypass capacitor C12, the resonance when the ground level is viewed from the point B The frequency can be a frequency close to the reduction target frequency f0. When this is done, point B becomes the end of the series resonant circuit at a frequency near the reduction target frequency f0, so that the ground impedance at point B is minimum near the reduction target frequency f0.
[0030]
As a result, the point B that is a noise source of unnecessary radiation is grounded via the first power supply path 21 that has a low impedance substantially equal to a short circuit in the vicinity of the reduction target frequency f0. For this reason, the noise component flowing into the first power supply path 21 from the SDRAMs 14 to 16 is suppressed to the minimum value, and the level of unnecessary radiation radiated from the first power supply path 21 is reduced.
[0031]
In addition, regarding the second power supply path 22, in the vicinity of the reduction target frequency f0, the point B serving as a noise source only affects the end portion having a low impedance that is substantially equal to a short circuit. Is minimal. Therefore, the noise component flowing into the second power supply path 22 from the SDRAMs 14 to 16 is suppressed to the minimum value, and the level of unnecessary radiation radiated from the second power supply path 22 is reduced. By both of these actions, unnecessary radiation from the printed circuit board is efficiently reduced.
[0032]
Although the case where the MPEG decoder IC 12 is configured to receive the operation power supply from both the first power supply path 21 and the second power supply path 22 has been described, the MPEG decoder IC 12 is configured to receive the operation power supply from any power supply path. The present invention can be similarly applied to a configuration in which the first power supply path 21 and the second power supply path 22 are coupled by a stray capacitance.
[0033]
【The invention's effect】
As described above, the printed circuit board of the DVD playback apparatus according to the present invention has the configuration in which the SDRAM operating with the direct current supplied from the first power supply path as the operating power supply and the MPEG decoder IC are mounted. The first bypass capacitor connected between the first power path and the ground level is an element having a self-resonance frequency higher than three times the frequency of the clock signal, and the second power path and the ground level. a second bypass capacitor connected between the self-resonant frequency is lower element than three times the frequency of the clock signal, generated between the first power supply path and the second power supply path floating A resonance frequency of a series resonance circuit in which an inductance component due to a pattern forming a capacitance component and a second power supply path and a second bypass capacitor are connected in series is expressed as The frequency is in the vicinity of three times the frequency of the lock signal . For this reason, the resonance frequency of the series circuit via the first power supply path and the series circuit via the second power supply path from the position near the SDRAM to the ground level is approximately three times that of the clock signal. Since the frequency can be set, unnecessary radiation having a frequency three times that of the clock signal supplied to the SDRAM can be efficiently reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory view schematically showing an outline of an IC mounting position and a shape of a power supply path in an embodiment of a printed circuit board of a DVD playback apparatus according to the present invention.
FIG. 2 is an equivalent circuit diagram of a series circuit formed by a first power supply path and a first bypass capacitor.
FIG. 3 is an equivalent circuit diagram of a series circuit formed by a second power supply path and a second bypass capacitor.
FIG. 4 is an explanatory diagram showing impedance characteristics of a first bypass capacitor and a second bypass capacitor.
[Explanation of symbols]
12 MPEG decoder IC
14-16 SDRAM (Synchronous DRAM)
21 1st power supply path 22 2nd power supply path C11 1st bypass capacitor C12 2nd bypass capacitor

Claims (2)

A first power supply path and a second power supply path having a voltage different from the voltage of the first power supply path are formed;
A synchronous DRAM that operates using a direct current supplied from a first power supply path as an operation power supply;
An MPEG decoder IC for supplying a clock signal to the synchronous DRAM and performing MPEG decoding using the synchronous DRAM as a work area;
A first bypass capacitor connected between the first power path and the ground level;
In a printed circuit board of a DVD playback device on which a second bypass capacitor connected between the second power supply path and the ground level is mounted,
The first bypass capacitor is an element having a self-resonance frequency higher than three times the frequency of the clock signal,
The second bypass capacitor is an element whose self-resonance frequency is lower than three times the frequency of the clock signal ,
A series resonant circuit in which a stray capacitance component generated between a first power supply path and a second power supply path, an inductance component resulting from a pattern forming the second power supply path, and a second bypass capacitor are connected in series. A printed circuit board of a DVD reproducing apparatus , wherein the resonance frequency of the DVD reproduction apparatus is set to a frequency in the vicinity of three times the frequency of the clock signal . 2. The printed circuit board of a DVD reproducing apparatus according to claim 1, wherein the MPEG decoder IC uses the direct current supplied from the first power supply path and the direct current supplied from the second power supply path as operation power supplies .

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