JP3809444B2 - Built-in data access apparatus and method in boundary scan test interface - Google Patents

Description

  The present invention relates to the technical field of boundary scan test interfaces, and more particularly to a built-in data access apparatus and method in a boundary scan test interface.

  As chip packages and multi-layer printed circuit board technology become more complex, traditional pinbed test methods become difficult to contact with nodes on the printed circuit board, and with the maturation of surface mount technology, many ICs are directly connected to the board. Since it was mounted on the surface of the IC, it was difficult to directly measure the internal signal of the IC. In order to solve this problem, a boundary scan technique was born. For example, there is a JTAG (Joint Test Action Group) boundary scan, and its official standard name is IEEE1149.1, and IEEE1149.4 digital test access port (Digital Test Access Port) interface, a boundary scan test interface that can test ICs It is said that. It tests the integrated circuit internal modules by serial scan chain, and according to JTAG interface structure shown in Fig. 1, it scans by 5 signal pins (TDI, TDO, TMS, TCK, nTRST) Perform chain data operations. Among them, the TDI pin inputs serial data, the TDO pin outputs serial data, the TMS pin selects and inputs a mode, the TCK pin inputs a clock signal, and the nTRST pin provides a system reset function. As shown, the JTAG structure comprises a test access port (TAP) controller (TAP controller 11), a test data register 12 (test data register), an instruction register 13, and a decoder 14.

  Within the test data register 12, a scan chain register 121 provides a scan chain and can store serial data input by the TDI pin, and an identification code register 122 stores a special code that is output. The bypass register 123 transmits the input of the TDI pin directly to the TDO pin and outputs it.

  The instruction register 13 stores the serial instruction input through the TDI pin and decodes it by the decoder 14 to control the operation of the TAP controller 11.

  The TAP controller 11 performs a state shift by inputting a TMS pin, and operates based on the data in the test data register 12 and the decoding result of the decoder 14. FIG. 2 is a state shift diagram of the TAP controller 11 that shifts the state by sampling the TMS signal at the TCK positive edge, and at the start, the TAP controller 11 enters the Test-Logic Reset state as shown. After that, the state of the three parts of the reset process 21, the data register process 22, and the instruction register process 23 is entered. If the TMS input is 1, the test logic reset state is maintained and unchanged, and when the TMS input is 0, the state shifts to the Run-Test / Idle state of the idle process 21. In the Run-Test / Idle state, if the TMS input is 0, the Run-Test / Idle state is retained and unchanged, and when the TMS input is 1, the state is the Select-DR-Scan of the data register processing 22. Shift to state. In the Select-DR-Scan state, if the TMS input is 0, the Capture-DR state is entered and processing is performed on the test data register 12. When the TMS input is 1, the state is changed to the Select- Shift to IR-Scan state. When in the Select-IR-Scan state, if the TMS input is 0, the Capture-IR state is entered, thereby performing processing for the instruction register. When the TMS input is 1, the Test-Logical Reset at the start of the state Shift to state.

  The above-described JTAG structure reads and writes through the TDI and TDO pins for both control signal transmission and register access. However, the TDI and TDO data read / write has its circularity and can be easily detected by humans. For this reason, for example, confidentiality register values cannot be protected. However, in current processor development, it is often necessary to protect development tools and prevent theft by others. Therefore, there is a need to solve the problem of how to protect access to sensitive data in the boundary scan test interface standard.

  An object of the present invention is to provide a built-in data access apparatus and method in a boundary scan test interface, which can read and write data without going through standard data input / output pins. It is intended to be an apparatus and method for achieving confidentiality data access protection.

  Another object of the present invention is to provide a built-in data access apparatus and method in a boundary scan test interface, which is compatible with the boundary scan test interface standard, can read and write confidential data, and is completely The apparatus and method shall not affect all the states of the boundary scan test interface and the data path.

The invention of claim 1 is a built-in data access device in a boundary scan test interface, the boundary scan test interface including a TAP controller, a test data register, an instruction register, and a decoder, the test data register being a serial data input The serial command input by the pin is stored, the TAP controller performs a state shift by inputting a mode selection input pin according to a predetermined state shift diagram, and the data stored in the test data register and the serial command stored by the command register The state shift to be performed includes at least one inactive state loop, the apparatus comprising a state detector, a shift register, a built-in register, and a comparator.
The state detector monitors the input of the mode selection input pin and outputs the first data when detecting the first setting input string, and then outputs the second data when detecting the second setting input string. The first setting input string and the second setting input string match different input strings of the inactive state loop;
The shift register stores a combination of first and second data output from the state detector, and the combination of the first and second data has an input key value;
The built-in register is used for data storage,
The comparison device compares the input key value with the set write key value, and when the two match, loads the specific write data into the built-in register, the built-in data access in the boundary scan test interface It is a device.
According to a second aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the first aspect, the combination of the first and second data further has information of specific write data. It is a built-in data access device in the interface.
According to a third aspect of the present invention, the internal data access device in the boundary scan test interface according to the second aspect further comprises a selector for selecting and outputting the contents of the internal register or the specific register defined by the boundary scan test interface. This is a built-in data access device in the boundary scan test interface.
According to a fourth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the third aspect, the comparison device compares the input key value with the set recovery key value and controls the selector when the two match. The built-in data access device in the boundary scan test interface is characterized in that the contents of the built-in register are output.
According to a fifth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the third aspect, the comparison device compares the input key value with the set read key value and controls the selector when the two match. The internal data access device in the boundary scan test interface is characterized in that the contents of the specific register are output.
According to a sixth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the second aspect, the input key value is an odd bit of the first and second data, and the specific write data is the first and second data. The built-in data access device in the boundary scan test interface is characterized by the combination of even bits.
According to a seventh aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the second aspect, the boundary scan test interface is a JTAG interface, and the input of the mode selection input pin is a TMS input. The built-in data access device in the boundary scan test interface.
The invention according to claim 8 is the internal data access device in the boundary scan test interface according to claim 2, wherein the boundary scan test interface is an IEEE1149.1 interface, and the input of the mode selection input pin is a TMS input. The built-in data access device in the boundary scan test interface.
The invention according to claim 9 is the built-in data access device in the boundary scan test interface according to claim 2, wherein the boundary scan test interface is an IEEE 1149.4 digital test access port interface, and the input of the mode selection input pin is a TMS input. The built-in data access device in the boundary scan test interface is characterized in that
According to a tenth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the seventh aspect, when the state shift diagram is started in a test logic reset (Test-Logic Reset) state and the TMS input is 1, The state is retained and unchanged, when the TMS input is 0, the state is shifted to the Run-Test / Idle state, and when the TMS input is 0, the state is retained and unchanged. When three consecutive TMS inputs are 1, the state shifts to the test logic reset state, forming at least one inactive state loop, which is an internal data access device in the boundary scan test interface .
According to the eleventh aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the tenth aspect, the first setting input string is set to “0111” and the second setting input string is set to “1”. The feature is a built-in data access device in the boundary scan test interface.
According to a twelfth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the eleventh aspect, the first data is set to “1” and the second data is set to “0”. Built-in data access device in boundary scan test interface.
According to a thirteenth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the tenth aspect, the first setting input string is “0 [0] 111” and the second setting input string is “1”. Among them, the built-in data access device in the boundary scan test interface is characterized in that [0] represents at least one zero.
According to a fourteenth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the thirteenth aspect, the first data is set to “1” and the second data is set to “0”. Built-in data access device in boundary scan test interface.
According to a fifteenth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the seventh aspect, the data output from the state detector is sampled by the TCK signal defined by JTAG and stored in the shift register. The feature is a built-in data access device in the boundary scan test interface.
According to a sixteenth aspect of the present invention, in the built-in data access device in the boundary scan test interface according to the second aspect, the specific register is an identification code register. Yes.
The invention according to claim 17 is the method of accessing a built-in data in the boundary scan test interface, wherein the boundary scan test interface includes a TAP controller, a test data register, an instruction register, and a decoder, and the test data register is a serial data input pin. The TAP controller performs a state shift by inputting a mode selection input pin according to a predetermined state shift diagram, and by the data in the test data register and the serial instruction stored in the instruction register. Driving, of which the state shift to perform includes at least one inactive state loop, the method comprising:
(A) The state detector monitors the input of the mode selection input pin, outputs the first data when detecting the first setting input string, and outputs the second data when detecting the second setting input string. Where the first set input string matches the input string of the inactive state loop, the second set input string is not the same as the first set input string and the input string of the inactive state loop A step that shall match
(B) storing a combination of the first and second data output from the shift register, wherein the combination of the first and second data includes an input key value;
(C) a step of comparing the input key value with the set write key value by a comparison device, and when the two match, loading specific write data into the built-in register;
The built-in data access method in the boundary scan test interface is characterized by comprising the above steps.
The invention according to claim 18 is the built-in data access method in the boundary scan test interface according to claim 17, wherein the combination of the first data and the second data further includes information of specific write data. The internal data access method in the interface is used.
According to a nineteenth aspect of the present invention, in the built-in data access method in the boundary scan test interface according to the eighteenth aspect, when (D) the input key value is compared with the set read key value by the comparison device , An internal data access method in the boundary scan test interface is characterized in that the contents of the internal register are output through an output path of a specific register defined by the boundary scan test interface.
When the invention of 請 Motomeko 20, in internal data access method in the boundary scan test interface of claim 19, wherein, for comparison with the recovery key value set input key value (E), both consistent, a special register The internal data access method in the boundary scan test interface is further provided with a step of outputting the content of the data through an output path of a specific register defined by the boundary scan test interface.
According to a twenty-first aspect of the present invention, in the built-in data access method in the boundary scan test interface according to the eighteenth aspect, during the step (B), the input key value is an odd number bit of the combination of the first and second data, and the specific write The built-in data access method in the boundary scan test interface is characterized in that the data is an even number bit of a combination of the first and second data.
The invention of claim 22 is the internal data access method in the boundary scan test interface according to claim 18, wherein the boundary scan test interface is a JTAG interface, and the input of the mode selection input pin is a TMS input. This is a built-in data access method in the boundary scan test interface.
The invention of claim 23 is the internal data access method in the boundary scan test interface according to claim 18, wherein the boundary scan test interface is an IEEE1149.1 interface, and the input of the mode selection input pin is a TMS input. This is a built-in data access method in the boundary scan test interface.
The invention of claim 24 is the internal data access method in the boundary scan test interface according to claim 18, wherein the boundary scan test interface is an IEEE 1149.4 digital test access port interface, and the input of the mode selection input pin is a TMS input. The built-in data access method in the boundary scan test interface is characterized by the following.
The invention of claim 25, in the internal data access method in the boundary scan test interface of claim 22, wherein, when the state shifts diagram begins with test logic reset (Test-Logic Reset) state and TMS inputs are 1, The state is retained and unchanged, when the TMS input is 0, the state is shifted to the Run-Test / Idle state, and when the TMS input is 0, the state is retained and unchanged. When three consecutive TMS inputs are 1, the state shifts to the test logic reset state, forming at least one inactive state loop, which is a built-in data access method in the boundary scan test interface .
According to a twenty-sixth aspect of the present invention, in the built-in data access method in the boundary scan test interface according to the twenty-fifth aspect, during the step (A), the first setting input string is “0111” and the first data is “1”. The internal data access method in the boundary scan test interface is characterized in that the second setting input string is set to “1” and the second data is set to “0”.
According to a twenty-seventh aspect of the present invention, in the built-in data access method in the boundary scan test interface according to the twenty-fifth aspect, the first setting input string is set to “0 [0] 111”, the first data is set to “1”, Built-in data access in the boundary scan test interface, wherein [0] represents at least one 0, the second setting input string is “1”, and the second data is “0” It is a way.
According to a twenty-eighth aspect of the present invention, in the built-in data access method in the boundary scan test interface according to the nineteenth aspect, the specific register is an identification code register. Yes.

  The present invention uses the inactive state loop in the boundary scan test interface state shift diagram to transmit the confidential signal and input the signal without going through the standard data input / output pins. Achieves the objective of protecting the transmission of confidentiality control signals, and is completely compatible with the boundary scan test interface standard without affecting all the states and data paths of the boundary scan test interface. .

  The present invention provides a built-in data access device in a boundary scan test interface that operates according to a predetermined state shift diagram that performs a state shift based on inputs. Of these, the state shift to perform includes at least one inactive state loop, the apparatus comprising a state detector, a shift register, a built-in register, and a comparator. The state detector monitors the input and outputs a first data when detecting a first set input string, and then outputs a second data when detecting a second set input string. The setting input string and the second setting input string match different input strings of the inactive state loop. The shift register stores a combination of first and second data output from the state detector. The combination of the first and second data has an input key value. The built-in register is used for data storage. The comparison device compares the input key value with the set write key value, and when the two match, loads the specific write data into the built-in register.

  The present invention also provides a built-in data access method in a boundary scan test interface that operates according to a predetermined state shift diagram that performs a state shift based on inputs. Wherein the performing state shift includes at least one inactive state loop, the method comprising: (A) monitoring the input and outputting a first data when detecting a first set input string; When detecting the second setting input string, it outputs second data, of which the first setting input string matches the input string of the inactive state loop, and the second setting input string is the first setting input. A step that is not the same as the string and matches the input string of the inactive state loop; (B) storing the combination of the first and second data output, of which the combination of the first and second data (C) Compare the input key value with the set write key value, and if both match, the specific write data is loaded into the built-in register. Step to, and includes the above steps.

  Refer to the structure diagram of FIG. 3 for the built-in data access apparatus and method in the boundary scan test interface of the present invention. It comprises a TAP controller 31, a test data register 32, an instruction register 33, a decoder 34, a confidential data detection and access controller 35, a built-in register 37 and a selector 38. The boundary scan test interface of the present invention may be JTAG, IEEE 1149.1, IEEE 1149.4 or other similar interface. In this embodiment, the boundary scan test interface is a JTAG interface, so the TAP controller 31, the test data register 32, the instruction register 33, and the decoder 34 operate according to the JTAG standard, which includes TDI, serial data input serial data. The scan chain data is scanned by adopting five signal pins: TDO for outputting TMS for inputting mode selection, TCK for inputting a click signal, and nTRST for system reset. The selector 38 described above is used to output the contents of the built-in register 37 or the identification code register 321 in the test data register 32, and the secret data detection and access controller 35 described above realizes reading and writing of confidential data based on the TMS input. .

  As further shown in FIG. 2, as can be seen from the state shift diagram defined by the JTAG standard, when the JTAG interface is disabled, the TMS pin input is a continuous 1 (ie, has a series of 1 inputs). Thus, when the JTAG interface holds the Test-Logical Reset state and the JTAG interface is to be operated, the TMS input is changed to 0 and the state shift is executed. However, if the TMS pin input is set to 0 and shifted to the Run-Test / Idle state so that a single 0 is not generated by mistake during a series of 1s, If 1, the state is shifted to the starting Test-Logic Reset state via the Select-DR-Scan state and the Select-IR-Scan state, and a practically inactive state loop is executed, and the actual operation This prevents the occurrence of malfunction.

  FIG. 4 shows the inactive state loop described above. None of the TMS inputs of this inactive state loop are in the JTAG interface and do not generate any actual operation, so that the present invention defines at least two TMS input strings that match this inactive state loop; Two different types of data A and B are input. In this embodiment, A is a binary number 0, B is a binary number 1, and according to the present invention, as shown in the figure, the TMS input string “0111” is preferably input data B (= 1). The subsequent TMS input string “1” is defined as input data A (= 0). In addition, in the Run-Test / Idle state, when the input is 0, none of the states are changed, and thereby the TMS input string “0 [0] 111” can be defined as the input data B, of which [0] Represents at least one zero.

  Further, FIG. 5 shows a circuit diagram of the above-described confidential data detection and access controller 35. It comprises a state detector 51, a shift register 52 and a comparison device 50. The comparator 37 with built-in comparator 50 has three comparators 53, 54, and 55, and the operation flow of the state detector 51 is as shown in FIG. 6. The TCK and TMS inputs and the TAP controller 31 When it is determined from the generated JTAG state that the state of the TAP controller 31 is the start Test-Logic Reset state, monitoring of the TMS input is started, and when the TMS input string “0111” is detected, the data output is performed. The terminal 511 outputs data B (= 1) (step S601). Thereafter, when the TMS input string “1” is detected, the data output terminal 511 outputs data A (= 0) (step S602). Data output from the data output terminal 511 is sampled from the TCK and stored in the shift register 52. Thus, by inputting an appropriate string combination to the TMS pin, the data output terminal 511 of the state detector 51 generates a data combination necessary for input, and this data combination is stored in the shift register 52. The

  A part of the combination of data stored in the shift register 52 is an input key value, and another part is a write data. In this embodiment, an odd bit of the combination of data is an input key value. The even bits of the data combination are written data, and the comparators 53, 54, 55 compare the input key value with the write key value, the read key value, and the recovery key value, and when the input key value and the write key value are the same. When the comparator 53 outputs a write control signal and the input key value is the same as the read key value, the comparator 54 outputs the read control signal and when the input key value is the same as the recovery key value, the comparator 55 recovers. Output a control signal.

  See also FIG. The write control signal of the above operation sets (SET) the built-in register 37, loads the above-mentioned write data, and when writing data confidentially, the data of the state detector 51 is combined by the combination of the strings of the TMS pin input. An input key value equal to this data and the write key value is generated at the output terminal 511, thereby generating a write control signal and writing this data into the built-in register 37.

  The read control signal for the above operation controls the selector 38 to output the contents of the built-in register 37, and the recovery control signal for the above operation controls the selector 38 to output the contents of the identification code register 321. When it is desired to read the contents of the built-in register 37, an input key value equal to the read key value is generated at the data output terminal 511 of the state detector 51 by combining an appropriate string of the TMS pin input, and thereby the read control signal And the selector 38 is controlled to output the contents of the built-in register 37 through the output path of the identification code register defined by the JTAG interface. When the contents of the internal register 37 are not read any more, an input key value equal to the recovery key value is generated at the data output terminal 511 of the state detector 51 by combining an appropriate string of the TMS pin input, and thereby recovery control is performed. A signal is generated to control the selector 38 and output the contents of the identification code register 321. That is, the contents of the identification code register are output through the output path of the identification code register defined by the JTAG interface. Recover to state.

  As can be seen from the above description, the present invention uses the inactive state loop in the state shift diagram of the boundary scan test interface to transmit the confidential signal and input the signal without going through the standard data input / output pins. Achieves the objective of protecting the transmission of confidentiality control signals within the boundary scan test interface standard, and does not completely affect all states and data paths of the boundary scan test interface; Compatible with scanning test interface standards.

It is a structural diagram of a well-known JTAG interface. It is a state shift figure of the TAP controller of a known JTAG interface. FIG. 3 is a structural diagram of a boundary scan test interface of the present invention. It is a non-action state loop display figure in the state shift figure of the TAP controller of this invention. FIG. 4 is an electrical schematic of the sensitive data detection and access controller of the boundary scan test interface of the present invention. It is a driving | operation flowchart of the state detector of this invention.

Explanation of symbols

11, 31 TAP controller 12, 32 Test data register 121 Scan chain register 122, 321 Identification code register 123 Bypass register 13, 33 Instruction register 14, 34 Decoder 21 Idle process 22 Data register process 23 Instruction register process 35 Sensitive data detection and access Controller 37 Built-in register 38 Selector 50 Comparator 51 Status detector 511 Data output terminal 52 Shift registers 53, 54, 55 Comparator

Claims (28)

A built-in data access device in a boundary scan test interface, the boundary scan test interface including a TAP controller, a test data register, an instruction register, and a decoder, the test data register receiving a serial command input by a serial data input pin The TAP controller executes a state shift by inputting a mode selection input pin according to a predetermined state shift diagram, and operates by a serial instruction stored in the data of the test data register and the instruction register. The state shift comprises at least one inactive state loop, the device comprising a state detector, a shift register, a built-in register, and a comparator.
The state detector monitors the input of the mode selection input pin and outputs the first data when detecting the first setting input string, and then outputs the second data when detecting the second setting input string. The first setting input string and the second setting input string match different input strings of the inactive state loop;
The shift register stores a combination of first and second data output from the state detector, and the combination of the first and second data has an input key value;
The built-in register is used for data storage,
The comparison device compares the input key value with the set write key value, and when the two match, loads the specific write data into the built-in register, the built-in data access in the boundary scan test interface apparatus.   2. The built-in data access device in a boundary scan test interface according to claim 1, wherein the combination of the first and second data further includes information of specific write data. .   3. The built-in data access device in the boundary scan test interface according to claim 2, further comprising a selector for selecting the contents of a built-in register or a specific register defined by the boundary scan test interface and outputting it. Built-in data access device in scan test interface.   4. The built-in data access device in the boundary scan test interface according to claim 3, wherein the comparison device compares the input key value with the set recovery key value and controls the selector to output the contents of the built-in register when the two match. A built-in data access device in a boundary scan test interface.   4. The built-in data access device in the boundary scan test interface according to claim 3, wherein the comparison device compares the input key value with the set read key value and controls the selector to output the contents of the specific register when they match. A built-in data access device in a boundary scan test interface.   3. The built-in data access device in the boundary scan test interface according to claim 2, wherein the input key value is an odd bit of the first and second data, and the specific write data is an even bit of a combination of the first and second data. A built-in data access device in a boundary scan test interface. 3. The built-in data access device in the boundary scan test interface according to claim 2, wherein the boundary scan test interface is a JTAG interface, and the input of the mode selection input pin is a TMS input. Built-in data access device. 3. The built-in data access device in the boundary scan test interface according to claim 2, wherein the boundary scan test interface is an IEEE 1149.1 interface, and the input of the mode selection input pin is a TMS input. Built-in data access device inside. 3. The built-in data access device in the boundary scan test interface according to claim 2, wherein the boundary scan test interface is an IEEE 1149.4 digital test access port interface, and the input of the mode selection input pin is a TMS input. Built-in data access device in the boundary scan test interface.   8. The built-in data access device in the boundary scan test interface according to claim 7, wherein the state shift diagram is started in a test logic reset (Test-Logic Reset) state and when the TMS input is 1, the state is retained and unchanged. When the TMS input is 0, the state is shifted to the Run-Test / Idle state, and when the TMS input is 0, the state is maintained and unchanged, and the subsequent three TMS inputs are 1. A built-in data access device in a boundary scan test interface characterized in that when 1, the state shifts to a test logic reset state to form at least one inactive state loop.   11. The built-in data access device in the boundary scan test interface according to claim 10, wherein the first setting input string is "0111" and the second setting input string is "1". Built-in data access device in the interface.   12. The built-in data access device in the boundary scan test interface according to claim 11, wherein the first data is set to “1” and the second data is set to “0”. Data access device.   11. The built-in data access device in the boundary scan test interface according to claim 10, wherein the first setting input string is “0 [0] 111”, the second setting input string is “1”, of which [0] is Built-in data access device in a boundary scan test interface, characterized in that it represents at least one zero.   14. The built-in data access device in the boundary scan test interface according to claim 13, wherein the first data is "1" and the second data is "0". Data access device.   8. A built-in data access device in a boundary scan test interface according to claim 7, wherein data output from the state detector is sampled by a TCK signal defined by JTAG and stored in a shift register. Built-in data access device in the interface.   3. The built-in data access device in the boundary scan test interface according to claim 2, wherein the specific register is an identification code register. In the built-in data access method in the boundary scan test interface, the boundary scan test interface includes a TAP controller, a test data register, an instruction register, and a decoder, and the test data register stores a serial instruction input by a serial data input pin. The TAP controller performs a state shift by inputting a mode selection input pin according to a predetermined state shift diagram, and operates by a serial instruction stored in the data of the test data register and the instruction register , and the execution thereof The state shift to include at least one inactive state loop, the method comprising:
(A) The state detector monitors the input of the mode selection input pin, outputs the first data when detecting the first setting input string, and outputs the second data when detecting the second setting input string. Where the first set input string matches the input string of the inactive state loop, the second set input string is not the same as the first set input string and the input string of the inactive state loop A step that shall match
(B) storing a combination of the first and second data output from the shift register, wherein the combination of the first and second data includes an input key value;
(C) a step of comparing the input key value with the set write key value by a comparison device, and when the two match, loading specific write data into the built-in register;
A built-in data access method in a boundary scan test interface characterized by comprising the above steps.   18. The built-in data access method in the boundary scan test interface according to claim 17, wherein the combination of the first and second data further includes information of specific write data. . 19. The built-in data access method in the boundary scan test interface according to claim 18, wherein (D) the input key value is compared with the set read key value by the comparison device, and when the two match, the contents of the built-in register are boundary scanned. A built-in data access method in a boundary scan test interface, wherein the data is output through an output path of a specific register defined by the test interface.   20. The built-in data access method in the boundary scan test interface according to claim 19, wherein (E) the input key value is compared with the set recovery key value, and when both match, the contents of the specific register are A built-in data access method in a boundary scan test interface, further comprising: outputting through an output path of a specific register to be defined.   19. The built-in data access method in the boundary scan test interface according to claim 18, wherein during step (B), the input key value is an odd bit of a combination of the first and second data, and the specific write data is the first and second data. A built-in data access method in a boundary scan test interface, characterized in that even bits of a combination of data are used. 19. The built-in data access method in the boundary scan test interface according to claim 18, wherein the boundary scan test interface is a JTAG interface, and the input of the mode selection input pin is a TMS input. Built-in data access method. 19. The built-in data access method in a boundary scan test interface according to claim 18, wherein the boundary scan test interface is an IEEE 1149.1 interface, and the input of the mode selection input pin is a TMS input. Internal data access method inside. 19. The built-in data access method in the boundary scan test interface according to claim 18, wherein the boundary scan test interface is an IEEE 1149.4 digital test access port interface, and the input of the mode selection input pin is a TMS input. Built-in data access method in boundary scan test interface.   23. The built-in data access method in the boundary scan test interface according to claim 22, wherein the state shift diagram starts in a test logic reset (Test-Logic Reset) state and when the TMS input is 1, the state is retained and unchanged. When the TMS input is 0, the state is shifted to the Run-Test / Idle state, and when the TMS input is 0, the state is maintained and unchanged, and the subsequent three TMS inputs are 1. A built-in data access method in a boundary scan test interface characterized in that when 1, the state shifts to a test logic reset state to form at least one inactive state loop.   26. The built-in data access method in the boundary scan test interface according to claim 25, wherein, during step (A), the first setting input string is set to “0111”, the first data is set to “1”, and the second setting input is set. A built-in data access method in a boundary scan test interface, wherein the string is “1” and the second data is “0”.   26. The built-in data access method in the boundary scan test interface according to claim 25, wherein the first setting input string is "0 [0] 111", the first data is "1", and [0] is at least one. A built-in data access method in a boundary scan test interface, wherein the second setting input string is set to “1” and the second data is set to “0”, representing two zeros.   20. The built-in data access method in the boundary scan test interface according to claim 19, wherein the specific register is an identification code register.

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