JP3809155B2 - Switching power supply controller - Google Patents

Description

  The present invention relates to a control device for a multiphase switching power supply device.

  The switching power supply device has features such as small size, light weight and high efficiency, and is widely used as a power source for microcomputers and personal computers incorporated in various devices. In these personal computers and the like, the voltage consumption and the high-speed processing are advanced, and the current consumption is increasing. Therefore, in the switching power supply device, the load current increases or decreases rapidly depending on the processing load in the personal computer or the like. In addition, the switching power supply device has a feature that it can easily cope with a wide input voltage range, and is also used as a power supply that can be supported in several countries around the world and a power supply with a wide input voltage specification setting. In a switching power supply device, it is necessary to ensure a stable output voltage against such changes in load current and input voltage. Furthermore, even when the output voltage has a transient response to a sudden change in load current or input voltage, the switching power supply is required to quickly recover to a stable state.

  For this purpose, the switching power supply device is provided with a control device such as a digital control type controller IC [Integrated Circuit], and this control device turns on and off switching elements such as FET [Field Effect Transistor] at high speed (non- Patent Document 1). The control device generates a PWM [Pulse Width Modulation] signal for turning on / off the switching element based on the output voltage of the switching power supply device or the like by feedback control using voltage mode control or current mode control.

Moreover, in order to suppress the ripple of an output voltage, there exists a multiphase system switching power supply device (refer patent document 1). In the multiphase system, a plurality of converter circuits are connected in parallel, and the plurality of converter circuits are controlled by a single control device. And in this control apparatus, the phase of the pulse of the PWM signal with respect to each converter circuit is shifted so that the ON period of the switching element of each converter circuit may not overlap.
JP 2002-44941 A Harada Kosuke, Ninomiya Tadashi and Keibun Kenji, “Basics of Switching Converters”, Corona, p. 48-79

  However, in the switching power supply device, the output circuit is composed of an LC smoothing circuit, so that a phase delay occurs in the control system. This phase delay increases as the frequency increases, and when the gain is 1 or more and the phase delay reaches 180 °, the switching power supply device oscillates the output voltage. Similarly, a multi-phase switching power supply device also has a problem of phase delay, and the output voltage may oscillate.

  Accordingly, an object of the present invention is to provide a control device for a switching power supply device that compensates for a phase in a multiphase switching power supply device.

The switching power supply control device according to the present invention detects a time ratio of a driving signal for controlling a switching element of a multiphase switching power supply device in which a plurality of converter circuits are connected in parallel, and corresponds to the time ratio. A time ratio generating means for generating the generated signal, a calculation means for calculating a signal corresponding to the time ratio of the drive signal generated by the time ratio generating means, blocking low frequency components and integrating, and a target in the switching power supply The control signal generating means for generating a control signal based on the difference value between the voltage and the output voltage detected by the switching power supply device, and the difference between the control signal generated by the control signal generating means and the signal calculated by the calculating means is calculated. a differential means for, viewing contains a drive signal generating means for generating a drive signal based on the calculated signal and the ramp signal by the differentiating means, a time ratio Generating means, and detects the duty ratio of the driving signal generated by the drive signal generating means.

  This switching power supply apparatus is a multiphase system in which a plurality of converter circuits are connected in parallel. In the control device, in order to control the output voltage to the target voltage by feedback control, the control signal generating means generates a control signal based on the difference value between the actual output voltage of the switching power supply device and the target voltage. In the control device, the time ratio of the drive signal for controlling the switching element is detected by the time ratio generating means, and a signal corresponding to the detected time ratio is generated. Further, in the control device, the low frequency component is blocked and integrated with respect to the signal corresponding to the time ratio by the calculating means, and the control signal and the signal calculated by the calculating means are differentiated by the difference means. And in a control apparatus, a drive signal is produced | generated based on the signal and ramp signal which differed by the drive signal production | generation means, and each drive signal is each output to the switching element of each converter circuit. In this way, the control device feeds back the time ratio that is the output of the control device, and performs a calculation that becomes phase advance (integration) and DC gain securing (low frequency component cutoff) for the signal corresponding to the time ratio, The control signal is corrected using the calculated time ratio, and the drive signal is generated based on the corrected control signal. Therefore, the transfer function in the control device has a phase advance, and the transfer function of each converter circuit driven by the drive signal also has a phase advance. Therefore, in the switching power supply device, the phase advance of the entire system is realized and the phase is compensated. As a result, the switching power supply device does not oscillate due to phase delay. The time ratio generating means may be configured as means for directly detecting the time ratio from the drive signal output from the control device, or may be configured as means for using a value calculated in the control device.

  The drive signal is a signal for turning on / off the switching element of the switching power supply device, and is, for example, a PWM signal. The control signal is a signal for performing feedback control, and is a signal based on the output voltage actually detected in the switching power supply device and the target voltage. The time ratio is the ratio of the period during which the switching element is turned on in one cycle of the drive signal (that is, the ratio of the on period in one cycle of the switching operation). For example, the pulse width or duty for each cycle of the PWM signal The ratio corresponds to the duty ratio. The signal corresponding to the time ratio is various signals representing the time ratio. For example, the signal of the time ratio actually detected from the drive signal, the signal obtained by averaging the detected time ratio, the average of the time ratio and the time ratio It is a value calculated in the control device corresponding to the value.

A control device for a switching power supply according to the present invention is a drive signal for controlling a switching element of a converter circuit corresponding to each converter circuit in a multiphase switching power supply in which a plurality of converter circuits are connected in parallel. A plurality of time ratio generating means for detecting a time ratio and generating a signal corresponding to the time ratio, and a signal corresponding to the time ratio of the drive signal generated by each time ratio generating means corresponding to each converter circuit A plurality of calculation means for calculating and blocking low frequency components and performing integration; an averaging means for averaging signals calculated by the plurality of calculation means; and a target voltage in the switching power supply device and detected by the switching power supply device A control signal generating means for generating a control signal based on a difference value from the output voltage, and a control signal generated by the control signal generating means; Difference means for calculating a difference from the signal averaged by the averaging means, and a plurality of drive signal generation means for generating a drive signal based on the signal calculated by the difference means and the ramp signal corresponding to each converter circuit only including, when ratio generating means, and detects the duty ratio of the driving signal generated by the drive signal generating means.

  The control device includes a time ratio generation unit, a calculation unit, and a drive signal generation unit corresponding to the plurality of converter circuits. In the control device, corresponding to each converter circuit, the time ratio generating means detects the time ratio of the drive signal for controlling the switching element of each converter circuit, and outputs a signal corresponding to the detected time ratio. Each is generated, the low frequency components are cut off from the signals corresponding to the respective time ratios by the respective arithmetic means, and the integration is performed. Further, in the control apparatus, the averaging means averages the signals calculated by the respective calculating means, and the difference means compares the control signal and the signal averaged by the averaging means. Then, the control device generates a drive signal based on the signal and the ramp signal that are different from each other by the drive signal generation means corresponding to each converter circuit, and outputs each drive signal to the switching element of each converter circuit. Thus, in this control device as well as the above control device, the calculation corresponding to the phase ratio and the DC gain is performed on the signal corresponding to the time ratio, and the control signal is obtained using the calculated time ratio. Is corrected, the transfer function in the control device becomes the phase advance. As a result, in the switching power supply device, the phase advance of the entire system is realized and phase compensation is performed, and oscillation due to phase delay does not occur. In particular, since the control device is configured to correct the control signal with the signal averaged by the averaging means, phase compensation up to a high frequency region is possible.

A control device for a switching power supply according to the present invention is a drive signal for controlling a switching element of a converter circuit corresponding to each converter circuit in a multiphase switching power supply in which a plurality of converter circuits are connected in parallel. A plurality of time ratio generating means for detecting a time ratio and generating a signal corresponding to the time ratio, and a signal corresponding to the time ratio of the drive signal generated by each time ratio generating means corresponding to each converter circuit Control signal generation that generates a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device, and a plurality of calculation means for calculating and blocking low frequency components and integrating And a control signal generated by the control signal generation means and a signal calculated by each calculation means corresponding to each converter circuit A plurality of differentiating means for calculating the difference, in correspondence with each converter circuit, seen including a plurality of drive signal generating means for generating a drive signal based on the calculated signal and a ramp signal with each difference means, the duty ratio generated The means detects the duty ratio from the drive signal generated by the drive signal generation means .

  The control device includes a time ratio generation unit, a calculation unit, a difference unit, and a drive signal generation unit, corresponding to the plurality of converter circuits. In the control device, corresponding to each converter circuit, the time ratio generating means detects the time ratio of the drive signal for controlling the switching element of each converter circuit, and outputs a signal corresponding to the detected time ratio. Each is generated, each low-frequency component is cut off for each signal corresponding to each time ratio by each calculation means and integration is performed, and each control means and each signal calculated by each calculation means is each difference by each difference means. To do. Then, in the control device, each drive signal generation unit corresponding to each converter circuit generates a drive signal based on the signal and the ramp signal obtained by the difference unit, and the generated drive signal is used as a switching element of each converter circuit. To each output. Thus, in this control device as well as the above control device, the calculation corresponding to the phase ratio and the DC gain is performed on the signal corresponding to the time ratio, and the control signal is obtained using the calculated time ratio. Is corrected, the transfer function in the control device becomes the phase advance. As a result, in the switching power supply device, the phase advance of the entire system is realized and phase compensation is performed, and oscillation due to phase delay does not occur. Since this control device does not require an averaging means unlike the control device, the configuration is simplified.

A control device for a switching power supply according to the present invention is a drive signal for controlling a switching element of a converter circuit corresponding to an arbitrary converter circuit in a multiphase switching power supply in which a plurality of converter circuits are connected in parallel. A time ratio generating means for detecting the time ratio and generating a signal corresponding to the time ratio and a signal corresponding to the time ratio of the drive signal generated by the time ratio generating means, and cutting off the low frequency component Calculation means for performing integration, control signal generation means for generating a control signal based on a difference value between a target voltage in the switching power supply apparatus and an output voltage detected by the switching power supply apparatus, and a control signal generated by the control signal generation means And a difference means for calculating a difference between the signal calculated by the calculation means and a difference means corresponding to each converter circuit. Signal and saw including a plurality of drive signal generating means for generating a drive signal based on the ramp signal, the duty ratio generating means, and detects the duty ratio of the driving signal generated by the drive signal generating means .

  The control device includes drive signal generation means corresponding to the plurality of converter circuits, and also includes time ratio generation means and calculation means for any one of the plurality of converter circuits. . Then, in the control device, the time ratio generating means detects the time ratio of the drive signal for controlling the switching element of an arbitrary converter circuit, generates a signal corresponding to the detected time ratio, and the arithmetic means calculates the time ratio. The low frequency component is cut off and integrated for the signal corresponding to. Further, in the control device, the difference means makes a difference between the control signal and the signal calculated by the calculation means. In the control device, each drive signal generation unit corresponding to each converter circuit generates a drive signal based on the signal obtained by the difference unit and the ramp signal, and outputs each drive signal to the switching element of each converter circuit. To do. Thus, in this control device as well as the above control device, the calculation corresponding to the phase ratio and the DC gain is performed on the signal corresponding to the time ratio, and the control signal is obtained using the calculated time ratio. Is corrected, the transfer function in the control device becomes the phase advance. As a result, in the switching power supply device, the phase advance of the entire system is realized and phase compensation is performed, and oscillation due to phase delay does not occur. In particular, since this control device can be configured with only one duty ratio generating means and computing means, the configuration is simplified.

A control device for a switching power supply according to the present invention is a drive signal for controlling a switching element of a converter circuit corresponding to an arbitrary converter circuit in a multiphase switching power supply in which a plurality of converter circuits are connected in parallel. A time ratio generating means for detecting the time ratio and generating a signal corresponding to the time ratio and a signal corresponding to the time ratio of the drive signal generated by the time ratio generating means, and cutting off the low frequency component Calculation means for performing integration, control signal generation means for generating a control signal based on a difference value between a target voltage in the switching power supply apparatus and an output voltage detected by the switching power supply apparatus, and a control signal generated by the control signal generation means Difference means for calculating the difference between the signal calculated by the calculation means and the signal calculated by the difference means and the ramp signal. Corresponding to each converter circuit other than an arbitrary converter circuit, and one or a plurality of driving signals generated by the drive signal generating means with a predetermined delay according to each converter circuit. look including a delay means, when the ratio generation unit, and detects the duty ratio of the driving signal generated by the drive signal generating means.

  The control device includes a time ratio generation unit, a calculation unit, and a drive signal generation unit for any one of the plurality of converter circuits, and includes a delay unit for each of the other converter circuits. ing. Then, in the control device, the time ratio generating means detects the time ratio of the drive signal for controlling the switching element of an arbitrary converter circuit, generates a signal corresponding to the detected time ratio, and the arithmetic means calculates the time ratio. The low frequency component is cut off and integrated for the signal corresponding to. Further, in the control device, the difference signal is used to make a difference between the control signal and the signal calculated by the calculation means, and the drive signal generation means generates a drive signal based on the difference signal and the ramp signal. In the control device, each delay means corresponding to another converter circuit delays the drive signal generated by the drive signal generation means, respectively, generates a drive signal corresponding to the other converter circuit, and corresponds each drive signal. Output to the switching element of each converter circuit. Thus, in this control device as well as the above control device, the calculation corresponding to the phase ratio and the DC gain is performed on the signal corresponding to the time ratio, and the control signal is obtained using the calculated time ratio. Is corrected, the transfer function in the control device becomes the phase advance. As a result, in the switching power supply device, the phase advance of the entire system is realized and phase compensation is performed, and oscillation due to phase delay does not occur. In particular, since this control device can be configured with only one duty ratio generating means and computing means, the configuration is simplified.

  It should be noted that the predetermined delay means that an on period of a drive signal for any converter circuit generated by the drive signal generation means (in order to turn on the switching elements of other converter circuits by shifting the phase by the multiphase method) The period for turning on the switching element) is delayed by a predetermined time determined for each converter circuit.

  The switching power supply controller according to the present invention may include an initial value generating unit that generates an initial value of the ramp signal based on the time ratios generated by the plurality of time ratio generating units.

  In the control device having each of the time ratio generating means corresponding to the plurality of converter circuits, the initial value generating means generates the initial value of the ramp signal based on the time ratio generated by each of the time ratio generating means, and generates the drive signal. A drive signal is generated based on the ramp signal and the control signal with the initial value taken into account by the means. Since the respective time ratios of the plurality of converter circuits are reflected in the output voltage, there is a difference in the time ratios of the respective converter circuits when the output voltage varies. Therefore, by resetting each ramp signal with the initial value based on the time ratio of each converter circuit, the initial value of each ramp signal varies along with the variation of the output voltage (and hence the variation of the control signal). As a result, in the control device, even when the output voltage fluctuates, the difference in the width of the ON period of the drive signal of each converter circuit can be suppressed, and the time ratio between the converters can be balanced. Therefore, a difference in output current between the converter circuits is also suppressed, and a current balance between the converter circuits can be achieved. For this reason, in this control device, it is possible to prevent the deterioration of the elements over time due to the imbalance in the current balance between the converter circuits, the element destruction, and the like, and no means for detecting the output current is required.

  In the switching power supply controller of the present invention, the initial value generating means includes a plurality of time averaging means for time averaging the time ratios generated by the respective time ratio generating means, and time averaging by an arbitrary time averaging means. It is good also as a structure containing the initial value calculating means which calculates the difference with the value calculated | required from each signal which carried out the time averaging by the several signal and the several time averaging means.

  In this control device, the time ratio generated by each time ratio generating means by each time averaging means is time averaged, and the time averaged signal by an arbitrary time averaging means by the initial value calculating means and a plurality of time averages The difference from the value obtained from each signal averaged by the means is calculated, and each difference value is set as the initial value of each ramp signal. The values obtained from the signals averaged by the plurality of time averaging means are the minimum value, maximum value, average value, etc. of the plurality of time averaged signals.

  In the switching power supply controller according to the present invention, it is preferable that the time averaging means is a low-pass filter.

  In this control device, the time ratios generated by the respective time ratio generating means are respectively input to the low-pass filters, and the time ratios input in the past by the respective low-pass filters are averaged. In this control device, the time averaging means can be configured easily using the averaging function of the low-pass filter.

  In the control device for a switching power supply according to the present invention, the time ratio generating means includes a counter, and the counter counts the on period or the off period of the drive signal at regular intervals, and the count value at the fall of the on period Alternatively, the count value at the rise of the off period may be held until the next count time.

  In this control device, the drive signal output from the control device is fed back to the counter. In the control device, the counter counts the ON period or OFF period of the switching element in the drive signal at regular intervals such as the master clock of the control device, and the count value at the fall of the ON period or at the rise of the OFF period The count value is held until the next count. Since this count value corresponds to the duty ratio, this control device can easily constitute the duty ratio generating means by the counter. In addition, the control device holds the count value until the next count time, so even if the output signal fluctuates and the control signal fluctuates, various calculations can be performed on the correct duty ratio, and high-precision control It can be performed.

  In the switching power supply controller of the present invention, the ramp signal is preferably a signal counted by a counter.

  In this control device, a drive signal is generated by using a signal counted by a counter for generating a duty ratio as a ramp signal in the drive signal generating means. Therefore, in this control apparatus, since the detection of the duty ratio and the generation of the ramp signal are configured by the same counter, the configuration is simplified.

  In the switching power supply device control device of the present invention, the calculation means may be a calculation circuit that combines a high-pass filter function and an integration function.

  In this control device, a low-frequency component is blocked and integrated with respect to a signal corresponding to a time ratio by an arithmetic circuit that combines a high-pass filter function and an integration function, and phase advance is performed on the signal corresponding to the time ratio. And an operation to ensure DC gain.

  In the switching power supply controller according to the present invention, the calculation means includes a high-pass filter that cuts off a low-frequency component included in a signal corresponding to a time ratio of the drive signal, and a signal in which the low-frequency component is cut off by the high-pass filter. It is good also as a structure containing the integration means to integrate.

  In this control device, the low-frequency component included in the signal corresponding to the time ratio is cut off by the high-pass filter, the signal that cut off the low-frequency component is integrated by the integrating means, and the phase advance is performed with respect to the signal corresponding to the time ratio. And an operation to ensure DC gain.

  ADVANTAGE OF THE INVENTION According to this invention, the phase in the switching power supply device of a multiphase system can be compensated, and it can prevent that an output voltage oscillates.

  Embodiments of a switching power supply control device according to the present invention will be described below with reference to the drawings.

  In the present embodiment, the switching power supply controller according to the present invention is applied to a controller IC of a multiphase switching power supply in which two converter circuits are connected in parallel. The converter circuit according to the present embodiment is a step-down DC / DC converter. The controller IC according to the present embodiment is a digital control type that performs processing at high speed, and feedback-controls two converter circuits by voltage mode control. The controller IC according to the present embodiment has four embodiments depending on the configuration for performing phase compensation. The first embodiment corresponds to claim 2 and the second embodiment is Corresponding to claim 3, the third embodiment corresponds to claim 4, the fourth embodiment corresponds to claim 5, and in particular, the first embodiment and the second embodiment. A configuration for performing current balance (time ratio balance) is also added to the controller IC.

  With reference to FIG. 1, the configuration of switching power supply device 1 according to the present embodiment will be described. FIG. 1 is a configuration diagram of a switching power supply device according to the present embodiment.

The switching power supply device 1 is a power supply circuit that converts a DC input voltage V _I of a power supply P into a DC output voltage V _O (<V _I ), and can be used in various applications. For example, VRM [Voltage Regulator Module] Used in. The switching power supply device 1 is a switching regulator that turns on / off the switching element by PWM control. The input voltage V _I is variable, and an input voltage range (for example, 5 to 12 V) is set. The output voltage V _O is set to a constant target voltage (for example, 1 V) according to the load L. The load L corresponds to, for example, a CPU, an MPU, or a DSP such as a communication device such as a computer or a router, and the load current greatly varies depending on the processing load.

  In addition, the switching power supply device 1 is a multi-phase method in order to suppress ripples in the output voltage. Therefore, in the switching power supply device 1, the first converter circuit 2 and the second converter circuit 3 are connected in parallel. In the switching power supply device 1, the switching elements of the two converter circuits 2 and 3 are subjected to switching control by shifting the turning-on timing of the switching elements of the converter circuits 2 and 3 by one controller IC 4.

The converter circuits 2 and 3 have the same configuration, and as a main configuration, two switching elements 10 and 11 or switching elements 12 and 13 such as FETs, and an inductor 14 or an inductor 15 are shared by the two circuits. A capacitor 16 is provided. In the first converter circuit 2, the first switching element 10 is turned on when the first PWM signal PS1 from the controller IC4 is a high signal (on period), and the second switching element 11 is turned on when the first PWM signal PS1 is a low signal (off period). ) Is turned on. In the second converter circuit 3, the first switching element 12 is turned on when the second PWM signal PS2 from the controller IC 4 is a high signal (on period), and the second switching element 13 is turned on when the second PWM signal PS2 is a low signal ( Turns on during the off period. The inductor 14 (15) and the capacitor 16 constitute a smoothing circuit. By the switching operation of the switching elements 10, 11 (12, 13), a pulse voltage having an amplitude equal to the input voltage V _I is output to the smoothing circuit, and the pulse voltage is averaged in the smoothing circuit. The controller IC 4, and generates a PWM signal PS1, PS2 voltage mode control based on the output voltage V _O of the digital to the output voltage V _O becomes the target voltage, controlling on / off switching elements 10-13.

  The configuration of the controller IC 4A according to the first embodiment will be described with reference to FIG. 2, FIG. 13, and FIG. FIG. 2 is a configuration diagram of the controller IC according to the first embodiment. FIG. 13 is a timing chart of duty ratio detection and PWM signal generation in the controller IC of FIG. 2, wherein (a) is a master clock, (b) is a first counter signal, a second counter signal, and a correction control signal. (C) is the first PWM signal, (d) is the first on-timing signal, (e) is the second PWM signal, (f) is the second on-timing signal, and (g) is The first pulse width to be held, and (h) is the second pulse width to be held. 14 is a timing chart of the duty ratio balance in the controller IC of FIG. 2, (a) is the first counter signal, the second counter signal and the correction control signal, (b) is the first PWM signal, c) is the second PWM signal, (d) is the first pulse width held, (e) is the second pulse width held, and (f) is the first initial value for the first counter signal. (G) is the second initial value for the second counter signal.

The controller IC 4A is a digital circuit that operates based on a master clock (for example, 10 MHz to 100 MHz), and controls the two converter circuits 2 and 3 in voltage mode. The controller IC 4A generates a control signal CS from the A / D converted digital output voltage V _O and the target voltage V _R by feedback control based on P control, and generates a control signal CS and a first counter signal (ramp signal) CT1. The first PWM signal PS1 is generated based on the control signal CS and the second PWM signal PS2 is generated based on the control signal CS and the second counter signal (ramp signal) CT2. In particular, the controller IC 4A feeds back the generated PWM signals PS1 and PS2 by means of a minor loop to achieve phase compensation and DC gain securing, and the pulse widths (duty ratios) D1 and D2 of the PWM signals PS1 and PS2 are predetermined. The control signal CS is corrected by the average signal AV of the phase compensation signals IE1 and IE2 that have been subjected to the respective calculations. Further, the controller IC4A is based on the pulse widths D1 and D2 of the PWM signals PS1 and PS2 in order to balance the duty ratio of the PWM signals PS1 and PS2 (and hence the balance of output current between the converter circuits 2 and 3). Thus, initial values CI1 and CI2 of the counter signals (ramp signals) CT1 and CT2 are generated. For this purpose, the controller IC 4A includes counters 20 and 20, arithmetic circuits 21 and 21, an averaging circuit 22, a subtractor 23, a multiplier 24, a subtractor 25, comparators 26 and 26, RS flip-flops 27 and 27, and initial value generation. A circuit 28 is provided. The controller IC 4A generates the PWM signals PS1 and PS2 for the two converter circuits 2 and 3, respectively, so as to correspond to the converter circuits 2 and 3, the counter 20, the arithmetic circuit 21, the comparator 26, and the RS flip-flop 27. Are provided. In the following description, a power supply voltage (for example, 5V) is set for the controller IC 4A for the high signal, and 0V is set for the low signal.

  In the first embodiment, the counters 20 and 20 correspond to a plurality of time ratio generating means described in the claims, and the arithmetic circuits 21 and 21 correspond to a plurality of arithmetic means described in the claims. The averaging circuit 22 corresponds to the averaging means described in the claims, the subtractor 23 and the multiplier 24 correspond to the control signal generating means described in the claims, and the subtractor 25 corresponds to the claims. The comparators 26 and 26 and the RS flip-flops 27 and 27 correspond to a plurality of drive signal generation units described in the claims, and the initial value generation circuit 28 corresponds to the claims. This corresponds to the initial value generation means described.

  The counter 20 detects a first pulse width D1 that is a time ratio of the first PWM signal PS1 or a second pulse width D2 that is a time ratio of the second PWM signal PS2, and is a first counter that is a ramp signal input to the comparator 26. The signal CT1 or the second counter signal CT2 is generated. Therefore, the counter 20 includes the first PWM signal PS1 or the second PWM signal PS2 generated by the controller IC 4A, the first on-timing signal OT1 or the second on-timing signal OT2, and the first initial signal generated by the initial value generating circuit 28. The value CI1 or the second initial value CI2 and the master clock MC are input.

  The counter 20 resets the counter signals CT1 and CT2 to the initial values CI1 and CI2 when the ON timing signals OT1 and OT2 are high signals, and counts every cycle of the master clock MC when the PWM signals PS1 and PS2 are high signals. (See FIGS. 13A to 13F and FIGS. 14A to 14C). The counter 20 stops counting up when the PWM signals PS1 and PS2 fall from a high signal to a low signal, and holds the count-up value when the PWM signals PS1 and PS2 are low signals (FIG. 13A to FIG. 13). (See (f) and FIGS. 14 (a) to 14 (c)). In the counter 20, the count-up value is held in each register (not shown) as pulse widths D1 and D2 (FIGS. 13B, 13G, 14H, 14A, 14D, 14D). e)). The pulse widths D1 and D2 held in the registers are read out to the arithmetic circuits 21 and 21 and the initial value generation circuit 28, respectively. Incidentally, the pulse widths D1 and D2 indicate the ratio of the period during which the first switching elements 10 and 12 are turned on in one period of the PWM signals PS1 and PS2 because the periods of the PWM signals PS1 and PS2 are constant. It corresponds to. 13 shows a case where the first initial value CI1 and the second initial value CI2 are both 0. FIG. 14 shows a case where the first initial value CI1 has a predetermined value and the second initial value CI2 is 0. is there.

  The first on-timing signal OT1 is a signal obtained by dividing the master clock MC by a frequency divider (not shown), and is a signal that defines one cycle of the first PWM signal PS1 (the switching cycle of the first converter circuit 2). Yes, a pulse defining the rising of the first PWM signal PS1 from a low signal to a high signal is output as a high signal (one cycle of the master clock MC) (see FIG. 13D). The second on-timing signal OT2 is a signal obtained by dividing the master clock MC by the frequency divider, is a signal that defines one cycle of the second PWM signal PS2 (the switching cycle of the second converter circuit 3), and the second PWM signal A pulse that defines the rise of PS2 from a low signal to a high signal is output as a high signal (one cycle of the master clock MC) (see FIG. 13F). The first PWM signal PS1 and the second PWM signal PS2 have the same cycle, and the phase of the turn-on timing is shifted by 180 °. The frequency of the PWM signals PS1 and PS2 is, for example, 100 kHz to 1 MHz, and corresponds to the switching frequency in the converter circuits 2 and 3.

  The arithmetic circuit 21 is an arithmetic circuit in which a secondary high-pass filter and an integrator are fused in order to realize phase advance and DC gain securing. The arithmetic circuit 21 reads the first pulse width D1 or the second pulse width D2 which is the duty ratio from each register, cuts off the low frequency component and performs integration with respect to the first pulse width D1 or the second pulse width D2. The first phase compensation signal IE1 or the second phase compensation signal IE2 is output to the averaging circuit 22. Thus, by providing the integrator in the arithmetic circuit 21, the transfer function of the controller IC 4A is advanced in phase, and phase compensation of the entire switching power supply device 1 can be realized. Further, the low-frequency component is cut off by the secondary high-pass filter in the arithmetic circuit 21, so that the integrated value can be prevented from being saturated (diverged to infinity).

  As shown in FIG. 3, the arithmetic circuit 21 includes D flip-flops 21a to 21c as delay units, a multiplier 21d with a multiplication coefficient (b1 + b2), a multiplier 21e with a multiplication coefficient (b1 * b2), and an adder 21f. have. The circuit configuration of the arithmetic circuit 21 is configured based on a transfer function H (Z) expressed by the following equation (1). FIG. 3 is a detailed circuit configuration diagram of the arithmetic circuit of FIG.

なお、演算回路２１は、図３に示す回路構成以外でも、式（１）の伝達関数を満たす回路であればよい。

The arithmetic circuit 21 may be a circuit that satisfies the transfer function of Expression (1) other than the circuit configuration shown in FIG.

  The averaging circuit 22 receives the first phase compensation signal IE1 and the second phase compensation signal IE2 from the arithmetic circuits 21 and 21, averages the two phase compensation signals IE1 and IE2, and subtracts the average signal AV from the subtractor 25. Output to. For this purpose, the averaging circuit 22 includes two multipliers 22a and 22a and an adder 22b. Each multiplier 22a multiplies the first phase compensation signal IE1 or the second phase compensation signal IE2 from each arithmetic circuit 21 by a gain ½, and outputs the multiplication value to the adder 22b. The adder 22b adds the multiplication values from the two multipliers 22a and 22a, and outputs the addition value as an average signal AV.

Subtractor 23, the target voltage V _R and output voltage V _O is input, subtracts the output voltage V _O from the target voltage V _R, the multiplier 24 the subtracted value (V _R -V _O) as a subtraction signal VS Output.

The multiplier 24 receives the subtraction signal VS, multiplies the subtraction signal VS by a gain G of P control, and outputs the multiplication value G (V _R −V _O ) to the subtracter 25 as a control signal CS.

  The subtracter 25 receives the control signal CS and the average signal AV, subtracts the average signal AV from the control signal CS, and uses the subtraction value (CS-AV) as the correction control signal RCS to each of the comparators 26 and 26. Output each.

  The comparator 26 determines whether the first counter signal CT1 or the second counter signal CT2, which is a ramp signal, reaches the correction control signal RCS. Therefore, the correction control signal RCS is input to the inverting input terminal of the comparator 26, and the first counter signal CT1 or the second counter signal CT2 is input to the non-inverting input terminal. The comparator 26 compares the correction control signal RCS with the counter signals CT1 and CT2, and sets the low signal until the counter signals CT1 and CT2 reach the correction control signal RCS, and when the counter signals CT1 and CT2 reach the correction control signal RCS. A high signal is set (see FIG. 13A). The comparator 26 outputs the output signal to the RS flip-flops 27 and 27 as the first comparator signal CO1 or the second comparator signal CO2, respectively.

  The RS flip-flop 27 generates the first PWM signal PS1 or the second PWM signal PS2. For this purpose, the first comparator signal CO1 or the second comparator signal CO2 and the first on-timing signal OT1 or the second on-timing signal OT2 are input to the RS flip-flop 27. In the RS flip-flop 27 that generates the first PWM signal PS1, when the first on-timing signal OT1 becomes a high signal, the low signal is switched to the high signal to hold the high signal, and when the first comparator signal CO1 becomes the high signal, the high signal Is switched to the low signal to hold the low signal, and the first PWM signal PS1 having the predetermined pulse width is output (see FIGS. 13C and 13D). In the RS flip-flop 27 that generates the second PWM signal PS2, the high signal is held by switching from the low signal to the high signal when the second on-timing signal OT2 becomes a high signal, and the high signal when the second comparator signal CO2 becomes the high signal. Is switched to the low signal to hold the low signal, and the second PWM signal PS2 having the predetermined pulse width is output (see FIGS. 13E and 13F).

  The initial value generating circuit 28 uses the first counter signal CT1 and the second counter signal CT1 in order to balance the time ratio between the first PWM signal PS1 and the second PWM signal PS2 (and hence the balance of output current between the converter circuits 2 and 3). A first initial value CI1 and a second initial value CI2 for resetting the counter signal CT2 are generated. For this purpose, the initial value generation circuit 28 includes two low-pass filters 28a and 28a and a calculation unit 28b.

  In the present embodiment, the low-pass filter 28a corresponds to the time averaging means described in the claims, and the calculation unit 28b corresponds to the initial value calculation means described in the claims.

  Each low-pass filter 28a reads the first pulse width D1 or the second pulse width D2, which is the time ratio held in each register, and averages the first pulse width D1 or the second pulse width D2 over time (FIG. 14 ( d) and (e)). Then, the computing unit 28b selects a smaller time average value from the time average value of the first pulse width D1 and the time average value of the second pulse width D2. Further, the calculation unit 28b calculates a first initial value CI1 by subtracting the selected small time average value from the time average value of the first pulse width D1 (see FIG. 14F). The first initial value CI1 is held in the register and serves as a reset value when the first counter signal CT1 is reset. Further, the calculation unit 28b calculates a second initial value CI2 by subtracting the selected small time average value from the time average value of the second pulse width D2 (see FIG. 14 (g)). The second initial value CI2 is held in the register and serves as a reset value when the second counter signal CT2 is reset. Incidentally, the reset value of the counter signal corresponding to the pulse width (time ratio) having a small time average value is 0, and the reset value of the counter signal corresponding to the pulse width (time ratio) having a large time average value is a predetermined value (plus When the two time average values are equal, the reset values of the two counter signals are both zero.

  Here, with reference to FIG. 4, the principle of realizing phase advance in the controller IC 4A will be described. FIG. 5 is a diagram illustrating an example of a control circuit that performs feedback in a feedback loop. Note that the phase advance is also realized by this principle in the controller ICs 4B, 4C, and 4D according to other embodiments.

  The control circuit 30 shown in FIG. 4 is configured in the same manner as the controller IC 4A, and shows an example of a control circuit that feeds back the integral value of the time ratios of the PWM signals PS1 and PS2 by a feedback loop. The control circuit 30 includes a multiplier 31 whose transfer function is −G, an integrator 32 whose transfer function is Gd, a multiplier 33 whose transfer function is kd, and an adder 34. The transfer function Gc (Z) of the control circuit 30 is obtained as a ratio of the change amount ΔV of the output voltage of the switching power supply device 1 input to the control circuit 30 and the change amount ΔD of the time ratio output from the control circuit 30. It is represented by the following formula (2). Further, the transfer function Gd (Z) of the integrator 32 is expressed by the following equation (3).

式（３）を式（２）に代入すると、制御回路３０の伝達関数Ｇｃ（Ｚ）は、以下に示す式（４）で求まる。

When Expression (3) is substituted into Expression (2), the transfer function Gc (Z) of the control circuit 30 is obtained by Expression (4) shown below.

ここで、一次のハイパスフィルタの伝達関数Ｈ（Ｚ）は、（１−Ｚ^-1）／（１−ｂ＊Ｚ^-1）；（ｂは係数）により表される。したがって、式（４）の伝達関数Ｇｃ（Ｚ）は、一次のハイパスフィルタの伝達関数で表されることが判る。すなわち、図４に示す帰還ループに積分器３２を有する制御回路３０の伝達関数Ｇｃ（Ｚ）は、一次のハイパスフィルタの伝達関数で表されることになる。一般に、一次のハイパスフィルタの伝達関数は、９０°の位相進みとなる。したがって、図４に示す帰還ループに積分器３２を有する制御回路３０の伝達関数Ｇｃ（Ｚ）も９０°の位相進みとなる。

Here, the transfer function H (Z) of the first-order high-pass filter is represented by (1-Z ⁻¹ ) / (1−b * Z ⁻¹ ); (b is a coefficient). Therefore, it can be seen that the transfer function Gc (Z) of Expression (4) is expressed by the transfer function of the first-order high-pass filter. That is, the transfer function Gc (Z) of the control circuit 30 having the integrator 32 in the feedback loop shown in FIG. 4 is represented by the transfer function of the first-order high-pass filter. In general, the transfer function of the first-order high-pass filter has a phase advance of 90 °. Therefore, the transfer function Gc (Z) of the control circuit 30 having the integrator 32 in the feedback loop shown in FIG. 4 also has a phase advance of 90 °.

  This can also be seen from the gain characteristic and phase characteristic of the transfer function Gc in the control circuit 30 shown in FIGS. Here, the transfer function Gc in the control circuit 30 is calculated with G as the transfer function of the multiplier 31 being 1. FIG. 5 is a diagram illustrating the gain characteristic of the transfer function in the control circuit of FIG. FIG. 6 is a diagram illustrating a phase characteristic of a transfer function in the control circuit of FIG. In the figure showing the gain characteristics, the vertical axis represents the gain [dB] and the horizontal axis represents the frequency [Hz]. In the diagram showing the phase characteristics, the vertical axis is the phase [°], and the horizontal axis is the frequency [Hz].

  As shown in FIG. 5, the gain of the transfer function Gc in the control circuit 30 decreases at a rate of −20 [dB / dec]. This is because the transfer function Gc of the control circuit 30 is proportional to the frequency.

  As shown in FIG. 6, the phase of the transfer function Gc in the control circuit 30 is 90 ° in a frequency band lower than a predetermined frequency (in the vicinity of 10 kHz in FIG. 6). This indicates that the phase of the transfer function Gc in the control circuit 30 is 90 ° phase advance.

  From the above, since the controller IC 4A fuses the integrator with the arithmetic circuit 21 in the feedback loop, similarly to the control circuit 30, the transfer function is expressed as a transfer function of the first-order high-pass filter, and 90 ° It is possible to realize the phase advance.

  By the way, the gain of the transfer function Gc in the control circuit 30 decreases at a rate of −20 dB / dec. This indicates that the DC gain of the transfer function Gc in the control circuit 30 is theoretically −∞ dB. The direct current gain is a gain value of a transfer function when the frequency is brought close to 0 as much as possible. Generally, the DC gain of the entire system including the control circuit is required to be about 20 to 60 dB. Therefore, it is necessary to design the circuit so that the DC gain of the entire system is about 20 to 60 dB. Therefore, in the controller IC 4A, by integrating a second-order high-pass filter with the arithmetic circuit 21, the low-frequency component of the feedback signal due to the feedback loop is blocked to prevent the gain from decreasing. Note that, in the controller ICs 4B, 4C, and 4D according to other embodiments, a DC gain is ensured by a secondary high-pass filter of an arithmetic circuit.

The gain characteristics and phase characteristics of the transfer function in the controller IC 4A, the converter circuits 2 and 3, and the switching power supply device 1 will be described with reference to FIGS. It is assumed that the input voltage V _I of the switching power supply device 1 is set to 10V. In addition, the transfer function in the controller IC 4A is calculated with G being 1 as the transfer function of the multiplier 24. FIG. 7 is a diagram illustrating the gain characteristic of the transfer function in the converter circuit of FIG. FIG. 8 is a diagram showing the phase characteristics of the transfer function in the converter circuit of FIG. FIG. 9 is a diagram illustrating a gain characteristic of a transfer function in the controller IC of FIG. FIG. 10 is a diagram illustrating a phase characteristic of a transfer function in the controller IC of FIG. FIG. 11 is a diagram illustrating a gain characteristic of a transfer function in the entire switching power supply apparatus of FIG. FIG. 12 is a diagram illustrating the phase characteristics of the transfer function in the entire switching power supply apparatus of FIG. Note that the controller ICs 4B, 4C, and 4D according to other embodiments, the converter circuits 2 and 3 controlled by these controller ICs, and the switching power supply device 1 are also the same as the gain characteristics and phase characteristics of the transfer function described here. The following characteristics can be obtained.

With reference to FIGS. 7 and 8, the gain characteristic and phase characteristic of the transfer function in the converter circuits 2 and 3 not including the controller IC 4A will be described. As shown in FIG. 7, the maximum value (resonance value) of the gain of the transfer function in the converter circuits 2 and 3 appears at 15 kHz which is the LC resonance frequency of the converter circuits 2 and 3. The zero cross frequency at which the gain is 0 dB is 55 kHz. Further, as shown in FIG. 8, the phase of the transfer function in the converter circuits 2 and 3 is −175 ° at 55 kHz which is the zero cross frequency. Therefore, the phase margin of the converter circuits 2 and 3 is 5 °, which is a very small value as the phase margin. Therefore, there is a possibility that the phase becomes 180 ° due to the delay of the output voltage detection system and the output voltage V _O oscillates. Therefore, in the controller IC 4A, the phase is advanced by the integration function of the arithmetic circuit 21.

  The gain characteristic and phase characteristic of the transfer function in the controller IC 4A will be described with reference to FIGS. As shown in FIGS. 9 and 10, the gain characteristic and the phase characteristic of the transfer function of the controller IC 4A are secondary characteristics fused to the arithmetic circuit 21 among the characteristics in the case of only the integrator shown in FIGS. In the frequency region where the low-frequency component is blocked by the high-pass filter, the gain returns to 0 dB and the phase to 0 °. If the direct current gain is insufficient, the necessary direct current gain can be obtained by making G, which is a transfer function of the multiplier 24, a transfer function having a high gain in the low frequency region.

  With reference to FIG.11 and FIG.12, the gain characteristic and phase characteristic of a transfer function in the switching power supply device 1 whole containing controller IC4A are demonstrated. Each of the characteristics shown in FIGS. 11 and 12 is obtained by multiplying the transfer function in the converter circuits 2 and 3 shown in FIGS. 7 and 8 and the transfer function in the controller IC 4A shown in FIGS. Phase characteristics. As shown in FIG. 11, the zero cross frequency at which the gain of the transfer function in the entire switching power supply device 1 is 0 dB is 35 kHz. Also, as shown in FIG. 12, the phase of the transfer function in the entire switching power supply device 1 is −130 ° at 35 kHz which is the zero cross frequency. Therefore, the phase margin of the entire switching power supply 1 is 50 °, and the switching power supply 1 as a whole becomes a stable control system. Moreover, as shown in FIG. 11, since the DC gain is 20 dB, the steady-state deviation of the switching power supply device 1 as a whole is also reduced.

  In this way, by integrating the integrator and the second-order high-pass filter into the arithmetic circuits 21 and 21 included in the feedback loop of the controller IC 4A, the transfer function of the controller IC 4A is advanced in phase, and further, the DC gain is ensured. . Therefore, the phase in the switching power supply device 1 can be compensated.

Here, the principle that the output currents between the two converter circuits 2 and 3 can be balanced by resetting the counter signals CT1 and CT2 with the initial values CI1 and CI2 instead of resetting them with 0 at the time of resetting the counter signals CT1 and CT2. Let me explain. The balance of the output current between the two converter circuits 2 and 3 (the balance of the time ratio between the first PWM signal PS1 and the second PWM signal PS2) is unbalanced due to the effect of switching of the converter circuits 2 and 3 itself. This is because the output voltage V _O varies in accordance with the period of the PWM signals PS1 and PS2. This is because when the output voltage V _O varies periodically, the control signal CS also varies periodically. For this reason, in one of the two comparators, the ramp signal arrives when the control signal CS is a small value. Therefore, the time until the ramp signal reaches the small value is short, and the time ratio of the PWM signal is always small. In the other comparator, since the ramp signal reaches when the control signal CS is a large value, the time until the ramp signal reaches the large value becomes long, and the time ratio of the PWM signal is always increased. Therefore, the respective time ratios of the PWM signals PS1 and PS2 are always small and large, and the output current balance between the converter circuits 2 and 3 becomes unbalanced.

  Therefore, the controller IC 4A obtains a time average value of the time ratios (pulse widths D1 and D2) of the two PWM signals PS1 and PS2, and generates a counter signal for generating a PWM signal of the comparator circuit having the larger time average value. The reset value (initial value) of (ramp signal) is set to a predetermined value greater than zero. The fact that the time average value of the time ratio is large corresponds to the fact that the counter signal has not reached until the control signal CS (actually, the correction control signal RCS) becomes a large value. Therefore, in generating the PWM signal for the converter circuit having the larger time ratio time average value, the reset value of the counter signal is set larger than 0, and the time until the counter signal reaches the large value of the correction control signal RCS is set. Shorten the time ratio of the PWM signal. Thus, by reducing the time ratio in one converter circuit, the time ratio in the other converter circuit is balanced, and the output current between the converter circuits 2 and 3 is balanced.

  In the controller IC 4A, the reset value of the counter signal is set to a value larger than 0 in generating the PWM signal for the converter circuit having the larger time ratio time average value. However, the converter circuit having the smaller time ratio time average value is used. In the generation of the PWM signal, the reset value of the counter signal may be set to a value smaller than 0, or in the generation of two PWM signals, the reset value of one counter signal is set to a value greater than 0 and the other counter The reset value of the signal may be a value smaller than 0.

  The operation of the controller IC 4A, the converter circuits 2 and 3, and the switching power supply device 1 will be described with reference to FIG. 1, FIG. 2, FIG. 13, and FIG.

An input voltage V _I is input to the switching power supply device 1. Then, in each of the converter circuits 2 and 3, the first switching elements 10 and 12 are alternately turned on based on the PWM signals PS1 and PS2 from the controller IC 4A, and the second switching element 11 is turned on when the first switching element 10 is on. Is turned off, and the second switching element 13 is turned off when the first switching element 12 is turned on. Further, in each of the converter circuits 2 and 3, the inductor 14 or the inductor 15 and the capacitor 16 average the input voltage V _I output as a pulse during the ON period of the first switching element 10 or the first switching element 12, and the voltage V Output _O. As described above, in the switching power supply device 1, since the two converter circuits 2 and 3 are controlled by the multi-phase method, the current ripple in each converter circuit 2 and 3 is small, and the ripple of the output voltage V _O is small. Become.

In the controller IC 4A, the output voltage V _O is subtracted from the target voltage V _R, and the control signal CS is generated by multiplying the subtraction value by the gain G. In addition, the controller IC 4A detects the pulse widths D1 and D2 of the two generated PWM signals PS1 and PS2, respectively, and performs integration and low-frequency component cut-off operations on the pulse widths D1 and D2, respectively. Signals IE1 and IE2 are obtained respectively. Further, the controller IC 4A averages the two phase compensation signals IE1 and IE2 to obtain an average signal AV. Then, the controller IC 4A subtracts the average signal AV from the control signal CS to generate a correction control signal RCS. Further, the controller IC 4A generates counter signals CT1 and CT2, which are ramp signals, by using the count-up when detecting the pulse widths D1 and D2. Then, the controller IC 4A compares the correction control signal RCS and the first counter signal CT1, and generates a first PWM signal PS1 that is a high signal during a period in which the first counter signal CT1 does not exceed the correction control signal RCS (FIG. 13). (See (b) and (c)). Further, the controller IC4A compares the correction control signal RCS with the second counter signal CT2, and generates a second PWM signal PS2 having a period during which the second counter signal CT2 does not exceed the correction control signal RCS as a high signal (FIG. 13). (See (b) and (e)). The first PWM signal PS1 and the second PWM signal PS2 have their high signal rising edges defined by the first on-timing signal OT1 and the second on-timing signal OT2, respectively, and their phases are shifted by 180 °. As described above, the controller IC 4A performs integration and low-frequency component cutoff on the respective time ratios (pulse widths D1 and D2) of the converter circuits 2 and 3 in the feedback loop, and controls the control signal according to the average value of the respective calculated values. By correcting CS, the phase is advanced by 90 ° and a DC gain is also secured.

  In the controller IC 4A, the pulse widths D1 and D2 held in the register are time-averaged, and the time average value having a smaller time average value is selected (see FIGS. 14D and 14E). Then, the controller IC4A obtains the first initial value CI1 by subtracting the small time average value selected from the time average value of the first pulse width D1, and obtains the small time average value selected from the time average value of the second pulse width D2. Is subtracted to obtain the second initial value CI2 (see FIGS. 14F and 14G). Then, the controller IC 4A resets the first counter signal CT1 with the first initial value CI1 when the first on-timing signal OT1 is a high signal, and the second counter signal CT2 when the second on-timing signal OT2 is a high signal. Is reset with the second initial value CI2 (see FIG. 14A). In the example of FIG. 14A, the first initial value CI1 has a predetermined value, and the second initial value is zero. As described above, in the controller IC 4A, the counter signals CT1 and CT2 are initialized by the difference of the time average values of the respective time ratios (pulse widths D1 and D2) of the converter circuits 2 and 3, whereby the PWM signals PS1 and PS2 The difference in each time ratio is suppressed, and the imbalance of the output current between the converter circuits 2 and 3 is prevented.

According to the controller IC 4A, the integration function and the high-pass filter function in the arithmetic circuits 21 and 21 in the feedback loop can realize a 90 ° phase advance and also ensure a DC gain. As a result, in each of the converter circuits 2 and 3, the phase is compensated and the DC gain is secured, and the phase of the switching power supply device 1 as a whole is compensated and the DC gain is secured. Therefore, in the switching power supply device 1, the phase lag does not reach 180 °, and the output voltage V _O does not oscillate. In particular, the controller IC 4A averages the phase compensation signals IE1 and IE2 obtained from the respective time ratios (pulse widths D1 and D2), and corrects the control signal CS by the averaged signal AV, whereby a high frequency region is obtained. Phase compensation is possible.

  The controller IC 4A can balance the duty ratio by resetting the counter signals CT1 and CT2 with the initial values CI1 and CI2 generated by the initial value generation circuit 28. As a result, the output current imbalance between the converter circuits 2 and 3 is suppressed, and the output current in the switching power supply device 1 can be balanced. Therefore, there is no element abnormality such as destruction of the element due to imbalance of the output current, and the output current can be balanced without means for detecting the output current.

  In the controller IC 4A, the time ratio (pulse widths D1 and D2) detected by the counter 20 is held in each register. Therefore, even if there is a predetermined time difference between detection of the time ratio and reading, the value of the time ratio is obtained. Will not change. Therefore, in the controller IC 4A, the calculation circuit 21 and the initial value generation circuit 28 perform calculation using the time ratio, but high-precision calculation can always be performed with an accurate time ratio. Incidentally, when the value of the control signal at the falling edge of the PWM signal is used as the value corresponding to the time ratio, the control signal varies due to the fluctuation of the output voltage, so that the value of the time ratio changes due to a predetermined time difference. .

  Further, in the controller IC 4A, the ramp signal (counter signals CT1 and CT2) is also generated by the counter 20 for detecting the time ratio (pulse widths D1 and D2). Simplify. Furthermore, in the controller IC 4A, the integrator and the high-pass filter are fused in the arithmetic circuit 21, so that the integrator and the high-pass filter do not need to be configured separately, and the configuration is simplified.

  With reference to FIG. 15, the configuration of a controller IC 4B according to the second embodiment will be described. FIG. 15 is a configuration diagram of a controller IC according to the second embodiment. Note that in the controller IC 4B according to the second embodiment, the same components as those of the controller IC 4A according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The controller IC 4B is substantially the same controller IC as the controller IC 4A according to the first embodiment, but the method for correcting the control signal CS by the phase compensation signals IE1 and IE2 is different in order to simplify the configuration of the controller IC 4A. . That is, in the controller IC 4B, the control signal CS is not corrected by the average signal AV of the phase compensation signals IE1 and IE2, but the control signal CS is corrected by the phase compensation signals IE1 and IE2. For this purpose, the controller IC 4B includes counters 20 and 20, arithmetic circuits 21 and 21, a subtractor 23, a multiplier 24, subtractors 40 and 40, comparators 26 and 26, RS flip-flops 27 and 27, and an initial value generation circuit 28. I have. In the controller IC 4B, in order to generate the PWM signals PS1 and PS2 for the two converter circuits 2 and 3, respectively, a counter 20, an arithmetic circuit 21, a comparator 26, and an RS flip-flop 27 corresponding to each converter circuit 2 and 3. And a subtractor 40 are provided.

  In the second embodiment, the counters 20 and 20 correspond to a plurality of time ratio generating means described in the claims, and the arithmetic circuits 21 and 21 correspond to a plurality of arithmetic means described in the claims. The subtractor 23 and the multiplier 24 correspond to the control signal generating means described in the claims, the subtractors 40 and 40 correspond to the plurality of difference means described in the claims, and the comparators 26, 26 and The RS flip-flops 27 and 27 correspond to a plurality of drive signal generation means described in the claims, and the initial value generation circuit 28 corresponds to the initial value generation means described in the claims.

  The subtractor 40 receives the control signal CS and the first phase compensation signal IE1 or the second phase compensation signal IE2 from each arithmetic circuit 21, and receives the first phase compensation signal IE1 or the second phase compensation signal IE2 from the control signal CS. And the subtraction value (CS-IE1) is output to each comparator 26 as the first correction control signal RCS1 or the subtraction value (CS-IE2) as the second correction control signal RCS2.

  Accordingly, each of the comparators 26 and 26 determines whether or not the first counter signal CT1 that is the ramp signal reaches the first correction control signal RCS1, or the second counter signal CT2 that is the ramp signal performs the second correction control. It is determined whether or not the signal RCS2 is reached.

  The operation of the controller IC 4B will be described with reference to FIG. Here, only operations different from those of the controller IC 4A according to the first embodiment will be described.

  The controller IC4B subtracts the first phase compensation signal IE1 from the control signal CS to generate a first correction control signal RCS1. In addition, the controller IC 4B subtracts the second phase compensation signal IE2 from the control signal CS to generate a second correction control signal RCS2. Then, the controller IC4B compares the first correction control signal RCS1 and the first counter signal CT1, and generates a first PWM signal PS1 that makes the period when the first counter signal CT1 does not exceed the first correction control signal RCS1 a high signal. To do. Further, the controller IC4B compares the second correction control signal RCS2 with the second counter signal CT2, and generates a second PWM signal PS2 that makes the period when the second counter signal CT2 does not exceed the second correction control signal RCS2 a high signal. To do.

  According to the controller IC 4B, in addition to the effects of the controller IC 4A according to the first embodiment, an averaging circuit composed of two multipliers and an adder is not required, so that the configuration is simplified.

  A configuration of a controller IC 4C according to the third embodiment will be described with reference to FIG. FIG. 16 is a configuration diagram of a controller IC according to the third embodiment. Note that in the controller IC 4C according to the third embodiment, the same components as those of the controller IC 4A according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  Compared with the controller IC 4A according to the first embodiment, the controller IC 4C corrects the control signal CS only with the first phase compensation signal IE1 corresponding to the first converter circuit 2 in order to simplify the configuration of the controller IC 4A. And a configuration that does not have a configuration for balancing the duty ratio (that is, an initial value generation circuit and a configuration related thereto). That is, the controller IC4C does not correct the control signal CS with the average signal AV of the two phase compensation signals IE1 and IE2, but corrects the control signal CS with the first phase compensation signal IE1, and the correction control signal RCS is The two comparators 26 and 26 are used. In the controller IC 4C, both the first counter signal CT1 and the second counter signal CT2 are reset to 0. For this purpose, the controller IC 4C includes a first counter 50, a second counter 51, an arithmetic circuit 21, a subtractor 23, a multiplier 24, a subtractor 52, comparators 26 and 26, and RS flip-flops 27 and 27. In the controller IC 4C, in order to generate the PWM signals PS1 and PS2 for the two converter circuits 2 and 3, respectively, the first counter 50 or the second counter 51, the comparator 26, RS corresponding to each converter circuit 2 and 3 Each flip-flop 27 is provided.

  In the third embodiment, the first counter 50 corresponds to the time ratio generating means described in the claims, the arithmetic circuit 21 corresponds to the arithmetic means described in the claims, and the subtractor 23 and the multiplier The device 24 corresponds to the control signal generating means described in the claims, the subtractor 52 corresponds to the difference means described in the claims, and the comparators 26 and 26 and the RS flip-flops 27 and 27 are claimed. It corresponds to a plurality of drive signal generating means described in the range.

  The first counter 50 is a counter having substantially the same configuration as the counter 20 according to the first embodiment, except that the first counter signal CT1 is reset. The first counter 50 always resets the first counter signal CT1 to 0 when the first on-timing signal OT1 is a high signal, and counts up every cycle of the master clock MC when the first PWM signal PS1 is a high signal. . The first counter 50 stops counting up when the first PWM signal PS1 falls from a high signal to a low signal, and holds the count-up value when the first PWM signal PS1 is a low signal. In the first counter 50, the count-up value is held in the register as the first pulse width D1. Incidentally, the first counter 50 generates a first counter signal CT1 that is a ramp signal and detects a first pulse width D1 that is a duty ratio.

  The second counter 51 is a counter having substantially the same configuration as that of the first counter 50, but is different only in that the time ratio is not detected. That is, the second counter 51 does not hold the count-up value in the register as the second pulse width D2. Therefore, the second counter 51 generates only the second counter signal CT2, which is a ramp signal.

  Incidentally, the second counter 51 may be configured to detect the second pulse width D2, which is a duty ratio. In this case, since the initial values CI1 and CI2 of the ramp signal can be obtained from the two pulse widths D1 and D2, an initial value generation circuit may be added to the configuration of the controller IC4C to balance the time ratio. .

  The subtractor 52 receives the control signal CS and the first phase compensation signal IE1 from the arithmetic circuit 21, subtracts the first phase compensation signal IE1 from the control signal CS, and corrects and controls the subtraction value (CS-IE1). The signal RCS is output to the two comparators 26 and 26, respectively.

  Accordingly, each of the comparators 26 and 26 determines whether or not the first counter signal CT1 or the second counter signal CT2 that is a ramp signal reaches the correction control signal RCS.

  The operation of the controller IC 4C will be described with reference to FIG. Here, only operations different from those of the controller IC 4A according to the first embodiment will be described.

  In the controller IC4C, only the first pulse width D1 of the generated first PWM signal PS1 is detected, the integration and the low frequency component are cut off for the first pulse width D1, and only the first phase compensation signal IE1 is obtained. Ask. Then, the controller IC 4C subtracts the first phase compensation signal IE1 from the control signal CS to generate a correction control signal RCS. The controller IC4C resets the counter signals CT1 and CT2 with 0 when the on-timing signals OT1 and OT2 are high signals, counts up based on the master clock after resetting, and counter signals CT1 and CT2 that become ramp signals Are generated respectively. Then, the controller IC4C compares the correction control signal RCS and the first counter signal CT1, and generates a first PWM signal PS1 that makes the period during which the first counter signal CT1 does not exceed the correction control signal RCS a high signal. Further, the controller IC4C compares the correction control signal RCS with the second counter signal CT2, and generates a second PWM signal PS2 having a period during which the second counter signal CT2 does not exceed the correction control signal RCS as a high signal.

  According to the controller IC 4C, in addition to the effects of the controller IC 4A according to the first embodiment, an averaging circuit composed of two multipliers and an adder is not required, so that the configuration is simplified. In particular, the controller IC 4C generates the phase compensation signal only on the side corresponding to the first converter circuit 2, so that the side corresponding to the second converter circuit 3 does not need a configuration for detecting an arithmetic circuit or a time ratio. Will be more simplified.

  With reference to FIG. 17, a configuration of a controller IC 4D according to the fourth embodiment will be described. FIG. 17 is a configuration diagram of a controller IC according to the fourth embodiment. In addition, in controller IC4D which concerns on 4th Embodiment, the same code | symbol is attached | subjected about the component similar to controller IC4C which concerns on 3rd Embodiment, and the description is abbreviate | omitted.

  Compared with the controller IC 4C according to the third embodiment, the controller IC 4D generates only the first PWM signal PS1 by voltage mode control and simplifies the configuration from the controller IC 4C, and the second PWM signal PS2 as the first PWM signal. Generated based on PS1. That is, after generating the first PWM signal PS1, the controller IC4D generates the second PWM signal PS2 by shifting the phase of the high signal of the first PWM signal PS1 by 180 °. For this purpose, the controller IC 4D includes a first counter 50, an arithmetic circuit 21, a subtractor 23, a multiplier 24, a subtractor 52, a comparator 26, an RS flip-flop 27, and a delay circuit 60. In the controller IC4D, in order to generate the first PWM signal PS1 by voltage mode control only for the first converter circuit 2, the first counter 50, the arithmetic circuit 21, the comparator 26, and the RS flip-flop corresponding to the first converter circuit 2 are generated. 27 is provided, and only the delay circuit 60 is provided corresponding to the second converter circuit 3.

  In the fourth embodiment, the first counter 50 corresponds to the time ratio generating means described in the claims, the arithmetic circuit 21 corresponds to the arithmetic means described in the claims, and the subtractor 23 and the multiplier The device 24 corresponds to the control signal generating means described in the claims, the subtractor 52 corresponds to the difference means described in the claims, and the comparator 26 and the RS flip-flop 27 are described in the claims. The delay circuit 60 corresponds to the drive signal generation means, and the delay circuit 60 corresponds to the delay means described in the claims.

  The delay circuit 60 is a delay circuit that delays the phase of the pulse of the PWM signal. Specifically, the delay circuit 60 delays the phase of the high signal of the first PWM signal PS1 by 180 ° (that is, delays the rising point of the high signal by a half cycle of the PWM signal) to generate the second PWM signal PS2. The delay circuit 60 only delays the phase of the pulse and does not change the pulse width. Therefore, in the controller IC4D, the pulse widths of the first PWM signal PS1 and the second PWM signal PS2 are the same.

  The operation of the controller IC 4D will be described with reference to FIG. Here, only operations different from those of the controller IC 4C according to the third embodiment will be described.

  The controller IC4D resets the counter signal CT1 with 0 when the first on-timing signal OT1 is a high signal, counts up based on the master clock after the reset, and generates only the first counter signal CT1 that becomes a ramp signal. Then, the controller IC4D compares the correction control signal RCS and the first counter signal CT1, and generates a first PWM signal PS1 having a period during which the first counter signal CT1 does not exceed the correction control signal RCS as a high signal. Further, in the controller IC 4D, the phase of the high signal of the first PWM signal PS1 is delayed by 180 ° to generate the second PWM signal PS2.

  According to the controller IC4D, in addition to the effects of the controller IC4C according to the third embodiment, the counter, the converter, and the RS flip-flop corresponding to the second converter circuit 3 are not required, so that the configuration is simplified. Further, in the controller IC4D, the pulse widths of the first PWM signal PS1 and the second PWM signal PS2 are always the same width, so that the time ratio can be balanced. As a result, the output current imbalance between the converter circuits 2 and 3 is suppressed, and the output current in the switching power supply device 1 can be balanced.

  As mentioned above, although embodiment which concerns on this invention was described, this invention is implemented in various forms, without being limited to the said embodiment.

  For example, in the present embodiment, the control device is configured by a digital circuit, but may be configured by an analog circuit. In this embodiment, each unit of the control device is configured by a digital circuit (hardware) of the controller IC. However, each unit of the control device may be configured by a program (software) incorporated in a computer such as a microcomputer. . A program for realizing each means may be distributed by distribution via a storage medium such as a CD-ROM or the Internet, or may be distributed as a control device in a state of being incorporated in a computer.

  In this embodiment, the present invention is applied to a DC / DC converter. However, the present invention can also be applied to an AC / DC converter and a DC / AC converter. In this embodiment, the present invention is applied to a non-insulating and step-down converter having no transformer. However, the present invention can also be applied to an insulating converter having a transformer, and can also be applied to a step-up or step-up / step-down converter. is there.

  In this embodiment, the present invention is applied to a multiphase switching power supply device in which two converter circuits are connected in parallel. However, the present invention is also applicable to a multiphase switching power supply device in which three or more converter circuits are connected in parallel. .

  Further, in the present embodiment, the means for detecting the time ratio and the means for generating the ramp signal are configured by the same counter, but a configuration may be provided in which a ramp circuit is provided separately from the counter for detecting the time ratio, or A configuration may be used in which the duty ratio is detected from the control signal using a D flip-flop or the like.

  Further, in the present embodiment, the arithmetic unit is configured by an arithmetic circuit in which a high-pass filter function and an integration function are combined. However, an arithmetic circuit having a circuit configuration different from the circuit shown in FIG. The integrating circuit may be configured separately.

  In the present embodiment, the rise of the on signal of the PWM signal is fixed at regular intervals by the on timing signal, but the fall of the off signal of the PWM signal is fixed at regular intervals by the off timing signal. It is good.

  Moreover, although applied to P control in this Embodiment, it is applicable also to other controls, such as PI control and PID control.

  In the first embodiment and the second embodiment, the initial value generation circuit is included to perform current balance (duty ratio balance). However, when current balance is performed using a current detector or the like. May not include an initial value generation circuit.

  In the first embodiment and the second embodiment, the minimum time-averaged time ratio is selected from the two time-averaged time ratios, and the selected time-averaged time ratio is selected from the time-averaged time ratios. The initial value of the ramp signal is obtained by subtracting the value, but the maximum time averaged time ratio may be selected from the two time averaged time ratios, or the average of the two time averaged time ratios may be calculated. Alternatively, the initial value may be obtained by taking the difference between the two duty ratios and averaging the difference values over time.

It is a block diagram of the switching power supply device which concerns on this Embodiment. It is a block diagram of controller IC concerning a 1st embodiment. It is a detailed circuit block diagram of the arithmetic circuit of FIG. It is a figure which shows an example of the control circuit which feeds back in a feedback loop. FIG. 5 is a diagram illustrating gain characteristics of a transfer function in the control circuit of FIG. 4. FIG. 5 is a diagram illustrating phase characteristics of a transfer function in the control circuit of FIG. 4. It is a figure which shows the gain characteristic of the transfer function in the converter circuit of FIG. It is a figure which shows the phase characteristic of the transfer function in the converter circuit of FIG. It is a figure which shows the gain characteristic of the transfer function in the controller IC of FIG. It is a figure which shows the phase characteristic of the transfer function in the controller IC of FIG. It is a figure which shows the gain characteristic of the transfer function in the whole switching power supply device of FIG. It is a figure which shows the phase characteristic of the transfer function in the whole switching power supply device of FIG. 3 is a timing chart of duty ratio detection and PWM signal generation in the controller IC of FIG. 2, wherein (a) is a master clock, (b) is a first counter signal, a second counter signal, and a correction control signal; ) Is a first PWM signal, (d) is a first on-timing signal, (e) is a second PWM signal, (f) is a second on-timing signal, and (g) is held. 1 pulse width, and (h) is the second pulse width held. FIG. 3 is a timing chart of a duty ratio balance in the controller IC of FIG. 2, where (a) is a first counter signal, a second counter signal and a correction control signal, (b) is a first PWM signal, and (c) is a first counter signal. 2 PWM signal, (d) is a first pulse width held, (e) is a second pulse width held, (f) is a first initial value for the first counter signal, ( g) is a second initial value for the second counter signal. It is a block diagram of controller IC concerning a 2nd embodiment. It is a block diagram of controller IC concerning a 3rd embodiment. It is a block diagram of controller IC concerning a 4th embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Switching power supply device, 2 ... 1st converter circuit, 3 ... 2nd converter circuit, 4, 4A, 4B, 4C, 4D ... Controller IC, 10, 12 ... 1st switching element, 11, 13 ... 2nd switching element , 14, 15 ... inductor, 16 ... capacitor, 20 ... counter, 21 ... arithmetic circuit, 21a to 21c ... D flip-flop, 21d, 21e ... multiplier, 21f ... adder, 22 ... averaging circuit, 22a ... multiplier , 22b ... adder, 23 ... subtractor, 24 ... multiplier, 25 ... subtractor, 26 ... comparator, 27 ... RS flip-flop, 28 ... initial value generation circuit, 28a ... low pass filter, 28b ... arithmetic unit, 30 ... Control circuit 31 ... multiplier 32 ... integrator 33 ... multiplier 34 ... adder 40 ... subtractor 50 ... first counter 51 ... second counter 52 ... subtractor, 60 ... delay circuit

Claims (12)

A time ratio generating means for detecting a time ratio of a drive signal for controlling a switching element of a multiphase switching power supply device in which a plurality of converter circuits are connected in parallel, and generating a signal corresponding to the time ratio;
A calculation unit that calculates a signal corresponding to the time ratio of the drive signal generated by the time ratio generation unit, cuts off a low-frequency component, and performs integration;
Control signal generating means for generating a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device;
Difference means for calculating a difference between the control signal generated by the control signal generation means and the signal calculated by the calculation means;
Look containing a drive signal generating means for generating a drive signal based on the calculated signal and the ramp signal by said difference means,
The switching power supply control device according to claim 1, wherein the duty ratio generating means detects a duty ratio from the drive signal generated by the drive signal generating means . Corresponding to each converter circuit in a multi-phase switching power supply device in which a plurality of converter circuits are connected in parallel, the time ratio of the drive signal for controlling the switching element of the converter circuit is detected, and the corresponding time ratio is supported. A plurality of time ratio generating means for generating a signal;
Corresponding to each converter circuit, a signal corresponding to the time ratio of the drive signal generated by each of the time ratio generating means is calculated, a plurality of calculating means for blocking and integrating the low frequency component,
Averaging means for averaging signals calculated by the plurality of calculating means;
Control signal generating means for generating a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device;
Difference means for calculating a difference between the control signal generated by the control signal generation means and the signal averaged by the averaging means;
Corresponding to each of the converter circuit, seen including a plurality of drive signal generating means for generating a drive signal based on the calculated signal and the ramp signal by said difference means,
The switching power supply control device according to claim 1, wherein the duty ratio generating means detects a duty ratio from the drive signal generated by the drive signal generating means . Corresponding to each converter circuit in a multi-phase switching power supply device in which a plurality of converter circuits are connected in parallel, the time ratio of the drive signal for controlling the switching element of the converter circuit is detected, and the corresponding time ratio is supported. A plurality of time ratio generating means for generating a signal;
Corresponding to each converter circuit, a signal corresponding to the time ratio of the drive signal generated by each of the time ratio generating means is calculated, a plurality of calculating means for blocking and integrating the low frequency component,
Control signal generating means for generating a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device;
Corresponding to each converter circuit, a plurality of difference means for calculating the difference between the control signal generated by the control signal generation means and the signal calculated by each calculation means,
Corresponding to each of the converter circuit, seen including a plurality of drive signal generating means for generating a drive signal based the on the calculated signal and a ramp signal with each difference means,
The switching power supply control device according to claim 1, wherein the duty ratio generating means detects a duty ratio from the drive signal generated by the drive signal generating means . Corresponding to an arbitrary converter circuit in a multiphase switching power supply device in which a plurality of converter circuits are connected in parallel, the time ratio of the drive signal for controlling the switching element of the converter circuit is detected, and this time ratio is supported. A time ratio generating means for generating a processed signal;
A calculation unit that calculates a signal corresponding to the time ratio of the drive signal generated by the time ratio generation unit, cuts off a low-frequency component, and performs integration;
Control signal generating means for generating a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device;
Difference means for calculating a difference between the control signal generated by the control signal generation means and the signal calculated by the calculation means;
Corresponding to each of the converter circuit, seen including a plurality of drive signal generating means for generating a drive signal based on the calculated signal and the ramp signal by said difference means,
The switching power supply control device according to claim 1, wherein the duty ratio generating means detects a duty ratio from the drive signal generated by the drive signal generating means . Corresponding to an arbitrary converter circuit in a multiphase switching power supply device in which a plurality of converter circuits are connected in parallel, the time ratio of the drive signal for controlling the switching element of the converter circuit is detected, and this time ratio is supported. A time ratio generating means for generating a processed signal;
A calculation unit that calculates a signal corresponding to the time ratio of the drive signal generated by the time ratio generation unit, cuts off a low-frequency component, and performs integration;
Control signal generating means for generating a control signal based on a difference value between a target voltage in the switching power supply device and an output voltage detected by the switching power supply device;
Difference means for calculating a difference between the control signal generated by the control signal generation means and the signal calculated by the calculation means;
Drive signal generation means for generating a drive signal based on the signal calculated by the difference means and the ramp signal;
Corresponding to each converter circuits other than the arbitrary converter circuit, seen including a one or more delay means applying a predetermined delay in response to each converter circuit to the drive signal generated by the drive signal generating means,
The switching power supply control device according to claim 1, wherein the duty ratio generating means detects a duty ratio from the drive signal generated by the drive signal generating means .   4. The switching power supply device according to claim 2, further comprising initial value generating means for generating an initial value of the ramp signal based on the time ratios generated by the plurality of time ratio generating means. Control device.   The initial value generating means includes a plurality of time averaging means for time averaging the time ratios generated by the respective time ratio generating means, a signal averaged by an arbitrary time averaging means, and a plurality of time averaging means. 7. The switching power supply control device according to claim 6, further comprising initial value calculation means for calculating a difference from a value obtained from each time-averaged signal.   8. The switching power supply controller according to claim 7, wherein the time averaging means is a low pass filter. The duty ratio generating means includes a counter,
The counter counts an on period or an off period of the drive signal at regular intervals, and holds the count value at the fall of the on period or the count value at the rise of the off period until the next count time. The control device for a switching power supply device according to any one of claims 1 to 8.   The control apparatus for a switching power supply according to claim 9, wherein the ramp signal is a signal counted by the counter.   The control device for a switching power supply according to any one of claims 1 to 10, wherein the arithmetic means is an arithmetic circuit in which a high-pass filter function and an integration function are combined.   The calculation means includes a high-pass filter that cuts off a low-frequency component included in a signal corresponding to a time ratio of the drive signal, and an integration means that integrates a signal whose low-frequency component is cut off by the high-pass filter. The control device for a switching power supply device according to any one of claims 1 to 10.

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