JP3806046B2 - Data receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission system that causes the timing of a receiving apparatus to follow the timing of a transmitting apparatus when transmitting data via a transmission line, and more particularly to a data receiving apparatus used in the data transmission system.
[0002]
[Prior art]
In data transmission such as video data, it is necessary to send a clock on the transmission side to the reception side and reproduce it on the reception side.
Examples of clock recovery methods include Scrambled-NRZI (SMPTE259M) and 8B / 10BCoding (DVB_ASI). However, these methods are channel coding, and the transmitter and the receiver need to be directly connected.
[0003]
Even when the transmission line is operating with a clock that is completely independent of the video data, there is a method of sending clock information called PCR adopted in MPEG as a method of clock recovery. This method has a drawback that overhead is increased because clock information must be sent in addition to data. Also, if the clock information sending interval is widened in order to reduce the overhead, the interval for controlling the reproduction clock is widened, and the frequency deviation in the video signal is likely to occur.
[0004]
A transmission system for providing data transmission by providing a FIFO memory for absorbing a speed difference between the transmission device and the transmission line when the operation clock frequency inside the transmission side and the reception side apparatus is different from the transmission speed of the transmission line. , The amount of data stored in the FIFO memory of the receiving device is monitored, and the clock frequency of the read clock of the receiving device is controlled according to the increase or decrease of the amount of data, so that the operating clock of the receiving device is A method of synchronizing with that of the transmission side device is described in Japanese Patent Laid-Open No. 10-93540, “Data transmission method”.
[0005]
To briefly introduce this method with reference to FIG. 2, the transmission device 1 outputs data using a transmission path clock, and the reception device 3 captures data using the transmission path clock. That is, since the transmission path 2 is a reference, the clock used in the transmission apparatus is not transmitted to the reception side.
[0006]
FIG. 3 shows a clock recovery method in the receiving apparatus, and data from the line is written in the FIFO memory 4 as received data input. The data written in the FIFO memory 4 is obtained as the output of the subtracter 5 and is output from the voltage controlled oscillator 9 controlled by the difference between the value obtained by subtracting the count value of the counter 7 from the count value of the counter 6 and the set value. Is read by a read clock. Reference numeral 8 denotes a low pass filter (LPF) for smoothing the control voltage (input voltage) of the voltage controlled oscillator 9.
[0007]
In the above, the set value is a constant determined by the packet size and the packet reception interval, and is normally set in advance to an amount in which the amount of written data occupies half of the capacity of the FIFO memory 4.
[0008]
The received data is written into the FIFO memory 4 at a high speed and in a burst manner. On the other hand, since the output from the FIFO memory 4 is video data, it is output continuously (270 Mbps for standard television and 1485 Mbps for high-definition television).
[0009]
The operation of clock recovery is as follows.
Now, when the amount of data stored in the FIFO memory 4 becomes lower than the set value, the control voltage of the voltage controlled oscillator 9 is lowered, so that the oscillation frequency (reading clock frequency) of the voltage controlled oscillator 9 is lowered. Therefore, the data is stored in the FIFO memory 4.
[0010]
On the other hand, when the amount of data stored in the FIFO memory 4 becomes higher than the set value, the control voltage of the voltage controlled oscillator 9 increases, so that the oscillation frequency (read clock frequency) of the voltage controlled oscillator 9 increases. 4 is increased, and therefore, the data in the FIFO memory 4 is reduced.
[0011]
From the viewpoint of ease of control of the voltage controlled oscillator 9, the smaller the packet size is, the more control points are provided, so that the control can be easily performed. However, if the packet size is reduced, the header information for each packet causes the overhead to increase and the line utilization rate to deteriorate.
[0012]
Further, since the capacity of the FIFO memory 4 can be increased as the setting value increases, and the FIFO memory 4 can absorb even if the received data amount fluctuates, the control of the voltage controlled oscillator is possible. Can be easily performed. However, if the set value is increased, the capacity of the FIFO memory 4 must be increased, and the delay also increases.
[0013]
In FIG. 3, the parts indicated by reference numerals 10 to 13 are detected by the header detection unit 10 in order to write only the necessary packets from the respective packets of the received data sent through the transmission path to the FIFO memory 4. Then, the amount of data included in the detected header is read, and the input control unit 11 performs control so that the gates 12 and 13 are opened only for a period corresponding to the size.
[0014]
[Problems to be solved by the invention]
The above-described conventional data transmission method (described in Japanese Patent Laid-Open No. 10-93540) is an effective method when the number of data transmission lines is small and the packet interval is short. However, when the line capacity increases, the number of data transmission lines increases, and the packet size increases, the data transmission line is a time division multiplexing (TDM) line. A large amount arrives and waits for a long time until the next arrival.
[0015]
As a result, the control voltage of the voltage controlled oscillator of the reception side device varies depending on the amount of data input, and varies compared to the frequency of the transmission side device. In order to suppress this variation, if a powerful low-pass filter is applied to the control input of the voltage controlled oscillator, the frequency follow-up speed of the receiving side device is slowed down even though the frequency of the transmitting side device has changed. There were drawbacks.
[0016]
An object of the present invention is to provide a data receiving apparatus that suppresses fluctuations in the received clock due to non-uniformity in the amount of received data and improves the response characteristics of the received clock.
[0017]
In order to achieve the above object, a data receiving apparatus of the present invention includes a first FIFO memory in which received data is written in synchronization with a reception clock,
Means for dividing the clock frequency of the reception clock by 1 / N, and outputting the reception clock divided by 1 / N to the first FIFO memory as a read clock of the first FIFO memory;
The amount of data stored in the first FIFO memory is compared with a set value, and when the amount of data stored in the first FIFO memory is larger than the set value, the data in the first FIFO memory Means for stopping reading of data from the first FIFO memory when the amount of data stored in the first FIFO memory is smaller than the set value;
A second FIFO memory to which data read from the first FIFO memory is written;
Means for monitoring the amount of data stored in the second FIFO memory and controlling the frequency of the read clock of the second FIFO memory in accordance with the amount of data stored in the second FIFO memory; With
N> 1 .
[0018]
In the data receiving apparatus of the present invention, when the clock frequency of the write clock of the first FIFO memory is K and the clock frequency of the write clock of the second FIFO memory is L, the clock frequency K and the clock frequency The relationship of K / N> L is established between L and L.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on embodiments of the invention with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an embodiment of the data receiving apparatus of the present invention.
In FIG. 1, 14 and 15 are FIFO memories, 16, 17 and 18 are counters, 19 and 20 are adders, 21 is a 1 / N frequency divider, 22 is a clock control circuit, 23 is a proportional control circuit, and 24 is an integration. A control circuit, 25 is a differential control circuit, and 26 is a voltage controlled oscillator.
[0020]
The operation will be described.
In FIG. 1, the received data input is written into the FIFO memory 14 in synchronization with the line clock. Here, the received data is obtained by extracting only data necessary for the receiving side apparatus from the time-division multiplexed data, and is input at high speed.
[0021]
The line clock is also supplied to and written into the FIFO memory 14 and is also supplied to the counter 16 that counts the number of received data written and the 1 / N frequency divider 21 that divides the clock frequency of the line clock by 1 / N. Is also supplied.
[0022]
The output of the 1 / N frequency divider 21 is supplied to the FIFO memory 14 via the clock control circuit 22, and is used as a read clock for reading out the written received data (that is, a read clock of the FIFO memory 14).
[0023]
Here, the following equation may be established between the clock frequency K of the line clock (which is also the write clock of the FIFO memory 14), the clock frequency L of the read clock of the FIFO memory 15, and the frequency division ratio N. is necessary.
K / N> L
The reason is that the read clock of the FIFO memory 15 is continuous (on the other hand, the read clock of the FIFO memory 14 is intermittently set by the clock control circuit 22). Is underflowed and data cannot be read from the FIFO memory 15.
[0024]
Further, the frequency division ratio N of the 1 / N frequency divider 21 is N> 1. This is because if N = 1, the data rate of the data read from the FIFO memory 14 becomes the same as the data rate of the line, and the effect of the FIFO memory 14 does not occur.
[0025]
The number of received data output from the counter 16 written to the FIFO memory 14 and the number of data read from the FIFO memory 14 output from the counter 17 are supplied to the adder 19 and the latter is subtracted from the former. The obtained subtraction result means the amount of data stored in the FIFO memory 14 (because the number of read data is subtracted from the number of data written).
[0026]
The line clock divided by the 1 / N frequency divider 21 is supplied to a clock control circuit 22 including a comparison circuit and an on / off circuit. The clock control circuit 22 compares the amount of data stored in the FIFO memory 14 supplied from the adder 19 with a predetermined set value. When the amount of stored data is larger than the set value, the clock control circuit 22 In other words, the data is read out, and when it is small, the clock is not passed, so that the data reading is stopped, so that it operates as a clock gate circuit.
With the configuration described above, the amount of data read from the FIFO memory 14 is made uniform.
[0027]
Such quantitatively uniformed data is directly written into the FIFO memory 15.
The configuration and operation of the FIFO memory 15 and its peripheral circuits are basically the same as the configuration and operation of the receiving apparatus described in the above-mentioned published patent publication (Japanese Patent Laid-Open No. 10-93540). If so, the amount of data stored in the FIFO memory 15 is monitored by the counter 17, the counter 18 and the adder 20 (corresponding to the counter 16, the counter 17 and the adder 19, respectively, and performing the same operation as described above). The voltage controlled oscillator 26 is controlled by the monitoring output, and the read clock frequency of the FIFO memory 15 is changed. This makes it possible to control the FIFO memory 15 so that neither underflow nor overflow occurs.
[0028]
In the present embodiment, as shown in FIG. 1, PID control is used for a control circuit that controls the read clock frequency of the FIFO memory 15. Here, the proportional control circuit 23 adjusts the response characteristic of the system, the integral control circuit 24 improves the steady-state deviation characteristic of the system, and the differential control circuit 25 functions to suppress overshoot and undershoot of the system.
[0029]
【The invention's effect】
According to the present invention, the amount of data stored in the FIFO memory of the reception side device is monitored, and the clock frequency of the read clock of the FIFO memory is controlled by increasing or decreasing the amount of stored data, so that the reception side device In the data receiving apparatus in which the internal operation clock frequency is made to coincide with the internal operation clock frequency of the transmitting side apparatus, the receiving side apparatus can stably reproduce the read clock even if the packet interval becomes long.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a data receiving apparatus of the present invention.
FIG. 2 shows a data transmission system described in Japanese Patent Laid-Open No. 10-93540.
FIG. 3 is a block diagram showing the configuration of a receiving side apparatus similarly described in Japanese Patent Laid-Open No. 10-93540.
[Explanation of symbols]
14, 15 FIFO memory 16, 17, 18 Counter 19, 20 Adder 21 1 / N frequency divider 22 Clock control circuit 23 Proportional control circuit 24 Integration control circuit 25 Differentiation control circuit 26 Voltage controlled oscillator

Claims (1)

A first FIFO memory in which reception data is written in synchronization with a reception clock;
Means for dividing the clock frequency of the reception clock by 1 / N, and outputting the reception clock divided by 1 / N to the first FIFO memory as a read clock of the first FIFO memory;
The amount of data stored in the first FIFO memory is compared with a set value, and when the amount of data stored in the first FIFO memory is larger than the set value, the data in the first FIFO memory Means for stopping the reading of data from the first FIFO memory when the amount of data stored in the first FIFO memory is smaller than the set value;
A second FIFO memory to which data read from the first FIFO memory is written;
Means for monitoring the amount of data stored in the second FIFO memory and controlling the frequency of the read clock of the second FIFO memory in accordance with the amount of data stored in the second FIFO memory; With
N> 1 and
When the clock frequency of the write clock of the first FIFO memory is K and the clock frequency of the read clock of the second FIFO memory is L, K / N between the clock frequency K and the clock frequency L A data receiving apparatus characterized in that a relationship of> L is established .

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