JP3795617B2 - Semiconductor device protection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a protection circuit for a semiconductor device such as a semiconductor integrated circuit (IC, LSI, etc.), and from a high voltage due to static electricity applied unexpectedly to a pad serving as a connection terminal with an external circuit of this type of semiconductor device. The present invention relates to a protection circuit provided in a semiconductor device in order to protect an internal circuit.
[0002]
[Prior art]
  As a protection circuit for protecting an internal circuit of a semiconductor device from a high voltage such as static electricity, various configurations are used, and an example is shown in FIG.
  FIG. 24 is a circuit diagram showing an example of an input circuit of a semiconductor device provided with a general protection circuit 9 and an internal circuit 3.
[0003]
  The protection circuit 9 includes diodes 91 and 92 and a resistor 4, and the internal circuit 3 includes a P-channel MIS field effect transistor 1 and an N-channel MIS field effect transistor 2.
  Here, the MIS type field effect transistor is a generic term for a field effect transistor having a (metal-insulating film-semiconductor) structure including a MOS type field effect transistor, which is hereinafter abbreviated as “MISFET”.
[0004]
  In the input circuit of this semiconductor device, the pad 10 is connected to the anode terminal of the diode 91 constituting the protection circuit 9 and one terminal of the resistor 4. The other terminal of the resistor 4 is connected to the cathode terminal of the diode 92 and the gate terminals of the P-channel MISFET 1 and the N-channel MISFET 2 constituting the internal circuit 3.
[0005]
  The first power supply terminal 11 is connected to one terminal of the P-channel MISFET 1 and the cathode terminal of the diode 91, and the second power supply terminal 12 is connected to one terminal of the N-channel MISFET 2 and the anode terminal of the diode 92. And connected to.
  Here, the first power supply terminal 11 is supplied with the reference potential (VDD), and the second power supply terminal 12 is supplied with the negative power supply potential (VSS).
[0006]
  The other terminal of the P channel MISFET 1 and the other terminal of the N channel MISFET 2 are both connected to the output terminal 13.
  The static electricity has a positive and negative polarity at a voltage of several KV to several tens of KV, and the protection circuit 9 needs to protect the internal circuit 3 from this static electricity applied to the pad 10 unexpectedly.
[0007]
  Therefore, when positive static electricity is applied to the pad 10 and reaches the connection point between the anode terminal of the diode 91 and the resistor 4, the diode 91 performs a forward operation, and a current flows through the first power supply terminal 11. The voltage at which current starts to flow through the diode 91 is called threshold voltage. Since the positive polarity voltage applied to the pad 10 is clamped by the forward threshold voltage value of the diode 91, no voltage higher than the forward threshold voltage is applied to the internal circuit 3.
[0008]
  On the other hand, when negative static electricity is applied to the pad 10 and reaches the cathode terminal of the diode 92 via the resistor 4, the diode 92 performs a forward operation, and a current flows through the pad 10 via the resistor 4. Therefore, since the negative voltage applied to the pad 10 is clamped by the forward threshold voltage value of the diode 92, the internal circuit 3 has an absolute value equal to or higher than the forward threshold voltage. No voltage is applied.
[0009]
  Further, since the resistor 4 is inserted in series between the pad 10 and the internal circuit 3, it plays a role of smoothing a noise component that rises sharply due to static electricity.
  By the way, with the recent miniaturization of MISFETs, the gate insulating films constituting the MISFETs tend to be thinner. When the gate insulating film constituting the MISFET is thinned, the breakdown resistance is also lowered, and thus the importance of the protection circuit is further increased.
[0010]
  In the protection circuit of the prior art using two diodes as described above, the protection capability depends on the area of the PN junction of the diode. That is, in the semiconductor device shown in FIG. 24, in order to protect the internal circuit 3 by the protection circuit 9 and improve the breakdown tolerance of the MISFETs 1 and 2 constituting the internal circuit 3, the diodes 91, What is necessary is just to increase the area of 92 PN junctions.
[0011]
  The reason is that if the area of the PN junction constituting the diodes 91 and 92 is increased, a large current can flow through the diodes 91 and 92 per unit time. Since the energization amount per unit area is reduced, the protection capability of the protection circuit is improved.
  In addition, the reduction in the amount of current per unit area of the PN junctions constituting the diodes 91 and 92 can suppress the generation of heat due to the current flowing through the PN junctions. Therefore, the thermal destruction of the diodes 91 and 92 can be prevented, thereby preventing the protection circuit 9 itself from being destroyed.
[0012]
[Problems to be solved by the invention]
  However, there is a big problem in increasing the area of the PN junction of the diodes 91 and 92. That is, it increases the area occupied by the protection circuit 9 in the semiconductor device.
  24 protects the internal circuit 3 by clamping a high voltage due to static electricity applied to the pad 10, corresponding to static electricity having positive and negative polarities, Diodes 91 and 92, which are separate clamping elements, are required for the polarity voltage.
[0013]
  Therefore, if the protection capability of the protection circuit is improved by increasing the area of the PN junction of the diode that is the clamp element, the installation area occupied by the protection circuit becomes very large. Furthermore, a space for forming power supply wirings having different polarities capable of allowing a surge current due to a high voltage to flow through both diodes is also required.
  This puts pressure on the installation area of circuits other than the protection circuit 9 installed around the pad 10 and leads to an increase in the area of the entire semiconductor device. Therefore, this means is not preferable because it goes against the demand for cost reduction by reducing the area of the semiconductor device.
[0014]
  Therefore, if the installation area occupied by the protection circuit 9 is reduced so that the area of the entire semiconductor device does not increase, a sufficient area of the PN junctions of the diodes 91 and 92 constituting the protection circuit 9 cannot be ensured and applied to the pad 10. In addition to the reduced ability to protect the internal circuit 3 from the static electricity generated, the width of each power supply wiring of the protection circuit 9 is also narrowed, so that the current capacity is reduced and the protection circuit 9 itself may be destroyed.
[0015]
  Therefore, as shown in FIG. 25, when the clamping element constituting the protection circuit 9 ′ is only the diode 91 and a negative high voltage is applied to the pad 10, the voltage is clamped by the breakdown voltage of the diode 91. A protection circuit designed to do this is also used.
  In this way, one clamp element is sufficient for one pad, and the power supply wiring is only one polarity.soTherefore, it is possible to increase the area of the PN junction of the diode, which is the clamp element, and to increase the width of the power supply wiring, thereby enhancing the durability.
[0016]
  However, according to the protection circuit 9 ′, the clamp voltage when the positive voltage is applied to the pad 10 is the forward threshold voltage value of the diode 91, but the negative voltage is applied to the pad 10. When the voltage is applied, the clamp voltage becomes a breakdown voltage (about 50 V) of the diode 91, and thus becomes a considerably large voltage. Moreover, there is a problem that the diode deteriorates when it repeats breakdown, which is not preferable.
[0017]
  The present invention has been made in order to solve such a problem, and a semiconductor device has a positive polarity and a high negative polarity voltage due to static electricity without using breakdown with one clamp element per pad. A semiconductor device capable of reliably protecting an internal circuit even when applied to a pad of the semiconductor device, and without squeezing an area for installing a circuit other than the protection circuit in the semiconductor device, and preventing the protection circuit itself from being destroyed. An object of the present invention is to provide a protection circuit.
[0018]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention is provided between a pad of a semiconductor device and an internal circuit.In the protection circuit of a semiconductor device,A clamp circuit unit and a gate circuit unit connected to the clamp circuit unit;Have the aboveThe clamp circuit isA gate terminal, a source terminal, a drain terminal, and a bulk terminal.MIS field effect transistor (MISFET)the aboveThe gate circuit section,It has a gate circuit resistance and a capacitor.
[0019]
  AndThe MISFET isSource terminal andthe aboveBulk terminalAndConnect to the pad and the internal circuit.the aboveThe drain terminal,First power terminalInconnection,the aboveGate terminal is, AboveAnd one terminal of the gate circuit resistorthe aboveConnect to one terminal of the capacitor.the aboveThe other terminal of the gate circuit resistor is,Connect to the second power supply terminal, the other terminal of the capacitor is,Connect to the first power supply terminal.
[0020]
  According to the protection circuit of this semiconductor device, when a positive surge voltage is applied to the pad, a current flows from one terminal of the MISFET to the semiconductor substrate, and the first power source is connected via the bulk terminal and the drain terminal of the MISFET. Current is passed through. Thereby, the positive surge voltage is clamped to the forward threshold voltage of the PN junction.
[0021]
  Further, when a negative surge voltage is applied to the pad, a negative surge voltage due to static electricity applied to the source terminal of the MISFET and the gate terminal of the MISFET connected to the second power supply via the gate circuit resistance. This MISFET is turned on by the potential difference.
  Thereby, a current flows from the first power supply to the pad via the drain terminal and the source terminal of the MISFET. Therefore, the negative surge voltage is clamped to the potential difference between the source and drain when the MISFET is on.
[0022]
  the aboveSemiconductor device has multiple pads and multiple padsThe paAnd a plurality of internal circuits that exchange signals via theIs the aboveWith multiple padsthe aboveProvided between multiple internal circuitsThe gate circuit portion is preferably provided in the semiconductor device in the previous period.
[0023]
  Also,The clamp circuit unit has a first resistor and a second resistor, and the first resistor isIt is inserted between the pad and the source terminal and bulk terminal of MISFET., The second resistor is connected to the MISFET.Inserted between source and bulk terminals and internal circuitThatTherefore, the protection performance can be enhanced.
  A latch-up prevention effect can be obtained by configuring at least the first resistor of the first resistor and the second resistor by a thin film resistor.
[0024]
  Further, by using a high voltage MISFET as the MISFET of the clamp circuit part, the gate circuit part can be omitted and the gate terminal of the high voltage MISFET can be directly connected to the second power supply terminal.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, several embodiments of a protection circuit for a semiconductor device according to the present invention will be described with reference to the drawings.
[0026]
  [First Embodiment]
  FIG. 1 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to the first embodiment of the present invention. The same reference numerals are given to the same parts as those in FIG.
  The protection circuit shown in FIG. 1 includes a clamp circuit unit 6 provided between the pad 10 of the semiconductor device and the internal circuit 3 and a gate circuit unit 8 connected to the clamp circuit unit 6.
[0027]
  The pad 10 has a role of a terminal for exchanging electrical signals between the internal circuit 3 of the semiconductor device and an external circuit, and is formed of the same material as a metal wiring made of aluminum or the like used for the semiconductor device. .
  The clamp circuit unit 6 has N channels.Le MThe gate circuit unit 8, which is configured by an IS field effect transistor (MISFET) 5 and connected to the clamp circuit unit 6, includes a gate circuit resistor 15 and a capacitor 16.
[0028]
  In the protection circuit shown in FIG.N channelThe connection terminal between the source terminal S and the bulk terminal B of the MISFET 5 is connected to the pad 10, the gate terminal of the P-channel MISFET 1 and the gate terminal of the N-channel MISFET 2 constituting the internal circuit 3.N channelThe drain terminal D of the MISFET 5 is connected to the first power supply terminal 11, and the gate terminal G is connected to one terminal of the gate circuit resistor 15 constituting the gate circuit unit 8 and one terminal of the capacitor 16, and the gate circuit thereof. The other terminal of the resistor 15 is connected to the second power supply terminal 12, and the other terminal of the capacitor 16 is connected to the first power supply terminal 11.
[0029]
  The first power supply terminal 11 is supplied with a reference potential (VDD), and the second power supply terminal 12 is supplied with a negative power supply potential (VSS).
  2 and 3 are cross-sectional views schematically showing the clamp circuit unit 6 shown in FIG. 1. FIG. 2 is a diagram for explaining the operation when clamping a positive surge voltage, and FIG. It is a figure for demonstrating the operation | movement in the case of clamping the surge voltage.
[0030]
  N channel shown in FIGS. 1 to 3Le MThe ISFET 5 has its source, gate, drain, and bulk terminals indicated by symbols S, G, D, and B, respectively. Each of these constitutes a MISFET, and the initial letters of the respective terminals are shown as symbols.
[0031]
  2 and 3 includes an N-type semiconductor substrate 100 provided with a P-type well 101 for forming an impurity region having a conductivity type different from that of the semiconductor substrate 100, and an N-channel channel.Le MISFET 5 is configured.
  That is, in the P-type well 101,N channelA P-type diffusion layer 53 that forms the bulk terminal B of the MISFET 5, an N-type diffusion layer 52 of impurities of the same conductivity type as the semiconductor substrate 100 that forms the source terminal S, and a distance from the N-type diffusion layer 52. An N type diffusion layer 51 for forming a drain terminal D is provided, and a gate electrode 50 for forming a gate terminal G is provided above the diffusion layer 52 and the diffusion layer 51.
[0032]
  Where N channelLe MThe gate electrode 50 that forms the gate terminal G of the ISFET 5 is made of polycrystalline silicon.
  An N-type diffusion layer 55 is formed around the P-type well 101 of the N-type semiconductor substrate 100 and connected to the first power supply terminal 11.N channelAn N-type diffusion layer 51 that forms the drain terminal D of the MISFET 5 is also connected to the first power supply terminal 11.
[0033]
  N channelThe P type diffusion layer 53 forming the bulk terminal B of the MISFET 5 and the N type diffusion layer 52 forming the source terminal S are connected to the pad shown in FIG.10Connected to.
  The gate electrode 50 forming the gate terminal G is connected to the gate circuit unit 8 shown in FIG. 1 through the gate connection terminal 57 and is connected to the second voltage terminal through the gate circuit resistor 15.
[0034]
  FIG. 4 is a plan view schematically showing the clamp circuit unit 6 in FIG. In FIG. 4, a large number of small square dots represent contact holes that connect the lower diffusion layer or electrode and the upper terminal (wiring), respectively.
[0035]
  FIG. 5 is an enlarged cross-sectional view close to the actual shape along the line AA in FIG. In FIG. 5, reference numeral 59 denotes a field oxide film formed on the semiconductor substrate 100 and the well 101, which insulates the diffusion layers 51, 52, 53, and 55 from each other. Reference numeral 60 denotes an insulating layer that insulates the first power supply terminal 11, the connection terminal 56, and the gate electrode 50 from each other. A gate insulating layer 54 is formed between the gate electrode 50 and the upper surface of the well 101.
[0036]
  Next, the operation of the protection circuit of this semiconductor device will be described mainly with reference to FIGS. First, voltage clamp characteristics of the clamp circuit unit 6 constituting the protection circuit will be described.
  First, when positive static electricity is applied to the pad 10 shown in FIG. 1, the positive surge voltage is applied to the N channel constituting the clamp circuit unit 6 from the pad 10.Le MThe connection terminal 56 (FIG. 2) between the source terminal S and the bulk terminal B of the ISFET 5 is reached.
[0037]
  N channel shown in FIG.Le MSince the P-type diffusion layer 53 forming the bulk terminal B of the ISFET 5 and the P-type well 101 have the same conductivity type, the P-type well 101 instantaneously has the same potential as the P-type diffusion layer 53. The P-type well 101 and N channelLe MA PN junction is formed by the N-type diffusion layer 51 that forms the drain terminal D of the ISFET 5.
[0038]
  N channelLe MA positive surge voltage reaching the source terminal S and the bulk terminal B of the ISFET 5 applies an electric field in which the PN junction formed by the P-type well 101 and the N-type diffusion layer 51 is in the forward direction.
  The threshold voltage of the PN junction refers to a voltage at which current begins to flow through the PN junction as described above. In particular, a voltage at which a current starts to flow when an electric field is applied in the forward direction to the PN junction is referred to as a forward threshold voltage. It is well known that the threshold voltage of the PN junction is determined by the impurity concentration of the P-type semiconductor and the N-type semiconductor, and the threshold voltage decreases as the impurity concentration increases.
[0039]
  Usually, N channelLe MThe impurity concentration of the P-type diffusion layer 53 that forms the bulk terminal B of the ISFET 5 and the N-type diffusion layer 51 that forms the drain terminal D is higher than that of the P-type well 101. The threshold voltage in the forward direction of the junction is low.
[0040]
  The voltage due to positive static electricity applied to the pad 10 is much higher than the threshold voltage in the forward direction of the PN junction formed between the P-type well 101 and the N-type diffusion layer 51. The PN junction operates in the forward direction, and a positive surge current Isp flows through the first power supply terminal 11 that supplies the reference potential, as indicated by an arrow line in FIG.
[0041]
  In addition, a PN junction having a somewhat higher threshold voltage is formed between the P-type well 101 and the N-type semiconductor substrate 100, which also operates in the forward direction. As indicated by the broken arrow, the current flows to the first power supply terminal 11 through the PN junction surface and the N-type diffusion layer 55.
  As a result, the positive surge voltage applied to the pad 10 is clamped by the low threshold voltage of the PN junction, and no further voltage is applied to the internal circuit 3 shown in FIG.
[0042]
  Next, an operation in the case where negative static electricity is applied to the pad 10 shown in FIG. 1 will be described with reference to FIG. A negative surge voltage due to negative static electricity is generated from the pad 10 shown in FIG.Le MThe source terminal S and the bulk terminal B of the ISFET 5 are reached.
[0043]
  Then, as in the case where a positive surge voltage due to positive polarity static electricity is applied, the P-type well 101 is immediately at the same potential as the P-type diffusion layer 53.
  N channelLe MThe N-type diffusion layer 51 that forms the drain terminal D of the ISFET 5 is connected to the first power supply 11 that supplies the reference potential. Therefore, the PN junction is composed of the P-type well 101 and the N-type diffusion layer 51. A reverse electric field is applied to.
[0044]
  By the way, a voltage at which a current starts to flow when an electric field is applied to the PN junction in the reverse direction is called a reverse threshold voltage, and is generally called a breakdown voltage. In particular, a phenomenon in which an electric field in the reverse direction is applied to the PN junction and a current flows is called a breakdown phenomenon. The breakdown voltage of the PN junction is determined by the impurity concentration of the P-type semiconductor and the N-type semiconductor, but is generally a voltage far exceeding the voltage at which the MISFET is turned on so as not to affect the operation of the normal MISFET.
[0045]
  P-type well 101 andN channelAs described above, a reverse electric field is applied to the PN junction formed by the N-type diffusion layer 51 that forms the drain terminal D of the MISFET 5.
  But,N channelThe negative power supply potential of the second power supply terminal 12 is applied to the gate terminal G of the MISFET 5 via the gate circuit resistor 15 constituting the gate circuit unit 8. The negative surge voltage applied to the source terminal S and the bulk terminal B is much larger than the negative power supply potential applied to the gate terminal G.Le MISFET 5 is turned on.
[0046]
  Therefore, before the PN junction constituted by the P-type well 101 and the N-type diffusion layer 51 forming the drain terminal D flows current due to the breakdown phenomenon, the N channelLe MThe N type diffusion layer 52 that forms the source terminal S of the ISFET 5 and the N type diffusion layer 51 that forms the drain terminal D are electrically connected. Therefore, as indicated by an arrow line in FIG. 3, a negative surge current flows from the first power supply terminal 11 that supplies the reference potential connected to the diffusion layer 51 to the pad 10 through the diffusion layer 52 and the connection terminal 56. Run Isn.
[0047]
  N channelLe MSince the conduction resistance between the source terminal S and the drain terminal D when the ISFET 5 is turned on is small, the potential difference generated between the source terminal S and the drain terminal D is also small. Therefore, to clamp the surge voltage with this small potential difference,FIG.No further potential difference is applied to the internal circuit 3 shown in FIG.
  Next, protection characteristics for the clamp circuit unit 6 of the gate circuit unit 8 constituting the protection circuit will be described.
[0048]
  The gate circuit resistor 15 and the capacitor 16 constituting the gate circuit unit 8 shown in FIG. 1 are capable of dealing with noise-related voltage fluctuations caused by static electricity superimposed on the second power supply terminal 12 that supplies a negative power supply potential. N channel constituting the clamp circuit section 6Le MThe gate terminal G of the ISFET 5 is protected.
  The gate circuit unit 8 includes N channels constituting the clamp circuit unit 6.Le MThe gate terminal G of the ISFET 5 is connected to the second power supply terminal 12 for supplying a negative power supply potential via the gate circuit resistor 15.
[0049]
  There may be a case where a noise voltage fluctuation due to static electricity or the like is superimposed on the negative power supply potential supplied to the second power supply terminal 12. That is, a case where a voltage due to static electricity having a positive or negative polarity is directly applied to the second power supply terminal 12, and a case where the voltage is indirectly applied by transmitting a circuit or the like constituting the semiconductor device. These are superimposed on the negative power supply potential as noise-related voltage fluctuations.
[0050]
  In any of these cases, the N channels constituting the clamp circuit unit 6Le MWhen the gate terminal G of the ISFET 5 is directly connected to the second power supply terminal 12, the noise voltage fluctuation described above is applied to the gate terminal G, and the N channel is applied.Le MThis will cause the ISFET 5 to malfunction.
  Specifically, a normal electrical signal exchanged by the internal circuit 3 via the pad 10 is transmitted to the N channel.Le MWhen the ISFET 5 is turned on, the ISFET 5 is clamped with the first power supply terminal 11 that supplies the reference potential.
[0051]
  As a result, normal electrical signals are not exchanged with the internal circuit 3, and malfunction occurs. Further, depending on the intensity of noise voltage fluctuation superimposed on the second power supply terminal 12 that supplies the negative power supply potential, the N channelLe MThe gate terminal G of the ISFET 5 may be destroyed.
[0052]
  Therefore, the gate circuit resistor 15 and the capacitor 16 constituting the gate circuit unit 8 include a second power supply terminal 12 that supplies a negative power supply potential, a first power supply terminal 11 that supplies a reference potential, and a clamp circuit unit. N channels that make up 6Le MEach is connected between the gate terminal G of the ISFET 5.
[0053]
  A CR time constant constituted by the capacitance component of the capacitor 16 and the resistance component of the gate circuit resistor 15 attenuates the noisy voltage fluctuation superimposed on the second power supply terminal 12 that supplies the negative power supply potential. Let As a result, the N channels constituting the clamp circuit 6Le MThe malfunction and destruction of the gate terminal G of the ISFET 5 are prevented.
[0054]
  The capacitance component of the capacitor 16 constituting the gate circuit unit 8 may be about several times the stray capacitance parasitic on the gate terminals of the P-channel MISFET 1 and the N-channel MISFET 2 constituting the internal circuit 3. As an example, it may be about 5 times. Preferably, the capacity of the capacitor 16 is as large as possible.
  The characteristic operations of the protection circuit of the semiconductor device according to the first embodiment of the present invention described above are summarized as follows.
[0055]
  When a surge voltage due to positive static electricity is applied to the pad 10, the N channel constituting the clamp circuit unit 6Le MA PN junction constituted by the P-type well 101 of the ISFET 5, the N-type drain terminal D, and the N-type semiconductor substrate 100 is biased in the forward direction, and a first potential is supplied by the forward operation. A positive surge current is passed through the power supply terminal 11. Therefore, the positive surge voltage is clamped at the low threshold voltage of the PN junction.
[0056]
  Further, when a surge voltage due to negative static electricity is applied to the pad 10, the N channel that constitutes the clamp circuit unit 6 is used.Le MBetween the bulk terminal B and the source terminal S of the ISFET 5 and the negative power supply potential supplied from the gate circuit unit 8 to which the gate terminal G is connected, the N channelLe MSince an electric field for turning on the ISFET 5 is applied, the source terminal S and the drain terminal D become conductive, and a surge current flows from the first power supply terminal 11 that supplies the reference potential to the pad 10. Therefore, negative surge voltage isN channelClamped to a small potential difference generated between the source terminal S and the drain terminal D of the MISFET 5.
[0057]
  The protection circuit of the semiconductor device of the first embodiment has a great feature compared to the conventional protection circuit. That is, the conventional protection circuit shown in FIG. 24 requires two diodes as clamping elements in order to clamp the positive and negative surge voltages applied to the pad 10.
  However, according to the protection circuit of the semiconductor device shown in FIG. 1, the clamp circuit unit 6 for clamping the positive and negative surge voltages applied to the pad 10 has one N channel as a clamp element.Le MOnly the ISFET 5 is provided.
[0058]
  Furthermore, in order to improve the protection capability of the conventional protection circuit shown in FIG. 24, it is necessary to increase the PN junctions of the two diodes 91 and 92. However, as described above, there is a problem that the area occupied by the protection circuit in the semiconductor device becomes large, and the area where other circuits are installed is pressed.
[0059]
  In contrast, in order to improve the protection capability of the protection circuit of the semiconductor device shown in FIG.Le MWhat is necessary is just to enlarge ISFET5. Specifically, the N channel shown in FIGS.Le MA P-type diffusion layer 53, an N-type diffusion layer 52, an N-type diffusion layer 51, and an N-type semiconductor substrate 100 corresponding to the bulk terminal B, source terminal S, and drain terminal D constituting the ISFET 5, respectively. The installation area can be increased.
[0060]
  This has the same effect as increasing the area of the PN junction of the diodes 91 and 92 of the conventional protection circuit shown in FIG.
  However, as compared with the conventional protection circuit shown in FIG. 24, the protection circuit of the semiconductor device shown in FIGS. 1 to 5 according to the present invention requires only one MISFET for one pad. The installation area of the clamp element in the semiconductor device can be very small. So thisN channelEven if the MISFET 5 is installed so as to have sufficient protection capability, there is no problem of squeezing the area where other circuits are installed.
[0061]
  There is a further advantage in that the number of clamp elements constituting this protection circuit is one. That is, in the conventional protection circuit shown in FIG. 24, a wiring for supplying a reference potential and a wiring for supplying a negative power supply potential are required as the power supply wiring.
  The wiring of the power supply system necessary for the protection circuit of the semiconductor device shown in FIG. 1 according to the present invention is also provided for the first power supply terminal 11 for supplying the reference potential and for the second power supply terminal 12 for supplying the negative power supply potential. is necessary.
[0062]
  However, the operation of the conventional protection circuit is performed by passing a current through the diodes 91 and 92 which are the clamp elements shown in FIG. A very large current flows through the diodes 91 and 92 in order to clamp a high voltage due to static electricity applied to the pad 10.
[0063]
  Generally, metal wiring such as aluminum is used for wiring in the semiconductor device. When a large amount of current is applied to the metal wiring, a wiring arrangement method such as widening the width of the metal wiring is used to cope with fusing of the metal wiring caused by stress such as heat generated by the current supply.
  For this reason, in order to realize the conventional protection circuit shown in FIG. 24, the metal wiring connecting the diode 91 and the first power supply terminal 11 and the diode 92 and the second power supply terminal 12 is very A wide one was necessary.
[0064]
  On the other hand, the protection circuit of the semiconductor device shown in FIG. 1 according to the present invention does not pass a current to the second power supply terminal 12 that supplies a negative power supply potential in the protection operation. Therefore, the wiring is connected to the second power supply terminal 12 for supplying a negative power supply potential.N channelThe metal wiring for connecting the gate terminal G of the MISFET 5 and the gate circuit resistor 15 constituting the gate circuit section 8 and the second power supply terminal 12 does not need to withstand energization of a large current, and is a metal used for wiring of a normal internal circuit. The width may be the same as the wiring.
[0065]
  Therefore, the protection circuit for a semiconductor device according to the first embodiment of the present invention is capable of generating two types of positive and negative surge voltages applied to the semiconductor device with one clamp element by using one metal wiring. One power supply terminal 11 can be energized and absorbed.
[0066]
  That is, since only one clamping element is required regardless of the polarity of the applied surge voltage, a very compact protection circuit can be configured. In addition, unlike the conventional example shown in FIG. 25, the surge voltage of one polarity is not protected by the breakdown operation of the clamp element, so that the clamp voltage increases or the clamp element deteriorates. There is no fear of speeding up.
[0067]
  [Second Embodiment]
  Next, a protection circuit for a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In FIG. 6, the same parts as those in FIG.
  The semiconductor device shown in FIG. 6 includes a plurality of pads 10a. . . 10n and a plurality of internal circuits 3a. . . 3n.
[0068]
  The protection circuit includes a plurality of pads 10a. . . 10n and a plurality of internal circuits 3a. . . 3n, a plurality of clamp circuit portions 6a. . . 6n and its clamp circuit portions 6a. . . 6n and one gate circuit unit 8 connected to 6n.
[0069]
  A plurality of clamp circuit sections 6a. . . 6n is N channelLe MISFET 5a. . . 5n, and the gate circuit unit 8 includes a gate circuit resistor 15 and a capacitor 16. thisGateThe configuration of the circuit unit 8 is shown in FIG. 1 in the first embodiment described above.GateThe configuration of the circuit unit 8 is the same.
[0070]
  Next, a connection state of each component of the protection circuit of the semiconductor device will be described.
  As shown in FIG. 6, a plurality of pads 10a. . . 10n are clamp circuit portions 6a. . . N channels that make up 6nLe MISFET 5a. . . 5n source terminal S and bulk terminal B connection terminal, internal circuit 3a. . . P channel composing 3nLe MISFET1 and N channelLe MConnected to each gate terminal of ISFET2, N channelLe MISFET 5a. . . Each drain terminal D of 5n is connected to the first power supply terminal 11.
[0071]
  N channelLe MISFET 5a. . . Each gate terminal G of 5n is connected to one terminal of a gate circuit resistor 15 and one terminal of a capacitor 16 constituting the gate circuit section 8, and the other terminal of the gate circuit resistor 15 is a second power supply terminal. 12 and the other terminal of the capacitor 16 is connected to the first power supply terminal 11.
[0072]
  The protection circuit of the semiconductor device of the second embodiment has a characteristic function of the protection circuit of the semiconductor device of the first embodiment shown in FIG. 1, and further reduces the area as the protection circuit. Is possible.
  That is, the plurality of pads 10a. . . 10n and a plurality of internal circuits 3a. . . 3n and clamp circuit portions 6a. . . 6n, each clamp circuit section 6a. . . This is because only one gate circuit portion 8 connected to 6n is provided.
[0073]
  The gate circuit unit 8 includes each clamp circuit unit 6a. . . N channels that make up 6nLe MISFET 5a. . . Since the potential is supplied to the 5n gate terminal G, there is no problem even if only one is provided in a certain portion of the semiconductor device.
  Therefore, according to the protection circuit of the semiconductor device of the second embodiment, the same effect as in the case of the first embodiment described above can be obtained, but furthermore, the installation area occupied by the protection circuit around the pad can be reduced. Therefore, the installation area occupied by other circuits other than the protection circuit provided around the pad is not pressed, which is very effective for reducing the area of the semiconductor device.
[0074]
  [Third Embodiment]
  Next, a protection circuit for a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. In FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
  The semiconductor device protection circuit shown in FIG. 7 is different from the semiconductor device protection circuit shown in FIG.Le MThis is only the point constituted by the ISFET 5 and the first resistor 41 and the second resistor 42.
[0075]
  The first resistor 41 is connected to the pad 10 and the N channel.Le MThe second resistor 42 is inserted between the source terminal S of the ISFET 5 and the connection terminal of the bulk terminal B.N channelIt is inserted between the connection terminal of the source terminal S and bulk terminal B of the MISFET 5 and the gate terminals of the P-channel MISFET 1 and the N-channel MISFET 2 constituting the internal circuit 3.
  Other configurations are the same as those of the protection circuit of the semiconductor device according to the first embodiment of the present invention shown in FIG.
[0076]
  In the third embodiment, the first resistor 41 and the second resistor 42 provided in the clamp circuit unit 6 function as current limiting elements, and the N channel.Le MThe ISFET 5 and the internal circuit 3 are protected.
  Even when static electricity having either positive or negative polarity is applied to the pad 10, the N channel constituting the clamp circuit unit 6 is used.Le MA current flows through the ISFET 5. Therefore, the first resistor 41 has itsN channelLimiting the current flowing through MISFET 5;N channelThe destruction of the MISFET 5 itself is prevented.
[0077]
  The second resistor 42 constituting the clamp circuit unit 6 has an N channel.Le MIt is provided between the ISFET 5 and the internal circuit 3. As a result, the clamp circuit 6 is removed from the pad 10 to limit the current flowing through the internal circuit 3, thereby preventing the internal circuit 3 from being destroyed.
  As described above, the protection circuit of the semiconductor device of the third embodiment shown in FIG. 7 can further improve the protection performance of the semiconductor device of the first embodiment shown in FIG.
[0078]
  In addition, the first resistor 41 is clampedCircuit part6, because the second resistor 42 protects the internal circuit 3.Circuit part6 is smaller than that of the first embodiment, and the entire clamp circuit can be further reduced.
[0079]
  However, since the first resistor 41 and the second resistor 42 of the clamp circuit unit 6 are connected in series between the pad 10 and the internal circuit 3, this prevents the internal circuit 3 from operating at high speed. It becomes. Therefore, in designing this semiconductor device, the resistance values of the first resistor 41 and the second resistor 42 are taken into consideration that the internal circuit 3 exchanges signals with the external circuit via the pad 10 at a high speed. Therefore, it is necessary to select a resistance value within a range that does not hinder the signal transmission.
[0080]
  [Fourth Embodiment]
  Next, a protection circuit for a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. In FIG. 8, the same parts as those in FIGS. 6 and 7 are denoted by the same reference numerals, and description thereof is omitted.
[0081]
The protection circuit of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. . . 10n and a plurality of internal circuits 3a. . . 3n and clamp circuit portions 6a. . . 6n and one gate circuit unit 8 connected to them. This is the same as the second embodiment shown in FIG.
  However, each clamp circuit section 6a. . . 6n is N channelLe MISFET 5a. . . 5n, the first resistor 41, and the second resistor 42, which are the same as those of the third embodiment shown in FIG.
[0082]
  Therefore, according to the protection circuit of the semiconductor device of the fourth embodiment, the installation area occupied by the protection circuit around the pad is reduced as in the protection circuit of the semiconductor device of the second embodiment shown in FIG. Therefore, it is very effective for reducing the area of the semiconductor device, and the protection performance of the semiconductor device can be improved similarly to the protection circuit of the semiconductor device of the third embodiment shown in FIG.
[0083]
  [Fifth Embodiment]
  Next, a semiconductor device protection circuit according to a fifth embodiment of the present invention will be described with reference to FIGS.
  FIG. 9 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to the fifth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals.
  In the protection circuit of the semiconductor device shown in FIG. 9, the clamp circuit portion 6 'connected between the pad 10 and the internal circuit 3 is composed of an N-channel high voltage MISFET 5'.
[0084]
  Then, the gate circuit unit 8 in the protection circuit of the semiconductor device shown in FIG. 1 is omitted, and the gate terminal G of the N-channel high voltage MISFET 5 ′ constituting the clamp circuit unit 6 ′ is directly connected to the second power supply terminal 12. Connect to. Other circuit configurations are the same as those of the first embodiment shown in FIG.
  Therefore, the semiconductor device protection circuit of the fifth embodiment can provide the same function as that of the semiconductor device protection circuit of the first embodiment shown in FIG. The installation area can be reduced.
[0085]
  Therefore, this fifthEmbodimentIn the protection circuit of the semiconductor device, a high breakdown voltage MISFET 5 'is used as a clamp element constituting the clamp circuit portion 6'. This high breakdown voltage MISFET 5 'has the configuration of its gate terminal G used in the first to fourth embodiments.N channelIt is slightly different from MISFET5.
  An example of the structure of the N-channel high voltage MISFET 5 'will be described below.
[0086]
(First example)
  FIGS. 10 and 11 are a plan view and a cross-sectional view similar to FIGS. 4 and 5 showing the first example, and corresponding parts are not necessarily the same as FIGS. is doing.
[0087]
  N channelThe main causes of the breakdown of the MISFET 5 are the gate electrode and the gate insulating film constituting the gate terminal G. Therefore, the high breakdown voltage type N-channel MISFET 5 ′ shown in FIGS. 10 and 11 uses the field oxide film 59 as the gate insulating layer 54, and further, through the insulating layer 60, a metal wiring such as aluminum. The gate electrode 50 is provided.
  By configuring in this way, the breakdown tolerance against noise voltage fluctuation due to static electricity superimposed on the voltage of the second power supply terminal 12 is remarkably improved.
[0088]
(Second example)
  FIGS. 12 and 13 are a plan view and a cross-sectional view similar to FIGS. 4 and 5 showing a second example of an N-channel high voltage MISFET 5 ′, which are not necessarily the same as FIGS. 4 and 5, but correspond. The same reference numerals are given to the parts.
[0089]
  In this example, the gate electrode 50 is shown in FIGS.N channelLike the MISFET 5, it is formed of polycrystalline silicon. However, a field oxide film 59 is used as the gate insulating layer 54, and a gate connection terminal 57 made of aluminum wiring is placed over the entire length of the gate electrode 50 made of polycrystalline silicon. A large number of contact holes 61 are arranged over the entire gate portion.
[0090]
  in this way,High pressure resistanceBy constructing the gate terminal G of the MISFET 5 ', the breakdown tolerance can be improved.
  The gate electrode 50 may be an aluminum gate instead of polycrystalline silicon. Thereby, the response speed can be increased and the threshold voltage can be lowered.
[0091]
(Third example)
  FIG. 14 is a cross-sectional view similar to FIG. 13 showing a third example of an N-channel high voltage MISFET 5 ′, and although not necessarily the same as FIG. 13, corresponding parts are denoted by the same reference numerals.
[0092]
  In this example, the gate electrode 50 is formed of polycrystalline silicon, and the gate insulating layer 54 is also formed of the N channel shown in FIG.Le MLike the ISFET 5, it is a thin insulating film. However, the N-type diffusion layer 52 that forms the source terminal S, the N-type diffusion layer 51 that forms the drain terminal D, and the gate electrode 50 have an offset gate structure.
  Even with this configuration,High pressure resistanceThe breakdown resistance of the gate insulating layer 54 constituting the gate terminal G of the MISFET 5 ′ can be improved.
[0093]
(Fourth example)
  FIGS. 15 and 16 are a plan view and a cross-sectional view similar to FIGS. 4 and 5 showing a fourth example of an N-channel high voltage MISFET 5 ′, which are not necessarily the same as FIGS. 4 and 5, but correspond. The same reference numerals are given to the parts.
[0094]
  Also in this example, the gate electrode 50 is formed of polycrystalline silicon, and the gate insulating layer 54 is also formed of the N channel shown in FIG.Le MLike the ISFET 5, it is a thin insulating film. However, a source LDD (lightly doped) region (thin impurity diffusion region) is provided between the gate electrode 50 and the N type diffusion layer 51 forming the source terminal S and the N type diffusion layer 51 forming the drain terminal D. 152 and a drain LDD region 151 are provided. Even with this configuration,High pressure resistanceThe breakdown resistance of the gate insulating layer 54 constituting the gate terminal G of the MISFET 5 ′ can be improved.
[0095]
(Fifth example)
  FIGS. 17 and 18 are sectional views similar to FIGS. 4 and 5 showing a fifth example of an N-channel high voltage MISFET 5 ′, and are not necessarily the same as FIGS. The same reference numerals are attached.
[0096]
  In this high breakdown voltage MISFET 5 ′, a P-type well 101 is provided on an N-type semiconductor substrate 100, and a gate electrode 50 is provided thereon via a gate insulating layer 54. On both sides of the gate electrode 50, an N type diffusion layer (hereinafter referred to as “source diffusion layer”) 52 that forms the source terminal S and an N type diffusion layer (hereinafter referred to as “drain diffusion layer”) that forms the drain terminal D. ) 51 is provided.
[0097]
  The source diffusion layer 52 is connected to the connection terminal 56 together with the P-type diffusion layer 53 that forms the bulk terminal B. The drain diffusion layer 51 is connected to the first power supply terminal 11 that also serves as a drain electrode.
[0098]
  Further, light doped diffusion layers 58 a and 58 b made of an impurity diffusion layer having an impurity concentration lower than that of the source diffusion layer 52 and the drain diffusion layer 51 are provided so as to surround the source diffusion layer 52 and the drain diffusion layer 51, respectively. . Further, field oxide films 59a and 59b, which are electric field relaxation silicon oxide films thicker than the gate insulating layer 54, are provided between the gate electrode 50 and the lightly doped diffusion layers 58a and 58b, respectively. Other configurations are shown in FIG. 4 and FIG.N channelThe same as MISFET5.
[0099]
  In general, the breakdown voltage of a MISFET is mainly determined by the extension of a depletion layer formed in a PN junction between a drain region composed of a high concentration impurity diffusion layer and a semiconductor substrate. The depletion layer becomes more difficult to stretch.
[0100]
  Therefore, in order to improve the breakdown voltage of the MISFET, the depletion layer generated in the PN junction may be easily extended. In general, the lower the impurity concentration in the PN junction, the easier the depletion layer extends. Often, a layer is formed between the drain region and the semiconductor substrate.
[0101]
  High breakdown voltage MISFET shown in FIG. 17 and FIG.5 'Then, light doped diffusion layers 58a and 58b made of impurity diffusion layers having an impurity concentration lower than that of the source diffusion layer 52 and the drain diffusion layer 51 are provided so as to surround the source diffusion layer 52 and the drain diffusion layer 51, respectively. The impurity concentration in the PN junction is lowered, and the depletion layer is easily extended.
[0102]
  Here, as the gate insulating layer 54, a silicon oxide film with a thickness of about 80 nm is preferably used. The gate electrode 50 is made of polycrystalline silicon (polysilicon) having a thickness of about 450 nm. The impurity used for the source diffusion layer 52 is preferably a phosphorus atom if it is N-type, and a boron atom if it is P-type. The field oxide films 59a and 59b formed at the ends of the gate electrode 50 facing the source diffusion layer 52 and the drain diffusion layer 51, respectively, are made of a silicon oxide film having a thickness of about 700 nm. The impurities used for the lightly doped diffusion layers 58a and 58b may be phosphorus atoms if they are N-type, and boron atoms if they are P-type.
[0103]
  If the impurity used for the drain diffusion layer 51 is also N-type, phosphorus atoms may be used, and if it is P-type, boron atoms may be used.
  Even with this configuration,High pressure resistanceThe breakdown resistance of the gate insulating layer 54 constituting the gate terminal G of the MISFET 5 ′ can be improved.
[0104]
  [Sixth Embodiment]
  Next, a protection circuit for a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG. In FIG. 19, the same parts as those in FIG. 9 are denoted by the same reference numerals.
  The semiconductor device protection circuit shown in FIG. 19 is different from the semiconductor device protection circuit shown in FIG. 9 in that the clamp circuit portion 6 ′ has an N-channel high voltage MISFET 5 ′, a first resistor 41 and a second resistor. This is only a point constituted by the resistor 42.
[0105]
  The first resistor 41 is interposed between the pad 10 and the connection terminal between the source terminal S and the bulk terminal B of the N-channel high breakdown voltage MISFET 5 ′, and the second resistor 42 is connected to the connection terminal. And the gate terminals of the P-channel MISFET 1 and the N-channel MISFET 2 constituting the internal circuit 3.
  Other configurations are the same as those of the protection circuit of the semiconductor device according to the fifth embodiment of the present invention shown in FIG.
[0106]
  In the sixth embodiment, the first resistor 41 and the second resistor 42 provided in the clamp circuit section 6 'function as current limiting elements and have a role of protecting the high voltage MISFET 5' and the internal circuit 3. .
  Therefore, similarly to the protection circuit of the semiconductor device of the third embodiment shown in FIG. 7, the protection performance of the semiconductor device of the fifth embodiment shown in FIG. 9 can be further improved.
[0107]
  [Supplementary explanation]
  The configuration and operation of the first to sixth embodiments of the present invention have been described above, but the present invention is not limited to these.
  The gate circuit resistor 15 constituting the gate circuit section 8 in the first to fourth embodiments of the present invention, and the first constituting the clamp circuit section 6 or 6 'in the third, fourth and sixth embodiments. The resistor 41 and the second resistor 42 may be either diffusion resistors or thin film resistors, or a combination of both.
[0108]
  As a material for the resistance, in the case of a thin film resistor, a refractory metal such as tungsten or titanium, polycrystalline silicon, or a laminate of polycrystalline silicon and a refractory metal may be used. Or the material which comprises other resistance can also be used freely. Furthermore, the resistance values of these resistors can be freely selected within a range that does not limit the operating speed of the semiconductor device.
[0109]
  For example, in the protection circuit of the semiconductor device according to the third embodiment of the present invention shown in FIG. 7, the first resistor 41 and the second resistor 42 connected in series between the pad 10 and the internal circuit 3 are Since the size of these resistors greatly affects the transmission speed of signals applied to the semiconductor device, the designer of the semiconductor device may select the resistance value in consideration of the operation speed of the circuit.
[0110]
  Note that the first resistor 42 is formed of a thin film resistor, which is effective in preventing latch-up. The reason will be described below.
  First, the latch-up phenomenon will be described. In a semiconductor device using a MISFET, a bipolar transistor exists in a parasitic structure, and a thyristor structure circuit is configured by these bipolar transistors.
[0111]
  For this reason, when an external high voltage or noise due to static electricity is used as a trigger and the thyristor structure circuit is turned on, an excessive power supply current flows. Once this excessive power supply current flows, the current continues to flow even if the cause of turning on the circuit of the thyristor structure is removed.
[0112]
  In addition, since many parasitic bipolar transistors are turned on and flow, the current value is several tens of times larger than the power supply current during normal operation. In some cases, the semiconductor device may be damaged. This phenomenon is called latch-up, and a countermeasure for preventing this latch-up is important for a semiconductor device using a MISFET.
[0113]
  Next, a latch-up generation mechanism will be described with reference to the drawings. FIG. 20 is a diagram for explaining latch-up.Le MISFET71 and N channelLe MIt is a circuit diagram of the inverter circuit of the semiconductor device comprised with ISFET72.
[0114]
  This inverter circuit is P channelLe MThe gate terminal G1 of the ISFET 71 and the N channelLe MThe gate terminal G2 of the ISFET 72 is connected to each other as an input terminal IN. P channelLe MThe drain terminal D1 of the ISFET 71 and the N channelLe MThe drain terminal D2 of the ISFET 72 is connected to each other as an output terminal OUT. And P channelLe MThe source terminal S1 and the bulk terminal B1 of the ISFET 71 are connected to the first power supply VDD, and the N channelLe MThe source terminal S2 and the bulk terminal B2 of the ISFET 72 are connected to the second power supply VSS.
[0115]
  FIG. 21 is a plan view schematically showing this inverter circuit. FIG. 22 is a cross-sectional view taken along the line CC of FIG. 21, and shows an equivalent circuit showing a thyristor structure with bipolar transistors existing parasitically therein. FIG. 23 shows only the equivalent circuit.
[0116]
  The structure of this semiconductor device will be described mainly with reference to the cross-sectional view shown in FIG. This semiconductor device includes an N-type semiconductor substrate 100 and a P channel.Le MAn ISFET 71 is formed, and an N channel is formed in a P type well 101 formed in an N type semiconductor substrate 100.Le MAn ISFET 72 is formed to constitute an inverter circuit using MISFET.
[0117]
  theseP channel MISFET 71, N channel MISFET 72In the inverter circuit according to FIG. 2, P-type and N-type impurity diffusion regions are formed on the same semiconductor substrate 100, so that PNP-type bipolar transistors Q1 and Q2 and NPN-type bipolar transistors Q3 and Q4 exist in a parasitic manner. . Further, the N type semiconductor substrate 100 and the P type well 101 have parasitic resistances r1 and r2, respectively.
[0118]
  The PNP type bipolar transistor Q1 has an N type semiconductor substrate 100 as a base and a P channel as an emitter.Le MThe source terminal S1 of the ISFET 71 is used, and the collector is a P-type wafer.Le 101. The PNP-type bipolar transistor Q2 has an N-type semiconductor substrate 100 as a base and a P-channel as an emitter.Le MThe drain terminal D1 of the ISFET 71 is used, and the collector is a P-type well 101.
[0119]
  Similarly, the NPN bipolar transistor Q3 has a base of P-type well 101 and an emitter of N-channel.Le MThe source terminal S2 of the ISFET 72 is used, and the collector is the N-type semiconductor substrate 100. The NPN bipolar transistor Q4 has a P-type well 101 as a base and an N-channel emitter as an emitter.Le MThe drain terminal D2 of the ISFET 72 is used, and the collector is an N-type semiconductor substrate 100.
[0120]
  The feature of this structure is that the collectors of the PNP bipolar transistors Q1 and Q2 and the bases of the NPN bipolar transistors Q3 and Q4 are common to the P type well 101. Similarly, the bases of the PNP type bipolar transistors Q1 and Q2 The collectors of the NPN bipolar transistors Q 3 and Q 4 are common to the N type semiconductor substrate 100. These bipolar transistors Q1, Q2, Q3, Q4 and resistors r1, r2 constitute a thyristor structure circuit.
[0121]
  The latch-up generation operation will be described with reference to the cross-sectional view of FIG. 22 and the equivalent circuit diagram of the thyristor structure of FIG.
  First, the case where a high external voltage or noise is applied to the output terminal OUT will be described.
[0122]
  When a voltage higher than the first power supply VDD is applied to the output terminal OUT shown in FIG. 23, the P channel shown in FIG.Le MThe drain terminal D1 of the ISFET 71 and the N-type semiconductor substrate 100 are forward biased, a current flows through the emitter and base of the PNP-type bipolar transistor Q2, and the emitter and collector are conducted. As a result, a current flows through the resistor r2, and a voltage is generated across the resistor r2.
[0123]
  The voltage generated at both ends of the resistor r2 becomes the base potential of the NPN bipolar transistor Q3, the base potential rises in the positive direction, and the emitter and collector of the NPN bipolar transistor Q3 are electrically connected. Transistor Q3 is turned on.
  When a current flows through the NPN bipolar transistor Q3, a voltage is generated across the resistor r1, thereby lowering the base potential of the PNP bipolar transistor Q1 and turning on the PNP bipolar transistor Q1.
[0124]
  Therefore, a current flows through the emitter and base of the PNP bipolar transistor Q1 and the resistor r2, and a voltage is generated again across the resistor r2, maintaining the ON state of the NPN bipolar transistor Q3 and applying it to the output terminal OUT. Even if the voltage is removed, an excessive current continues to flow between the first power supply VDD and the second power supply VSS.
[0125]
  Further, when a voltage equal to or lower than the first power supply VDD is applied to the output terminal OUT, the N channelLe MThe drain terminal D2 of the ISFET 72 and the P-type well 101 are forward-biased, current flows through the base and emitter of the NPN bipolar transistor Q4, and the emitter and collector are conducted. As a result, a current flows through the resistor r1, a voltage is generated across the resistor r1, and the PNP bipolar transistor Q1 is turned on.
[0126]
  As a result, a voltage is generated across the resistor r2, and the NPN bipolar transistor Q3 is turned on. For this reason, a voltage is generated again at both ends of the resistor r1, the PNP bipolar transistor Q1 is kept on, and even if the voltage applied to the output terminal OUT is removed, the first power supply VDD and the second power supply VSS Excessive current continues to flow between them.
[0127]
  In this state, the collector currents of the NPN-type bipolar transistor Q3 and the PNP-type bipolar transistor Q1 supply the base current as in the case where a voltage equal to or higher than the first power supply VDD is applied to the output terminal OUT. The current continues to flow until the power supply voltage supplied between the first power supply VDD and the second power supply VSS is cut off.
[0128]
  The latch-up generation mechanism is not limited to the above example, and many factors are conceivable. In any case, when a current flows in an N-type semiconductor substrate provided with a MISFET or a P-type well and the voltage drop between the internal resistor r1 and the resistor r2 exceeds a certain limit value, latch-up occurs.
[0129]
  According to the equivalent circuit diagram of FIG. 23, the voltage value at which both ends of the resistor r1 and the resistor r2 are equal to the voltage VEB between the base and emitter of the PNP bipolar transistor Q1 and the NPN bipolar transistor Q3 is a fixed limit value. Become. This is one of the conditions for the occurrence of latch-up.
[0130]
  Therefore, the causes of latch-up can be summarized as follows. Excessive current flowing in the semiconductor substrate or well of the semiconductor device, that is, carriers injected into the semiconductor substrate or well turn on the bipolar transistor, and the circuit operation of the thyristor structure constituted by these Causes latch-up.
[0131]
  Although there are many means for preventing this latch-up, as is clear from the above description, the carrier injected into the semiconductor substrate or well serves as a trigger for generating latch-up. Limiting injection is an effective means of preventing latch-up.
[0132]
  By the way, the diffusion resistor is configured by selectively providing an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate or well in the semiconductor substrate or well. Therefore, a diode having a PN junction is parasitically present in the diffusion resistor.
  On the other hand, since the thin film resistor is provided on the field oxide film or the insulating layer on the semiconductor substrate or well, the diode is not parasitic like the diffused resistor.
[0133]
  In the protection circuit of the conventional semiconductor device as shown in FIG. 24, when a diffused resistor is used for the resistor 4, diodes that are parasitic on the diffused resistor are often used as the diodes 91 and 92 of the clamp element. This is because the resistor 4 as the current limiting element and the diodes 91 and 92 as the voltage clamp elements can be built as the same element, so that the entire protection circuit can be saved.
[0134]
  In this way, except for the case where a diffused resistor is positively used as the resistance of the protection circuit, when a resistance component is required purely as a current limiting element, carrier injection occurs in the semiconductor substrate or well, and latch-up occurs. It is better to use a thin film resistor than a diffused resistor as a trigger.
[0135]
  Therefore, in the third, fourth, and sixth embodiments of the present invention, the first resistor 41 and the second resistor 42 that constitute the clamp circuit section 6 or 6 'are N channels that are clamp elements.Le MSince these are current limiting resistors that limit the current flowing through the ISFET 5 or the high withstand voltage MISFET 5 ′ and the internal circuit 3 and protect them from destruction, an effect of preventing latch-up can be obtained by configuring these resistors with thin film resistors. be able to.
[0136]
  That is, when the first resistor 41 is formed of a diffused resistor, when a high voltage or noise due to static electricity having a positive or negative polarity is applied to the pad 10, the first resistor 41 passes through a diode that is parasitic on the first resistor 41. As a result, the semiconductor substrate and well are energized, and carriers are injected into the semiconductor substrate and well, causing latch-up.
[0137]
  However, by configuring the first resistor 41 with a thin film resistor, the first resistor 41 can be used as a pure resistor having no path for injecting carriers into the semiconductor substrate or well region, and a semiconductor device due to high voltage or noise caused by static electricity. It is possible to provide a protection circuit that prevents the breakdown and the occurrence of latch-up.
[0138]
  Further, the N channel which is the clamp element described in the first to fifth embodiments of the present invention.Le MIn the ISFET 5, a P-type well 101 is provided in an N-type semiconductor substrate 100, and the N-channel is connected to the P-type well 101.Le MA P type diffusion layer 53 that forms the bulk terminal B of the ISFET 5, an N type diffusion layer 52 that forms the source terminal S, and an N type diffusion layer 51 that forms the drain terminal D are provided.
[0139]
  However, without providing the P-type well 101, the N-channel is formed on the P-type semiconductor substrate 100.Le MEven if each of the diffusion layers forming the bulk terminal B, source terminal S, and drain terminal D of the ISFET is provided, it is possible to provide a protection circuit having the features of the present invention.
[0140]
  In any case, various modifications can be made without departing from the gist of the present invention. A configuration in which the conventional protection circuit 9 shown in FIG. 24 and the protection circuit according to the present invention are combined may be employed. Specifically, the protection circuit of the present invention may be provided between the protection circuit 9 and the internal circuit 3 shown in FIG. 24 or between the protection circuit 9 and the pad 10.
[0141]
【The invention's effect】
  As described above, according to the present invention, even if a positive and negative voltage due to static electricity is applied to a pad of a semiconductor device, one breakdown element is provided for each pad of the semiconductor device. The internal circuit can be reliably protected without using the. In addition, since the arrangement space can be reduced, it is possible to prevent the protection circuit itself from being destroyed without squeezing an area for installing a circuit other than the protection circuit in the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing the clamp circuit unit 6 shown in FIG. 1 and showing a current flow when a positive high voltage is applied to a pad.
FIG. 3 is a cross-sectional view schematically showing the clamp circuit unit 6 shown in FIG. 1, and showing a current flow when a negative high voltage is applied to a pad.
FIG. 4 is a plan view schematically showing the clamp circuit section 6 in the same manner.
FIG. 5 is an enlarged cross-sectional view close to the actual shape along the line AA in FIG. 4;
FIG. 6 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a third embodiment of the present invention.
FIG. 8 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a fifth embodiment of the present invention.
10 is a plan view showing a first example of a high voltage MISFET 5 ′ in FIG. 9. FIG.
11 is a cross-sectional view taken along line AA in FIG.
12 is a plan view showing a second example of the high voltage MISFET 5 ′ in FIG. 9. FIG.
13 is a cross-sectional view taken along line AA in FIG.
14 is a cross-sectional view similar to FIG. 13, showing a third example of the high voltage MISFET 5 ′ in FIG.
15 is a plan view showing a fourth example of the high breakdown voltage MISFET 5 ′ in FIG. 9. FIG.
16 is a cross-sectional view taken along line AA in FIG.
FIG. 17 is a plan view showing a fifth example of the high voltage MISFET 5 ′ in FIG. 9;
18 is a cross-sectional view taken along line AA in FIG.
FIG. 19 is a circuit diagram showing a protection circuit and an internal circuit of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 20 is a circuit diagram of an inverter circuit of a semiconductor device for explaining latch-up.
FIG. 21 is a plan view of a semiconductor device schematically showing the inverter circuit of FIG. 20;
FIG. 22 is a cross-sectional view taken along the line CC of FIG. 21, and shows an equivalent circuit showing a thyristor structure with a bipolar transistor that is parasitically present in the line.
FIG. 23 is a circuit diagram showing only the equivalent circuit.
FIG. 24 is a circuit diagram showing an example of a protection circuit and an internal circuit of a conventional semiconductor device.
FIG. 25 is a circuit diagram showing another example of a protection circuit and an internal circuit of a conventional semiconductor device.
[Explanation of symbols]
1: P channelLe MIS-type field effect transistor
2, 5, 5a, 5n: N channelLe MIS-type field effect transistor
5 ': High breakdown voltage MIS type field effect transistor
3, 3a, 3n: Internal circuit 6, 6a, 6n, 6 ': Clamp circuit section
8: Gate circuit part 10, 10a, 10n: Pad
11: First power supply terminal 12: Second power supply terminal
13: Output terminal 15: Gate circuit resistance
16: Capacitor 41: First resistor 42: Second resistor
50: Gate electrodes 51 and 52,55: N-type diffusion layer
53: P-type diffusion layer 54: Gate insulating layer 56: Connection terminal
57: Gate connection terminal 58a, 58b: Lightly doped diffusion layer
59,59a, 59b: Field oxide film (electric field relaxation silicon oxide film)
60: Insulating layer 61: Contact hole
100: Semiconductor substrate 101: P-type well
151: Drain LDD region 152: Source LDD region

Claims (3)

In the protection circuit of the semiconductor device provided between the pad of the semiconductor device and the internal circuit ,
A clamp circuit unit, and a gate circuit unit connected to the clamp circuit unit ,
The clamp circuit unit includes a MIS field effect transistor including a gate terminal, a source terminal, a drain terminal, and a bulk terminal ,
The gate circuit unit includes a gate circuit resistor and a capacitor,
Prior Symbol M IS-type field effect transistor, the source terminal and the bulk terminal, is connected to said pads and the internal circuit, the drain terminal is connected to the first power supply terminal, said gate terminal, connected to one terminal of the capacitor and one terminal of the gate circuit resistance, the other terminal of the gate circuit resistor is connected to the second power supply terminal, the other terminal of the capacitor, the A protection circuit for a semiconductor device, wherein the protection circuit is connected to a first power supply terminal. Said semiconductor device, and a plurality of internal circuits via a plurality of pads and the plurality of Pas head for exchanging signals,
The clamp circuit are respectively provided between the plurality of internal circuits and the plurality of pads, said gate circuit section, according to claim 1, characterized in that provided one on year semiconductor device Protection circuit for semiconductor devices. The clamp circuit unit has a first resistor and a second resistor;
The first resistor is interposed between the pad and a source terminal and a bulk terminal of the MIS field effect transistor ,
Said second resistor, a semiconductor device according to claim 1 or 2, characterized in the inserted Turkey between the source terminal and the bulk terminal and the internal circuit of the MIS-type field effect transistor Protection circuit.

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