JP3794963B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a variable capacitance element using a PN junction, and more particularly to measures for expanding a capacitance change range.
[0002]
[Prior art]
Conventionally, a variable capacitance element is used as a frequency switching circuit element in an oscillation circuit, for example. In particular, one type of high-performance variable capacitance element uses a junction capacitance of a PN junction diode.
[0003]
For example, as disclosed in Japanese Patent Laid-Open No. 10-74661, a PN junction is formed by sequentially injecting N-type impurities and P-type impurities, and this PN junction is used as a capacitor of a variable capacitance element. A functioning semiconductor device is disclosed.
[0004]
FIG. 9 is a block diagram schematically showing a configuration of a conventional device including an oscillation circuit provided on a semiconductor substrate and an external variable capacitance element. As shown in the figure, in the conventional device, an oscillation circuit (including a bipolar transistor BT) is provided on a semiconductor substrate 100 in a package, and a mother substrate (not shown) on which the semiconductor substrate 100 is mounted. On top of this, a variable capacitance element VAR such as a variable capacitance diode and a resonant inductor Ind are provided.
[0005]
Thus, when providing an oscillator having a frequency variable function, an active element is arranged in an oscillation circuit to obtain a low phase noise characteristic and a variable function, and a variable capacitance diode necessary for realizing a resonance state. The variable capacitance element VAR is disposed outside the package. The variable capacitance element VAR and the oscillation circuit in the package are connected to each other by a PAD, a package lead, or the like, and a resonance circuit is configured by the oscillation circuit, the resonance inductor Ind, and the variable capacitance element VAR.
[0006]
As described above, in a device having an oscillation circuit and having a resonance circuit using a variable capacitance element to change its frequency, a variable capacitance element, etc. Generally, a high-performance passive element is provided outside a package in which a semiconductor integrated circuit is arranged.
[0007]
This variable capacitance element has a higher performance as the capacitance change rate is higher, but it is common to use a change in the depletion layer range formed at the PN junction in the semiconductor layer. In other words, the variable capacitance element using the PN junction has a large capacitance when the depletion layer is narrow, and has a small capacitance when the depletion layer is extended, thereby exhibiting a change in capacitance. For this reason, a sufficient depth or width for extending the depletion layer is required.
[0008]
[Problems to be solved by the invention]
However, the conventional device shown in FIG. 9 has the following problems because variable capacitance elements such as variable capacitance diodes are arranged outside the package.
[0009]
Since the resonance circuit includes many parasitic capacitances Cpara of PAD, leads, and wires, the sum of the capacitance of the variable capacitance element and the parasitic capacitance Cpara becomes the capacitance of the entire resonance circuit. However, since the parasitic capacitance Cpara is fixed, the change range of the oscillation frequency of the entire resonance circuit is narrowed. On the other hand, when the oscillation frequency is high, for example, when a high frequency signal of 1 GHz or higher is handled, it is necessary to reduce the inductance value or the capacitance value of both or one of the resonant inductor Ind and the variable capacitance element VAR. However, even if the capacitance of the variable capacitance element is reduced, it is difficult to reduce the capacitance of the entire resonant circuit due to the presence of the large parasitic capacitance Cpara. It is becoming increasingly difficult to cope with a frequency of several GHz or higher.
[0010]
Therefore, it is preferable that at least the oscillation circuit and the resonance capacitor unit are provided on a common semiconductor substrate and incorporated in one package. That is, since a bipolar transistor is mainly used for the oscillation circuit (oscillation element), it is preferable to form the bipolar transistor and the variable capacitance element on a common semiconductor substrate. In that case, the collector layer of the bipolar transistor and the variable capacitance diode including the PN junction are formed in a substantially common semiconductor layer.
[0011]
However, in a bipolar transistor used in an oscillation circuit, the collector layer tends to be thinned with the recent progress of high frequency. Therefore, in a variable capacitance element having a P-type layer and an N-type layer in a semiconductor layer formed simultaneously with the collector layer, a sufficient depth for the depletion layer formed at the PN junction to extend in the process. Or, it is difficult to ensure the area. That is, it is difficult to reduce the capacity of the entire resonance circuit.
[0012]
An object of the present invention is to provide a semiconductor device including a variable capacitance element having a large capacitance change range and a method for manufacturing the same.
[0013]
[Means for Solving the Problems]
The semiconductor device of the present invention is a semiconductor device including a variable capacitance element, and the variable capacitance element is Provided inside the semiconductor substrate, A first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type formed on the first semiconductor layer so as to protrude from the surface of the semiconductor substrate. .
[0014]
This Formed between first and second semiconductor layers Since a depletion layer that changes in response to voltage application is formed at the PN junction, a variable capacitance element using this depletion layer as a capacitor is obtained. Since the depletion layer extends to the depth of the first semiconductor layer, the depletion layer extends more than in the case where the P-type layer and the N-type layer are provided in the first semiconductor layer. Will expand. That is, even in a shallow collector layer, the capacitance change range can be widened to cope with the progress of higher frequencies. The number of variable capacitance elements required in a certain device can be reduced by improving the performance of the variable capacitance elements (increasing the PN junction concentration). In other words, the number of variable capacitance elements provided on one semiconductor substrate can be reduced, so that the semiconductor device can be highly integrated.
[0015]
A collector layer made of a first conductivity type third semiconductor layer; a base layer made of a second conductivity type fourth semiconductor layer provided on the third semiconductor layer; and the fourth semiconductor layer. A bipolar transistor having an emitter layer of a first conductivity type provided thereon, and a collector layer made of the third semiconductor layer is provided inside the semiconductor substrate, and the fourth semiconductor layer The base layer made of is formed on the collector layer made of the third semiconductor layer so as to protrude from the surface of the semiconductor substrate. As a result, the variable capacitance element and the bipolar transistor with good high frequency characteristics can be mixedly mounted on one semiconductor substrate.
[0016]
The first semiconductor layer is a Si layer, and the second semiconductor layer is Made of SiGe or SiGeC Therefore, excellent characteristics using a heterojunction can be exhibited.
[0017]
An oscillation circuit is further provided, and the variable capacitance element is connected to the oscillation circuit, whereby a resonance circuit having an excellent frequency adjustment function can be configured.
[0018]
A manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device in which a variable capacitance element and a bipolar transistor are provided on a common semiconductor substrate, OK In the variable element formation region On the surface of the semiconductor substrate. Forming a first semiconductor layer of the first conductivity type, and On the surface of the semiconductor substrate. Of the first conductivity type Collector layer And after the step (a), the semiconductor substrate is epitaxially grown. To protrude from the surface of the On the first semiconductor layer A second conductivity type second semiconductor layer is formed in the variable capacitance element formation region, and a second conductivity type base layer is bipolar formed on the collector layer so as to protrude from the surface of the semiconductor substrate by epitaxial growth. A step (b) of forming in the transistor formation region, a step (c) of forming an emitter layer on the base layer, and have.
[0019]
With this method, a semiconductor device including a variable capacitor and a bipolar transistor on one semiconductor substrate can be formed with a small number of steps.
[0021]
In the step (b), Si _1-xy Ge _x C _y By forming the second and fourth semiconductor layers including the (0 <x <1, 0 ≦ y <1) layer, the bipolar transistor having excellent frequency characteristics and the variable capacitance element having a large capacitance change range are provided. A semiconductor device can be formed.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device including a variable capacitance element of the present invention and a manufacturing method thereof will be described with reference to the drawings.
[0023]
(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device in which a variable capacitance element (variable capacitance diode), a MIS capacitance element, and a resistance element according to the first embodiment of the present invention are provided on a common semiconductor substrate. As shown in the figure, the silicon substrate 10 is provided with a variable capacitance diode VAR, a resistance element RES, and a MIS capacitance element MIS.
[0024]
The silicon substrate 10 is formed by depositing a thin silicon oxide film 13 in a deep trench and then embedding the polysilicon 12 and a silicon oxide film 13 buried in a shallow trench. A second separation region 15 is provided. The variable capacitance element VAR, the resistance element RES, and the MIS capacitance element MIS are separated from each other by the first and second isolation regions 11 and 15, and the active region in each element is partitioned by the second isolation region 15. ing.
[0025]
Here, the variable capacitance element VAR is formed by doping arsenic (As) in the silicon substrate 10. ⁺ Layer 16 and N ⁺ A lead layer 18 formed by doping a surface portion of the layer 16 with high-concentration arsenic; ⁺ A SiGe film formed by epitaxial growth on the layer 16 and partially containing boron (B) and a P film having a thickness of 110 nm made of Si film. ⁺ Layer 21 and P ⁺ P covering layer 21 ⁺ And a P-type electrode 22 made of a titanium silicide layer thereon. P ⁺ Layer 21 is 40 nm thick undoped Si _0.85 Ge _0.15 Film and boron-doped Si with a thickness of 40 nm _0.85 Ge _0.15 A film and an undoped Si film having a thickness of 30 nm are included. N ⁺ P of layer 16 ⁺ In the variable capacitance region 16a adjacent to the layer 21, the impurity concentration in the vicinity of the surface is 1 × 10. ¹⁸ cm ^-3 And shows an impurity concentration profile in which the impurity concentration gradually decreases from the surface toward the inside of the substrate. The variable capacitance region 16 a and the extraction layer 18 are separated from each other by the second separation region 15.
[0026]
FIG. 10 shows N of the variable capacitance element of this embodiment. ⁺ It is a figure which shows the result of having actually measured the density | concentration profile in the layer 16 by SIMS. In the figure, the horizontal axis represents the depth from the upper surface of the silicon substrate. As shown in FIG. 10, N of the variable capacitance element of the present embodiment. ⁺ It can be seen that the impurity concentration in the layer 16 has a maximum value on the surface and gradually decreases from the surface toward the back.
[0027]
Resistive element RES is formed of P provided on silicon oxide film 15a embedded in a wide shallow trench. ⁺ A resistance film 23 made of a type polysilicon film is provided.
[0028]
The MIS capacitive element MIS is formed by doping arsenic (As) into the silicon substrate 10. ⁺ Layer 17 and N ⁺ N serving as a lower electrode formed by doping the surface portion of the layer 17 with high-concentration arsenic ⁺⁺ Layer 19 and N ⁺ A lead-out layer 20 formed by doping a surface portion of the layer 17 with high-concentration phosphorus (P); ⁺⁺ A capacitor insulating film 24 made of a thermal oxide film formed on the layer 19 and a P provided on the capacitor insulating film 24 ⁺ And an upper electrode 25 made of a titanium silicide layer thereon. And N ⁺⁺ The layer 19 and the extraction layer 20 are separated from each other by the second separation region 15.
[0029]
Further, an interlayer insulating film 30 covering the substrate, a barrier film 31 and a tungsten plug 32 penetrating the interlayer insulating film 30 and connected to the respective parts 22, 18, 23, 20, 25, an Al alloy film 33 and the upper layer A wiring made of an antireflection film 34 is provided. The barrier film 31 extends between the interlayer insulating film 30 and the Al alloy film 33.
[0030]
A feature of the present embodiment is that the PN junction portion, which is the capacitance portion of the variable capacitance element VAR, is not an inside of the silicon substrate 10 but is formed of an epitaxially grown SiGe film. ⁺ Layer 21 and N in silicon substrate 10 ⁺ This is a point formed over the layer 16 and the variable capacitance region 16a.
[0031]
2A and 2B are cross-sectional views schematically showing the configuration of the main parts of the conventional variable capacitor and the variable capacitor of this embodiment, respectively, in order. As shown in FIG. 2A, in the conventional variable capacitance element, P is formed in the silicon substrate. ⁺ Layer and N ⁺ A PN junction is present in the silicon substrate. The range where the depletion layer (see the broken line) extends from the region of a certain depth in the silicon substrate to N ⁺ N up to the bottom of the layer ⁺ As the thickness of the layer decreases, the region where the depletion layer extends becomes narrower, and the change range of the capacitance of the variable capacitance element becomes smaller. However, as shown in FIG. 2B, in the case of the variable capacitor according to the present embodiment, the range in which the depletion layer extends is N from the region near the surface of the silicon substrate. ⁺ Spreads to the bottom of the layer. Therefore, according to the variable capacitance element of the present embodiment, the region where the depletion layer can extend is N as compared with the case where the PN junction is present in the silicon substrate. ⁺ Since the entire depth of the layer is secured, the capacity change range is expanded. In particular, the wider the depletion layer, the larger the capacitance change range of the variable capacitance element, so that it is possible to cope with the progress of higher frequency.
[0032]
The number of variable capacitors required in a certain device can be reduced by improving the performance of the variable capacitors. In other words, the number of variable capacitance elements provided on one semiconductor substrate can be reduced, so that the semiconductor device can be highly integrated.
[0033]
Next, a method for manufacturing the semiconductor device of this embodiment will be described. FIGS. 3A to 3F and FIGS. 4A to 4E are cross-sectional views showing a manufacturing process of a semiconductor device provided with the variable capacitance element of this embodiment.
[0034]
First, in the step shown in FIG. 3A, the surface portion of the silicon substrate 10 is oxidized to form a silicon oxide film 40 having a thickness of about 500 nm.
[0035]
Next, in the step shown in FIG. 3B, the silicon oxide film 40 is patterned by photolithography and wet etching to form an implantation mask 41 having an opening in the variable capacitance formation region Rvarc. Then, after removing the resist film, arsenic ions (As ⁺ ), Implantation energy 30 keV, dose amount 1.5 × 10 ¹⁵ cm ^-2 The silicon substrate 10 is implanted under these conditions. Further, the oxidation and annealing at 1000 ° C. are continuously performed, and As is activated and diffused, thereby burying N ⁺ Layer 42 is formed.
[0036]
Next, in the step shown in FIG. 3C, after removing the implantation mask 41 and the thermal oxide film formed before annealing by wet etching, the thickness is about 0.55 μm on the upper surface of the silicon substrate 10 by epitaxial growth. The Si epitaxial layer 42 is formed. At this time, embedded N ⁺ Impurities in the layer 42 diffuse into the Si epitaxial layer 42 and enter the variable capacitance formation region Rvarc. ⁺ Layer 16 is formed.
[0037]
Next, in the step shown in FIG. 3D, after forming a mask film 44 composed of an oxide film having a thickness of about 10 nm and a nitride film having a thickness of about 200 nm, the mask film 44 is patterned to form a first film. A first mask (not shown) having an opening at a portion where the isolation region is to be formed is formed. Then, dry etching is performed using the first mask to form a trench having a depth of about 3 μm in the silicon substrate 10. Further, boron (B) is implanted into a region of the silicon substrate 10 located at the bottom of the trench to form a high concentration layer 43 for preventing the inversion layer from being formed. Oxidation forms a silicon oxide film 13. Further, polysilicon is buried in the trench to form the first isolation region 11.
[0038]
Next, in the step shown in FIG. 3E, the first mask is further patterned to form a second mask 45 having an opening in a region where a second isolation region is to be formed. Then, a shallow trench 46 having a depth of about 400 nm is formed in the silicon substrate 10 using the second mask 45.
[0039]
Next, in the step shown in FIG. 3F, a silicon oxide film is deposited and CMP is performed, and the silicon oxide film is buried in the shallow trench 46 to form the second isolation region 15.
[0040]
Next, in the step shown in FIG. 4A, after removing the second mask, a resist film (not shown) having an opening in which a lead layer or the like is to be formed is formed by photolithography, and Si epitaxial is formed. Phosphorus ions (P ⁺ ) Is implanted to form the lead layer 18 in the variable capacitance formation region Rvarc. Thereafter, annealing is performed at 950 ° C. to lower the resistance of the extraction layer 18.
Next, in the step shown in FIG. 4B, N in the variable capacitance formation region Rvarc. ⁺ Arsenic ions (As ⁺ ) With an implantation energy of 30 keV and a dose of 2.8 × 10 ¹² atoms ・ cm ^-2 The variable capacitance region 16a is formed by implanting under these conditions. Thereafter, an RTA process is performed under the conditions of 1000 ° C. and 10 seconds in order to activate As in the variable capacitance region 16a. As a result of this series of processes, an As concentration profile is formed in which the concentration gradually decreases from the substrate surface toward the inside as shown in FIG.
[0041]
Next, in the step shown in FIG. 4C, an oxide film having a thickness of about 40 nm and a polysilicon film having a thickness of 100 nm are sequentially formed and then patterned to open only above the variable capacitance region 16a. A mask 47 is formed. Then, on the upper surface of the variable capacitance region 16a, Si _0.85 Ge _0.15 P having a thickness of about 110 nm made of a film and a Si film ⁺ Layer 21 is grown epitaxially. At this time, P is caused by in-situ doping. ⁺ Part of layer 21 has a concentration of about 6 × 10 ¹⁸ cm ^-3 Of boron. P ⁺ Layer 21 is 40 nm thick undoped Si _0.85 Ge _0.15 Film and boron-doped Si with a thickness of 40 nm _0.85 Ge _0.15 A film and an undoped Si film having a thickness of 30 nm are included.
[0042]
Next, in the step shown in FIG. 4D, a polysilicon film 48 having a thickness of 100 nm is deposited on the substrate. Then, the implantation energy of boron is 8 keV, and the dose amount is 1.6 × 10. ¹⁶ cm ^-2 The polysilicon film 48 is made to have a low resistance by being implanted under these conditions.
[0043]
Next, in the step shown in FIG. 4E, the polysilicon film 48 is patterned to form P in the variable capacitance forming region Rvarc. ⁺ A P-type electrode 22 in contact with the layer 21 is formed. Further, after removing the oxide film on the P-type electrode 22 by wet etching, sputtering is performed to deposit a titanium film having a thickness of about 40 nm on the substrate. Thereafter, an RTA process for silicidation reaction is performed, and an unreacted titanium film on the oxide film is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and then a low resistance RTA process is performed to form a P-type electrode 22. A titanium silicide layer is formed.
[0044]
Subsequent steps are not shown, but the semiconductor shown in FIG. 1 can be obtained by sequentially performing commonly used steps such as an interlayer insulating film forming step, a planarization step by CMP, a contact forming step, an aluminum wiring forming step, etc. A variable capacitance element of the device is formed.
[0045]
In the present embodiment, the As implantation condition into the variable capacitance region 16a is the implantation energy of 30 keV and the dose amount of 2.8 × 10. ¹² atoms ・ cm ^-2 However, the injection conditions can be optimized according to the type and application of the variable capacitance element so that a desired capacitance change can be obtained within the voltage variable range used in the circuit.
[0046]
Further, it is preferable to optimize the boron concentration and the Ge composition ratio in the SiGe layer in order to set the leakage current of the PN junction to a desired value. Further, the mask 47 includes a polysilicon film to suppress abnormal growth during SiGe epitaxial growth. However, when the growth mode (selective growth or non-selective growth) can be easily controlled, the mask 47 is formed of polysilicon. The film may not be included.
[0047]
FIGS. 5A and 5B are diagrams showing the voltage dependence characteristics of the capacitance of the variable capacitance element in the semiconductor device formed by the method of the present invention for different impurity concentration profiles. 5A and 5B, the horizontal axis represents the voltage applied to the P-type electrode 22, and the vertical axis represents the unit capacitance (C / μm) of the variable capacitance element. ² ). Further, the characteristics shown in FIG. 5A are as follows. The ion implantation conditions for the variable capacitance region 16a are as follows: implantation energy 30 keV, dose amount 2.8 × 10 ¹² atoms ・ cm ^-2 It is a thing when. The characteristics shown in FIG. 5B are as follows. The ion implantation conditions for the variable capacitance region 16a are as follows: implantation energy 30 keV, dose amount 2.2 × 10. ¹² atoms ・ cm ^-2 It is a thing when. In the characteristic shown in FIG. 5A, the change in capacitance between 1V and 2V is about 1.9. Further, in the characteristic shown in FIG. 5B, the capacitance change between 1V and 2V is about 2.0. Thus, it can be seen that the capacitance change ratio between arbitrary voltages can be controlled by changing the dose.
[0048]
The capacitance change between 1V and 2V when the variable capacitance element was formed only by injection into the conventional Si epitaxial layer 42 (see FIG. 3C) was about 1.1.
[0049]
Further, as in the present embodiment, the P-type electrode 22 including the polysilicon film is replaced with P ⁺ By providing on the layer 21, it is possible to prevent the contact (tungsten plug 32) from being directly formed on the SiGe film, introducing defects into the thin SiGe layer, ⁺ Short-circuit defects caused by penetrating the layer 21 can be suppressed.
[0050]
In this embodiment, P ⁺ The layer is mainly composed of a SiGe film, but P is formed by using an epitaxially grown Si film instead of the SiGe film. ⁺ Even if the layer is formed, it is possible to expand the range of capacitance change by expanding the range in which the depletion layer extends. However, in particular P ⁺ By configuring the layer with a SiGe film, a higher concentration of boron can be doped. ⁺ There is an advantage that the capacity change range can be further expanded by increasing the concentration of the layer.
[0051]
(Second Embodiment)
FIG. 6 is a cross-sectional view of a semiconductor device in which a variable capacitance element (variable capacitance diode) and an NPN-HBT (heterobipolar transistor) according to the second embodiment of the present invention are provided on a common semiconductor substrate. In the first embodiment, the example of the semiconductor device provided with only the variable capacitance element has been described. On the other hand, as shown in FIG. 6, in the present embodiment, the variable capacitance element VAR is provided on the same semiconductor substrate as the NPN-HBT constituting the oscillation circuit.
[0052]
The silicon substrate 50 is formed by depositing a thin silicon oxide film 53 in a deep groove and then embedding a polysilicon 52 and a silicon oxide film 53 embedded in a shallow groove. A second separation region 55 is also provided. The variable capacitance element VAR and the NPN-HBT are separated from each other by the first and second isolation regions 51 and 55, and the active region in each element is partitioned by the second isolation region 55.
[0053]
Here, the variable capacitance element VAR is formed by doping arsenic (As) in the silicon substrate 50 and has a depth of 0.55 μm. ⁺ Layer 56 and N ⁺ A lead layer 58 formed by doping a surface portion of the layer 56 with high-concentration arsenic; ⁺ A SiGe film formed by epitaxial growth on the layer 56 and partially containing boron (B) and a P film having a thickness of 110 nm made of Si film. ⁺ Layer 61 and P ⁺ P covering layer 61 ⁺ And a P-type electrode 62 made of a titanium silicide layer thereon. P ⁺ Layer 61 is 40 nm thick undoped Si. _0.85 Ge _0.15 Film and boron-doped Si with a thickness of 40 nm _0.85 Ge _0.15 A film and an undoped Si film having a thickness of 30 nm are included. N ⁺ P of layer 56 ⁺ In the variable capacitance region 56a close to the layer 61, the impurity concentration near the surface is 1 × 10. ¹⁸ cm ^-3 And shows an impurity concentration profile in which the impurity concentration gradually decreases from the surface toward the inside of the substrate. The variable capacitance region 56 a and the extraction layer 58 are separated from each other by the second separation region 55.
[0054]
NPN-HBT is the N of variable capacitance element VAR. ⁺ Collector diffusion layer 57 formed simultaneously with layer 56 and N doped with a relatively low concentration of arsenic ^- Type collector layer 59 and N for contacting the electrode ⁺ A collector extraction layer 60 and a first deposited oxide film 70 having a collector opening 71 and a thickness of about 30 nm are provided. On the upper surface of the silicon substrate 50, the portion exposed to the collector opening 71 is A Si / SiGe layer 79 is provided in which a SiGe layer having a thickness of about 80 nm doped with a P-type impurity and a Si film having a thickness of about 30 nm are stacked. The Si / SiGe layer 79 functions as a base layer, and is formed on a portion of the silicon substrate 50 exposed to the collector opening 71 by selective growth. The Si / SiGe layer 79 has an undoped Si thickness of 40 nm. _0.85 Ge _0.15 Film and boron-doped Si with a thickness of 40 nm _0.85 Ge _0.15 A film and an undoped Si film having a thickness of 30 nm are included. And the lower part of the center part of the Si / SiGe layer 79 functions as an internal base. The upper part (mainly Si film) of the central part of the Si / SiGe layer 79 functions as an emitter layer. Further, an external base implantation region by boron ion implantation is formed over the surface portions of the Si / SiGe layer 79 and the collector diffusion layer 57, and the surface portion of the collector diffusion layer 57 is formed as a part of the external base implantation region. And the concentration is 3 × 10 ¹⁷ atoms ・ cm ^-3 A junction leak prevention layer 66 of a certain degree is formed.
[0055]
On the Si / SiGe layer 79 and the first deposited oxide film 70, a second deposited oxide film 72 for an etch stopper having a thickness of about 30 nm is provided. In the second deposited oxide film 72, A base bonding opening 74 and a base opening 78 are formed. Then, P having a thickness of about 150 nm is formed to fill the base junction opening 74 and extend onto the second deposited oxide film 72. ⁺ A polysilicon layer 75 and a third deposited oxide film 77 are provided. A portion of the Si / SiGe layer 79 excluding the region below the base opening 78 and P ⁺ An external base is constituted by the polysilicon layer 75.
[0056]
P ⁺ Of the polysilicon layer 75 and the third deposited oxide film 77, a portion of the second deposited oxide film 72 located above the base opening 78 is opened, and P ⁺ A fourth deposited oxide film 80 having a thickness of about 30 nm is formed on the side surface of the polysilicon layer 75. Further, a sidewall 81 made of polysilicon having a thickness of about 100 nm is formed on the fourth deposited oxide film 80. Is provided. N filling the base opening 78 and extending on the third deposited oxide film 77. ⁺ A polysilicon layer 82 is provided. ⁺ The polysilicon layer 82 functions as an emitter lead electrode. By the fourth deposited oxide film 80, P ⁺ Polysilicon layer 75 and N ⁺ The polysilicon layer 82 is electrically insulated. The third deposited oxide film 77 causes P ⁺ The upper surface of the polysilicon layer 75 and N ⁺ The polysilicon layer 82 is insulated.
[0057]
In addition, P ⁺ Polysilicon layer 75 and N ⁺ A titanium silicide layer is formed on each polysilicon layer 82.
[0058]
Further, an interlayer insulating film 65 covering the substrate, a barrier film 63 and a tungsten plug 64 penetrating the interlayer insulating film 65 and connected to the respective parts 62, 58, 60, 82, 75, an Al alloy film 67 and the upper layer A wiring made of an antireflection film 68 is provided. The barrier film 63 extends between the interlayer insulating film 65 and the Al alloy film 67.
[0059]
Here, also in the present embodiment, N of the variable capacitance element VAR. ⁺ The impurity concentration profile of the layer 61 is as shown in FIG. That is, it has the same impurity concentration profile as that of the first embodiment, which is the highest concentration on the surface portion of the silicon substrate 50 and gradually decreases downward. On the other hand, the collector layer 59 and the collector diffusion layer 57 in the NPN-HBT have a profile such that the surface portion of the silicon substrate 50 has a relatively low concentration and the impurity concentration gradually increases downward.
[0060]
FIG. 7 is a block diagram showing the circuit configuration of the main part of the semiconductor device of this embodiment. As shown in the figure, an oscillation circuit including an NPN-HBT, a variable capacitance element VAR, and a resonance inductor Ind are provided on a silicon substrate 50 and housed in one package. A resonance circuit is configured by the oscillation circuit, the variable capacitance element VAR, and the resonance inductor Ind. Here, the structures of the NPN-HBT and the variable capacitance element VAR are as shown in FIG. Although illustration of the structure of the resonant inductor is omitted, the resonant inductor Ind is formed of a conductor film patterned in a spiral shape, for example. Further, a parasitic capacitance Cpara of PAD exists between the oscillation circuit and the variable capacitance element VAR.
[0061]
On the silicon substrate 50, a circuit other than the resonance circuit, for example, a logic circuit including a MIS transistor may be provided.
[0062]
According to the semiconductor device of this embodiment, the following effects can be exhibited by providing the variable capacitance element VAR and the oscillation circuit (bipolar transistor) on one semiconductor substrate. In the semiconductor device of the present embodiment, since the parasitic capacitance Cpara is only the parasitic capacitance around the PAD, as compared with the conventional semiconductor device shown in FIG. 9, the variation range of the oscillation frequency is suppressed from being narrowed by the parasitic capacitance. Can do. That is, by reducing the capacitance of the variable capacitance element VAR, the resonance frequency of the resonance circuit can be increased, so that it is possible to cope with the progress of higher frequency. Therefore, the capacitance change width of the variable capacitance diode, which is a variable capacitance element, can be reduced, and the burden on device design can be reduced.
[0063]
In that case, when the variable capacitance element and the NPN-HBT are provided on the common silicon substrate 50, the variable capacitance element and the NPN-HBT are formed simultaneously with the collector diffusion layer 57 in accordance with the reduction in the depth of the collector diffusion layer 57 of the NPN-HBT as the frequency increases. N ⁺ The depth of layer 56 needs to be reduced. As a result, P of the variable capacitance element VAR ⁺ Layer 61 and N ⁺ The extending range of the depletion layer formed between the layers 56 is also narrowed.
[0064]
However, according to the semiconductor device of this embodiment, P, which is an epitaxial layer, is formed. ⁺ Layer 61 and the underlying silicon layer N ⁺ Since the PN junction is formed between the layer 56 (particularly the variable capacitance region 56a), the range in which the depletion layer can be extended in accordance with the application of voltage can be increased. In other words, the variable capacitance element VAR and the NPN-HBT are maintained while appropriately maintaining the capacitance change characteristic of the variable capacitance element VAR (variable capacitance diode) according to the higher frequency of the NPN-HBT (heterojunction bipolar transistor). It can be provided on the same semiconductor substrate. In particular, the wider the depletion layer, the smaller the capacitance of the variable capacitance element. Therefore, it is possible to cope with an increase in the frequency.
[0065]
The number of variable capacitors required in a certain device can be reduced by improving the performance of the variable capacitors. In other words, the number of variable capacitance elements provided on one semiconductor substrate can be reduced, so that the semiconductor device can be highly integrated.
[0066]
Note that the resonant inductor is not necessarily provided on the same semiconductor substrate as the oscillation circuit (NPN-HBT) and the variable capacitance element VAR. The effect can be demonstrated.
[0067]
8A to 8C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention.
[0068]
Prior to the step shown in FIG. 8A, the steps corresponding to FIG. 3A to FIG. 4B in the first embodiment are completed. Accordingly, first and second isolation regions 51 and 52 are formed in the silicon substrate 50. In the variable capacitance forming region Rvarc, N formed by doping arsenic (As). ⁺ Layer 56 and N ⁺ A lead layer 58 formed by doping high concentration arsenic is provided on the surface of the layer 56. In the HBT formation region Rhbt, N of the variable capacitance element VAR ⁺ Collector diffusion layer 57 formed simultaneously with layer 56 and N containing a relatively low concentration of arsenic ^- Type collector layer 59 and N for contacting the electrode ⁺ A collector lead layer 60 is formed.
[0069]
8A, after depositing a first deposited oxide film 70 having a thickness of 30 nm on the substrate, the first deposited oxide film 70 is patterned, and the upper portion of the variable capacitance region 56a in the variable capacitance formation region Rvarc. And a collector opening 71 is formed in the HBT formation region Rhbt. Then, on the upper surfaces of the variable capacitance region 56 a and the collector layer 59, Si _0.85 Ge _0.15 P having a thickness of about 110 nm made of a film and a Si film ⁺ The layer 61 and the Si / SiGe layer 79 are each epitaxially grown. At this time, P is caused by in-situ doping. ⁺ The layer 61 and part of the Si / SiGe layer 79 have a concentration of about 6 × 10 ¹⁸ cm ^-3 Of boron. P ⁺ The layer 61 and the Si / SiGe layer 79 are 40 nm thick undoped Si. _0.85 Ge _0.15 Film and boron-doped Si with a thickness of 40 nm _0.85 Ge _0.15 A film and an undoped Si film having a thickness of 30 nm are included.
[0070]
Next, in the step shown in FIG. 8B, a second deposited oxide film 72 having a film thickness of 30 nm serving as an etch stopper is formed on the substrate, and then the second deposited oxide film 72 is patterned by dry etching. Thus, the base bonding opening 74 is formed. At this time, the central portion of the Si / SiGe layer 79 is covered with the second deposited oxide film, and the peripheral portion of the Si / SiGe layer 79 and the first deposited oxide film 70 are formed in the base junction opening 74. Are exposed.
[0071]
Next, ion implantation of a P-type impurity such as boron (B) is performed using the resist mask used to form the base junction opening 74, and the Si / SiGe layer 79 and the collector diffusion layer 57 are formed on the surface portions. An external base implantation region is formed over the entire surface. At this time, as a part of the external base implantation region, a concentration of 3 × 10 6 is formed on the surface of the collector diffusion layer 57. ¹⁷ atoms ・ cm ^-3 A junction leak prevention layer 66 of a certain degree is formed.
[0072]
Next, 1 × 10 on the substrate by CVD. ²⁰ atoms ・ cm ^-3 Highly doped P of about 150 nm thick ⁺ A polysilicon layer 75 is deposited, and then a third deposited oxide film 77 having a thickness of about 100 nm is deposited. Next, the third deposited oxide film 77 and P are dried by dry etching. ⁺ The polysilicon layer 75 is patterned to form the third deposited oxide film 77 and P in the HBT formation region Rhbt. ⁺ A base opening 78 reaching the second deposited oxide film 72 is formed at the center of the polysilicon layer 75. The base opening 78 is smaller than the central portion of the second deposited oxide film 72, and the base opening 78 does not straddle the base bonding opening 74. By this step, an external base constituted by the P + polysilicon layer 75 and the portion excluding the central portion of the Si / SiGe layer 79 is formed.
[0073]
Next, in the step shown in FIG. 8C, a deposited oxide film having a thickness of about 30 nm and a polysilicon film having a thickness of about 150 nm are deposited on the entire surface of the wafer by CVD. Then, the deposited oxide film and the polysilicon film are etched back by anisotropic dry etching, and P ⁺ Sidewalls 81 made of polysilicon are formed on the side surfaces of the polysilicon layer 75 and the third deposited oxide film 77 with the fourth deposited oxide film 80 interposed therebetween. Next, wet etching using hydrofluoric acid or the like is performed, and the exposed portions of the second deposited oxide film 72 and the fourth deposited oxide film 80 are removed. At this time, in the base opening 78, the upper Si layer of the Si / SiGe layer 79 is exposed.
[0074]
Next, in the step shown in FIG. 8D, N having a thickness of about 250 nm is formed. ⁺ After depositing the polysilicon film, N is performed by dry etching. ⁺ By patterning the polysilicon film, an N + polysilicon layer 82 serving as an emitter lead electrode is formed in the HBT formation region Rhbt. At this time, P ⁺ The outside of the polysilicon layer 75 is not patterned.
[0075]
Next, in the step shown in FIG. 8E, the first deposited oxide film 70, the third deposited oxide film 77, P are formed by dry etching. ⁺ The polysilicon layer 75 and the second deposited oxide film 72 are patterned to determine the shape of the external base in the HBT formation region Rhbt, and the P-type electrode 62 is formed in the variable capacitance formation region Rvarc.
[0076]
Although illustration of subsequent processes is omitted, the semiconductor shown in FIG. 6 is performed by sequentially performing a titanium silicide layer forming process, an interlayer insulating film forming process, a planarization process by CMP, a contact forming process, an aluminum wiring forming process, and the like. Forming device.
[0077]
As described above, according to the manufacturing method of the present embodiment, the variable capacitance element VAR having the large capacitance change range is shared by the variable capacitance element VAR and the NPN-HBT while sharing the steps as much as possible between the variable capacitance element VAR and the NPN-HBT. It can be formed on a semiconductor substrate.
[0078]
As the variable capacitance element, P made of an epitaxial layer is used. ⁺ Layer and P ⁺ A polysilicon film is necessary. In NPN-HBT, a SiGe base layer and a P serving as an external base are used. ⁺ Since the polysilicon film is formed, the NPN-HBT and the variable capacitor can be formed on the same substrate by using the NPN-HBT process.
[0079]
In the present embodiment, P of the variable capacitor VAR ⁺ By configuring the layer 61 mainly with a SiGe film, P 1 can be obtained as in the first embodiment. ⁺ There is an advantage that the capacity change range can be expanded by increasing the concentration of the layer.
[0080]
According to the manufacturing method of the present embodiment, P of the variable capacitor VAR ⁺ The layer 61 and the Si / SiGe layer 79 that is the base layer of the NPN-HBT are formed from a common epitaxial layer, and the P-type electrode 62 of the variable capacitance element VAR and the P-base that is the external base of the NPN-HBT. ⁺ By forming the polysilicon layer 75 from a common polysilicon film, it is possible to reduce the number of processes, and to stabilize device characteristics.
[0081]
Note that P in the first and second embodiments described above. ⁺ A SiGeC film may be provided instead of the SiGe film in the layers 21 and 61.
[0082]
In addition, P of the variable capacitance element VAR ⁺ Instead of the SiGe layer that is the layer and the base layer of the NPN-HBT, a Si film may be provided. However, the use of the SiGe film can further increase the frequency of the NPN-HBT. Note that the SiGe film or the SiGeC film may be formed of a film having a gradient composition. In that case, there is an advantage that the base traveling speed in the HBT can be further increased.
[0083]
【The invention's effect】
According to the semiconductor device of the present invention, by using the epitaxially grown layer, it is possible to ensure a wide range in which the depletion layer serving as the capacitance portion of the variable capacitance element extends, and to ensure a wide capacitance change range.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device in which a variable capacitor, a MIS capacitor, and a resistor are provided on a common semiconductor substrate according to a first embodiment of the present invention.
FIGS. 2A and 2B are cross-sectional views schematically showing a configuration of a main part of a conventional variable capacitor and a variable capacitor of the present embodiment, respectively, in order.
FIGS. 3A to 3F are cross-sectional views illustrating the first half of a manufacturing process of a semiconductor device including the variable capacitor according to the first embodiment. FIGS.
FIGS. 4A to 4E are cross-sectional views illustrating the latter half of the manufacturing process of the semiconductor device including the variable capacitor according to the first embodiment. FIGS.
FIGS. 5A and 5B are diagrams showing the voltage dependence characteristics of the capacitance of a variable capacitance element in a semiconductor device formed by the method of the present invention for different impurity concentration profiles. FIGS.
FIG. 6 is a cross-sectional view of a semiconductor device in which a variable capacitor and an NPN-HBT are provided on a common semiconductor substrate according to a second embodiment of the present invention.
FIG. 7 is a block diagram illustrating a circuit configuration of a main part of a semiconductor device according to a second embodiment.
FIGS. 8A to 8C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention. FIGS.
FIG. 9 is a block diagram schematically showing a configuration of a conventional device including an oscillation circuit provided on a semiconductor substrate, an external variable capacitor, and the like.
FIG. 10 shows N of the variable capacitance element according to the first embodiment of the present invention. ⁺ It is a figure which shows the result of having actually measured the density | concentration profile in a layer by SIMS.
[Explanation of symbols]
10,50 silicon substrate
11, 51 First separation region
12,52 polysilicon
13,53 Silicon oxide film
15, 55 Second separation region
16,56 N ⁺ layer
16a, 56a Variable capacity area
17 N ⁺ layer
18, 58 drawer layer
20 Lead layer
21,61 P ⁺ layer
22,62 P-type electrode
23 Resistor film
24 Gate insulation film
25 Gate electrode
30, 65 interlayer insulation film
31, 63 Barrier film
32,64 Tungsten plug
33,67 Al alloy film
34, 68 Anti-reflective coating
57 Collector diffusion layer
59 Collector layer
60 N ⁺ Collector extraction layer
66 Junction Leakage Prevention Layer
70 First deposited oxide film
71 Collector opening
72 Second deposited oxide film
74 Base joint opening
75P ⁺ Polysilicon layer
77 Third deposited oxide film
78 Base opening
79 Si / SiGe layer
80 Fourth deposited film
81 sidewall
82 N ⁺ Polysilicon layer

Claims (4)

A semiconductor device comprising a variable capacitance element and a bipolar transistor on a silicon substrate ,
The variable capacitance element is
A first conductivity type first Si epitaxial layer formed on the silicon substrate;
An element isolation region provided on a surface portion of the first Si epitaxial layer;
An undoped SiGe film and a second conductivity type epitaxially grown on the first Si epitaxial layer so as to protrude from the substrate surface constituted by the upper surface of the first Si epitaxial layer and the upper surface of the element isolation region . Comprising a SiGe film and a Si film;
The bipolar transistor above so as to protrude from the substrate surface consisting of an upper portion of the upper and the element isolation region and the collector layer made of the first Si epitaxial layer of the first conductivity type, said first Si epitaxial layer An undoped SiGe film and a second conductivity type SiGe film epitaxially grown on the first Si epitaxial layer, a base layer made of the Si film, and a first conductivity type emitter layer provided on the base layer Preparation
A semiconductor device, wherein the first Si epitaxial layer has a thickness of 0.55 μm or less . The semiconductor device according to claim 1,
The concentration of the impurity in the region of the first conductivity type included in said first Si epitaxial layer variable capacitance element, from the substrate surface consisting of the upper surface of the upper surface and the element isolation region of the first Si epitaxial layer It has decreased gradually toward the inside,
In the area of bipolar transistors
The concentration of the first conductivity type impurity contained in the first Si epitaxial layer gradually increases from the substrate surface formed by the upper surface of the first Si epitaxial layer and the upper surface of the element isolation region toward the inside. to which, the semiconductor device. The semiconductor device according to claim 1,
A semiconductor device, wherein the undoped SiGe film or the second conductivity type SiGe film is made of SiGeC. The semiconductor device according to claim 1,
A semiconductor device further comprising an oscillation circuit, wherein the variable capacitance element is connected to the oscillation circuit.

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