JP3793214B2 - Display device and control method thereof - Google Patents

Description

  The present invention relates to a display device and a display device control method.

  In general, an information processing system (or device) uses a display device as means for realizing a visual expression function of information. As is well known, CRT display devices are widely used as such display devices.

    In the CRT display device, the display device itself does not have any display memory function, so display data at all times must be continuously supplied to the display device, and supply of display data is stopped. As a result, the display screen was not immediately displayed.

  Therefore, in the display control in the CRT display device, an image writing operation to be displayed on a video memory (hereinafter referred to as VRAM) provided in the information processing device and a display data reading operation from the VRAM are always executed. Must.

  In the case of the above-described CRT display control, writing of display data to the video memory for updating display information and reading for display are performed independently. There is an advantage that desired display data can be written at an arbitrary timing without considering any display timing.

  However, in general, since the depth of a CRT display device increases in proportion to the display area, the volume of the entire CRT display device only increases. That is, the CRT display device has disadvantages in terms of downsizing because freedom of installation location, portability, and the like is lost.

  To compensate for this, there is a liquid crystal display (hereinafter referred to as “LCD”). The LCD can be made extremely thin with respect to its display area as compared with a CRT display device. Among such LCDs, there is a display (hereinafter referred to as FLCD) using ferroelectric liquid crystal liquid crystal cells.

One of the characteristics of the FLCD is that the liquid crystal cell has display state storability with respect to application of an electric field. In other words, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC elements therein maintain their respective alignment states even when the electric field is removed. As a result, such an FLC element has bistability, and an FLCD utilizing the bistability of such an FLC element has a characteristic of storing display contents (Patent Literature). 1).
JP-A-63-243922

  When driving an FLCD, unlike a CRT or other liquid crystal display, a display image is stored and displayed, so that there is a time margin for a continuous refresh drive cycle. As a result, apart from the continuous refresh drive, so-called partial rewrite drive that updates the display state of only the changed part on the display screen becomes possible.

  On the other hand, this means that the previous information will continue to be displayed unless the display data is newly updated. For example, if the host computer is down, the previous display will continue forever. Only the display control of the display device could not cope with these situations.

  In the case of an FLCD, a binary halftone process is performed to increase the display color in a pseudo manner. As a representative example of this processing, an ED (error diffusion) method is known which achieves both image quality of a natural image and image quality of a character image. In this ED process, an error generated in a certain pixel is diffused (distributed) to neighboring pixels one after another, so that the image is required to be continuous in this process.

  In addition, when this ED method is used, it is inevitable that an error occurs with the original image. Therefore, for example, a change in image quality due to the occurrence of this error as the display color is increased becomes a problem.

  Further, a display device having a certain level of intelligence function such as an FLCD has only one specific display mode like a CRT display device, and is different from a display device that responds to a change in state only by controlling display data. However, some display devices themselves have two or more operation modes. However, in the past, it was difficult to recognize the operation mode state other than confirming the display on the display screen, whether the device was turned off or not, or the device malfunctioned, etc. The reality is that it cannot be easily recognized.

The present invention has been made in view of the above problems, and there is provided a display device and a display device capable of reliably and quickly visually confirming the current display operation state even in a display device having a plurality of operation modes. An object is to provide a control method. As one means for achieving this object, for example, the following configuration is provided. That is,
A plurality of operations including a display operation mode in which an image is displayed by line-sequential scanning driving a display device including a plurality of pixels and the line-sequential scanning driving is performed, and a power saving operation mode in which the line-sequential scanning driving is not performed. A display device comprising a mode,
Mode setting means for setting the operation mode;
Display means provided separately from the indicator for displaying the operation mode set by the mode setting means;
Display control means for displaying the display means in a mode corresponding to the operation mode.

  Further, the display device has a function of holding a display state of an image.

  Further, the display means is composed of a light emitting diode, and the display control means controls the lighting and extinguishing time of the light emitting diode corresponding to the operation mode of the device.

  Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of a display system including an apparatus (FLCD) of this embodiment. In FIG. 1, 1 controls the display device (FLCD) 3 of this embodiment via the FLCD interface 2 and a host for supplying display data to the FLCD 3, 2 designates an interface between the FLCD 3 of this embodiment and the host 1 side. It is an FLCD interface that manages, and is actually mounted in the host 1 as one interface board. The FLCD 3 is a panel controller that performs various display controls of the FLC panel 5 and displays display data from the FLC panel 5.

  Note that the FLCD interface 2 may be fixedly connected to the system, ordinarily as a card (or board) in a portion called an expansion slot provided in an information processing apparatus represented by a workstation or a personal computer. It may be connected. The host 1 and the FLCD interface 2 can be connected by the ISA interface specification, the VL interface specification, or the PCI interface specification. The FLCD 3 and the FLCD interface 2 are connected by a cable 7.

  In this system, the host 1 loads and executes an OS and applications. The screen information being executed is stored in the VRAM provided in the FLCD interface 2 and displayed on the FLCD 3. Any OS or application may be used. For example, the OS includes MS-WINDOWS (registered trademark) of Microsoft Corporation in the United States, and is an application that operates on the OS.

  FIG. 2 shows the concept of data flow related to image display in the system shown in FIG. 1 of the present embodiment.

  When the application or OS writes to the VRAM in the FLCD interface 2, the FLCD interface 2 performs binarization halftone processing (ED processing in the embodiment) and stores it in the capacity of one screen of the FLCD 3. Are written in a frame memory (4 bits for each pixel = R, G, B, I). The contents of this frame memory are transferred to the FLCD 3 and displayed.

  That is, in the general display device, the contents of the VRAM are transferred to the display device as they are, whereas in the FLCD interface 2 in this embodiment, a frame memory is interposed between the VRAM and the FLCD 3. .

  FIG. 3 shows a specific block configuration of the FLCD interface 2 in the present embodiment.

  In the figure, a CPU 300 is provided in the FLCD interface 2 and controls the entire interface. The CPU 300 operates in accordance with a program stored in the ROM 308.

  Reference numeral 301 denotes a VRAM in which 1 byte (8 bits) is assigned to each pixel of R, G, and B (total 3 bytes = 24 bits = about 16 million colors). In general, when 8 bits are given to each color element of RGB, a color image reproduced by the color element is called a full color image. The VRAM has a capacity capable of storing an image having a size of 1280 × 1024 dots (1280 × 1024 × 3≈4 Mbytes).

  Reference numeral 302 denotes an SVGA chip (accelerator) for controlling access to the VRAM 301, which can perform drawing (writing) and reading on the VRAM 301 based on commands from the host 1. Further, it has a function of drawing graphics and the like based on commands from the CPU 300 and each function described later. Note that an LSI for drawing various graphics on the VRAM 301 is widely used as a display control chip, and is itself known.

  Reference numeral 303 denotes a rewrite detection / flag generation circuit. When the SVGA chip 302 performs writing (drawing processing) to the VRAM 301, the write enable signal (actually including a chip select signal) is used as a trigger to detect a write address, It detects how many lines have been updated and holds it.

  More specifically, the rewrite detection / flag generation circuit 303 uses a write enable signal when the SVGA chip 302 writes to the VRAM 301, and latches the output address at that time in a register (not shown). To do. Then, it calculates the number of lines on the display screen from the latched address data (it can be calculated by a circuit that divides the write address by the number of bytes in one line) and corresponds to the rewritten line. Set "1" to the region flag to be used.

  In this embodiment, the number of lines of the entire screen of the FLCD 3 is 1024 (0th line to 1023th line), and each area has 32 lines as one unit, so the area flag is a total of 32 (= 1024/32) bits. is there. That is, each bit in the 32-bit flag holds whether or not writing has been made to each area of the 0th to 31st lines, the 32nd to 63rd lines, ..., 992 to 1023.

  The fact that the number of lines is used as a unit, rather than holding whether or not each line has been rewritten, generally means that when changing the display image, there is almost no rewriting of only one line, and it extends over multiple lines. This is because. Note that the number of lines allocated to one area is not limited to 32, and may be other than this. However, if the number is too small, the number of bits of the area flag increases. In addition, the number of times of partial rewrite processing, which will be described later, is increased accordingly, and the rate of occurrence of overhead increases. In addition, if the number of lines to be allocated is too large, there is a problem that there is a high possibility that an unnecessary part of the partial rewriting process increases.

  Further, although the description will be given later, the total display possible of the FLCD 3 is 1280 × 1024, but in order to be able to display with other numbers of dots (for example, 1024 × 768, 600 × 480, etc.), a rewrite line is calculated. Therefore, the information amount of one line used for the purpose is programmable. The number of display dots can be changed by instructing from the host side.

  The rewrite detection / flag generation circuit 303 described above notifies the CPU 300 of the contents of the area flag when it is detected that the area has been rewritten in units of 32 lines written in the VRAM 301. Further, as will be described later, the area flag is also cleared to zero in response to a request from the CPU 300.

  A line address generation circuit 304 receives the head address of the line instructed from the CPU 300 and the number of offset lines from the line, and outputs an address for data transfer and its control signal to the SVGA chip. . The SVGA chip 302 receives this address data and signal, and outputs image data (RGB each having 8 bits) of the number of lines designated from the corresponding line to the degamma circuit 309.

  The degamma circuit 309 includes a look-up table, and the contents can be freely changed based on an instruction from the CPU 300. Although the details of the role of the degamma circuit 309 will be described later, it is for changing the contrast of the display image in accordance with the contents set by the color adjustment switch 108 provided in the FLCD 3. The image data corrected by the degamma circuit 309 is output to the binarized halftone processing circuit 305.

  The binarized halftone processing circuit 305 converts the image data (RGB each 8 bits per pixel) sent from the SVGA chip 302 via the degamma circuit 309 into RGB and luminance signals I (each Quantize to 1 bit for a total of 4 bits). The present applicant has already proposed a technique for binarizing RGB from 8 bits for each RGB into 1 bit for each and generating a binary signal I indicating the brightness level (for example, Japanese Patent Application No. Hei 4- 126148). In addition, the binary halftone processing circuit 305 includes a buffer memory necessary for error diffusion processing in order to perform the processing.

  The binarized halftone processing circuit 305 receives an error diffusion table (parameter), which is a parameter when binarizing, an output line position and the number of lines, based on an instruction from the CPU 300, and outputs it accordingly. To do. The reason why the error diffusion table is not fixed and can be dynamically set by the CPU 300 is, for example, to be able to change the color scheme or the like based on an instruction from a CPU (not shown) on the information processing apparatus side. It is.

  A frame memory 306 stores an image to be displayed on the FLCD 3 (1-bit RGBI data per pixel). As described above, the maximum displayable size of the FLCD 3 in the embodiment is 1280 × 1024 dots, and each dot is 4 bits. Therefore, the FLCD 3 has a capacity of 1 Mbyte (in the calculation, 640 Kbytes).

  A frame memory control circuit 307 controls writing and reading of the frame memory 306 and transfer to the FLCD 3. Specifically, RGBI data output from the binarized halftone processing circuit 305 is stored in the frame memory, and an area designated by the CPU 300 is transferred to the data transfer bus 310 (in which the data bus has a 16-bit width). The data for four pixels can be sent at a time). Further, except when the image data having a certain number of lines is transferred to the FLCD 3 (that is, when the transfer of the image data instructed by the CPU 300 is completed and there is no next transfer instruction), the FLCD 3 When a data transfer request is received from the CPU 300, the CPU 300 is notified as an interrupt signal. Note that the data format when transferring to the FLCD 3 is a set of a total of 4 bits of RGBI, and the data is also stored in the frame memory 306 in this format.

  Further, even when the image data from the binarized halftone processing circuit 305 is completely stored in the frame memory, the frame memory control circuit 307 outputs an interrupt signal to that effect to the CPU 300. Further, when the transfer of the image data of the line instructed from the CPU 300 is completed (if there is an instruction to transfer a plurality of lines, the transfer of the image data of the instructed number of lines is completed), the fact is also shown. An interrupt signal is output to the CPU 300.

  There are other interrupts to the CPU 300 than the above. For example, it is a case where data is received from a serial communication line (for example, a communication line of RS-232C specification, etc.) 311 provided exclusively for communication with the FLCD 3. Details of this will be described later.

  Now, in the configuration described above, when the host 1 receives a drawing request for characters, graphics, etc. from an execution program such as an OS or an application, it outputs a command or image data for the request to the SVGA chip 302 in the FLCD interface 2. When receiving the image data, the SVGA chip 302 writes the image in the designated position of the VRAM 301 and, when receiving a drawing command such as graphic data, draws the graphic image at a corresponding position on the VRAM 301. That is, the SVGA chip 302 performs a writing process on the VRAM 301.

  The rewrite detection / flag generation circuit 303 monitors the writing of the SVGA chip 302 as described above. As a result, a flag for the written area is set and the CPU 300 is notified of it.

  The CPU 300 reads the area flag stored in the rewrite detection / flag generation circuit 303 and resets the area flag to the rewrite detection / flag generation circuit 303 to prepare for the next rewrite. Note that this reset operation may be performed using hardware means so as to be performed simultaneously with reading.

  The CPU 300 determines from the read area flag which bit is set, that is, which area (there may be a plurality of areas) has been rewritten. Then, in order to transfer the area determined to have been rewritten from the VRAM 301 to the binarized halftone processing circuit 305, the start address of the transfer start line (usually the address at the left corner of the screen) and how many lines of images from that position are displayed. Data indicating whether to transfer is output to the line address generation circuit 304.

  The point to be noted here is that when it is detected that writing has been performed to, for example, the tenth area of the VRAM 301, that is, the area of the 320 to 351 lines, the address of the first pixel on the 320th line is sent to the line address generation circuit. Instead of giving an instruction to transfer 32 lines from there, transfer is performed from the head pixel address of a line five lines before the 320th line (315th line). That is, a transfer instruction is given to the 315th to 351st lines.

  The reason is as follows. In general, when error diffusion processing is performed, a two-dimensional matrix having weighting element values (values indicating distribution ratios) is used in order to diffuse generated errors to unprocessed pixel groups. The generated error propagates one after another. Here, assuming two pixels A and B, the influence of an error that occurs when binarization processing is performed at the position of the pixel A on the position of the pixel B (unprocessed pixel) will be considered.

  In this case, the influence of the error generated in the A pixel on the B pixel becomes smaller as the distance between the AB pixels is larger. In other words, if there is a certain distance, the influence of the error from the A pixel on the B pixel position is so small that it can be ignored. The above five lines are based on this reason.

  The distance for ignoring the influence of the error is determined depending on the size of the error diffusion matrix and the weighting element value. In addition, the error diffusion processing in the binarized halftone processing circuit 305 in the present embodiment is directed from the upper left corner to the lower right corner of the image because of the above consideration.

  In addition, the CPU 300 gives an instruction indicating which part of the line data of the binarized halftone processing result is output to the binarized halftone processing circuit 305.

  That is, as described above, when data is written to the 320th line to the 351st area of the VRAM 301, the data of the 315th to 351st lines are transferred to the binarized halftone processing circuit 305. The CPU 300 instructs the binarized halftone processing circuit 305 to output data of lines 320 to 351.

  As a result, the binarized halftone processing circuit 305 outputs data of 320 to 351 lines affected by the image of the unmodified part before the 319th line to the frame memory control circuit 307.

  The frame control memory circuit 307 writes line unit data (4 bits per pixel) output from the binarized halftone processing circuit 305 to the corresponding frame memory 306 based on an instruction from the CPU 300. In other words, the CPU 300 knows the number of lines output from the binarized halftone processing circuit and the number of lines in the image and the line address to be input to the frame memory control circuit 307 ( Write start address to frame memory 306) and data indicating how many lines of data are to be continuously written are set.

  In this way, an image of only the rewritten (updated image) portion and a natural image of the joint portion with the image that has not been rewritten are written in the frame memory 306. When the frame memory control circuit 307 completes the storage of the data transferred from the binary halftone processing circuit 305 in the frame memory 306 for the area instructed by the CPU 300, the frame memory control circuit 307 generates the interrupt signal shown above. .

  By the way, the processing speed of the binarized halftone processing circuit 305 in this embodiment is about 1/30 second at the present time for one screen. This is about half of the vertical synchronization signal such as CRT which is about 60 Hz. However, rewriting of the entire screen is rare as long as a normal application is used. In other words, the number of lines processed by the binarized halftone processing circuit 305 is actually not so large, and the amount of processing is inevitably small, and the period until the processing when viewed as a whole screen is completed is the display of the CRT. If it is less than half the area, it is faster than CRT.

  The frame memory control circuit 307 also receives an output instruction to the FLCD 3 from the CPU 300, which will be described in detail later. The output instruction instructs the FLCD 3 from which line (the head address of the line) and how many lines (the number of continuous lines) are transferred. The frame memory control circuit 307 also instructs the CPU 300 even when this transfer is completed. An interrupt signal is generated to notify that. This is as described above.

Hereinafter, the data format transferred by the frame memory control circuit 307 to the FLCD 3 is:
Write line address + RGBI + RGBI + ... RGBI
It is.

  The FLCD 3 receives such data, and uses the data immediately following it for driving the FLCD 3 in accordance with the head address.

  Writing from the binary halftone processing circuit 305 may output processing results of a plurality of discontinuous areas, and the transfer instruction to the FLCD 3 to the frame memory control circuit 307 is a transfer instruction to the previous FLCD. Since it is after the completion notification is received, the image data written in the frame memory 306 does not always become image data output to the FLCD 3 immediately. That is, as described above, by processing through the frame memory 306, writing to the VRAM 301 and output to the FLCD 3 are processed completely asynchronously.

  Next, the detailed configuration of the FLCD 3 shown in FIG. 1 will be described with reference to FIGS. 4 is a diagram showing a schematic configuration of the FLCD 3 of the present embodiment, FIG. 5 is a diagram showing an overview of the FLCD 3 of the present embodiment, and FIG. 6 is a diagram showing a connection portion of the FLCD with the host side (FLCD interface side). .

  In FIG. 4, reference numeral 101 denotes an NFX controller that performs various main controls, details of which will be described later, 102 denotes a U-SEG driver for driving a signal line of a display element of the U-segment of the FLC panel 150, and 103 denotes an L of the FLC panel 150. An L-SEG driver for driving the signal lines of the display elements of the segment, and the two drivers 102 and 103 alternately drive every other segment of the display elements. Reference numeral 104 denotes a COM driver which is a driver for a common signal line of the display element of the FLC panel 150.

  The display pixels of the FLC panel 150 of this embodiment are attached when, for example, a segment drive signal which is a drive signal line in the horizontal direction of the display element and a common drive signal which is a drive signal line in the vertical direction of the matrix are driven together. Become ready. As described above, the segment drive signal is configured to be driven by the two driver circuits 102 and 103, and the U-SEG driver 102 and the L-SEG driver are alternately arranged every other segment signal line of the FLC panel. The circuit is distributedly mounted so as to be driven at 103 to equalize the amount of heat generated.

  Reference numeral 105 denotes a temperature sensor that measures the temperature of the FLC panel 150 arranged so as to be in direct contact with the FLC panel surface, 106 denotes a brightness adjustment trimmer for adjusting brightness, and 107 denotes image quality for adjusting image quality. An adjustment trimmer 108 is a color adjustment switch 108 for adjusting the color, and 109 is an LED which is a state notification means for notifying the state of the FLC panel 150. In the present embodiment, as shown in FIG.

  A switching power source 120 generates various driving power sources for the FLCD 3 of the present embodiment, and can be supplied with power from the general commercial power source 121 via a power switch 122 that controls power supply. The power switch 122 is also disposed in the lower right portion of the FLCD 3 as shown in FIG. In the present embodiment, it is configured to be operable with AC power supplies of various voltages from 85 V to 264 V (48 Hz to 62 Hz) so that it can be used in various countries around the world.

  Reference numeral 130 denotes an inverter that drives fluorescent lamps (hot cathode fluorescent lamps) 131 to 134 that irradiate the FLC panel 150 of this embodiment with light.

  In this embodiment, the FLCD 3 having the above configuration can be a display device with a very small depth because it uses an FLC panel. In this embodiment, the (host 1 and) FLCD interface 2 is connected via an interface cable 11, and the FLCD 3 is connected to a receiving connector 15 provided on the back of the display device as shown in FIG. This is done by fixing the cable-side connector 12 with a fixing screw 13. In other words, in this embodiment, the display device and the interface unit can be connected by simply connecting the single cable 11.

  FIG. 7 shows a detailed configuration of the FNX controller shown in FIG.

  In FIG. 7, reference numeral 160 denotes a system controller that can be constituted by, for example, a microcomputer. The system controller 160 manages various display controls (to be described later) of the embodiment FLCD 3 and displays received via the FLCD interface 2. Data is displayed on the FLC panel 150 via the driver controller 190. The system controller 160 includes a ROM 161 and a RAM 162, and controls various controls according to a control procedure described later stored in the ROM 161.

  The various statuses of the system controller 160 and the contents stored in the RAM 162 according to the present embodiment can be read on the host side via the FLCD interface 2, and a part can be directly written. Details of these will be described later.

  Reference numeral 171 denotes a temperature interface that converts the temperature detected by the temperature sensor 105 into a corresponding analog signal and supplies the analog signal to the system controller. Reference numeral 172 denotes an inverter 130 that controls the hot cathode fluorescent lamps 131 to 134 (backlights). A backlight controller that controls the amount of light, a VOP controller that controls the image quality of the FLC panel 150 by controlling the liquid crystal drive voltage regulator 183, and a setting value of the brightness adjustment trimmer 106 and the image quality adjustment trimmer 107 that are supplied to the system controller 160 And a trimmer interface for supplying the system controller with the normal setting of the color adjustment switch (SESW) 108.

  Reference numeral 181 denotes a power switch controller for controlling the driving power supply of the liquid crystal driving power switch 182; 182, a liquid crystal driving power switch for controlling the driving power supply to the FLC panel 150; and 183, a liquid crystal driving voltage regulator.

  Here, input / output signals with the FLCD interface 2 will be described. The BUSY signal is an image data request signal to the host side, AHDL is a scan address / image data identification signal from the host side, “H” indicates a scan address, and “L” indicates image data. PD0 to PD15 are 16-bit addressed image data, FCLK is a transfer clock of image data from the host side, SIN is serial communication data from the host side, SOUT is serial communication data from the FLCD 3 to the host side, POWERON is FLCD A power-on signal indicating that power is supplied to the interface 2, RESET is an FLCD reset signal from the host side, ENABLE is a signal specific to this embodiment, and is a connector connection signal with the FLCD interface 2, It has a negative logic configuration. When the cable 11 shown in FIG. 6 is disconnected, this signal does not become a low level, and the disconnection of the cable can be easily recognized on the FLCD 3 side. When this cable disconnection is recognized, no subsequent display data is received and the display screen is not updated. In the absence of this signal, the user cannot accurately recognize this state simply by shifting to the sleep mode, which is a power saving operation mode described later in detail with no display data. There is a possibility that the state that is not performed continues.

  However, in this embodiment, this cable disconnection can be accurately and quickly known, and the display state of the LED 109 described above is different from the power saving operation mode, so that the current state such as cable disconnection can be easily performed. Can be recognized, and the process of eliminating the problem can be executed quickly.

  FIG. 8 shows a detailed configuration of a portion related to input / output of image data in FIG.

  Input / output of image data is supplied to the FCL panel mainly by the driver controller 190 and the FLC panel 150 drivers 102 to 104 and displayed.

  The driver controller 190 has at least the following configuration. Two buffers 521 and 522 capable of storing at least one line of image data (PD0-15) from the system controller 160, an input-side switch 523 for controlling the switching of the buffers 521 and 522, and an output-side switch 524 are provided. The display image data ID0-7U / L is output to the segment drivers 102 and 103 for switching.

  Further, the timing controller 525 for generating various FLC panel 150 drive timing signals including control of these switches, the line address for displaying the display data sent from the FLCD interface 2, and the contents from the system controller 160 are stored. Is received.

  Similarly, the contents can be written from the system controller 160, the scanning address register 527 for holding the address data corresponding to the display data, and the DST register 528 to which the display start (DST) for instructing the start of display control execution from the system controller 160 is written. It is made up of. When DST is written to the DST register 528, writing operation for one scanning line of the FLC panel is started.

  Further, the U-SEG driver 102 includes a U-SEG latch circuit 531 and a U-SEG latch for fetching every other data corresponding to the U-SEG in the display data sent from the buffer (521 or 522). The U-SEG memory 532 stores latch display data in the circuit 531 according to the drive timing signal from the timing controller 525, and the driver circuit 533 drives the U-SEG signal according to the display data from the memory 532.

  The L-SEG driver 103 also includes an L-SEG latch circuit 538 and an L-SEG latch for fetching every other data corresponding to the L-SEG of the display data sent from the buffer (521 or 522). The L-SEG memory 537 stores latch display data in the circuit 538 in accordance with the drive timing signal from the timing controller 525, and the driver circuit 536 drives the L-SEG signal in accordance with the display data from the memory 537.

  The COM driver 104 also stores an address decoder 541 that stores address information from the scanning address register 527 in accordance with a timing signal from the timing controller 525, and an address memory 542 that stores contents of the address decoder 541 in accordance with a timing signal from the timing controller 525. The first half of the scan selection signal is output to the selected common signal line according to the address stored in the address decoder 541, and the second half of the scan selection signal is output to the selected common signal line according to the address stored in the address memory 542. The driver circuit 543 is configured.

  Next, FIG. 9 shows a detailed configuration of the switching power supply 120 shown in FIG.

  The switching power supply 120 first removes a noise component entering by the noise filter 123 from the power from the commercial power supply 121 received via the power switch 122, and then the switching circuit 124 including the switching regulator control circuit 126 and the transformer 126. Thus, a predetermined high-frequency signal is generated and supplied to a power supply circuit 129 for driving a backlight constituted by a 5-terminal regulator 127, a + 5V power supply circuit 128 for logic circuit, and hot cathode fluorescent lamps 131-134. The five-terminal regulator 127 is composed of four circuits 127a to 127d that generate + 35V, + 26V, + 17V, and + 9V DC power supplies with respect to the GND terminal. In addition, reference numeral 165 in FIG. 9 denotes an AFC detection circuit, which is a circuit for detecting when the power supplied to the switching power supply 120 is stopped. An output signal (AFC signal) from the AFC circuit 165 is This is an emergency interrupt signal to the system controller 160.

  The display device of this embodiment is provided with a temperature sensor 105 in the FLC panel 150 in order to always obtain good display quality regardless of environmental temperature fluctuations, and based on the detected temperature, the driving voltage and one scanning line driving time ( 1H) and an optimum value is selected for the drive waveform, and drive control of the FLC panel is performed. FIG. 10 shows a configuration of a portion related to this temperature compensation.

  In this embodiment, an analog signal corresponding to the temperature detected by the temperature sensor 105 is converted into temperature information by a digital signal by the analog-digital converter 904 through the temperature sensor interface 171. Further, an analog signal from the image quality adjustment trimmer is converted into a digital signal by the analog-digital converter 905 through the trimmer interface 174 and finely adjusted in addition to the temperature information. Based on the adjusted temperature information, a temperature compensation table is searched to obtain a Vop code for determining a drive voltage and a 1H code for determining 1H time.

  The Vop code is supplied to a digital / analog converter constituting the Vop controller 173 and converted into an analog signal DAOUT. The liquid crystal drive voltage regulator 183 generates liquid crystal drive voltages V1, V5, V3, V4, and V2 based on the analog signal DAOUT.

  The 1H code is set in a timer unit in the system controller and generates a liquid crystal driven basic clock. This basic clock is supplied to the driver controller 190, and further supplied as CSCLK to the U-SEG driver, L-SEG driver, and COM driver.

  The drive waveform is determined by the waveform setting unit 903 based on temperature information output from the analog-digital converter 904 and before being adjusted by the image quality adjustment trimmer. That is, it does not depend on the operation of the image quality adjustment trimmer by the user. The waveform determining unit 903 selects an optimal waveform from the predetermined waveform based on the temperature information and sets it as waveform data in the driver controller 190. Waveform data is supplied as SWFD0-3 to the U-SEG driver and L-SEG driver in synchronization with CSCLK, and as CWFD0-3 to the COM driver. As will be described later, the drive waveform of this embodiment constitutes 1H with the CSCLK5 clock, and the time of 1H is adjusted to the optimum value for the temperature of the FLC panel by varying the pulse width of CSCLK.

  The operation of the driver controller 190 will be described later.

  Next, transfer of display data and various control commands between the FLCD interface 2 and the FLCD 3 in the present embodiment having the above-described configuration will be described in detail below.

From the FLCD interface 2 described above,
Write line address + RGBI + RGBI ...
Are transferred via the data transfer bus 310, the head write address is stored in the reception address register, and the subsequent pixel data RGBIRGBI... Is stored in one of the buffers 521, 522. The system controller 160 reads the address of the reception address register 526 and writes it to the scanning address register 527, and then instructs the DST register 528 to start driving one scanning line. Further, the system controller 160 generates a data transfer request signal to the FLCD interface 2 at time intervals depending on the temperature obtained from the temperature sensor 105.

  Therefore, when the frame memory control circuit 307 of the FLCD interface 2 is instructed to transfer requests for 32 lines from the CPU 300, for example, every time a data transfer request from the FLCD 3 is received, the frame memory control circuit 307 outputs in line units according to the format shown above. To do. In this way, when transfer of all the specified lines is completed and the next transfer request instruction has not been received, and when a data transfer request signal is received from the FLCD 3, it notifies the CPU 300 as an interrupt signal. .

  Upon receiving this notification, the CPU 300 determines whether there is untransferred data of the partially rewritten image. If not, the CPU 300 instructs the FLCD 3 to transfer the image data of the entire screen stored in the frame memory 306 in an interlaced manner. Let That is, each time this interrupt signal is received, for example, the frame memory control circuit performs transfer line by line in the order of the first line, the third line,..., The 1023rd line, the second line,. An instruction is given to 307. Actually, when a transfer request signal is received from the FLCD 3, a line to be transferred when the next transfer request signal is received is designated. The control on the FLCD 3 side will be described later.

  As described above, the reason for interlaced transfer when there is no change in the image is as follows.

  Since the FLCD 3 used in the present embodiment has a function of storing and holding the display image as described above, theoretically, it is only necessary to transfer the image of only the changed portion. However, because it was found that there was a slight difference in brightness between an image that did not change at all and that did not refresh and an image that was changed and was newly displayed (partially rewritten). is there.

  That is, when the display image is partially updated, the FLCD 3 in this embodiment updates the display of the FLCD only with the updated portion. When there is no change to the display image, the FLCD 3 A process of transferring all the images in 306 to the FLCD 3 in an interlaced manner is performed. The reason for interlaced transfer instead of sequentially transferring each line is that the liquid crystal display generally does not respond quickly, so that the apparent display image can be updated faster.

  The operation processing procedure of the CPU 300 in the FLCD interface 2 will be described with reference to FIG.

  The meaning of each flag used below is as follows.

A) Quantization completion flag:
A flag that holds information indicating whether or not the frame memory control circuit 307 has finished storing the image data output from the binarized halftone processing circuit 305 in the frame memory 306.

B) Transfer completion flag:
A flag that holds information indicating whether or not the frame memory control circuit 307 has transferred the image at the position designated by the CPU 300 to the FLCD 3.

C) Transfer request flag:
A flag that holds information indicating whether the FLCD 3 has requested the next data transfer request. However, this transfer request flag is not set unless the frame memory control circuit 307 completes the transfer for the number of lines instructed by the CPU 300 (because the transfer request signal during this period is sent from the frame memory control circuit 307. This is because it is used for transfer timing and no interrupt signal is generated for the transfer request signal).

  Now, it is assumed that the area flag (32 bits) read from the rewrite detection / flag generation circuit 303 is as illustrated (timing T1).

  In this case, the CPU 300 can detect the area position (hereinafter referred to as “area NO”) “2” that is initially set to “1” by checking from the head. Therefore, the address and the number of lines to be set in each of the frame memory control circuit 307, the binary halftone processing circuit 305, and the line address generation circuit 304 are calculated according to this area NO, and are set in that order.

  The reason why the frame memory control circuit 307 is first used is that the operation is performed when the enable signal (see FIG. 3) of each circuit is in an enable state. This is because a higher-order circuit outputs even though it is not ready.

  When the address and the number of lines are set in the last line address generation circuit 304, the SVGA chip 302 sets the enable signal of the lower binary halftone processing circuit 305 as a trigger and starts data transfer.

  The binarization halftone processing circuit 305 generates RGBI 4-bit image data by error diffusion processing based on 8-bit RGB in accordance with this, but reaches the line (fifth line) set by the CPU 300. First, an enable signal to the lower frame memory control circuit 307 is set, and the processing result is output.

  The frame memory control circuit 307 sequentially stores the processed image data input from the binarized halftone processing circuit 305 from the address position of the frame memory 306 instructed by the CPU 300. Thus, when the frame memory control circuit 307 completes the storage process, it outputs an interrupt signal indicating the storage completion to the CPU 300. In response to this interrupt signal, the CPU 300 sets a quantization completion flag (timing T2), and instructs the frame memory control circuit 307 to transfer to the FLCD 3 (set address and number of lines).

  Further, the CPU 300 searches whether there is an area NO set other than the area NO “2” in the area flag, and if there is an area NO set other than the area NO “2”, that portion. The same processing is performed for. In the case shown in the figure, the writing is confirmed for the area NO “4”, and therefore the processing up to the storage in the frame memory 306 is also performed for the area NO “4”. When this storage process is completed (timing T3), the same process is performed for the area NO set in the subsequent area flags.

  In this process, upon receiving an interrupt from the frame memory control circuit 307 indicating that the transfer of the area NO “2” previously instructed is completed, the transfer completion flag for the area NO “2” is set to 1 (timing T4). ), It is determined whether or not there is another region NO in which the quantization completion flag is “1”. Then, if there is another area NO whose quantization completion flag is “1”, an instruction to transfer to the FLCD 3 is given.

  Note that which of timing T4 and timing T3 occurs earlier depends on the amount of data to be processed and is undefined.

  In this way, when the transfer completion notification is received and there is no more data to be transferred next, the frame memory control circuit 307 outputs an interrupt signal based on the data transfer request signal from the FLCD 3 (timing T5). In response to this, the CPU 300 performs an area flag read process of the rewrite detection / flag generation circuit 303.

  When there is no “1” bit in the read area flag at this time, the address of one line to be transferred in order to perform interlaced transfer (interlaced transfer line by line) of the frame memory 306 as described above. Set. When this transfer is completed, the frame memory control circuit 307 receives a data transfer request signal from the FLCD 3. At that time, since the transfer of one line of data has been completed, the frame memory control circuit 307 interrupts the CPU 300.

  The CPU 300 reads the area flag from the rewrite detection / flag generation circuit 303 every time this interrupt is applied, but continues the previous interlaced transfer while all the bits are “0”. Become.

  As described above, according to the present embodiment, when the area flag in FIG. 11 is read and there is any area NO in which “1” is set in one of them, the area flag is as shown in the flag table shown in the figure. Each process is performed as if the right is shifted to the right.

  Next, an example of processing of the CPU 300 for realizing the processing of the FLCD interface 2 in this embodiment will be described with reference to the flowcharts of FIGS. The following control procedures are stored in the ROM 308, for example.

  FIG. 12 is a flowchart showing a main processing routine of the CPU 300 in the FLCD interface 2 of this embodiment.

  When the FLCD interface 2 is powered on, the process proceeds to the process of FIG. First, in step S1, a series of initialization processing such as initialization of each circuit in the FLCD interface 2 is executed. At this time, the FLCD 3 also issues a command such as Unit Start and receives status information from the FLCD 3 in response thereto.

  Next, in step S2, it is determined whether or not there has been a state instruction regarding display, such as the number of display dots, via the bus 102 of the host 1 (reference numeral 6 in FIG. 1). If there is a state instruction regarding display such as the number of display dots, the process proceeds to step S3, and environmental information for each circuit 305 to 307 including the rewrite detection / flag generation circuit 303 is set to the instructed process, for example, the display dot number. set.

  On the other hand, if it is determined in step S2 that there is no instruction from the host 1, the process proceeds to step S4 to search for the current situation. In subsequent step S5, processing corresponding to the current situation is performed. For example, the display capability of the FLCD 3 is changed.

  The FLCD 3 in this embodiment has a display capacity of 1280 × 1024 dots. However, for example, when an instruction is given from the host 1 to set it to 1024 × 768, the image is displayed at the center of the display screen of the FLCD 3. Is preferable because it gives the operator a natural feeling. Therefore, in the present embodiment, in the process in step S3, a display screen changing process for realizing this is performed. For example, the rewrite detection / flag generation circuit 303 performs the above process by dividing the rewritten address by the number of bytes for one line when specifying the rewritten line position. In this case, the number of bytes for one line is determined by the number of display dots.

  At the same time, it is necessary to perform corresponding processing on the FLCD 3 side. For this reason, a command to that effect is issued from the FLCD interface 2 to the FLCD 3 via the serial communication line 311 to correspond to each other's operations.

  In the following description, a case where a display instruction of 1280 × 1024 dots is received will be described.

  When the frame memory control circuit 307 receives an instruction to transfer an image of the number of lines instructed from the CPU 300 to the FLCD 3 as described above, the frame memory control circuit 307 performs the transfer in synchronization with the data transfer request signal sent from the FLCD 3. When a transfer instruction from the FLCD 3 is not received, or when the instructed transfer is completed, when this data transfer request signal is received from the FLCD 3, it is output as an interrupt signal to the CPU 300 as it is. On the other hand, if the frame memory control circuit 307 receives a series of transfer requests and receives a data transfer request from the FLCD 3 during the transfer, the frame memory control circuit 307 does not output the signal to the CPU 300.

  Hereinafter, the processing of the CPU 300 when receiving this interrupt signal, that is, the interrupt processing after the transfer of data to be sent is completed will be described with reference to FIG. FIG. 13 is a flowchart of an interrupt routine in the CPU 300 that is activated when a data transfer request signal is received from the frame memory control circuit 307.

  When the data transfer request signal is received from the frame memory control circuit 307, first, in step S11, the area flag (32 bits) is read from the rewrite detection / flag generation circuit 303 and the rewrite detection / flag generation circuit 303 is reset. The power region flag is cleared to zero.

  Subsequently, in step S12, it is determined whether or not there is a set bit in the read area flag, that is, whether or not there is a rewritten portion. Here, if it is determined that there is no set bit and all the bits are “0”, the process proceeds to step S13 to perform processing for interlaced transfer. In other words, when no writing is detected in the VRAM 301, every time a data transfer request is received from the FLCD 3, an interlace transfer is performed (an instruction to transfer one line of data from the frame memory 306 in an interlaced manner). Will do. Then, the process ends and returns.

  On the other hand, if the set bit exists in the area read in step S12, the process proceeds to step S14 to calculate the address and the number of lines to be set in each circuit. If the bits for the areas NO10 to 12 (area of 289 to 384 lines) are set together, the addresses and the number of lines are calculated using these as one area.

  When the calculation in step S14 is completed, the process proceeds to steps S15 to S17, and information corresponding to the frame memory control circuit 307, the binary halftone processing circuit 305, and the line address generation circuit 304 is set and binarized. Halftone processing (quantization processing) is started. As described above, the line address generation circuit 304 is set to an address five lines before the first line of the rewritten area. However, when the area NO “1” is rewritten, there is no line five lines before. In this case, the address determined from the area NO is used as it is. Then, the process ends and returns.

  As a result of the above processing, the region flag is read, and the first quantization processing is started when there is a set bit in the region flag.

  FIG. 14 shows the output from the circuit 307 when the frame memory control circuit 307 receives the quantized image data from the binarized halftone processing circuit 305 and stores it in the frame memory 306. 6 is a flowchart showing processing for an interrupt signal.

  First, in step S21, it is determined whether or not the frame memory control circuit 307 is currently performing a transfer process of the partially rewritten image to the FLCD 3. If the frame memory control circuit 307 is currently transferring the partially rewritten image to the FLCD 3, the process proceeds to step S23.

  On the other hand, when the frame memory control circuit 307 is not currently transferring the partially rewritten image to the FLCD 3, that is, at that time, the interlaced transfer is being performed, and the first partially rewritten image is stored in the frame memory 306. If it is determined that the processing has been completed, the process proceeds to step S22, and the address and the number of lines are set in the frame memory control circuit 307 in order to transfer the quantized image data that has been stored. The rewritten image is transferred. Then, the process proceeds to step S23.

  In step S23, the already read area flag is checked to determine whether there is an area to be quantized next. Next, if there is no region to be quantized, the process is terminated.

  On the other hand, if it is determined in step S23 that there is an unquantized processing region, the process proceeds to step S24, where the address and the number of lines for the unquantized processing region are calculated. In steps S25 to S27, information is transmitted to each circuit. To start the next quantization process. Note that the processing from step S24 to step S27 is the same as that from step S14 to step S17 described above, and therefore detailed description thereof is omitted. Then, the process ends.

  Next, interrupt processing notified when the frame memory control circuit 307 completes transfer of the partially rewritten image instructed by the CPU 300 to the FLCD 3 will be described with reference to the flowchart of FIG.

  First, in step S31, it is determined whether there is data to be transferred next. There are two cases where there is no data to be transferred: when the image of all areas for partial rewriting has been transferred to the FLCD 3, and when the above-described quantization processing has not been completed and is waiting for it. is there. In any case, when it is determined that there is no data to be transferred, the processing is terminated.

  If it is determined in step S31 that there is data to be transferred, the process proceeds to step S32, and the transfer start line address and the number of lines are set to the frame memory control circuit 307 in order to transfer the area to the FLCD 3. To start the transfer process. Then, the process ends.

  As described above, the CPU 300 can update the display of the above-described partial rewrite portion and perform interlaced display when there is no change by performing the above processing. The core of these processes is of course the CPU 300, but the influence of the provision of the frame memory 306, that is, the part depending on the frame memory control circuit 307 is significant.

  As described above, according to the present embodiment, writing to the VRAM 301 and display updating to the FLCD 3 can be performed completely asynchronously, so that display utilizing the characteristics of the FLCD 3 to the maximum can be performed.

  In the above embodiment, when the frame memory control circuit 307 receives a transfer instruction by partial rewriting from the CPU 300, the frame memory control circuit 307 must output an interrupt signal based on the data transfer request signal from the FLCD 3 to the CPU 300 during the transfer of the partially rewritten image. However, an interrupt signal may be output regardless of the operating state.

  In this case, the CPU 300 knows the number of lines to be transferred when a partial rewrite instruction is issued. Therefore, the CPU 300 counts down every time an interrupt signal is received and checks the value to transfer the interrupt. It can be determined whether the interrupt is due to completion or an interrupt during interlace transfer.

  Further, the processing procedure of the CPU 300 in the above embodiment is an example, and the present invention is not limited thereby. In short, as described above, when the partially rewritten image is transferred to the FLCD 3, it is sufficient that the frame memory 306 is interposed to perform the asynchronous rewriting.

  Next, communication performed via the serial communication line 311 between the FLCD interface 2 and the FLCD 3 in this embodiment will be described.

  In FIG. 3, the serial communication line 311 is shown as a single line, but actually, the RS-232C specification capable of full-duplex communication is used, and the number of lines is the same as the serial interface. It shall conform to the specifications (cross interface). The data transfer bus 310 includes the data bus and the data transfer request line described above. In addition, when the power supply of the FLCD interface 2 (the power supply on the information processing apparatus side) is turned on, A signal line for transmitting one logic level signal for notifying the FLCD 3 to that effect is also included. Of course, other predetermined signals such as a transfer clock are also included.

  In addition, communication on the serial communication line 311 is performed in accordance with an asynchronous system of 9600 bps, a data bit length of 8 bits, and an even parity standard. However, these are conditions that are generally performed in the serial communication as usual, and are not specific to the present invention, and thus detailed description thereof is omitted.

  The communication described below makes it possible to use the system of this embodiment including the FLCD 3 in an optimal state. For example, even when the power of the FLCD 3 is turned on after the host side is turned on, the problem that only the image by partial rewriting is transferred and the full screen is not displayed is also solved by this. .

  In principle, this communication is performed using data in units of 1 byte. This is because the amount of data transfer and reception for both control units (CPU 300 and system controller 160) is small, and the control becomes simple.

  The serial communication protocol includes a code for the FLCD 3 from the FLCD interface 2 side (CPU 300) and a code for the FLCD interface 2 from the FLCD 3 (system controller 160). In order to avoid confusion, the former (FLCD interface 2 → FLCD3) code is called “command” or “command code”, and the latter (FLCD3 → FLCD interface 2) code is called “attention” or “attention code”.

  In addition, there is a return of a status from the FLCD 3 in response to a command from the FLCD interface 2 to the FLCD 3, and a transmission of a specific command / status using an issue of attention from the FLCD 3 to the FLCD interface 2 as an activation factor.

  FIG. 16 shows the details of the command of this embodiment and the status from the FLCD 3 corresponding thereto. In the figure, “H” in the code column of the major item “command” indicates a hexadecimal number, and “x” indicates variable 4 bits. In addition, “B” in the major item “status” indicates a binary number, and “x” indicates a variable 1 bit (different from “x” in the command).

  Hereinafter, each command and its status will be described in order.

Request Unit ID: 00H
This command is a command for inquiring the type of the connected FLCD 3.

status:
When the FLCD 3 receives this command, it adds ID information stored in the ROM 161 in the system controller 160 and sends a status in the form of 00xxxxB when normal and 01xxxxB when abnormal.

  Here, the most significant bits of the lower 6 bits indicate whether the FLCD 3 is in color display (: 0) or monochrome display (: 1), and the next upper 2 bits are the screen size (the maximum number of dots that can be displayed). Is, for example, 15 inches (: 0) or 21 inches (: 01). That is, on the FLCD interface 2 side, it is possible to know what FLCD is connected by issuing this command “00H”. Although color display is used in this embodiment, a monochrome display device can be connected to the FLCD interface 2, and such a command is prepared.

  The reason for the abnormality (at the time of error) is to cope with the case where the command is sent from the FLCD interface 2 to the FLCD 3 and is not sent normally due to the influence of noise, etc. In such a case, a status whose upper 2 bits begin with “01” is returned. Since the status at the time of error is common to each command, the attention at the time of error for the received command will be described here.

  The lower 6 bits of the status at the time of error are composed of a combination of 4 bits of type data indicating the type of error and 2 bits of content data indicating the content. The type data and content data are as follows.

Type data: Send Diagnostic error Content data:
This is an error corresponding to “Send Diagnostics (self-diagnostic result)”, a checksum error of the ROM 161 in the system controller 160, an error of the RAM 162 used as a work memory (verification error in writing and reading), an AC failure error, Includes errors during other display operations. The FLCD 3 also has a cable disconnection error, but normally communication cannot be performed in this state.

Type data: Error at reception This is an error at reception, such as parity error, overrun, undefined command, etc.

Type data: Send Host ID error Contents data:
When the “Send Host ID” command is received, an error indicating that the Host (FLCD interface 2) is determined to be an undefined ID. Type data: Set Mode error Content data “Set Mode” Impossible (indicates inability to transition to the designated mode), indicates that an undefined operation mode has been performed.

Type data: Read / Write error Contents data:
This is for the “Read / Write” command, and indicates that writing to the Read Only area, access to the Hidden area, and Address are not defined.

Type data: Set Address error Contents data:
This corresponds to the “Set Address” command and indicates that an out-of-range address has been set.

Type data: Unit Start error Contents data:
This corresponds to the “Unit Start” command, and indicates that the state is not yet ready for starting, is in the error state, and has already started.

Type data: Request Attention error Contents data:
This corresponds to the “Request Attention” command and indicates that there is no attention to be transmitted.

Type data: Request Status error Contents data:
This corresponds to the “Request Status” command and indicates that there is no status to be transmitted.

  That's it. Note that the above is an example. For example, since the type data is 4 bits, 16 types of type data can be defined in principle. Further, as described above, since the status transmitted by the FLCD 3 when an error occurs with respect to the received command is common to each command, description of the attention at the time of error for the command described below is omitted. To do.

Request 1H: 01H
As will be described in detail later, the FLCD 3 changes its operation speed (image display period for one scan) depending on the FLC panel temperature detected by the temperature sensor 105. This command is for the FLCD interface 2 to inquire the FLCD 3 about the current driving speed for one scan (1H information of the FLCD panel). As a response from the FLCD 3, as shown in FIG. 16, 1H information indicating the current one scanning drive cycle is returned with lower 6 bits.

  The FLCD interface 2 receives the response status by issuing this command, changes the interlace jump interval, and changes the rate of partial rewriting and full screen update.

  As described above, when there is no more data to be transferred to the FLCD 3, the FLCD interface 2 displays an interlaced display. For example, while a moving image or the like is displayed in a predetermined area of the FLCD 3, the display is updated. This means that the image of only the part has been updated. Therefore, when the display time of this moving image is long, a luminance difference between the image of the unchanged portion and the changed portion is generated, and this is gradually emphasized.

  Therefore, it is necessary to display an image for the entire screen at a certain interval even while partial rewriting continues. In consideration of such a point, in this embodiment, control is performed so that one screen is updated (transfers all image data in the frame memory 306) within a period of at least 1 Hz. This 1 Hz, that is, the number of frames that can be displayed in one second changes with the drive cycle of one scanning line of the FLCD 3 depending on the temperature, so it is necessary to use such a command.

  This command also affects the interlace display interval when there is no change in the screen. That is, when the temperature is not so high, the display speed of the FLCD 3 is slowed down, so that the interlaced display interval in such a case is increased to speed up the apparent update of all images. On the contrary, if the temperature allows a sufficient display speed, the interlace interval can naturally be reduced.

Unit Start: 02H
This command is for starting drawing of the connected FLCD 3 (instructing to start driving). Only after this, the FLCD 3 can display an image. The FLCD 3 only needs to output a Busy signal and respond as to whether or not the operation has started normally. Therefore, there is no operand in the normal status as shown in the figure.

Request Attention inf. : 03H
This command is used to request transmission of the detailed contents of the attention when the attention is received from the FLCD 3. In response to this, the FLCD 3 sends the lower 6 bits with a code indicating the content of the attention.

Request Attention Bit: 04H
This command is for requesting transmission of the attention status bit possessed by the FLCD 3. The attention status of the FLCD includes, for example, whether the FLCD has become Ready, whether the 1H information has been changed, whether the contrast has been changed, whether an error has occurred, etc. A status in which the data indicating the contents of is set in the lower 6 bits is transmitted.

Get Mode: 05H
This is a command for requesting transmission of the display mode of the current FLCD 3. As will be described in detail later, the display mode of the FLCD 3 includes, for example, a normal operation mode having an operation mode number 0 (a normal drawing state display mode in which an LED and a backlight are turned on and performing scanning), and a static mode having an operation mode number 1. (Mode that stops receiving image data and freezes the display image in which the LED and backlight are lit and scanning is stopped: suitable for still image viewing) Sleep mode that is operation mode number 2 (stops image display and back There is also a mode to stop driving the light: power saving, life extension effect of backlight and FLCD). The FLCD 3 returns an operation mode number indicating which display mode is currently operating as a status.

Request Status: 06H
This is a command for requesting retransmission of the status when a parity error or the like occurs in the attention sent from the FLCD 3. In response to this, the FLCD 3 again sends attention indicating the same content as that sent last time.

Attention Clear: 0AH
This command clears the attention of the FLCD 3. The FLCD only needs to notify whether or not it has been cleared normally. If it is normal, the status of all the bits “0” is transmitted.

Get Contrast Enh. : 0BH
This command is for acquiring a contrast enhancement value determined by the setting values of the brightness / image quality trimmers 106 and 107 of the FLCD 3, and the degamma circuit 309 described above according to the response (6 bits in the status) to this. Update the contents of the degamma table. Note that when the degamma table is updated, the contrast of only the partially rewritten image is changed, so that all the images in the VRAM 301 are written and binarization processing is performed on all the images. All images are transferred to the FLCD 3.

Get Multi: 0CH
The FLCD 3 in the present embodiment has three scan modes. The scan mode information set in the header portion of the image data from the FLCD interface 2 and the three scan modes specified by the Set Multi command described later. The setting in Set Multi has priority over the designation in the previous multi-scan mode.

  These three scanning modes are modes in which an input line of image data is displayed as an image of n lines (currently, n is any one of 1, 2, and 4). There are a simultaneous selection mode, a 2-simultaneous selection mode of 02H, and a 4-simultaneous selection mode of 03H. For example, in recent years, when multimedia is being avoided, the default of moving image display is at most about 300 × 200 dots, and some applications have a fixed size. In this case, since the display image becomes too small, two lines or four lines of the same image are displayed with respect to one line of the received original image.

  In this way, it is possible to display an image with no visual burden even if it is a small image as it is. In addition, for the FLCD interface 2, data on the same line is not transferred a plurality of times, so the burden is small. However, in the main scanning direction, the frame memory control circuit 307 is instructed to continuously transfer the same pixel n times. Of course, the number of repetitions in the main scanning direction may be separately designated.

  This Get Multi command is for requesting transmission of the current state of the FLCD (the current state is returned in the 6 bits of the status). The reason for providing this command is that the information processing system (for example, a personal computer) is turned off and then turned on again after setting n to “2” for the FLCD 3 with the Set Multi command described later. This is to prevent inconsistency between the image data sender and the receiver.

Send Diagnostic: 1xH
This command is for requesting the FLCD 3 to perform self-diagnosis and to transmit the result. The 4 bits indicated by “x” designate the diagnosis mode. There are several diagnosis modes, and the FLCD 3 returns a diagnosis result for the designated mode as status information.

Send Host ID: 2xH
This command is for notifying the FLCD 3 of the ID (type) of the FLCD interface 2. Of the 4 bits of “x”, 2 bits are the version of the FLCD interface 2, and the remaining 2 bits are the ID of the card of the FLCD interface 2 (also the type of information processing apparatus). When the FLCD 3 determines that the received ID is acceptable, it returns a status of all bits “0”.

Set Mode: 3xH
This command corresponds to the “Get Mode” command, and has the 4 bits “x” and instructs the FLCD 3 to set the normal mode, static mode, or sleep mode as described above. Send. When the FLCD 3 can normally shift to the mode, the status of all bits “0” is returned. The command issuance timing is, for example, when the user of the host 1 inputs an instruction to enter the mode and the FLCD interface 2 receives this instruction. In addition, when a predetermined period (this period is programmable by the user) elapses and the image no longer changes, the mode may be shifted to the static mode.

Set Multi: 4xH
This command corresponds to “Get Multi” described above, and gives an instruction to display an image of one line on the FLCD 3 as an image of 1, 2, or 4 lines. The 4 bits indicated by “x” indicate that the scan mode information set in the header portion of the image data from the FLCD interface 2 when 0, 01H is the one-line selection mode, and 02H is the two-line selection mode simultaneously. The selection mode, 03H, is a four simultaneous selection mode.

  The status normally returns all bits “0”. In this embodiment, for example, when a so-called VGA mode of horizontal 640 dots and vertical 480 dots is selected, it is detected and two lines are driven simultaneously, and 1280 dots × 960 dots of the FLCD 3 are driven. . However, since it is desired to be able to change according to the user's preference, various settings may be made by the environment setting utility program of the FLCD interface of the information processing apparatus.

  From this point on, Write High / Low Memory (8xH, 9xH) and Read High / Low Memory (08H, 09H) write data to any address in the system controller 160 (address space is 64K bytes) in the FLCD 3. Or give reading instructions. One byte of data to be written is indicated by the lower 4 bits of each of Write High / Low Memory. It should be noted that there is no operand (variable 4 bits) with respect to Read High / Low Memory.

  In any case, it is necessary to specify an address to be written or an address to be read. This address is lower than each of the illustrated Set HH / MH / ML / LL Address commands (Ax, Bx, Cx, DxH). Set with 4 bits (16 bits in total). The address is an address to be read or written. After the address is determined in this way, reading or writing is performed with a Read command or a Write command.

  In the Read command, the upper 4 bits or lower 4 bits of the contents of the byte at the specified address are returned as the status. For other commands, if it is normal, the attention of all bits “0” is returned. return it.

  The reading or writing with respect to the memory in the FLCD 3 is mainly used for debugging, but is not limited to this, and can be changed by changing the work area in the FLCD 3. It is also possible to store an operation processing program of the system controller 160 in the FLCD 3 resident in the RAM and store a program with improved functions from the host 1 on the RAM.

  The command (command code) sent from the FLCD interface 2 to the FLCD 3 and the response status to the command have been described above.

  Next, a case where the FLCD 3 spontaneously sends attention to the FLCD interface 2 will be described.

Attention by the FLCD 3 is in the following format. That is,
10xxxxxxxxB
It is. That is, the most significant bit (MSB) is set to “1”.

  The reason is that when the FLCD interface 2 sends a command to the FLCD 3 and the FLCD 3 voluntarily sends an attention to the FLCD 120, the FLCD interface 2 side does not receive a response to the sent command. This is to make it possible to determine that a spontaneous attention has been received. That is, as described above, the MSB of all response attentions for command issuance is “0”, so that determination on the FLCD interface 2 side is easy.

  The lower 6 bits of the attention from the FLCD 3 are as follows.

Bit 0: Set when FLCD becomes READY,
Bit 1: 1 Set when the 1H information is changed,
Bit 2: Set when contrast enhancement is changed,
Bit 3: Undefined Bit 4: Set when a recoverable error occurs in the FLCD,
Bit 5: Set if an unrecoverable error occurs on the FLCD,
That's it.

  Here, the recoverable error includes, for example, when it is not an attention state, when image data is not sent even after a predetermined period, and when a non-definition display mode is set. Unrecoverable errors cannot be detected due to disconnection of temperature sensor 105, cannot be detected due to short circuit, sampling timeout by A / D converter, conversion end timeout, data set timeout, ROM check error by self-diagnosis, RAM check There are errors.

  The ROM check or the like is also performed by self-diagnosis performed by an instruction from the FLCD interface. However, the error referred to here is the one when an error occurs in the initial check when the FLCD 3 described below is turned on. .

  When the FLCD interface 2 issues a command and the FLCD 3 issues a spontaneous attention, that is, when both send the first code, the attention from the FLCD 3 is processed with priority. This is because the request from the FLCD is closest to the user interface of image display.

  A specific example viewed from the FLCD interface 2 side of the communication protocol based on the above commands and attentions will be described with reference to FIGS. The FLCD 3 will be described later together.

  FIG. 17 shows a sequence in the case of acquiring the ID of the FLCD 3 from the FLCD interface 2 to the FLCD 3.

  First, the FLCD interface 2 (CPU 300) sends a Request Unit ID (00H) to the FLCD 3 via the serial communication line 311. In response to this, the FLCD 3 (system controller 160) reads information unique to the FLCD written in its own ROM 161 and returns it to the FLCD interface 2 as a status.

  In the above sequence, for example, when a communication error occurs in a command issued from the FLCD interface 2 (for example, a parity error), the FLCD 3 displays an error status to indicate that the reception has not been performed normally. return it. When the FLCD interface 2 receives this status, it again performs the process of generating the same command. Conversely, when there is a communication error in the attention from the FLCD 3, the FLCD interface 2 sends a Request Status command to prompt the status to be retransmitted.

  FIG. 18 shows a sequence when spontaneous attention is generated from the FLCD 3 (in this case, attention is generated when the contrast enhancement is changed).

  First, the FLCD 3 transmits “10000100B” indicating spontaneous attention indicating that the contrast enhancement has been changed to the FLCD interface 2 via the serial communication line 311 by the process shown in step S415 of FIG.

  Since the FLCD interface 2 can receive this attention and know that the contrast enhancement has been changed, it sends out a Request Status command (06H) for inquiring how the contrast enhancement has been changed. In response, the FLCD 3 sends binary data indicating the contrast enhancement held in step S413 to the FLCD interface 2.

  The FLCD interface 2 receives this contrast enhancement value and rewrites the degamma table in the degamma circuit 309 by referring to the ROM 308. Then, an Attention Clear command is issued to end the processing for this attention. Since the FLCD 3 knows that the de-gamma conversion based on the contrast value has been completed or has been promised to be changed, the FLCD 3 returns an attention “00000000B” to the effect that it has been accepted, and ends this processing.

FIG. 19 shows command issuance from the FLCD interface 2 (here, Set
A sequence in a case where the (Multi command) and a spontaneous attention from the FLCD 3 (here, an attention for notifying that 1H has been changed by the temperature sensor 105) are reversed are shown.

  When the FLCD interface 2 knows that the MSB of the received attention is “1”, this attention determines that the FLCD 3 has issued an attention, and postpones the processing for the previously sent Set Multi command. . Then, the Request Attention inf. A command is issued to instruct transmission of one scan driving cycle value. In response to this, the FLCD 3 sends 1H based on the temperature value from the current temperature sensor 105 to the FLCD interface 2 with reference to the temperature compensation table 901 shown in FIG. To do.

  In response to this, the FLCD interface 2 changes its own operation content as described above, issues an Attention Clear command to the FLCD 3, and receives "00000000B" from the FLCD 3, thereby receiving an attention from the FLCD 3. The process for is terminated.

  Thereafter, the FLDC 3 performs processing for the previously received Set Multi command and returns a status. The FLCD interface 2 receives 00000000B whose status is normal end, and ends the processing for the Set Multi command.

  In the above description, the protocol for some commands and attentions has been described, but the protocol for other commands or attentions also follows the same sequence. I can think of it. Therefore, the description other than this is omitted.

  Next, the operation when the FLCD 3 according to this embodiment is turned on and when the FLCD interface 2 is turned on (also turning on the information processing apparatus) will be described.

  In general, for example, even if a host side device such as a personal computer and a display device are configured integrally or separately, such a difference in configuration does not cause much problem. This is because a general display device simply displays image data output from the host device, and when the information from the host device stops, the display also stops and does not communicate with each other. Because.

  However, since the FLCD 3 of this embodiment described above has a self-memory function in the FLCD panel 150 and the display device also has a certain level of intelligence, it is necessary to grasp and process each other's state. In this embodiment, the problem is solved as follows.

  The data transfer bus 310 includes one signal line indicating whether the power of the FLCD interface 2 is turned on. By using this signal line, the following control is possible.

Case 1. When the power of the FLCD interface 2 is turned on first and then the power of the FLCD 3 is turned on. In this case, the FLCD 3 is in the initial processing stage when the power is turned on, and the POWERON signal in the data transfer bus 310 is set to L. Therefore, it is possible to know that the power of the FLCD interface 2 is turned on. When this is detected and the initialization process of the FLCD interface 2 is completed, the attention (10000001B = FLCD3 is in the ready state) Is sent to the FLCD interface 2.

  Upon receiving this attention, the FLCD interface 2 recognizes that the FLCD 3 is ready to operate, issues an Attention Clear command, waits for the reception of the attention “00000000B” from the FLCD 3, and then sends a unit start. As a result, a BUSY signal is sent to the FLCD 3 to display the image.

  Actually, when the FLCD 3 is turned on, for example, the FLCD interface 2 issues a command for sending a contrast value of 1H in order to obtain a contrast value when the power is turned on, and a 1H value to be described later. , Process to acquire each information.

Case 2. When the FLCD 3 is turned on first and the FLCD interface 2 is turned on later (for example, when the power of the FLCD 3 as a display device is forgotten while the host 1 is turned off) etc)
In this case, when the initialization process of the FLCD interface 2 is completed, the FLCD interface 2 waits for the POWERON signal to be set to L by the FLCD interface, and issues a Unit Start command. In response to this, the FLCD 3 can resume its own operation.

  Although the description will be omitted, the operation processing of the system controller 160 in the FLCD 3 will be described below. In the following description, a case where a chip configuration computer (MPU) is used as the main of the system controller 160 will be described as an example.

  FIG. 20 is a flowchart showing the basic processing at the start of operation after power-on of the FLCD 3 or in the reset state in this case.

  When the power switch 122 is turned on and the apparatus is turned on, the process proceeds to the process shown in FIG. 20. First, in step S41, the initial initialization process of the system controller 160 is performed, and an interrupt is set. Subsequently, in step S42, a self-diagnosis routine is executed by the system controller 160, and it is determined whether or not its own operation is normal. In step S43, if the AFC signal from the AFC circuit 165 is not output as a result of diagnosis of the AFC signal and ENABLE signal in the self-diagnosis routine in step S42, and the ENABLE signal is low when the cable 11 is disconnected. It is determined whether or not it is a level. If the cable is not properly connected or if the voltage drops again due to the input of the switching power supply 120 or some other cause, the process returns to step S41, and the subsequent display control of the FLC panel 150 is not performed. Thereby, display control is performed carelessly, and it is possible to effectively prevent display other than desired.

  On the other hand, if the cable 11 is connected in step S43, the ENABLE signal is low level, the switching power supply 120 is normal, and the AFC signal is output, the process proceeds to step S44, where the system controller 160 Initialization process 2 is performed, and resource settings and the like are performed. In step S45, the driver controller 190 is initialized. Subsequently, in step S46, a power ON wait process is executed, and then the operation selection process in step S47 is performed.

  Further, in the present embodiment apparatus, the processing of FIG. 20 is not executed only when the power is turned on, but is also executed when an interrupt is generated after the interrupt is set.

  That is, when the ACF detection circuit 165 detects that the power supply to the switching power supply has been stopped for some reason and an AFC signal is output, when a reset signal is received from the FLCD interface 2, and ENABLE Even when the signal is turned off, processing such as initialization is executed.

  When the AFC detection circuit 165 detects an abnormality in the power supply and outputs an AFC signal, an AFC detection interrupt process S50 indicated by AFC detection is executed. When the interruption process is started, all other interruptions are prohibited in step S51. In step S52, the power OFF routine is executed. Thereafter, in step S53, the 15V power supply is turned off and the LED display 109 is turned off. Then, the initialization process from step S41 is executed.

  On the other hand, when the apparatus according to the present embodiment is in a reset state, a reset interrupt process S55 is executed. When the interruption process is started, first, all other interruptions are prohibited in step S56. In subsequent step S57, the power OFF sequence is executed. Thereafter, in step S53, the 15V power supply is turned off and the LED display 109 is turned off. Then, the initialization process from step S41 is executed.

  Further, when the cable 11 between the apparatus of this embodiment shown in FIG. 6 and the FLCD interface 2 is disconnected from the connector 15 for some reason, or when the cable 11 is disconnected halfway, the ENABLE signal is It is reset and does not go low. In this case, cable disconnection interrupt processing S58 indicated by ENABLE signal OFF is executed. When the interrupt process is started, all other interrupts are prohibited in step S59. Then, the process proceeds to step S57 described above, and a power OFF sequence is executed. Thereafter, in step S53, the 15V power supply is turned off and the LED display 109 is turned off. Then, the initialization process from step S41 is executed.

  Next, the details of the self-diagnosis routine shown in step S42 of FIG. 20 will be described with reference to FIG.

  First, in step S61, signal check processing for checking the ENABLE signal and the AFC signal from the AFC circuit 165 is performed. In step S62, the ROM 161 is checked. Subsequently, the check process of the RAM 162 in step S63 is executed, and the process returns.

  Details of the signal check processing in step S61 are shown in FIG.

  First, in step S65, it is checked whether the AFC signal is at a high level and the AFC signal is not output (the power supply is normal). If the AFC signal is not output, the process proceeds to step S66, for example, an AC fail bit of an error status that can be read in the FLCD interface 2 is set, and the process returns.

  On the other hand, if the AFC signal is output, the process proceeds from step S65 to step S67, and it is checked whether the ENABLE signal is at a low level and the cable is correctly connected. If the ENABLE signal is at a low level and the cable is correctly connected, the process is terminated and the process returns.

  On the other hand, if the ENABLE signal is not at a low level and the cable is not properly connected, the process proceeds from step S67 to step S68, where, for example, a cable disconnection bit of an error status that can be read in the FLCD interface 2 is set and the process returns.

  FIG. 23 shows details of the check process of the ROM 161 in step S62 in FIG. In the ROM check process, all data in the ROM area is added in units of words, and a 16-bit unsigned integer that ignores overflow is compared with a pre-calculated value (checksum = xxxxh) to confirm that they match. Perform the process.

  First, in step S71, sum, which is a register for storing the addition result, is cleared. Subsequently, in step S72, the ROM start address is stored in an address register holding an address value for ROM check. In step S73, the contents written from the address specified by the ROM address register are read out and added to the contents of the register sum. At this time, the addition result is a 16-bit unsigned integer ignoring overflow.

  In step S74, the value of the address register is updated so as to designate the next address of the ROM. In step S75, it is checked whether or not the updated address value exceeds the ROM end address, that is, whether or not the processing for the entire area of the ROM has been completed. If the processing for all the areas has not been completed, the process returns to step S73, and the content of the next word updated in step S74 is read and added with the content of the register sum.

  On the other hand, if the processing for all the areas of the ROM is completed in step S75, the process proceeds from step S75 to step S76, and the addition result of the register sum is compared with a pre-calculated value (checksum = xxxxh). When the addition result of the register sum matches the value calculated in advance (checksum = xxxxh), the ROM is returned as normal and the process returns.

  Here, if the addition result of the register sum is different from the pre-calculated value (checksum = xxxxh), it is a ROM error, and an error bit as an unrecoverable error is set in step S77 and returned. To do. Thereafter, for example, an unrecoverable error action is issued to the above-described FLCD interface 2 to perform a process of shifting to the silent mode in the operation mode.

  Next, details of the check process of the RAM 162 in step S63 of FIG. 21 are shown in FIGS. In the RAM check process, after data is written in the RAM area in units of words, this data is read and it is confirmed that the written data matches. The data to be written is, for example, (00h) and (FFh). At the time of writing, the data stored in the address to be written is temporarily saved in a register, and is returned to the RAM again when the check for the address is completed.

  In this embodiment, a plurality of register groups are allocated in the RAM. This register group is referred to as register bank 0, register bank 1,. First, in order to check the area from the top of the RAM to the register bank 1, the register is set to 1 in the register bank in step S81. In step S82, (00h) as pattern data to be written is registered as a pattern 0 in the patn0 register, and (FFh) as a pattern to be subsequently written is registered as a pattern 1 in the patn1 register. In step S83, a RAM start address, which is the first RAM address, is set in the address register.

  Since the RAM check is now ready, in step S84, the contents of the RAM address designated by the address register are read out and stored in the save register. In step S85, the contents of the patn0 register are written to the RAM address specified by the address register, and the written contents are read out and stored in the patn register. In step S86, the contents of patn read out are compared with the contents of the written patn0 register.

  If a RAM error occurs and the contents of both registers differ, the process proceeds to step S101 in FIG. 25, and the contents saved in the save register are written to the RAM address indicated by the address register. In step S102, the error status RAM error bit is set and the process returns. Thereafter, for example, an unrecoverable error action is issued to the above-described FLCD interface 2 to perform a process of shifting to the silent mode in the operation mode.

  On the other hand, if the contents of patn read in step S86 match the contents of the written patn0 register, the process proceeds to step S87, and then the contents of the patn1 register are written to the RAM address specified by the address register. Subsequently, the written contents are read out and stored in the patn register. In step S88, the contents of patn read out are compared with the contents of the written patn1 register. If a RAM error occurs and the contents of both registers are different, the process proceeds to step S101.

  On the other hand, if the contents of patn read in step S88 and the contents of the written patn1 register match, the process proceeds to step S89, and is indicated by the address register of the RAM saved in the save register in step S84. Restore the contents of the address. In subsequent step S90, the address register is incremented to be the RAM address to be checked next. Then, in step S91, all the areas up to the register bank 1 are checked, and it is checked whether or not the contents of the address register are equal to or greater than the address of the register bank 1. If the address is up to register bank 1, the process returns to step S84, and the check for the next address is continued.

  On the other hand, when the check for the area up to the register bank 1 is completed and the content of the address register is equal to or greater than the address of the register bank 1, the process proceeds to step S92 shown in FIG.

  In step S92, in order to perform a RAM check from the register bank 1 area to the end of the RAM, the register is set to 0 in the register bank, and write pattern 0 and pattern 1 are set in the register again. In step S93, the contents of the RAM address designated by the address register are read out and stored in the save register. In step S94, the contents of the patn0 register are written to the RAM address designated by the address register, and the written contents are read out and stored in the patn register. In step S95, the contents of patn read out are compared with the contents of the written patn0 register. If a RAM error occurs and the contents of both registers are different, the process proceeds to step S101.

  On the other hand, if the contents of patn read in step S95 match the contents of the written patn0 register, the process proceeds to step S96, and then the contents of the patn1 register are written to the RAM address specified by the address register. Subsequently, the written contents are read out and stored in the patn register. Then, in step S97, the read patn content is compared with the written patn1 register content. If a RAM error occurs and the contents of both registers are different, the process proceeds to step S101.

  On the other hand, if the contents of patn read in step S97 and the contents of the written patn1 register match, the process proceeds to step S98, and is indicated by the RAM address register saved in the save register in step S93. Restore the contents of the address. In subsequent step S99, the address register is incremented to be a RAM address to be checked next. In step S100, all the RAM area checks are completed, and it is checked whether or not the contents of the address register are equal to or higher than the final address of the RAM. If it is equal to or less than the final address, the process returns to step S93, and the check for the next address is continued.

  On the other hand, if the check for the RAM area is completed and the content of the address register is equal to or greater than the final address of the RAM, the process is terminated and the process returns.

   Next, the power ON wait process in step S46 of FIG. 20 will be described with reference to FIG.

  First, in step S111, the power switch controller 181 is instructed to turn on the 15V power source that is the LED power source. Subsequently, after waiting for 16 ms, the LED 109 is turned on in step S112. After waiting for another 16 ms, an AFC interrupt to the system controller 160 is permitted in step S113. Next, in step S114, if the RESET signal from the FLCD interface 2 side is reset at this time and is not at the H level, it waits for it to become the H level.

  In step S115, it is confirmed that the POWERON signal indicating that the power supply on the FLCD interface 2 side is turned on is set. Here, if the POWERON signal is not set, it waits for the power supply on the FLCD interface side to be turned on. If the host-side power supply is turned on and the POWERON signal is set, the process proceeds to step S116, and the FLC control portion shown in FIG. 9 of the system controller 160 is initialized (stopped).

  In step S117, internal variables are initialized. Specifically, the status (errstat) indicating the error state is cleared to 0, and then the display mode control (dispmode) is set to notstarted, which is a mode in which no display is performed. Also, the scan mode is set to x1 scan mode (x1 mode), a dummy address is set to the immediately preceding scan address (preadd), and the ON / OFF flag (timer) of the timer unit 902 is set to OFF. Then, initialization processing is performed to control the FLC control unit so as not to display the FLCD panel 150 by turning off the FLC control unit.

  Next, in step S118, it is checked whether or not an error status is set by the above self-diagnosis routine or the like. If the error status is not set, the process proceeds to step S119, and the power ON sequence is executed. In the following step S120, the operation of the FLC control unit stopped in step S116 is enabled, the SCSW is turned on, the trimmer interface 174 is activated, and a drive signal based on the set value of the image quality adjustment trimmer 107 and the detected value of the temperature sensor 105 is generated. Control. In step S121, unit ready tension is issued to the FLCD interface 2 side via the serial interface 11, and the process returns.

  On the other hand, if the error status is set in step S118, the process proceeds to step S122, and a self-diagnosis error attention issuance process is executed via the serial interface 11 on the FLCD interface 2 side. In step S123, errstat indicating an error state is set as an error. Next, in step S124, the LED 109 in the non-recoverable mode, which will be described later, is set to a blink mode in which the LED 109 is turned on and off at an early cycle, and the LED 109 is blinked at an early cycle. Thereby, it can be easily visually confirmed that the FLCD 3 is in an error occurrence state. Then, the process proceeds to the power ON sequence in step S119.

  Next, the power ON sequence routine of step S119 in FIG. 26 will be described with reference to FIG.

  First, in step S130, the VOP controller 173 is reset. In step S131, the color switch routine is executed, and in step S132, (S / CCR) is set to the high level. In step S133, a temperature compensation routine is executed. In step S134, it is checked whether a return code (end code) as a result of the temperature compensation routine processing is zero. If the return code is not 0, the process proceeds to step S139, where (ffff) H is set as the return code, and the process returns.

  On the other hand, if the return code is 0 in step S134, the process proceeds to step S135, and the VEESW signal for energizing the output channel power supply (VEE) of each driver circuit is turned ON. The VOP controller 173 is instructed to turn on the output channel power supply of each driver circuit. After waiting for 16 ms, the DRVSW signal is turned ON in step S136 and the output of the liquid crystal drive voltage regulator is turned on. In step S137, the BLSW signal is turned ON, and the backlight controller 172 is instructed to turn on the backlight power. Then, 0 is set as a return code and the process returns.

  FIG. 28 shows a timing chart of signals in the result of a series of operations when the FLCD 3 described above is powered on. In the serial communication shown in FIG. 1, the unit ready attention is issued and the Clear attention command is returned from the FLCD shown in FIG. 26, and then the FLCD 2 is shifted to the normal display mode after the backlight is turned on. Then, the process proceeds to the transmission of the unit start command and the transmission of the status shown in 4.

  Next, the operation selection process after step S47 shown in FIG. 20 following the power ON will be described with reference to FIGS.

  In the operation selection process, first, a work register initialization process is executed in step S140. The work register 0 (rw0) is the user trimmer monitoring timing drawing line number counter (link) value, the work register 1 (rw1) is the display operation set by dispmode, and the error state is errstat. 2 (rw2) is sent to the scan mode (scannode) added to the image data header, work register 3 (rw3) is sent to the immediately preceding scan address (readed), and work register 4 (rw4) is sent to the status and attention. At this time, in addition to the transmission data, the transmission priority order, the holding operation information after the transmission, and the transmission image including the attention information must be set in the attention, and the buffer of the transmission data buffer for buffering the transmission image, etc. Pointer ( The uffpointer), initializes 5 is set to ON / OFF flag of the timer unit 902 (timer) respectively a (rw5) the work register.

  Subsequently, in step S141, it is checked whether the power of the FLCD interface 2 is turned on and the POWERON signal from the FLCD interface 2 is at a high level. If the POWERON signal is at a high level, the process proceeds to step S142, where rw1 is checked to see if the operation mode is NORMAL, which is the normal operation mode. If the operation mode is not the normal operation mode (NORMAL), the process proceeds to step S176.

  On the other hand, if rw1 is NORMAL and the operation mode is the normal operation mode, the process proceeds to step S143 to check rw5. rw5 indicates whether or not the timer unit 902 is in operation. If rw5 is ON, it indicates that the timer unit 902 is in operation. If the timer unit 902 is not in operation, the process proceeds to step S144, the timer is restarted, rw5 is turned on, and the process proceeds to step S145 in FIG.

  On the other hand, if rw5 is ON and the timer unit 902 is operating in step S143, the process proceeds to step S145 in FIG. In step S145, it is checked whether rw0, which is a drawing line number counter (link) for user trimmer monitoring timing, is zero. If rw0 is not 0, the normal drawing process of step S146 is executed. In step S147, rw0, which is the user trimmer monitoring timing drawing line number counter (link), is decremented by 1, and 0 is stored in the timeout retry counter (ahdiret). In subsequent step S148, it is checked whether or not it is Attention Time Out. If it is not Attention Time Out, the process proceeds to step S149. Then, it is checked whether there is data received from the FLCD interface 2 or not. If there is no reception data, the process proceeds to step S150 to check whether there is transmission data to the FLCD interface 2 or not. If there is no transmission data, the process returns to step S141, and the normal drawing process described above is performed.

  In the above state, if transmission data is generated in step S150, the process proceeds from step S150 to step S151 and subsequent steps, and transmission mode processing is executed. First, in step S151, post-processing of Phase Overdrive is performed to stop driving of the FLCD panel 150. In subsequent step S152, transmission buffer data transmission processing is performed. Thereafter, the value of this buffer address pointer is set in rw4 to enable the buffer to be read again and used, and rw5 is turned off to reset the ON / OFF flag of the timer unit 902. Then, the process returns to step S141.

  On the other hand, if there is received data in step S149, the process proceeds from step S149 to step S155, and post-processing of Phase Overdrive is performed to stop driving of the FLCD panel 150. In step S156, the SC reception processing routine is executed to receive data from the FLCD interface 2.

  Thereafter, in step S157, the data added to the image data header portion received by SC reception is set in the work register area of the RAM 162. That is, the display operation mode (dispmode) and error state (errstat) of rw1 are set, the buffer pointer (buffpointer) of the transmission data buffer of (rw4) is updated, and the ON / OFF flag (timer) of the timer unit 902 of rw5 Is set to OFF, and a mask 1 (scmodmsk1) for extracting the scanning mode from the header portion of the image data is set in rw6. If it is c0000H, it follows the image data header part, and if it is 0000H, it is specified by communication. In addition, a mask 2 (scmodmsk2) for extracting the scanning mode from the header portion of the image data is set in rw7. If it is 00000H, the image data header part or x1 is designated. If it is 4000H, x2 is designated. If it is 8000H, x4 is designated. According to specification by communication. Then, the process returns to step S141.

  Further, in the case of an attention timeout in step S148, the process proceeds from step S148 to step S160, where post-processing of Phase Overdrive is performed to stop driving of the FLCD panel 150. In a subsequent step S161, a flag (attntmoutflg) indicating an attention timeout is set (ON). Next, in step S162, the LED 109 is set to a blinking mode that blinks at an early cycle of the non-recoverable mode. As a result, the operator can easily visually check that the device is in an error state only by looking at the LED display on the display device.

  In step S163, errstat indicating an error state is set as an error, the display operation mode (dispmode) and error state (errstat) of rw1 are set, and the ON / OFF flag (timer) of the timer unit 902 of rw5 is set to OFF. Return to S141.

  On the other hand, if the drawing line number counter for user trimmer monitoring timing of rw0 is 0 in step S145, the process proceeds to step S165, and post-processing of Phase Overdrive is performed to stop driving of the FLCD panel 150. In step S166, a temperature compensation routine is executed, and in step S167, a color adjustment switch routine is executed.

  After that, in step S168, 0 (rw0) of the work register is set to the drawing line number counter (linc) value for user trimmer monitoring timing, 1 (rw1) of the work register is set to the display operation set by dispmode, and the error state is set to errstat. Then, the work register 4 (rw4) is set to the buffer pointer (buffpointer) of the transmission data buffer, the ON / OFF flag (timer) of the timer unit 902 of the work register 5 (rw5) is set to OFF, and the process returns to step S141. .

  If the POWERON signal is not at the high level in the determination in step S141 in FIG. 29, the power supply on the FLCD interface 2 side is not turned on, so the process proceeds to step S170, and after waiting for 64 μs, again in step S171. It is checked whether the POWERON signal is at a high level. Again, if the POWERON signal is not at a high level, the power OFF sequence is executed in step S172, and the process proceeds to the power-on processing from step S41 in FIG.

  On the other hand, if the POWERON signal is at a high level in step S171, the process proceeds from step S171 to step S173 to check whether rw5 is ON (timer unit 902 is operating). If the timer unit is not operating, the process returns to step S141.

  On the other hand, if the timer unit 902 is operating in step S173, the process proceeds to step S174, and panel drive stop processing is performed to stop driving of the FLCD panel 150. Then, in step S175, the work register 4 (rw4) is set to the buffer pointer (buffpointer) of the transmission data buffer, and the ON / OFF flag (timer) of the timer unit 902 of the work register 5 (rw5) is set to OFF. Return to.

  Further, if the normal operation mode is not determined in the determination of the display operation mode in step S142, the process proceeds from step S142 to step S176, and the setting of 1 (rw1) of the work register is changed to the normal operation mode in the display device of this embodiment. It is determined whether it is a static operation mode (static) that is two other possible display operation modes, or a sleep operation mode (sleep) that is a low power consumption mode. If it is not in any mode, the process proceeds to step S180.

  On the other hand, if the mode is one of the modes, the process advances from step S176 to step S177 to check the brightness adjustment trimmer 106 and the image quality adjustment trimmer 107 which are user trimmers. Then, a color switch routine according to the setting of the color adjustment switch 108 is executed.

  Thereafter, in step S179, rw1 is set to display mode set by dispmode, the error state is set to errstat, work register 4 (rw4) is set to the buffer pointer (buffpointer) of the transmission data buffer, and the process proceeds to step S180.

  In step S180, similarly to step S176, the setting of 1 (rw1) of the work register is the static operation mode (static) which is the other two display operation modes that can be changed as the normal operation mode in the display device of this embodiment. Alternatively, it is determined whether or not the sleep operation mode (sleep) which is the low power consumption mode. If it is not in any mode, the process proceeds to step S182.

  On the other hand, if it is any mode, the process proceeds from step S180 to step S181, and the process proceeds to step S182 as a blinking display in which the LED 109 blinks in a short cycle.

  In step S182, the process waits for about 1H and then proceeds to step S183. In step S183, it is checked whether or not it is Attention Time Out. If it is not Attention Time Out, the process proceeds to step S184. Then, it is checked whether there is data received from the FLCD interface 2 or not. If there is no reception data, the process proceeds to step S185 to check whether there is transmission data to the FLCD interface 2. If there is no transmission data, the process returns to step S141, and the normal drawing process described above is performed.

  In the above state, if transmission data to be transmitted is generated in step S185, the process proceeds from step S185 to step S186, and the data in the transmission buffer is transmitted to the FLCD interface 2 via the serial communication line. In step S187, the value of this buffer address pointer is set in rw4 so that the next buffer storage data can be read and used. Then, the process returns to step S141.

  On the other hand, if there is received data in step S184, the process proceeds from step S184 to step S190, and the SC reception processing routine is executed to receive data from the FLCD interface 2. Thereafter, in step S191, the data added to the image data header portion received by SC reception is set in the work register area of the RAM 162. That is, the display operation mode (dispmode) of rw1 is set, the buffer pointer (buffpointer) of the transmission data buffer of (rw4) is updated, and the mask 1 (smodmodsk1) that extracts the scanning mode from the header portion of the image data is set to rw6. set. If it is c0000H, it follows the image data header part. If it is 0000H, it is specified by communication. Also, a mask 2 (scmodmsk2) for extracting the scanning mode from the header portion of the image data is set in rw7. If it is 00000H, the image data header part or x1 is designated. If it is 4000H, x2 is designated. If it is 8000H, x4 is designated. According to specification by communication. Then, the process returns to step S141.

  Further, in the case of an attention timeout in step S183, the process proceeds from step S183 to step S195, and a flag (attntmoutflg) indicating the attention timeout is set (ON). In step S196, the LED 109 is set to a blinking mode that blinks at an early cycle. As a result, the operator can easily visually check that the device is in an error state only by looking at the LED display on the display device.

  In step S197, errstat indicating an error state is set as an error, the display operation mode (dispmode) and error state (errstat) of rw1 are set, and the ON / OFF flag (timer) of the timer unit 902 of rw5 is set to OFF. Return to S141.

  The display mode in the above description will be described. The FLCD 3 of this embodiment has three display modes in the normal operation state. As shown in FIG. 32, the normal operation display mode (Normal) and the still image are displayed. There are three display modes that are optimal for a static display mode (Static), a sleep mode (Sleep) in a low power consumption state in which the display screen of the FLCD 3 is completely black erased, and the backlight is also turned off. In addition, there is a display mode when an unrecoverable error occurs. In this case, the screen display maintains the state immediately before the unrecoverable error occurs. In order to make it possible to determine the state of each operation mode, the LED 109 is also controlled to blink. In the sleep mode, as described above, the LED blinks at intervals of 1 second, and in the case of an unrecoverable error, faster blinking is performed. It is blinking at 0.5 second intervals.

  In the present embodiment, as described above, the lighting state of the LED is distinguished in each operation state, so that what has been far from the display device for a while can know the current state of the display device only by looking at the lighting state of this LED. be able to. As a result, it is not mistaken for a power-off state in spite of the operation in the sleep mode, and it is possible to easily know whether or not an unrecoverable error has occurred, thereby preventing erroneous operation and taking appropriate measures. Is also possible.

  Details of the normal drawing process shown in FIG. 30 will be described below. Prior to the description of this process, the image data display position of the FLCD panel 150 in this embodiment will be described. The image data display position of the FLCD panel 150 forms one pixel with four colors of RGBW, and the pixel data is also represented by four colors D0 to D3. For example, the display panel of this embodiment has 1280 pixels × In the case of 1024 lines, as shown in FIG. 33, the segment data is composed of 5119 in total for one common scan line address A0 to A11.

  Then, the FLCD interface 2 on the host side sets the BUSY signal to negative and sets it to not busy. Receiving this, the FLCD interface 2 sets AHDL to the high level and simultaneously sends a 12-bit scan address to the image data buses PD0 to PD15 in synchronization with FCLK for one clock. Therefore, the NFX controller 101 of the FLCD 3 receives this in accordance with the one-line writing period (1H) of the FLCD 3, and sets BUSY to the high level again.

  A timing chart during this period is shown in FIG.

  Furthermore, FIG. 35 shows an actual data format sent from the FLCD interface 2 in accordance with the timing chart shown in FIG. As shown in FIG. 35, display data from D0 to D15 to D5104 to D5119 are sequentially sent in synchronization with the FCLK signal using PD0 to PD15.

Here, the display mode is also sent as described above simultaneously with the scan address when AHDL is at the high level. The transfer procedure in this case is shown in FIG. As shown in FIG. 36, the scan address is 12 bits, and the upper 4 bits have room, so that the scan mode can be instructed by the most significant 2 bits using this. That is, if the most significant 2 bits are (00), the scanning mode is x1, if it is (01), the scanning mode is x2, and if it is (10), the scanning mode is x4.
This scanning mode is always set in the header portion sent prior to the image data. When a scan mode different from the scan mode data sent immediately before is received, the previous scan mode is changed to the received scan mode. However, when the scan mode is specified by the SetMulti command by serial communication, the scan mode specified by the command is given priority.

  Details of reception of display data sent from the FLCD interface 2 and drawing processing on the FLCD panel 150 as described above (normal drawing processing shown in FIG. 30) will be described below with reference to FIGS. .

  In the normal drawing process in step S146 of FIG. 30, first, in step S201, SDI is sent out, one of the buffers 521 and 522 shown in FIG. In step S202, the interrupt factor register is cleared. Thereafter, in step S203, the BUSY signal, which is an image data request signal for the FLCD interface 2, is set to be negative and not busy.

  When the FLCD 3 sets the BUSY signal to be negative and is not busy, the FLCD interface 2 sequentially sets image data with scanning addresses to the image data buses PD0 to PD15 in synchronization with FCLK at the same time as setting the AHDL to the high level. . When the driver controller 190 receives the scan address, the driver controller 190 stores it in the reception address register 526 and sends an IREQ signal. Therefore, in step S204, it is checked whether or not the scan address has been received. Investigate. If it has not been received yet, it is checked in step S205 whether an AHDL signal has timed out without receiving an AHDL signal. If no time-out has occurred, the process returns to steps S204 and 205 described above.

  If the driver controller 190 receives a scan address, the process proceeds from step S204 to step S206, and the BUSY signal is set to the high level in accordance with the one-line writing period (1H) of the FLCD 3. In subsequent step S207, scan code mask processing is performed to extract only the upper two bits of the scan code of the received scan address shown in FIG. 36, and the scan mode code is determined below.

  First, in step S208, it is checked whether or not the mode change instruction specifies a mode different from the previous mode. If it is not MODE change, it progresses to step S209, and a scan address is investigated and it is investigated whether it is an address range. If it is an address range instruction, the process proceeds to step S210 to check whether the addresses are the same. If it is not the same address, the process proceeds to step S211 in FIG.

  After step S211, normal address drawing processing is performed. First, the scan address received in step S211 is read from the reception address register 526 of the driver controller 190 and stored in the scan address register 527 again. Subsequently, the address value read in step S212 is stored in rw3 as the previous scan address value (preadd). In step S213, the CPU waits for a compare interrupt bit of the timer unit 902 (until the drive start timing of a new scan address). The transferred image data is stored in one of two buffers 521 and 522.

  Thereafter, 1H is started in step S214, and the FLCD panel 150 is driven and the display data is rewritten by the COM driver 104 and the segment drivers 102 and 103 with the configuration shown in FIG. In step S215, the timer unit 902 is cleared, and in the next step S216, after the 1H operation on the driver controller 190 side is performed, it waits for the LATHD signal sent from the driver controller to become high level. Then return.

  The driver controller 190 sends each driver based on the information set in the scan address register 527. This is started when the system controller 160 writes to the DST register 528. When writing to the DST register 528 is performed, transmission of a driver control signal is started as a new 1H period in synchronization with TOUT0 output from the timer unit 902, and simultaneously stored in the buffer 521 or 522 which is a 1H delay buffer. The image data is divided and transferred to the U-SEG driver 102 and the L-SEG driver 103. Details of the 1H control will be described later.

  As a result, normal address drawing is performed, and display update control of the line sent on the FLCD side is performed.

  On the other hand, if it is determined in step S210 that the address range is the same address, the process proceeds from step S210 to step S220, and the received address value is stored in rw3 as the previous scan address value (preadd). In step S221, a dummy address is set in the scan address (CSADS) register 527. In step S222, the timer unit 902 waits for a compare interrupt bit (until the drive start timing of the immediately preceding scan address).

  Thereafter, in step S223, data is written to the DST register 528 to start 1H, and the drive of the FLCD panel 150 and the display data rewrite control are performed by the COM driver 104 and the segment drivers 102 and 103 with the configuration shown in FIG. In step S224, the timer unit 902 is cleared. In the next step S225, after the 1H operation on the driver controller 190 side is performed, it waits for the LATHD signal to become high level.

  When the LATHD signal becomes high level, the scan address value (preadd) just set to rw3 in step S226 is stored in the scan address (CSADS) register 529. In step S227, the CPU waits for the compare interrupt bit of the timer unit 902 (until the next scan address driving start timing). Thereafter, 1H is started in step S228. In step S229, the timer unit 902 is cleared, and in the next step S230, after the 1H operation on the driver controller 190 side is performed, it waits for the LATHD signal to become high level.

  When the LATHD signal becomes high level, the process proceeds to step S231, where SDI is sent and segment data transfer is started, and scanning of the next line is started from the FLCD panel 150. Then, in the following steps S232 to S236, processing similar to that in steps S221 to S225 described above is performed, and then in step S237, a dummy address is set in rw3, and this is set as the immediately preceding scan address value (preadd). Then return.

  Thereby, repeated display control of the same address becomes possible.

  Furthermore, if the change of the scan mode is instructed in the determination of step S208, the process proceeds from step S208 to step S240, and the received scan mode value is stored in rw2. In step S241, a dummy address is set in the scan address (CSADS) register 527. In step S242, the timer waits for the compare interrupt bit of the timer unit 902 (until the dummy address drive start timing comes).

  Thereafter, in step S243, writing to the DST register 528 is started to start 1H, and the drive of the FLCD panel 150 and the display data rewrite control are performed by the COM driver 104 and the segment drivers 102 and 103 with the configuration shown in FIG. Then, in step S244, the process waits for the DACT signal to become low level, and proceeds to step S245, where rw5 is set to OFF and the timer is stopped.

  Subsequently, 4 bits excluding the common scan address shown in FIG. 36 of the received data masked in step S246 are checked to check whether the lower 2 bits of the scan code portion are 0 or not. If the lower 2 bits are 0, the process proceeds to step S247, where the scan mode is set to the scan code designated here, and the scan mode is designated. Then, the scan address (CSADS) register 527 of the driver controller 190 is updated and the process returns.

  On the other hand, if the lower 2 bits of the scan code portion are not 0 in step S246, the process proceeds to step S249. In this case, since it is considered that the designation of the scan mode is incorrect, a recoverable error attention (scan error attention) is selected and transmitted to the FLCD interface 2 in step S250. In subsequent step S251, the current scan mode is set in rw2, the buffer pointer is updated, stored in rw4, and the process returns. Thereafter, the process shifts to normal drawing processing in the normal display mode.

  Further, if the scan address is not in the address range in step S209, the process proceeds to step S260, and the dummy address is set in the scan address (CSADS) register 527. In step S261, the timer unit 902 waits for a compare interrupt bit (until the dummy address drive start timing comes). Thereafter, in step S262, data is written to the DST register 528 to start 1H, and the drive of the FLCD panel 150 and the display data rewrite control by the COM driver 104 and the segment drivers 102 and 103 are performed with the configuration shown in FIG. In step S263, the process waits for the DACT signal to become a low level, and then proceeds to step S264, where rw5 is set to OFF and the timer is stopped.

  In step S265, an attention outside the address range is selected. In step S266, the same attention is checked. In step S267, it is checked whether there is the same attention. here. If there is the same attention, the process returns to the normal scan stop mode.

  On the other hand, if there is no same attention in step S267, the process proceeds to step S268, where an attention outside the selected address range is transmitted, and the buffer pointer of rw4 is updated. Then, the process returns as described above.

  In the loop processing of steps S204 and 205 described above, if the AHDL signal from the FLCD interface 2 has timed out without going high, the process proceeds from step S205 to step S270 in FIG. 42, and the BUSY signal is set to low level. In a subsequent step S271, a dummy address is set in the scan address (CSADS) register 527. In step S272, the CPU waits for the compare interrupt bit of the timer unit 902 (until the dummy address driving start timing comes).

  After that, in step S273, the DST register 528 is written to start 1H, and the FLCD panel 150 is driven by the COM driver 104 and the segment drivers 102 and 103 and the display data is rewritten with the configuration shown in FIG. Then, in step S274, the process waits for the DACT signal to become low level and proceeds to step S275, where rw5 is set to OFF and the timer is stopped.

  In step S276, it is checked whether or not the AHDL timeout retry counter (ahdlretry) is zero. If 0, the process proceeds to step S277, where recoverable error attention (AHDL timeout attention) is selected, and is transmitted to the FLCD interface 2 in step S278. Then, the process proceeds to step S280.

  In step S280, the AHDL time-out retry counter (ahdlretry) is incremented, the work register 1 (rw1) is set to display operation set by dispmode, and the error state is set to errstat, and the work register 3 (rw3) Is updated to the buffer address of 4 (rw4) of the work register. Then, the process returns to the normal scan stop mode.

  If the AHDL timeout retry counter (ahdlretry) is not 0 in step S276, the process advances to step S279 to check whether the AHDL timeout retry counter (ahdlretry) is 40 or less. If the AHDL timeout retry counter (ahdlretry) is 40 or less, the process advances to step S280.

  On the other hand, if the retry counter (ahdlretry) of the AHDL timeout is not less than 40 in step S279, the process proceeds to step S281 and a recoverable attention is selected. In step S282, it is checked whether or not there is the same attention. here. If there is no same attention, the process proceeds to step S283, and an unrecoverable attention is selected. In step S284, this is transmitted.

  In step S287, an AHDL error is set in the error status. In step S288, the LED 109 blinks at a short cycle (0.5 second interval), and the process proceeds to step S280.

  On the other hand, if there is the same attention in step S282, the process proceeds to step S285, where an unrecoverable attention is selected, and the transmission buffer is replaced without transmitting this attention in step S286. Then, the process proceeds to step S287.

  The timeout period of AHDL in the above is specifically 25 ms after the BUSY signal is raised. When this time elapses, the BUSY signal is output, and after issuing a recoverable error attention, the BUSY signal is reset again. Therefore, the reception of the AHDL signal again is monitored. When an AHDL signal is received, a Clear attention is issued and thereafter the normal operation is performed. This state transition is shown in FIG.

  Further, after the AHDL timeout occurs and a recoverable error attention is issued, when this retry reaches a specified number of times (40 times), the mode shifts to a silent mode in which the FLCD panel 150 is not scanned. Then, a Clear attention is issued, and then an unrecoverable attention is issued. This state transition is shown in FIG.

  Further, even if the attention is cleared, BUSY is maintained at a low level until AHDL is received, and it is treated that a new AHDL timeout has occurred when 25 ms elapses. The state transition at this time is shown in FIG.

  As described above, the display data is exchanged by the FLCD 3 side, and it is possible to improve the display image quality by correcting the scanning timing according to the temperature of the FLCD panel described below.

  Hereinafter, the correction control of the scanning timing according to the detected temperature in the FLCD panel 150 in the present embodiment will be described. An example of drive waveforms by the segment drivers 102 and 103 and the COM driver 104 in this embodiment is shown in FIG. This waveform is a waveform defined by CWFD0-3 and SWFD0-3 from the driver controller 190 shown in FIG. 10, and this waveform depends on the 1H code output from the temperature compensation table and the clock timing generated by the timer unit 902. One period is determined, and the peak value is determined by the output voltages V1, V5, V2, V3, V4, and VC of the liquid crystal drive voltage regulator 183.

  An example of the FLCD panel drive waveform of this embodiment is shown in FIG. The scan selection signal in the figure shows the drive signal waveform of the COM driver 104, and the information signal shows the drive waveform of the SEG drivers 102 and 103. The relationship between Vopcode and FLCD panel drive voltage is as shown below.

DAOUT = VopCode × 5.0 / 256
V1-VC = VC-V2 = 3.49 × DAOUT
= 0.0681 x VopCode [V]
V5-VC = 1.58 x DAOUT
= 0.0309 x VopCode [V]
V3-VC = VC-V4 = 1.44 × DAOUT
= 0.0282 x VopCode [V]
The relationship between 1HCode and 1H is
1H = (CSCLK period) × 5 × (1HCode + 1) × 0.4 × 5
[Μsec].

  Compensation of the temperature characteristics for the driving conditions of the FLCD panel that generates the above driving waveform is based on the temperature signal in the vicinity of the FLCD panel 150 detected by the temperature sensor 105 and the driving voltage (Vop) applied to the panel and the driving cycle ( 1H). Then, the temperature signal is finely adjusted by the image quality adjustment trimmer 107 in order to absorb all variations of the electrical system and variations of the FLCD panel characteristics.

  Note that the drive waveform voltage is configured such that the voltage value changes vertically symmetrically with a temperature change around Vc. This compensation is performed by the configuration shown in FIG.

  Examples of the temperature compensation table 901 shown in FIG. 10 are shown in FIGS. FIG. 48 shows the output 1H time and the Vop drive voltage output value with respect to the input AD value from the analog-digital conversion circuits 904 and 905 input to the temperature compensation table 901. The temperature increases as the AD value decreases. When the AD value is 0, the temperature is approximately 60 ° C., and when the AD value is approximately 175, the temperature is approximately 5 ° C. In this embodiment, the temperature is designed not to rise above 60 ° C., and the table is provided with compensation data up to 60 ° C.

  FIG. 49 shows an example of the frame frequency at the start of each environmental temperature and at the time when the internal temperature is saturated after a sufficient time has elapsed from the start.

  Here, the frame frequency is the reciprocal of the time during which 1024 scanning lines in this embodiment are rewritten.

  Next, specific control of temperature compensation outlined above will be described below with reference to FIGS. In this embodiment, the user trimmer monitoring interval is every 100 ms that does not depend on 1H, and the process is terminated when the value of the user trimmer does not change with respect to the immediately preceding value, and when there is a change, the temperature compensation is performed. I do. Even when there is no change in the user trimmer, temperature compensation is performed every 30 seconds.

  This temperature compensation routine is the process of step S133 or step S166 described above. In this embodiment, the analog adjustment signal Vu input to the system controller from the image quality adjustment trimmer 107 via the trimmer interface 174 needs to be converted into a corresponding digital signal (UVR) by the analog-digital converter 905 and fetched. First, in step S301, the analog-digital converter 905 is designated as an input target.

  In step S302, the analog-digital converter 905 is activated. In subsequent step S303, it is checked whether the return code is 0 or not. This is because, when the analog-digital converter 905 is activated in step S302, analog-digital conversion is performed within a predetermined time, and an interruption to the effect of completion of conversion is made. At this time, analog-digital conversion is completed. The return code is 0, and if it is not 0, a timeout of analog-digital conversion has occurred. For this reason, when the return code is not 0 in step S303, the process proceeds to an analog-digital conversion timeout process in step S345 and subsequent steps shown in FIG.

  On the other hand, when the return code is 0 in step S303, the process proceeds to step S304, and the conversion result of the analog-digital converter 905 is set in the uvr register holding the user trimmer AD value. In step S305, the temperature compensation timing counter (compc) is decremented by one. In step S306, it is checked whether the temperature compensation timing counter (compc) is zero. If the temperature compensation timing counter (compc) is not 0, the process proceeds to step S307, where the user trimmer AD value set and read in step S304 is compared with the previous user trimmer AD value stored in uvrprev. Check if is equal. If the two values are equal, the adjustment by the user has not been performed, and the process proceeds to step S310 in FIG.

In step S310, the user trimmer monitoring interval of 100 ms is divided by 1H, the result is stored in the user trimmer monitoring timing drawing counter (linc), and the process proceeds to step S311.
Then, the AHDL timeout counter value is set, 0 is set in the return code, and the process is terminated.

  On the other hand, if the temperature compensation timing counter (compc) is 0 in step S306, or if the user trimmer AD value read in step S307 is different from the previous user trimmer AD value, the process proceeds to step S315. In step S315, the uvr register value holding the user trimmer AD value is stored in uvrprev. In step S316, in order to read the detected temperature from the temperature sensor 105, the analog-digital converter 904 is designated as an input target.

  In step S317, the analog-digital converter 904 is activated. In subsequent step S320, it is checked whether the return code is 0 or not. If the return code is not 0 in step S320, the process proceeds to an analog-digital conversion timeout process in step S345 and subsequent steps shown in FIG.

  On the other hand, if the return code is 0 in step S320, the process proceeds to step S321, and it is checked whether or not the detected temperature near the panel is equal to or higher than a predetermined upper limit value of temperature. If it is equal to or higher than the upper limit value, the routine proceeds to a temperature upper limit routine (comp tmpperr) shown in FIG.

  In step S322, if the detected temperature near the panel is equal to or lower than the upper limit value of the predetermined temperature, the process proceeds to step S323 to check whether the detected temperature near the panel is equal to or lower than the lower limit value of the predetermined temperature. . If it is equal to or lower than the lower limit value, the routine proceeds to a temperature lower limit routine (comp tmpperr) shown in FIG.

  Further, in step S323, if the detected temperature near the panel is equal to or higher than the lower limit value of the predetermined temperature, the process proceeds to step S325 shown in FIG. In step S325, it is checked whether the detected temperature near the panel is equal to or higher than a predetermined boundary temperature. If the detected temperature in the vicinity of the panel is not equal to or higher than the predetermined boundary temperature, the process proceeds to step S326, and it is checked whether or not the detected temperature range is a high temperature range. If the detected temperature region is a high temperature region, the process proceeds to step S330.

  On the other hand, if the detected temperature region is not the high temperature region, the process proceeds from step S326 to step S327, and the waveform change routine is executed. Subsequently, in step S328, the boundary temperature for the high temperature region is set as a new boundary temperature. In step S329, the temperature compensation table for the high temperature region is selected. Then, the process proceeds to step S330. In step S330, the uvr register value holding the user trimmer AD value is registered as a new measured temperature, the AD value of the temperature sensor 105 and the image quality adjustment trimmer adjustment value are added and stored in advance, and the process proceeds to step S335 in FIG. .

  On the other hand, if the temperature in the vicinity of the panel detected in step S325 is equal to or higher than the predetermined boundary temperature, the process proceeds to step S331, and it is checked whether or not the detected temperature range is a low temperature range. If the detected temperature region is the low temperature region, the process proceeds to step S330.

  On the other hand, if the detected temperature region is not the low temperature region, the process proceeds from step S331 to step S332, and a waveform change routine is executed. In this routine, the drive condition is set with reference to the waveform data table in the temperature compensation table corresponding to the detected temperature, the waveform is determined, the waveform can be changed according to the temperature, and the return code is set to 0 It is. Subsequently, in step S333, the low temperature region boundary temperature is set as a new boundary temperature. In subsequent step S329, the temperature compensation table for the low temperature region is selected. Then, the process proceeds to step S330.

  Further, when the process proceeds from step S330 to step S335, the 1HCode table for the timer unit 902 of the temperature compensation table is read according to the value of the value storing the AD value of the temperature sensor 105 to which the image quality adjustment trimmer adjustment value is added in step S335, and the system Set to the clk register in the controller 160. In step S336, this is set in a 16-bit timer (not shown). In step S337, the clk register is incremented and output as 1HCode (hcode) to be set in the timer register 902.

  In step S338, the VopCode table for the driver controller 190 of the temperature compensation table is read according to the value of the value storing the AD value of the temperature sensor 105 to which the image quality adjustment trimmer adjustment value is added. Subsequently, the VopCode read in step S339 is set in the digital / analog converter of the Vop controller 173.

  In step S339-2, 300 is set in the temperature compensation timing counter (compc), and the flow advances to step S340.

  In the next step S340, the value of advance storing the AD value of the temperature sensor 105 to which the image quality adjustment trimmer adjustment value has been added is set as hcode (a code for notifying the host of 1H) as a code table. In subsequent step S341, it is checked whether this data is the same as the previous value. If it is the same as the previous value, the process proceeds to step S310.

  On the other hand, if hcode is not the same as the previous value in step S341, the process proceeds to step S342, and 1H code change attention is selected. In step S343, the attention is transmitted from the FLCD interface 2. Then, the process proceeds to step S310.

  52, if the detected temperature of the temperature sensor 105 is equal to or higher than the predetermined upper limit value in step S322 of FIG. 52, the process proceeds to step S360 shown in FIG. 56, and analog-digital conversion is performed in order to read the detected temperature from the temperature sensor 105. The device 904 is designated as an input target. In step S361, the analog-digital converter 904 is activated. In subsequent step S362, it is checked whether the return code is 0 or not. If the return code is not 0 in step S362, the process proceeds to an analog-digital conversion time-out process in step S345 and subsequent steps shown in FIG.

  On the other hand, if the return code is 0 in step S362, the process proceeds to step S363, and it is checked whether the detected temperature of the temperature sensor 105 is equal to or higher than a predetermined upper limit as a result of reading again. If not, the process proceeds to step S321 in FIG.

  On the other hand, if the detected temperature is equal to or higher than the predetermined upper limit value in step S363, it is determined that the thermistor that is the temperature sensor is disconnected, and the process proceeds to step S364, where the error state is set in errstat indicating the error state, and then continues. In step S365, the thermistor disconnection error bit of the self-diagnosis result code diagnosis is set. In step S366, the thermistor disconnection error attention is selected. In step S377, the attention is transmitted to the FLCD interface 2. In step S388, the LED 109 is set to a short-period blanking state indicating an error state, the process is terminated, and the process returns.

  52, if the detected temperature of the temperature sensor 105 is equal to or lower than a predetermined lower limit value in step S323 of FIG. 52, the process proceeds to step S390 shown in FIG. The device 904 is designated as an input target. In step S391, the analog-digital converter 904 is activated. In subsequent step S392, it is checked whether or not the return code is 0. If the return code is not 0 in step S392, the process proceeds to an analog-digital conversion timeout process in step S345 and subsequent steps shown in FIG.

  On the other hand, if the return code is 0 in step S392, the process proceeds to step S393, and it is checked whether the detected temperature of the temperature sensor 105 is equal to or lower than a predetermined lower limit as a result of reading again. If it is not less than the lower limit, the process proceeds to step S321 in FIG.

  On the other hand, if the detected temperature is equal to or lower than the predetermined lower limit value in step S393, it is determined that the thermistor, which is a temperature sensor, is short-circuited, and the process proceeds to step S394, where an error state is set in errstat indicating an error state and continues. In step S395, the thermistor short-circuit error bit of the self-diagnosis result code diagnosis is set. In step S396, the thermistor short-circuit error attention is selected. In step S397, the attention is transmitted to the FLCD interface 2. In step S398, the LED 109 is set to a short-period blanking state indicating an error state, the process is terminated, and the process returns.

  Further, when the return code is not 0 in each of the above steps, it is determined that the analog-digital conversion has timed out, and the process proceeds to step S345 shown in FIG. In step S345, the error state is set in errstat indicating the error state, and in the subsequent step S346, the AD conversion error bit of the self-diagnosis result code diagnosis is set. In step S347, AD conversion error attention is selected.

  In step S348, the attention is transmitted to the FLCD interface 2. In step S349, the LED 109 is set to a short-period blanking state indicating an error state. In step S350, the return code is set to ffffH, the process ends, and the process returns.

  As described above, in the present embodiment, the user trimmer monitoring interval is every 100 ms, and if the value of the user trimmer does not change with respect to the immediately preceding value, the temperature compensation routine is terminated, and when there is a change. Performs temperature compensation. Even when there is no change in the user trimmer, temperature compensation is performed every 30 seconds.

  Next, the panel stop process of FIG. 29 will be described with reference to FIG. Here, the driver controller 190 and the COM driver 104 are post-processed to stop driving the FLCD panel 150.

  First, in step S401, SDI is sent to start segment data transfer, and scanning of the next line is started from the FLCD panel 150. Then, the line buffer is changed. In step S402, a dummy address is set in the scan address (CSADS) register 527. Next, in step S403, the timer unit 902 waits for a compare interrupt bit (until the scanning address driving start timing comes).

  In step S404, data is written to the DST register 528 to start 1H, and the FLCD panel 150 is driven by the COM driver 104 and the segment drivers 102 and 103 and the display data is rewritten with the configuration shown in FIG. In step S405, the process waits for the DACT signal to go low. If the DACT signal goes low, the timer unit 902 is cleared in step S406 and the process returns.

  Next, details of step S131 of FIG. 27 and other color switch routines will be described below with reference to FIG.

  First, in step S410, the trimmer interface 174 is activated to take in a gray code (GrayCode) that is a set value of the color adjustment switch (contrast enhancement switch) 108 for performing color adjustment, that is, the value of the contrast enhancement switch (value). In step S411, it is checked whether or not this value is equal to the value of the immediately previous contrast enhancement switch. If it is equal to the previous value, the process ends and returns.

  On the other hand, if it is not equal to the value of the immediately previous contrast enhancement switch (value), the process proceeds from step S411 to step S412 to perform a gray-binary conversion process on the read value to convert the gray code into a corresponding binary code. This value is set as a new contrast enhancement value (cecode). In step S414, the CE code change attention is selected, and this is transmitted to the FLCD interface 2 and the process returns.

  As described above, the setting value of the color adjustment switch 108 (the value of the contrast enhancement switch (CESW)) can be sent from the FLCD 3 to the FLCD interface 2. The detailed configuration of the color adjustment switch 108 in the FLCD 3 is shown in FIG. 60, and the relationship with the value of the contrast enhancement switch is shown in FIG.

  As shown in FIG. 60, in this embodiment, the color adjustment switch 108 is a three-circuit switch, which generates an 8-position gray code according to the ON / OFF state of each switch, and pull-up resistor Rp of the trimmer interface 174. Thus, the switch circuit is configured to output a high level when the switch circuit is open and a low level when the switch circuit is closed. The state of each signal is as shown in FIG. 61. Position 0 is 16 gradations, which is the basic specification of the FLCD panel 150 with the smallest gradation, and the gradation is raised below, and at position 7, the level is approximately 32K. It is the structure which instructs the key.

  Upon receiving the CESW gray code, the system controller 160 converts the gray code shown in FIG. 61 into a binary code in step S413 and sends it to the FLCD interface 2 in step S415. Details of this transmission processing are as shown in detail in FIG.

  The FLCD interface 2 that has received the switch value rewrites the degamma table in the degamma circuit 309 configured by a lookup table by referring to the ROM 308. As a result, the contrast of the display image on the FLCD panel 150 is changed. The image data from the host 1 corrected by the degamma circuit 309 is output to the binarized halftone processing circuit 305, and the binarized halftone processing circuit 305 outputs the image data to each of the RGB 8 bits based on the error diffusion method. RGB is binarized from 1 bit to 1 bit, and a binary signal indicating the level of luminance is output.

Next, details of the power OFF sequence in step S57 in FIG. 20 will be described below with reference to FIG. In the present embodiment, the power OFF sequence is executed in the following three cases.
1. When the power source of the SW power source 120 is turned off and the AFC signal from the SW power source 120 is energized and executed (returns to the entry point of hardware reset after the processing in FIG. 62).
2. When the RESET signal from the FLCD interface 2 is activated and executed (waits for the RESET signal to be deactivated after the processing in FIG. 62 is completed, and returns to the hardware reset entry point after the RESET signal is deactivated). .
3. When the POWERON signal from the FLCD interface 2 is deactivated and executed (in this case, wait for the POWERON signal to be energized after the completion of the processing in FIG. 62, and then enter the hardware reset entry point after the POWERON signal is energized. Return to.)

  In the power OFF sequence, first, in step S420, the process waits for the completion of 1H, which is scanning by the driver controller 190, and the arrival of the DACT signal for informing the end of 1H, and then instructs the backlight controller 172 in step S421. Turn off the BLSW and turn off the backlight. In subsequent steps S422 to S424, an all black erasing process for writing all black on the FLCD panel 150 is executed. This is because the FLCD panel 150 is configured to store display data, and if this process is not performed, previous display data remains on the display screen.

  Specifically, in step S422, the COM driver 104 and both segment drivers 102 and 103 are energized and set so that all outputs select VC. In subsequent step S423, the information signal to the segment drivers 102 and 103 is fixed to V4 which is an information signal level for displaying darkness during (1H × 30). In step S424, Vc is fixed for (1H × 30). As a result, all the display segments of the FLCD panel 150 are completely erased.

  Therefore, in the subsequent step S425, the DRVSW signal is turned off to turn off the output of the liquid crystal driving voltage. Then, after waiting for 2 ms, the process proceeds to step S426, where the VEESW signal for energizing the output channel power supply (VEE) of each driver circuit is turned OFF. Thereafter, the process is terminated and the process returns.

  FIG. 63 shows a timing chart of the power OFF sequence of the display device of this example using this power OFF sequence. The example shown in FIG. 63 shows a case from an interrupt routine based on AFC detection in which the AFC signal is deactivated.

  In this embodiment, the FLCD interface 2 and the FLCD 3 communicate various control data and the like by serial communication. For this purpose, the system controller 160 of the FLCD 3 performs the following communication control.

  In the normal mode during normal drawing, the reception buffer and transmission buffer of the RAM 162 built-in are polled every 1H. In the static mode, the static mode, the sleep mode in which all blacks are being erased, and the wait mode, such as in an unrecoverable error state, the reception buffer and the transmission buffer are set each time serial communication transmission / reception processing and transmission from the buffer are completed. Poll.

  First, the reception buffer is checked. If there is new reception data, the reception process described below is performed. Next, when there is transmission data in the transmission data buffer, transmission processing is performed.

  In the above processing, in the case of normal drawing, until the polling is performed simultaneously with the driving of the FLCD panel 150, when the reception processing or the transmission processing from the transmission buffer is performed, the corresponding processing is performed after the driving is stopped. Do. It should be noted that during the period from when the power is turned on to when the unit ready attention is issued and during the self-diagnosis, processing for the transmission / reception command and the received command is not performed, but is performed after the end of the processing.

  Since the communication control procedure is as described above, it will not be described again here, but the internal processing of the FLCD 3 operates as follows.

  That is, when a command is received, the driving of the FLCD panel 150 is stopped, and the received command is processed and the status is transmitted. At this time, the transmitted status is as shown in the flowchart above. Since the pointer is not operated until the next command is received, the status is also held until the next command is received. Therefore, even when it is necessary to retransmit, it can be retransmitted promptly without performing any special operation. The state of the internal processing of the FLCD 3 during this period is shown in FIG.

  Also, even when serial communication is performed using attention issuance as an activation factor, the attention state is set until a command (ClearAttention) for canceling the attention state is received from the attention issuance, and only a specific command is responded during this time. Detailed information (AttentionInformation) of the attention event is held during the attention. FIG. 65 shows the internal processing state of the FLCD 3 during this time.

  Further, when a command is received during the attention state, the status for the received command is transmitted after the attention state is resolved. Also, the control is performed so that the Sended Status for the specific command is not held, and the immediately preceding one is held without being updated. The internal processing state of the FLCD 3 during this period is shown in FIG.

  The buffering control to the transmission data buffer such as the transmission image and the status will be described. The FLCD 3 of the present embodiment, in addition to the transmission data for the transmission of the status and the attention, the transmission priority and the holding operation after the transmission A transmission image including information and detailed information (AttentionInformation) of an attention event is set. If the previous transmission has not ended or the attention has not ended, buffering is performed according to the priority order, and transmission and holding operations are performed when transmission is possible.

  An example of the transmission image of the present embodiment in the above processing is shown in FIG. 67, and an example of setting the priority order in the transmission image is shown in FIG.

  In the present embodiment, the memory space of the FLCD 3 can be accessed by a serial communication command, and the memory space of the ROM 161 can be read / written to / from the memory space of the RAM 162. At this time, if a memory space accessible by communication is defined as an access space, and an actual address space in the ROM 161 and RAM 162 is defined as a real address space, in this embodiment, memory access is reduced in order to reduce the amount of transmission during serial communication. Since mapping is performed, the real address space cannot be recognized by communication access. The access space of 64 Kbytes is mapped to an arbitrary address in the 16 Mbyte real address space in units of 4 Kbytes.

  The mapping of memory access of the FLCD 3 of this embodiment will be described below with reference to FIG.

  The designated address space in the command by the serial communication is 16 bits shown in 1001, and the lower 12 bits are used as the lower 12 bits of the real address space, and the remaining upper 4 bits are used as a pointer to the attribute table 1002. ing. In this embodiment, the attribute table 1002 has a total structure of 16 words and can be specified by 4 bits.

  This attribute table 1002 includes a 12-bit real address portion that designates a block partitioned in units of 4 Kbytes in the real address space, and a 4-bit portion that designates the read / write attribute of each block, as indicated by 1003. It is configured.

  Since mapping is performed using the attribute table as described above, a larger capacity real address space can be accessed with a small amount of communication, and communication efficiency is improved.

  Hereinafter, the above-described serial communication processing of the present embodiment with the above control will be described below with reference to FIGS. First, the SC reception processing routine in step S190 of FIG. 31 will be described with reference to FIGS.

  In the SC reception process, first, it is checked whether or not there is reception data in step S430 of FIG. Here, if there is no reception data, it returns as it is. On the other hand, if there is received data, the process proceeds from step S430 to step S431, and it is checked whether the reception is normal. If it is not normal reception, it progresses to step S432, an error status is selected according to the error content, and the transmission process of the error status selected in subsequent step S433 to the FLCD interface 2 is executed.

  On the other hand, if the reception is normal in step S431, the process proceeds to step S434, where the upper 4 bits of the received command are examined to determine the command type. In step S436, one of the following processes shown in FIGS. 71 to 82 is executed in response to a command request. After that, the process ends and returns.

  Next, processing corresponding to the received command in step S436 will be described.

  If the upper 4 bits are (0x) h in step S434, the processing of FIG. 71 is executed. First, in step S440, the remaining lower 4 bits are checked to further determine the command type, and in the SC reception processing routine 3, processing corresponding to the command request is executed and the process returns. The SC reception process 3 will be described later.

  If the upper 4 bits are (1x) h in step S434, the processing of FIG. 72 is executed. In this case, since it is an instruction for self-diagnosis of the FLCD 3, first, the above-described self-diagnosis routine shown in FIG. 21 is executed in step S445. In step S446, the status is selected based on the result of self-diagnosis, and is transmitted to the FLCD 2 in step S447. Then, the process ends and returns.

  If the upper 4 bits are (2x) h in step S434, the processing of FIG. 73 is executed. In this case, since this is a command for notifying the host ID, it is first checked whether or not the host ID received in step S450 is recognized in advance. If the host ID sent from the host side (FLCD interface 2 side) is recognized in advance, that is, if the connection is permitted, the process proceeds to step S451, where the sent host ID is sent. Are stored in a predetermined storage area. In step S452, the normal end status is selected and generated, and transmitted in step S453. Then, the process ends.

  On the other hand, if the host ID is not recognized in advance in step S450, the process proceeds from step S450 to step S454 to select and generate an abnormal end status (undefined host ID), and the process proceeds to step S453 to display the FLCD. Sent to interface 2

  If the upper 4 bits are (3x) h in step S434, the processing of FIG. 74 is executed. In this case, since it is an instruction to switch the display mode of the FLCD 3, the call destination is first determined by the transition code in step S455, and the operation mode routine described above is executed in step S456. Then, the display mode is set to a display mode determined from the three modes of normal display, static display, and sleeve. Then, the process ends and returns.

  If the upper 4 bits are (4x) h in step S434, the processing of FIG. 75 is executed. In this case, since this is a command for setting the FLCD 3 to the multi-drive mode, first, the MultiValue sent together with the command is captured and stored in step S460. In step S461, mask pattern 1 is tabulated and stored, and in step S462, mask pattern 2 is tabulated and stored. In step S463, a normal end status is selected and generated, and transmitted in step S464. Then, the process ends.

  On the other hand, in the case of a normal user use state, if the upper 4 bits are (4x) h or more in step S434, the process proceeds to FIG. 76, and an error end indicating an undefined command is completed in step S465. To return. This is because a command of (8x) h or more is for debugging, and is not used when the general user is using the application program.

  However, at the time of setting to a maintenance mode (debug mode) (not shown), it is necessary to use even a command of (8x) h or more, and in such a case, the process proceeding to FIG. 76 is not performed. The processing shown in FIGS. 77 to 82 is configured to be executable. Hereinafter, the SC reception process in the maintenance mode will be described. In this case, in addition to the processes in FIGS. 71 to 75, the following command reception and corresponding processes are executed.

  If it is determined in step S434 that the upper 4 bits are (8x) h, the processing in FIG. 77 is executed. In this case, it is a WriteHighMemory command for instructing to write upper data to the memory (RAM 162) of the FLCD 3. For this reason, it is first determined whether or not the real address space of the memory designated in step S470 is writable. As a premise of this command execution, it is essential that the memory address to which data is to be written is set by the SetHH / MH / ML / LLAdress command to be described later. Reference numeral 1001 in FIG. Among the indicated addresses, this is done by examining a status bit that indicates whether or not the attribute table designated by the attribute table designation information can be written.

  If writing is possible, the process proceeds to step S471, where data in the set real address space is once loaded. In step S472, the received data is set in the upper 4 bits, and this data is stored again in the real address space set in step S473. Thereafter, a normal end status is selected in step S474, and the flow advances to step S475. In step S475, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, as a result of examining the attribute in step S470, if writing is not possible, the process proceeds to step S476, the write-impossible status is selected, and the process proceeds to step S475. In step S475, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  If the upper 4 bits are (9x) h in step S434, the process of FIG. 78 is executed. In this case, since it is a SetLowMemory command for instructing to write lower data to the memory (RAM 162) of the FLCD 3, first, in step S480, whether or not the real address space of the instructed memory is writable is the same as in step S470. Judging.

  If writing is possible, the process proceeds to step S481, and data in the set real address space is once loaded. In step S482, the received data is set in the lower 4 bits, and this data is stored again in the real address space address position set in step S483. Thereafter, a normal end status is selected in step S484, and the process proceeds to step S485. In step S485, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, as a result of examining the attribute in step S480, if writing is not possible, the process proceeds to step S486, the write-impossible status is selected, and the process proceeds to step S485. In step S485, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  If it is determined in step S434 that the upper 4 bits are (ax) h, the processing in FIG. 79 is executed. In this case, since it is a command for setting the upper 4 bits (A15-A12) of the address bits of the memory address of the FLCD 3 including the above-described data writing, it is first included in the OP code of the command received in step S490. The received 4-bit data is set in the 15-12 bits of the access space address and stored.

  In this case, since it is an instruction of the attribute table, the real address space address is loaded in step S491, and bits 23-12 of the real address space address are cleared. In step S493, the attribute table is subtracted from the received data, and in step S494, 15-4 bits of the attribute data are stored in 23-12 bits of the real address space address. Then, the attribute data read / write attribute is stored.

  Thereafter, a normal end status is selected in step S497, and the flow advances to step S498. In step S498, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  If it is determined in step S434 that the upper 4 bits are (bx) h, the processing in FIG. 80 is executed. In this case, since the upper 4 bits (A11-A8) of the address bits of the memory address of the FLCD 3 including the data writing described above are set, the OP code of the command received in step S500 is first set. The included 4-bit received data is stored in the 11-8 bits of the access space address.

  In step S501, the received data is set and stored in the 11-8 bits of the real address space address. Subsequently, a normal end status is selected in step S502, and the process proceeds to step S503. In step S503, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  If it is determined in step S434 that the upper 4 bits are (cx) h, the processing in FIG. 81 is executed. In this case, since this is a command for setting the lower and middle 4 bits (A7-A4) of the address bits of the memory address of the FLCD 3 including the above-described data writing, the OP code of the command received in step S505 is first used. The included 4-bit received data is stored in the 7-4 bits of the access space address.

  In step S506, the received data is set and stored in 7-4 bits of the real address space address. Subsequently, the normal end status is selected in step S507, and the process proceeds to step S508. In step S508, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  Furthermore, when the upper 4 bits are (dx) h in step S434, the processing of FIG. 82 is executed. In this case, since it is a command for setting the lower 4 bits (A3-A0) of the address bits of the memory address of the FLCD 3 including the above-described data writing, it is first included in the OP code of the command received in step S510. The received 4-bit received data is stored in the 3-0 bits of the access space address.

  In step S511, the received data is set and stored in the 3-0 bits of the real address space address. Subsequently, a normal end status is selected in step S512, and the process proceeds to step S513. In step S513, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  The real address space designation by address mapping shown in FIG. 69 is realized by the above address set command, and the contents of the memory of the FLCD 3 can be freely accessed on the FLCD interface 2 side by the above-described data set command. It is possible to easily rewrite the control program of the FLCD by using it, and it is very easy to cope with version upgrade of the control program.

  Further, the memory content reading process in the maintenance mode will be described later.

  Details of the case where the SC reception processing routine 3 of step S441 is executed when the upper 4 bits are (0x) h in step S434 described above will be described. In this case, the processes of FIGS. 83 to 95 are executed according to the value of the lower 4 bits. Hereinafter, description will be made according to the value of the lower 4 bits.

  If it is determined in step S440 that the lower 4 bits are 0 and the total 8 bits are (00) h, this is an ID request command for the unit of the FLCD 3, and the process proceeds to FIG. First, in step S520, the unit ID of the FLCD 3 is set to the status. In step S521, this status is transmitted to the FLCD interface 2, and the processing ends and returns.

  On the other hand, if the lower 4 bits are 1 and the total of 8 bits is (01) h in step S440, it is a 1H request command for the unit of the FLCD 3, and the process proceeds to FIG. In step S525, the current 1HCode of the FLCD 3 is set as the status. In step S526, this status is transmitted to the FLCD interface 2, and the processing ends and returns.

  On the other hand, if the lower 4 bits are 2 and the total 8 bits are (02) h in step S440, this command is a command to start the FLCD 3 unit and output the BUSY signal. Transition. In step S530, it is checked whether or not the current operation mode of the FLCD 3 is a standby state. Here, if not in the standby state, the process proceeds to step S531, and the operation mode is set. Subsequently, a normal end status is selected in step S532, and the process proceeds to step S533. In step S533, the selected status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the current operation mode is the standby state in step S530, the process proceeds to step S534, an error end that is already in the start state is set, and the process proceeds to step S533. In step S533, the set status is transmitted to the FLCD interface 2 and the process returns.

  On the other hand, if the lower 4 bits are 3 and the total of 8 bits is (03) h in step S440, the request is a request command for attention information, and the process proceeds to FIG. In step S535, it is checked whether the state of the FLCD 3 is an attention state. If the current state is the attention state, the process proceeds to step S536 to set attention information. In step S537, the set attention information is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the current state is not the attention state in step S535, the process proceeds to step S538 to set an error end that is not the attention state. In step S537, the set status is transmitted to the FLCD interface 2 and the process returns.

  On the other hand, if the lower 4 bits are 4 and the total of 8 bits is (04) h in step S440, the process proceeds to the processing of FIG. 87 because it is an attention status bit request command. In step S540, it is checked whether or not the state of the FLCD 3 is an attention state. If the current state is the attention state, the process proceeds to step S541 to set the attention bit. In step S542, the set attention status bit is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the current state is not an attention state in step S540, the process proceeds to step S543 to set an error end that is not an attention state. In step S542, the set status is transmitted to the FLCD interface 2 and the process returns.

  On the other hand, if the lower 4 bits are 5 and the total 8 bits are (05) h in step S440, this is a command for requesting the display mode (normal display mode, static mode, sleep mode) of FLCD 2, so that FIG. Transition to processing. In step S545, the current display mode of the FLCD 3 is set as the above-described display mode in the status. In step S546, this status is transmitted to the FLCD interface 2, and the process ends and the process returns.

  On the other hand, if the lower 4 bits are 6 and the total 8 bits are (06) h in step S440, the command requests a status for the command, and the process proceeds to FIG. In step S550, it is checked whether the state of the FLCD 3 is a command holding state. If the command is currently held, the process advances to step S551 to set the held command as the status. In step S552, the set status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if it is determined in step S550 that the command is not currently held, the process proceeds to step S553, the status is set, and the process proceeds to step S552. The error status set in step S552 is transmitted to the FLCD interface 2 and the process returns.

  On the other hand, in step S440, when the lower 4 bits are 8 and the total 8 bits are (08) h, and when the lower 4 bits are 9 and the total 8 bits are (09) h, the upper 4 bits of the memory of the FLCD 3 This is a command for reading the contents on the FLCD interface 2 side. This is a debugging command, as in the case where the upper 4 bits are 8 to d described above.

  If the lower 4 bits are 8 and the total 8 bits are (08) h in step S440, this is a command for reading the contents of the upper 4 bits of the memory of the FLCD 3, and the process proceeds to the processing of FIG. In step S555, it is determined whether or not the real address space of the memory instructed can be read. As a precondition for executing this command, it is essential that a memory address to which data is to be written is set by a SetHH / MH / ML / LLA dress command, which will be described later, and is shown by reference numeral 1001 in FIG. This is done by checking a status bit that indicates whether or not the attribute table specified by the attribute table specification information in the command can be read.

  If reading is possible, the process proceeds to step S556, and the data in the set real address space is loaded. In step S557, the upper 4 bits are set in the status. In step S558, the set status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the attribute is not readable as a result of checking in step S555, the process proceeds to step S559 to select a readable status, and the selected status is transmitted to the FLCD interface 2 in step S558. Then, the process ends and returns.

  If the lower 4 bits are 9 and the total 8 bits are (09) h in step S440, the command reads the contents of the lower 4 bits of the memory of the FLCD 3, and the process proceeds to FIG. 91. In step S560, it is determined whether or not the real address space of the memory instructed can be read. As a precondition for executing this command, it is essential that a memory address to which data is to be written is set by a SetHH / MH / ML / LLA dress command, which will be described later, and is shown by reference numeral 1001 in FIG. This is done by checking a status bit that indicates whether or not the attribute table specified by the attribute table specification information in the command can be read.

  If the data can be read, the process advances to step S561 to load data in the set real address space. In step S562, the lower 4 bits are set in the status. In step S563, the set status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, as a result of examining the attribute in step S560, if it is not readable, the process proceeds to step S564, where the unreadable status is selected, and the selected status is transmitted to the FLCD interface 2 in step S563. Then, the process ends and returns.

  On the other hand, if the lower 4 bits are a and the total 8 bits are (0a) h in step S440, the process proceeds to the process of FIG. In step S565, it is checked whether or not the state of the FLCD 3 is an attention state. If the current state is the attention state, the process advances to step S566 to clear the attention state and set the end status. In step S567, the set attention end status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the current state is not the attention state in step S565, the process proceeds to step S568 to set an error end that is not the attention state. In step S567, the set status is transmitted to the FLCD interface 2 and the process returns.

  On the other hand, if the lower 4 bits are b and the total of 8 bits is (0b) h in step S440, it is a contrast enhancement transmission request command of the FLCD, and the processing shifts to the processing in FIG. In step S570, the CE (Gray Code) of the FLCD 3 is converted into a binary code. Details of this are described above. In step S571, the contrast enhancement converted to the binary information is set as the status. In step S572, the set status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the lower 4 bits are c and the total 8 bits are (0c) h in step S440, it is an FLCD multi-drive mode (scanning mode) acquisition request command, and the process proceeds to FIG. In step S575, MultiValue indicating the scanning mode of the FLCD 3 is set as the status. In step S576, the set status is transmitted to the FLCD interface 2. Then, the process ends and returns.

  On the other hand, if the lower 4 bits are not the code described above in step S440 (7h, 0dh, 0e, 0fh), the process proceeds to FIG. In step S580, the error end of the undefined command is set. In step S581, the set error end is transmitted to the FLCD interface 2. Then, the process ends and returns.

  Next, the transmission processing to the FLCD interface 2 described above will be described in detail with reference to FIG.

  First, in step S651, it is checked whether or not the SCI buffer that is a hardware buffer for transmission is empty. If the SCI buffer is not empty, the process proceeds to step S660, where the transmission buffer is searched for the next position of the higher priority shown in FIG. In subsequent step S661, data is set at the insertion position. In step S662, the buffer pointer (buffpointer) of the SCI buffer is updated, and the process returns.

  On the other hand, if the SCI buffer is empty, the process advances to step S652 to check whether the transmission information is lower than the priority level 3 shown in FIG. If the priority is higher than level 3, the process advances to step S653 to check whether the state is an attention state. If it is in the attention state, the process proceeds to step S660. If not, the process proceeds to step S654.

  On the other hand, if the priority is lower than level 3, the process proceeds to step S654. In step S654, it is checked whether the SCI buffer is empty. If the SCI buffer is not empty, the process proceeds to step S660.

  On the other hand, if the SCI buffer is empty in step S654, the process proceeds to step S655, and the system controller 160 transmits the data instructed to be transmitted by the buffer pointer (buffpointer) of the SCI buffer to the FLCD interface 2. Subsequently, in step S656, the current hold state update process (hold state clear process) is executed to update the hold state, and in step S657, the transmission buffer is updated. In step S658, the buffer pointer (buffpointer) of the SCI buffer is updated, and the process returns.

  Details of the hold state update processing in step S656 in the above processing will be described below with reference to the flowchart in FIG.

  First, each routine shown below is selected and executed by the clear code held in step S600. That is, if the clear code is 0, there is no need to do anything in step S601, and the process returns as it is.

  On the other hand, when the clear code is 2, since the attention bit is cleared, the process proceeds from step S605 to step S606, the attention bit of the holdstat that is the transmission status / attention holding state is cleared, and the process ends. Return.

  If the clear code is 3, since the attention is held, the process proceeds from step S610 to step S611, and the transmitted attention image is set as the transmitted attention image senttten. In step S612, the holdstat attention bit, which is the transmission status / attention holding state, is set and the process returns, and the process ends.

  Further, when the clear code is 4, since the status is clear, the process proceeds from step S615 to step S616, and the status bit of holdstat which is the transmission status / attention holding state is cleared and returned, and the process ends.

  On the other hand, when the clear code is 5, since the status is held, the process proceeds from step S620 to step S621, and the transmitted status image is set to the transmitted status image senddata. In step S622, the status bit of holdstat, which is the transmission status / attention holding state, is set and the process returns, and the processing ends.

  Furthermore, if the clear code is other than the above values, it is an error, so the process advances from step S625 to step S626, and returns without doing anything as an error.

  As described above, according to the present embodiment, in the information processing system (or apparatus), a ferroelectric liquid crystal (Ferroelectric Liquid Crystal) that can be made extremely thin as compared with a CRT as a means for realizing a visual expression function of information. In view of the fact that the display using liquid crystal cells (FLCD) has the characteristic of storing the display contents, it has an intelligence function such as checking the state of each other with the host side. In addition, it can be automatically set to the optimum state regardless of the state on the host side so that display contents are not difficult to see at the time of shutdown, and it can be used without a sense of incompatibility even when compared with conventional display devices. The state on the display device side is configured to be easily recognizable by changing the display mode of the LED, and appropriate measures can be taken.

  In view of the fact that the display speed of the FLCD changes slightly depending on the temperature (the speed increases as the temperature rises), the data transfer cycle is changed accordingly to further improve the display image quality. Can be planned.

  Further, since communication other than the transfer of display image data to the FLCD is performed using serial communication, the transfer of the display image data to the FLCD is not sacrificed, and the display image quality can be prevented from being impaired.

  Further, the example in which two interfaces of the bus 310 dedicated to image data and the serial communication line 311 for exchanging commands and attentions are provided between the FLCD interface 2 and the FLCD 3 in the present embodiment has been described. However, since these interfaces are actually connected in a single cable, it seems to the user as if data is being exchanged via one interface, avoiding confusion in wiring. I am doing so. And even if this cable is disconnected, this can be easily recognized, and even if the display data on the display device side from the host side is lost, the display content will be distorted Can be prevented.

  The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Needless to say, the present invention can also be applied to a case where the present invention is achieved by supplying a program to a system or apparatus.

  As described above, according to the present embodiment, even in a display device having a plurality of operation modes, a display device and a display device control method capable of visually confirming the current display operation state reliably and quickly Can be provided.

  Furthermore, even if the display device has a display content storage function, it is possible to prevent the display content from being reliably left and difficult to see. In addition, when the connection cable is not correctly connected, it is possible to prevent unnecessary information from remaining on the display by stopping the display control. Furthermore, by performing the initialization process when the connection cable is disconnected, it is possible to prevent malfunctions in the same way as other abnormalities.

It is a block block diagram of the information processing system in one Example which concerns on this invention. It is a figure which shows the concept of the data flow regarding the display of the image in the system of a present Example. It is a figure which shows the specific block configuration of the FLCD interface in a present Example. It is a block block diagram of FLCD in a present Example. It is a figure which shows the external appearance of the display apparatus of a present Example. It is a figure which shows the connection part with the host side of a display apparatus of a present Example. It is a figure which shows the detailed structure of the FNX controller shown in FIG. It is a figure which shows the detailed structure of the part regarding the input / output of the image data in FIG. It is a figure which shows the detailed structure of the switching power supply 120 shown in FIG. It is a figure which shows the structure of the part concerning temperature compensation in the display apparatus of a present Example. It is a figure which shows transition of the flag during operation | movement of CPU in the FLCD interface in a present Example. It is a flowchart which shows the main process routine of CPU in the FLCD interface in a present Example. 4 is a flowchart of an interrupt routine that is activated when a data transfer request signal is received from a frame memory control circuit in an FLCD interface in the present embodiment. It is a flowchart which shows the process started when the notification of the completion of quantization from the frame memory control circuit in a present Example is received. It is a flowchart which shows the process started when the transfer completion notification to FLCD is received from the frame memory control circuit in a present Example. It is a figure which shows the list of the commands sent to FLCD from the FLCD interface in a present Example. It is a figure which shows an example of the sequence of communication with the FLCD interface and FLCD in a present Example. It is a figure which shows an example of the sequence of communication with the FLCD interface and FLCD in a present Example. It is a figure which shows an example of the sequence of communication with the FLCD interface and FLCD in a present Example. It is a flowchart which shows the basic process at the time of the operation | movement start after power-on of the FLCD of a present Example or a reset state. It is a flowchart which shows the detail of the self-diagnosis routine in a present Example. It is a flowchart which shows the detail of the check routine of the AFC signal in a present Example. It is a flowchart which shows the detail of the check process of ROM in FIG. It is a flowchart which shows the detail of the check process of RAM in FIG. It is a flowchart which shows the detail of the check process of RAM in FIG. FIG. 21 is a flowchart showing details of power-on wait processing in FIG. 20. FIG. It is a flowchart which shows the detail of the power ON sequence process in FIG. It is a timing chart of the signal in a series of operation at the time of power ON of FLCD3 in this example. It is a flowchart which shows the detail of the operation | movement selection process shown in FIG. 20 in a present Example. It is a flowchart which shows the detail of the operation | movement selection process shown in FIG. 20 in a present Example. It is a flowchart which shows the detail of the operation | movement selection process shown in FIG. 20 in a present Example. It is a figure which shows the example of the screen display in each operation mode of FLCD in a present Example, the backlight, and the drive state of LED. It is a figure for demonstrating the image data display position of the FLCD panel in a present Example. It is a figure for demonstrating the transfer timing of the display data in a present Example. It is a figure which shows the actual data format sent from a FLCD interface according to the timing chart shown in FIG. It is a figure for demonstrating the scan address and scan code transfer timing of a present Example. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. FIG. 31 is a flowchart showing details of normal drawing processing shown in FIG. 30 in the embodiment. FIG. It is a figure which shows the state transition at the time of returning to normal by the retry at the time of timeout generation of AHDL in a present Example. It is a figure which shows a state transition when this retry reaches the specified number of times (40 times) after AHDL timeout occurs in this embodiment and a recoverable error attention is issued. It is a figure which shows a state transition when AHDL is not received even if attention is cleared at the time of timeout occurrence of AHDL in a present Example. It is a figure which shows the example of the FLCD panel drive waveform of a present Example. It is a figure which shows the example of the temperature compensation table in a present Example. It is a figure which shows the example of the frame frequency in the state in which the frame frequency at the time of a start in this Example and internal temperature were fully saturated. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the temperature compensation routine in a present Example. It is a flowchart which shows the detail of the panel stop process in a present Example. It is a flowchart which shows the detail of the color switch routine in a present Example. It is a figure which shows the detailed structure of the part corresponding to the color adjustment switch shown in FIG. 7 and the color adjustment switch of a trimmer interface in a present Example. It is a figure which shows the relationship between the setting state from a color adjustment switch and a Gray code | cord | chord in a present Example. It is a flowchart which shows the detail of the power OFF sequence of a present Example. It is a timing chart of the power OFF sequence by the power OFF sequence in a present Example. It is a figure which shows the state of an internal process when FLCD of a present Example receives the command by serial communication. It is a figure which shows the state of an internal process in case the FLCD of a present Example performs serial communication by using attention issue as a starting factor. FIG. 10 is a diagram illustrating a state of internal processing when a command is received during an attention state when the FLCD of this embodiment performs serial communication using attention issue as an activation factor. It is a figure which shows the example of the transmission image used by the serial communication of a present Example. It is a figure which shows the example of a setting of the priority of transmission using the transmission data buffer used by the serial communication of a present Example. It is a figure for demonstrating the address space at the time of the memory access of FLCD of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the SC reception process in the serial communication process of a present Example. It is a flowchart which shows the transmission process to the FLCD interface of a present Example. It is a flowchart which shows the detail of the hold state update process of a present Example.

Explanation of symbols

1 Host 2 FLCD interface 3 FLCD
4 Panel controller 5 FLC panel 12 Cable side connector 13 Fixing screw 15 Receiving connector 101 NFX controller 102 U-SEG driver 103 L-SEG driver 104 COM driver 105 Temperature sensor 106 Brightness adjustment trimmer 106 Image quality adjustment trimmer 108 Color adjustment switch 109 LED
DESCRIPTION OF SYMBOLS 120 Switching power supply 121 General commercial power supply 122 Power switch 123 Noise filter 126 Control circuit for switching regulator 124 Switching circuit 127 5 terminal regulator 128 + 5V power supply circuit 129 Power supply circuit for backlight drive 130 Inverter 131-133 Fluorescent lamp (hot cathode fluorescent lamp )
150 FLC panel 160 System controller 161 ROM
162 RAM
165 AFC detection circuit 171 Temperature interface 172 Backlight controller 173 VOP controller 174 Trimmer interface 181 Power switch controller 182 Liquid crystal drive power switch 183 Liquid crystal drive voltage regulator 300 CPU
301 VRAM
302 SVGA chip 303 Rewrite detection / flag generation circuit 304 Line address generation circuit 305 Binary halftone processing circuit 306 Frame memory 307 Frame memory control circuit 308 ROM
310 Data Transfer Bus 311 Serial Communication Line 521, 522 Buffer 523 Input Side Switch 524 Output Side Switch 525 Timing Controller 526 Reception Address Register 527 Scan Address Register 528 DST Register 531 U-SEG Latch Circuit 532 U-SEG Memory 533, 536, 543 Driver circuit 537 L-SEG memory 538 L-SEG latch circuit 541 Address memory 1
542 Address memory 2
901 Temperature compensation table 902 Timer unit 904, 905 Analog-digital converter

Claims (4)

A plurality of operations including a display operation mode in which an image is displayed by line-sequential scanning driving a display device including a plurality of pixels and the line-sequential scanning driving is performed, and a power saving operation mode in which the line-sequential scanning driving is not performed. A display device comprising a mode,
Mode setting means for setting the operation mode;
Display means provided separately from the indicator for displaying the operation mode set by the mode setting means;
Display control means for displaying the display means in a mode corresponding to the operation mode.   The display device according to claim 1, wherein the display device has a function of maintaining a display state of an image.   The said display means is comprised with the light emitting diode, The said display control means controls the lighting and extinction time of the said light emitting diode corresponding to the operation mode of the said apparatus. Display device.   A display device control method for displaying an image by line-sequential scanning driving a display device including a plurality of pixels, wherein the display device performs a display operation mode for performing the line-sequential scanning driving and the line-sequential scanning driving. A display device control method comprising: a plurality of operation modes including a power saving operation mode that is not performed; and display means provided separately from the display device in a manner corresponding to the operation mode. .

Images