JP3787950B2 - Video signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing circuit suitable for application to a camera device, for example.
[0002]
[Prior art]
Conventionally, in signal processing in a camera apparatus, luminance and chroma signals during an effective video period are integrated, and automatic integration control (AE) and auto white balance control (AWE) are realized by a microcomputer or the like using the integration result. I am doing so.
[0003]
[Problems to be solved by the invention]
However, in the signal processing in the conventional camera device, when integrating the video signal, a register for securing the integration result is required according to the number of area divisions of the screen, and the bit word length is also large, so integration is required. There is a disadvantage that the scale of the circuit becomes large. In addition, since the microcomputer circuit for realizing automatic exposure control (AE) and auto white balance control (AWE) uses a large number of general-purpose registers having a large word length, the camera system has both an integration circuit and a microcomputer. However, there is a disadvantage that the circuit scale for configuring both circuits becomes large.
[0004]
In consideration of such a point, an object of the present invention is to provide a video signal processing circuit capable of reducing the circuit scale.
[0005]
[Means for Solving the Problems]
The video signal processing circuit of the present invention comprises: Imaged A register block for storing information relating to a video signal, a bus select block for switching and transmitting information stored in the register block to a plurality of buses, and a plurality of buses switched by the bus select block. A calculation block that performs calculation using information and stores the calculation result as information on the video signal in the register block; A video terminal to which a captured video signal is supplied, a switching terminal to which a timing switching signal is supplied, a timing selection block for selecting a timing for switching a plurality of buses in the bus select block, the register block, and the bus select A CPU timing generation circuit for generating a control pulse required when operating as a CPU for calculating information on the video signal for the block and the calculation block; and for the register block, the bus select block, and the calculation block An integration area timing generation circuit for generating a timing for defining an integration area when integrating the video signal, and for obtaining an integration result of the video signal during an effective video period of the video signal, from the switching terminal. Supplied By switching a plurality of buses in the bus select block according to the timing switching signal, the register block, the bus select block, and the arithmetic block are switched to an operation path at the time of integrating the video signal supplied from the video terminal. Outside the effective video period of the video signal, the bus select block is used to switch a plurality of buses in accordance with the timing switching signal supplied from the switching terminal in order to calculate the integration result of the video signal. The block, the bus select block, and the calculation block are switched to an operation path at the time of CPU operation that functions as a CPU for calculating information related to the video signal. It is what I did.
[0006]
Such a video signal processing circuit operates as follows.
First, the operation path of the integration circuit at the time of video signal integration will be described. In order to obtain video information during the effective video period, the operation is switched to the operation path at the time of this video signal integration by the timing switching signal. The video signal (luminance signal or chroma signal) is supplied to the bus select block, and is supplied to the arithmetic block via the other bus. Further, a plurality of register outputs of the register block are supplied to the bus select block and supplied to the arithmetic block via one bus. The addition output of the arithmetic block is supplied to the input of the register block. Such an operation path forms an integration operation of the luminance signal.
[0007]
In this way, the integrated luminance values of a plurality of areas in the video screen can be stored in the registers of the register block, respectively. Further, the integration value stored in the register after the integration operation is stopped is supplied to the bus select block and output to the external block via one bus. By using such an operation path at the time of video signal integration, luminance information can be read using an external microcomputer, so that automatic exposure control (AE) or the like can be realized using this luminance information. it can.
[0008]
Next, control during CPU control Le The operation path of the circuit will be described. Outside the effective video period, in order to function as a CPU for calculating the integration result of the video signal, the operation path at the time of this CPU is switched by a timing switching signal. In the register block, the CPU command in the case where the integration result of area 1 and the integration result of area 2 are distributed to two registers, and the addition result of area 1 + area 2 is returned to one register will be described. .
[0009]
The integration result of area 1 is supplied from the register to the bus select block, and is supplied to the arithmetic block via one bus. Further, the integration result of area 2 is supplied from the register to the bus select block, and is supplied to the arithmetic block via the other bus. The addition output of area 1 + area 2 of the operation block is supplied to the input of one register of the register block. A CPU operation for calculating the integration result of the video signal is formed by such an operation path.
[0010]
In this way, the integration results of area 1 and area 2 stored in the two registers of the register block can be added using the operation block. By using such an operation path at the time of CPU, the integration results of area 1 and area 2 stored in the two registers of the register block are added using the arithmetic block and stored in one register of the register block. can do. Other blocks can be controlled using such calculation results.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The video signal processing circuit of this embodiment described below is applied to a processing circuit for a video signal imaged by a camera device.
[0012]
In FIG. 1, a video signal processing circuit according to the present embodiment includes a register block 1 for storing information relating to a video signal, a bus select block 4 for switching information stored in the register block 1 to a plurality of buses, and transmitting the information. An arithmetic block 8 that performs an operation using information sent through a plurality of buses switched by the bus select block 4 and stores the operation result in the register block 4 as information relating to a video signal, and an imaging such as a CCD (not shown) The terminal 13 to which the video signal (luminance signal or chroma signal) is supplied from the means, the terminal 14 to which the timing switching signal (V blanking signal, etc.) is supplied, and the timing for switching a plurality of buses in the bus select block 4 are selected. Timing select block 15 and control pulses necessary for CPU operation Includes a CPU timing generating circuit 19 for raw, an integration area timing generator circuit 20 for generating a timing that defines the integration area when the video signal integration.
[0013]
The register block 1 has a two-channel register including a register (1) 2 and a register (2) 3. The bus select block 4 includes a select 5 for switching the outputs of the register (1) 2 and the register (2) 3, a selector 6 for switching the outputs of the register (1) 2 and the register (2) 3, and an output of the selector 6 And a selector 7 for switching between a video signal (luminance signal or chroma signal) from the terminal 13. The arithmetic block 8 includes a common bus A9 for sending the output of the register (1) 2 or register (2) 3 switched by the select 5 to the arithmetic block 8 and an external block, a video signal (luminance signal or chroma signal), and a selector 6 The output of the register (1) 2 or the register (2) 3 switched by the common bus B10 for sending the output to the arithmetic block 8, the adder 11 for adding the outputs of the common bus A9 and the common bus B10, and the output of the adder 11 The register block 4 includes a register (1) 2 and a common bus C12 that feeds back to the register (2) 3.
[0014]
The timing select block 15 switches the outputs of the CPU timing generation circuit 19 and the integration area timing generation circuit 20 and supplies them to the register (2) 3 of the register block 1, and the CPU timing generation circuit 19 and the integration area timing generation. The selector 17 that switches the output to the circuit 20 and supplies it to the register (1) 2 of the register block 1, and the outputs of the CPU timing generation circuit 19 and the integration area timing generation circuit 20 to switch the output of the selector 5 of the bus select block 4 And a selector 18 that supplies the control terminal. The output of the CPU timing generation circuit 19 is supplied to the control terminal of the selector 6 of the bus select block 4. A timing switching signal (V blanking signal or the like) is supplied from the terminal 14 to the control terminal of the selector 6 of the bus select block 4.
[0015]
The register block 1 is composed of a multi-bit register group, the inputs of the registers (1) 2 and (2) 3 are connected to a common common bus C, and the outputs are the selectors 5 and 6 of the bus select block 4. Connected to the input terminal. The bus select block 4 has a function of selecting the outputs of the registers (1) 2 and (2) 3 of the register block 1 by the selector 5 and outputting them to the common bus A9, and the registers of the register block 1 that are output to the common bus A9. (1) A function for outputting the outputs of 2 and (2) 3 to an external block, a video signal (luminance signal or chroma signal) supplied from the terminal 13, and each register (1) 2, (2) of the register block 1 3 is selected by the selector 7 and output to the common bus B10.
[0016]
The operation block 8 has a function of performing a logical operation or an arithmetic operation on the outputs of the common bus A9 and the common bus B10. In the present embodiment, the calculation block 8 is only the addition calculation by the adder 11. The timing select block 15 performs switching control between the CPU timing generation circuit 19 and the integration area timing generation circuit 20 using a signal (V blanking signal or the like) synchronized with the video signal.
[0017]
The video signal processing circuit of the present embodiment configured as described above operates as follows.
First, the operation path at the time of video signal integration according to the present embodiment will be described with reference to FIG. During the effective video period, in order to obtain video information, the timing switching signal supplied from the terminal 14 is switched to the operation path at the time of this video signal integration.
In FIG. 2, a video signal (luminance signal or chroma signal) supplied from the outside to the terminal 13 is supplied to the selector 7 of the bus select block 4, and the other addition input of the adder 11 of the arithmetic block 8 via the common bus B10. Supplied to the terminal. The register output from the register (1) 2 of the register block 1 is supplied to the selector 5 and supplied to one addition input terminal of the adder 11 of the arithmetic block 8 through the common bus A9. The addition output of the adder 11 of the arithmetic block 8 is supplied to the input of the register (1) 2 of the register block via the common bus C12. Such an operation path forms an integration operation of the luminance signal.
[0018]
Here, the signal relating to the timing defining the integration area at the time of video signal integration output from the integration area timing generation circuit 20 is supplied to the selector 17 of the timing select block 15, and the timing switching supplied from the terminal 14 in the selector 17. The switching is controlled by the signal, and the control signal CTL1 is supplied to the control terminal of the register (1) 2 of the register block 1. The control signal CTL1 is a control signal for performing the register operation within the integration area with respect to the register (1) 2 and stopping the register operation outside the integration area.
[0019]
Also, a signal relating to the timing defining the integration area at the time of video signal integration output from the integration area timing generation circuit 20 is supplied to the selector 17 of the timing select block 15, and the timing switching signal supplied from the terminal 14 in the selector 17. And is supplied as a control signal CTL2 to the control terminal of the selector 5 of the bus select block 4. The control signal CTL2 is a signal for switching the integration area with respect to the register (1) 2. For example, when the integration result of the area 1 is allocated to the register (1) 2 and the integration result of the area 2 is allocated to the register (2) 3. Is a control signal used for
[0020]
As described above, by using the control signal CTL1 and the control signal CTL2, the integrated luminance values of the two areas in the video screen can be stored in the register (1) 2 and the register (2) 3, respectively.
[0021]
Further, the integration values stored in the registers (1) 2 and (2) 3 after the integration operation stop are supplied to the selector 5 and output to the external block via the common bus A9.
[0022]
By using such an operation path at the time of video signal integration, luminance information can be read using an external microcomputer, so that automatic exposure control (AE) or the like can be realized using this luminance information. it can.
[0023]
Next, an operation path at the time of CPU control according to the present embodiment will be described with reference to FIG. Outside the effective video period, in order to function as a CPU for calculating the integration result of the video signal, the operation path at the time of this CPU is switched by a timing switching signal supplied from the terminal 14.
In FIG. 3, the integration result of area 1 is assigned to register (1) 2 and the integration result of area 2 is assigned to register (2) 3 as described above, and the addition result of area 1 + area 2 is assigned to register (1). A CPU command when operating to return to 2 will be described.
[0024]
The integration result of area 1 is supplied from the register (1) 2 to the selector 5 and supplied to one addition input terminal of the adder 11 of the arithmetic block 8 through the common bus A9. The integration result of area 2 is supplied from the register (2) 3 to the selector 6 and supplied to the other addition input terminal of the adder 11 of the arithmetic block 8 through the common bus B10. The addition output of area 1 + area 2 of adder 11 of operation block 8 is supplied to the input of register (1) 2 of the register block via common bus C12. A CPU operation for calculating the integration result of the video signal is formed by such an operation path.
[0025]
Here, the control pulse signal necessary for the CPU operation output from the CPU timing generation circuit 19 is supplied to the selectors 16 and 17 of the timing select block 15, and the timing switching signal supplied from the terminal 14 in the selectors 16 and 17 is used. The switching is controlled, and the control pulse is supplied to the control terminals of the register (1) 2 and the register (2) 3 of the register block 1. The control pulse is a control signal for causing the register (1) 2 and the register (2) 3 to perform a CPU operation.
[0026]
Further, a control pulse signal necessary during the CPU operation output from the CPU timing generation circuit 19 is supplied to the selector 18 of the timing select block 15 and is controlled to be switched by the timing switching signal supplied from the terminal 14 in the selector 18. It is supplied to the control terminal of the selector 5 of the bus select block 4. Further, a control pulse signal necessary for the CPU operation output from the CPU timing generation circuit 19 is supplied to the control terminal of the selector 6 of the bus select block 4. The control pulse is a control signal for performing switching control of the selectors 5 and 6.
[0027]
As described above, by using the control pulse, the integration results of the areas 1 and 2 stored in the register (1) 2 and the register (2) 3 are added using the adder 11 of the calculation block 8. be able to.
[0028]
By using such an operation path at the time of CPU, the integration result of area 1 and area 2 stored in register (1) 2 and register (2) 3 of register block 1 is added to adder 11 of arithmetic block 8. Can be used for addition operation. Other blocks can be controlled using such calculation results.
[0029]
Next, FIG. 4 shows another configuration of the video signal processing circuit of the present embodiment. The video signal processing circuit shown in FIG. 4 is configured so that the register of the register block 1 has four channels, the selector of the bus control block 4 is switched from four inputs to one output, and the arithmetic block 8 is provided with a multiplier. Since the others are the same as those shown in FIG. 1, the differences from the video signal processing circuit shown in FIG. 1 will be described, and the description of the other components will be omitted.
[0030]
The register block 1 has four-channel registers including a register (1) 2, a register (2) 3, a register (3) 21, and a register (4) 22. The bus select block 4 includes a selector 23 for switching the outputs of the four channels of the register (1) 2, the register (2) 3, the register (3) 21, and the register (4) 22, and the register (1) 2 and the register. (2) It has a selector 24 for switching the outputs of the four-channel registers of 3, the register (3) 21, and the register (4) 22. The arithmetic block 8 sends the output of the register (1) 2, the register (2) 3, the register (3) 21 or the register (4) 22 switched by the selector 23 to the adder 11, the selector 25 and the external block. A9, the video signal (luminance signal or chroma signal) and the output of the register (1) 2 or register (2) 3 or register (3) 21 or register (4) 22 switched by the selector 24 26, the multiplier 27 that multiplies the output of the selector 25 and the output of the selector 26, the adder 11 that adds the outputs of the common bus A9 and the multiplier 27, the adder 1, and the multiplier 27. And the output of the selector 28 is changed to the register (1) of the register block 4. And a and register (2) 3 and the register (2) 3 and a register (3) 21 and the register (4) common bus C12 to be fed back to the four-channel registers 22.
[0031]
The timing select block 15 switches the outputs of the CPU timing generation circuit 19 and the integration area timing generation circuit 20 to register (1) 2, register (2) 3, register (2) 3 and register (3) of the register block 1. The selector 16 supplied to the four-channel registers 21 and the register (4) 22 and the outputs of the CPU timing generation circuit 19 and the integration area timing generation circuit 20 are switched and supplied to the control terminal of the selector 23 of the bus select block 4. And a selector 18. Note that the output of the CPU timing generation circuit 19 is supplied to the control terminal of the selector 24 of the bus select block 4. Further, a timing switching signal (V blanking signal or the like) is supplied from the terminal 14 to the control terminals of the selectors 26 and 28 of the arithmetic block 8.
[0032]
The operation of the video signal processing circuit shown in FIG. 4 configured as described above will be described. The video signal processing circuit shown in FIG. 4 stores the integration value of the integration area of 4 channels in the register of the register block 1 and is switched from 4 inputs to 1 output in the selectors 23 and 24 of the bus control block 4. Since the multiplication operation is performed by the multiplier and the others are the same as those shown in FIG. 1, the differences from the video signal processing circuit shown in FIG. 1 will be described, and description of other operations will be omitted. .
[0033]
First, in the operation path at the time of video signal integration, the video signal is integrated for the areas of the four channels of area 1 to area 4, and the integrated value of each area 1 to area 4 is the register (1) 2 of the register block 1. The data is stored in registers of four channels, ie, register (2) 3, register (2) 3, register (3) 21, and register (4) 22. At this time, the output of the common bus B10 from the selector 25 is supplied to one multiplication input terminal of the multiplier 27 of the arithmetic block 8, and the video signal (luminance signal or chroma signal) supplied from the selector 26 to the terminal 13 is the arithmetic block 8. Is supplied to the other multiplication input terminal of the multiplier 27. In this way, the multiplier 27 weights the integral value of each area 1 to area 4 to the video signal, whereby the weighted value can be integrated.
[0034]
Next, in the CPU operation, the data is stored in the 4-channel registers of the register (1) 2, the register (2) 3, the register (2) 3, the register (3) 21, and the register (4) 22 of the register block 1. The integrated values of the areas 1 to 4 are supplied to the selectors 23 and 24 of the bus select block 4 and output to the common bus A9 and the common bus B10. The output of the common bus A9 is supplied from the selector 25 to one multiplication input terminal of the multiplier 27 of the arithmetic block 8, and the output of the common bus B10 is supplied from the selector 26 to the other multiplication input terminal of the multiplier 27 of the arithmetic block 8. . In this manner, the multiplier 27 causes the four-channel registers of the register (1) 2, the register (2) 3, the register (2) 3, the register (3) 21, and the register (4) 22 of the register block 1 Can operate to execute multiply instructions. Other blocks can be controlled using such calculation results.
[0035]
The video signal processing circuit according to this embodiment includes a register block 1 that stores information relating to a video signal, a bus select block 4 that switches information stored in the register block 1 to a plurality of common buses 9 and 10, and a bus. A video signal including a calculation block 8 that performs a calculation using information transmitted via a plurality of common buses 9 and 10 switched in the select block 4 and stores the calculation result in the register block 1 as information relating to the video signal. In the processing circuit, by switching the plurality of common buses 9 and 10 in the bus select block 4, an integration circuit for integrating the video signal to obtain subject luminance information or chroma information, or other subject information from subject luminance information or chroma information. The controller circuit that controls the block of The other was double as by selectively switching the controller circuit, an integrating circuit and a controller circuit, respectively there is no need to provide a single, it is possible to reduce the circuit scale significantly.
[0036]
In the video signal processing circuit of this embodiment, the register block 1 uses both the integration register used for the integration circuit and the control register used for the control circuit in the register block 1 described above. The signal integration operation and the control operation for controlling other blocks can be performed using the same circuit.
[0037]
Further, in the video signal processing circuit of this embodiment, in the bus selection block 4, the integration information used for the integration circuit from the register block 1 and the control information used for the control circuit are read from the register block 1 in the plurality of common buses. Since the bus selection block 4 is used by switching between 9, 10, the video signal integration operation and the control operation for controlling other blocks can be performed using the same circuit.
[0038]
Further, in the video signal processing circuit of this embodiment, in the above-described calculation block 8, the integration calculation circuit used for the integration circuit and the control calculation circuit used for the control circuit are used together. The video signal integration operation and the control operation for controlling other blocks can be performed using the same circuit.
[0039]
The video signal processing circuit of this embodiment is provided with the timing select block 15 for selecting the timing for switching the plurality of common buses 9 and 10 in the bus select block 4 as described above. The common buses 9 and 10 in FIG. 4 are switched so that they are shared by switching the common buses 9 and 10 to the integration circuit during the effective video period of the video signal and to the control circuit during the vertical blanking period of the video signal. Therefore, the plurality of common buses 9 and 10 in the bus select block 4 are selected by switching the timing, and the integration operation of the video signal and the control operation for controlling other blocks are performed in each block using the same circuit. Can do.
[0040]
【The invention's effect】
The video signal processing circuit of the present invention is switched between the register block for storing information relating to the video signal, the bus select block for switching the information stored in the register block to a plurality of buses, and the bus select block. A video signal processing circuit comprising: a calculation block that performs calculation using information sent via a plurality of buses and stores the calculation result in the register block as information relating to the video signal; By switching the bus, an integration circuit that integrates the video signal to obtain subject luminance information or chroma information, or a controller circuit that controls other blocks from the subject luminance information or chroma information subject information, The integration circuit or the controller Le Since the circuit is shared by selectively switching, the integration circuit and the control Le There is no need to provide a single circuit, and the circuit scale can be greatly reduced.
[0041]
In the video signal processing circuit according to the present invention, the integration register used for the integration circuit in the register block and the control register used for the control circuit are combined in the register block. The integration operation and the control operation for controlling other blocks can be performed using the same circuit.
[0042]
In the video signal processing circuit according to the present invention, in the above description, in the bus select block, the integration information used for the integration circuit is read from the register block and the control information used for the control circuit is read from the plurality of registers. Since the bus is also used by switching the buses, the video signal integration operation and the control operation for controlling other blocks can be performed using the same circuit in the bus select block.
[0043]
In the video signal processing circuit according to the present invention, the integration arithmetic circuit used for the integration circuit in the arithmetic block and the control arithmetic circuit used for the control circuit are combined in the arithmetic block. The video signal integration operation and the control operation for controlling other blocks can be performed using the same circuit.
[0044]
The video signal processing circuit according to the present invention includes a timing select block for selecting a timing for switching the plurality of buses in the bus select block, and the plurality of the bus select blocks in the bus select block according to the timing in the timing select block. By switching the bus, the bus is shared by switching the plurality of buses to the integration circuit during the effective video period of the video signal and to the control circuit during the vertical blanking period of the video signal. There is an effect that a plurality of buses in the select block are selected by switching timing, and the integration operation of the video signal and the control operation for controlling other blocks can be performed in each block using the same circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video signal processing circuit according to an embodiment of the present invention.
FIG. 2 is a diagram showing an operation path during video signal integration according to an embodiment of the present invention.
FIG. 3 is a diagram showing an operation path for a CPU according to an embodiment of the present invention.
FIG. 4 is a block diagram showing another configuration of the video signal processing circuit according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Register block, 2 ... Register 1, 3 ... Register 2, 4 ... Bus select block, 5 ... Selector, 6 ... Selector, 7 ... Selector, 8 ... Operation block, 9 ... Common bus A, 10 ... Common bus B, 11 ... Adder, 12 ... common bus C, 13 ... terminal, 14 ... terminal, 15 ... timing select block, 16 ... selector, ... selector, 17 ... selector, 18 ... selector, 19 ... CPU timing generation circuit, 20 ... integration area timing generation Circuit, 21 ... Register 3, 22 ... Register 4, 23 ... Selector, 24 ... Selector, 25 ... Selector, 26 ... Selector, 27 ... Multiplier, 28 ... Selector, CTL1 ... Control signal 1, CTL2 ... Control signal 2

Claims (1)

A register block for storing information about the imaged video signal;
A bus select block for switching and transmitting information stored in the register block to a plurality of buses;
An arithmetic block that performs an operation using information transmitted via a plurality of buses switched by the bus select block and stores an operation result as information on the video signal in the register block;
A video terminal to which the captured video signal is supplied;
A switching terminal to which a timing switching signal is supplied;
A timing select block for selecting a timing for switching a plurality of buses in the bus select block;
A CPU timing generation circuit for generating a control pulse required when the register block, the bus select block, and the calculation block are operated as a CPU for calculating information on the video signal;
An integration area timing generating circuit for generating a timing for defining an integration area when integrating the video signal with respect to the register block, the bus select block, and the arithmetic block;
In order to obtain an integration result of the video signal during the effective video period of the video signal, the bus selection block switches a plurality of buses according to the timing switching signal supplied from the switching terminal, whereby the register block, Switching the bus select block and the calculation block to the operation path during the integration operation of the video signal supplied from the video terminal,
Outside the effective video period of the video signal, the register block is switched by switching a plurality of buses in the bus select block by the timing switching signal supplied from the switching terminal in order to calculate an integration result of the video signal. A video signal processing circuit , wherein the bus select block and the calculation block are switched to an operation path during a CPU operation to function as a CPU for calculating information relating to the video signal.

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