JP3779863B2 - Phase shift oscillation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit that can not only generate an output signal that is phase-locked with an input signal that changes periodically, but also can arbitrarily shift the phase of an output signal that has been locked once.
[0002]
[Prior art]
The oscillation circuit may be used, for example, to receive an arbitrary input signal from the outside and generate a signal in phase with the input signal. For example, when a digital television signal is received, an internal clock signal that is phase-locked with a synchronizing signal such as a vertical synchronizing signal is generated. As a circuit for generating a signal phase-locked to such an arbitrary input signal, an oscillation circuit using a phase-locked loop (PLL) is well known.
[0003]
FIG. 5 is a block diagram of an example of a general PLL oscillation circuit. The voltage controlled oscillation circuit (VCO) 18 is an oscillation circuit that receives a control voltage from an LPF (low-pass filter) 16 and changes the frequency of the output signal in accordance with the control voltage. The output signal of the voltage controlled oscillating circuit (VCO) 18 is frequency-divided by the frequency dividing ratio N by the frequency dividing circuit 12, and then the phase of the input signal is compared. The phase comparison circuit 14 outputs a signal having a frequency component corresponding to these phase differences. The LPF 16 cuts the high frequency component of the output signal of the phase comparison circuit 14 and generates a control signal corresponding to the phase difference between the input signal and the output signal. The frequency Fo of the output signal So of the VCO 18 is controlled by the control signal output from the LPF 16 so that the signal obtained by dividing the output signal has the same frequency and phase as the input signal. The frequency dividing circuit 12 often uses a program counter capable of arbitrarily setting the frequency dividing ratio N. The frequency dividing ratio N is controlled and changed by, for example, a CPU (central processing unit, not shown). . As a result, the frequency Fo of the output signal is N times the frequency of the input signal.
[0004]
[Problems to be solved by the invention]
By the way, there are many requests to lock the phase of the output signal once, shift it by a predetermined amount, and lock the phase again. For example, when Y / C separation of a digital NTSC composite color video signal is performed, a color signal is separated by a color separation filter, and a luminance signal is obtained by subtracting the color signal from the composite color video signal. In the color signal separation processing in such a color separation filter, signal delay occurs. In a television broadcasting station, a plurality of video sources are transmitted to an editing studio via a cable (signal line) or the like, and a signal delay occurs between the plurality of signal lines. Therefore, it is necessary to adjust the phase between the plurality of signals.
[0005]
As one method for solving such a problem, there is used a method of providing a variable delay circuit for each of a plurality of signal lines and adjusting a phase between them. For example, Japanese Examined Patent Publication No. 7-112146 discloses a variable delay circuit capable of varying the delay amount using a plurality of stages of delay elements. However, a variable delay circuit using such a plurality of stages of delay elements is relatively expensive.
[0006]
If the output signal is a pulse signal or the like, it is relatively easy to delay the phase of the pulse signal with respect to the phase of a certain reference signal by using a flip-flop or the like. However, in this case, a phase shift amount shorter than one clock cannot be realized if it is a synchronous type, and an arbitrary phase shift amount cannot be realized even if it is an asynchronous type.
[0007]
Therefore, the present invention is intended to provide a phase shift oscillation circuit capable of generating a signal whose phase is shifted by an arbitrary amount with respect to a reference signal with a relatively inexpensive circuit configuration. At this time, the phase shift amount can be made shorter than one clock.
[0008]
[Means for solving the problems]
The phase shift oscillation circuit according to the present invention makes it possible to arbitrarily shift the phase of the output signal by skillfully controlling the control voltage applied to the voltage controlled oscillation means. The analog / digital converting means converts the periodically changing input signal into digital data according to the frequency of the output signal. This digital data is stored in a storage means such as a RAM. For example, the setting means includes an operation panel such as a display device, numeric keys, and arrow keys, and sets a phase shift amount indicating how much the phase of the output signal is shifted by the user with respect to the phase of the input signal. Used for. The arithmetic control means calculates the calculated value of the digital data that should be obtained when the phase of the output signal is shifted by the phase shift amount using the digital data, and the analog-digital conversion means corresponding to the calculated value The control voltage is controlled in the direction in which the actual measurement value of the digital data from the input data coincides with the calculated value. Thus, the phase of the output signal is shifted according to the phase shift amount set by the user.
[0009]
In addition, the arithmetic control means calculates a digital data calculation value that should be obtained when the phase of the output signal is shifted by the phase shift amount using the digital data previously stored in the storage means. The calculated value of an arbitrary reference point of the input signal may be calculated using the value. The calculated value of the reference point can be calculated by using a plurality of digital data. Then, using the actual measurement value of the digital data from the analog / digital conversion means, the actual measurement value of the reference point corresponding to the calculated value of the reference point is calculated, and the calculated value of the reference point and the corresponding actual measurement value are matched. The control voltage may be controlled.
[0010]
The arithmetic control means compares the measured value with the calculated value for all other digital data except the digital data generated when the phase is in the transition state where the phase is shifting, and the phase of the output signal is Control may be continued so as to be maintained in the set state. However, this increases the calculation load, and sufficient accuracy is often obtained without necessarily performing successive comparisons. Therefore, a calculated value may be calculated only for arbitrary digital data from among a plurality of digital data. This arbitrary digital data may be, for example, one (or one set) per cycle of the output signal. More specifically, the phase shift by the arithmetic control unit is performed by changing the control voltage for a predetermined time to change the frequency of the output signal of the voltage controlled oscillation unit.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. At this time, the elements corresponding to those of the prior art example will be described with the same reference numerals. The embodiments described below are preferable specific examples of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention particularly limits the present invention in the following description. As long as there is no description of the effect, it is not limited to these aspects.
[0012]
FIG. 1 is a block diagram showing an example of an embodiment of a phase shift oscillation circuit according to the present invention. The analog / digital conversion circuit (ADC) 20 receives the input signal Si and receives the output signal So at the clock (CLK) input terminal, and converts the input signal Si into digital data according to the frequency Fo of the output signal So. At this time, the input signal is, for example, a digital television signal, and the output signal is, for example, an internal clock signal. The digital data output from the ADC 20 is temporarily stored in the memory 22 and used for later-described computation in the CPU (central processing unit) 24. The memory 22 is, for example, a RAM (Random Access Memory) or a cache memory. A nonvolatile memory such as a hard disk (magnetic disk device) is also used as necessary. The digital / analog converter circuit (DAC) 26 receives a calculation result in the CPU 24 and outputs a control voltage for controlling the frequency Fo of the output signal So of the voltage controlled oscillation circuit (VCO) 18. The CPU 24 and the DAC 26 constitute a calculation control unit. The operation panel 28 is setting means including a display device, numeric input keys, cursor keys, and the like. The user can set a desired phase shift amount by using the operation panel 28.
[0013]
The address counter 30 receives and counts the output signal So at the clock (CLK) input terminal, and designates the address of the memory 22 that stores the digital data from the ADC 20. At this time, the CPU 24 treats an arbitrary predetermined number of addresses in the memory 22 (for example, 150 addresses here) as one set (one set). If digital data is stored in the two sets and the phase shift described below is not performed, the corresponding address of each set has a digital point at the corresponding point of the phase of the input signal that varies periodically. Data is stored. That is, the digital data stored at the 100th address of one set and the data stored at the 100th address of the other set are obtained by AD-converting the same phase point of the input signal into digital data It is. In other words, the CPU 24 sets, as one set of addresses, a predetermined number that satisfies this relationship according to the cycle of the input signal. Such processing is well known in digital oscilloscopes and the like, and is used to repeatedly display a corresponding waveform portion in a periodically changing input signal on a display screen.
[0014]
The phase of the output signal So of the VCO 18 is normally controlled so as to lock the phase to the feature point of the input signal set by the user. In the case of a television signal, the feature point of the input signal is, for example, a vertical synchronization signal. However, in the phase shift oscillation circuit according to the present invention, the phase of the output signal once locked to the feature point of the input signal can be further phase-shifted by an arbitrary amount as needed.
[0015]
The phase shift of the output signal So is performed by changing the control voltage supplied to the VCO 18 for a predetermined time obtained by the calculation by the CPU 24 and changing the frequency of the output signal So. FIG. 2 is an explanatory diagram of a phase shift method of the output signal So. Here, a timing chart when the ADC 20 receives the output signal So as CLK is drawn with respect to a portion where the phase shift is performed. At this time, FIG. 2A shows the case where the phase shift is performed, and FIG. 2B shows the case where the phase shift is not performed. In this example, the CPU 24 reduces the control voltage output from the DAC 26 by the time W, thereby reducing the frequency Fo of the output signal So of the VCO 18 by the time W, thereby delaying the phase of the output signal So by ΔΦ. Conversely, the phase of the output signal So can be advanced by increasing the frequency of the output signal So for a predetermined time.
[0016]
FIG. 3 is a schematic diagram illustrating the positional relationship between the input signal Si and the phase shift. The input signal is a signal that is periodically repeated with the period of time points To and Te as one cycle. At this time, the time point To which is the start point is, for example, a feature point of the input signal set by the user.
[0017]
Here, the phase relationship between the input signal Si and the output signal So at an arbitrary time point (in this example, when the ADC 20 receives 100 clocks) t1 from the start point To will be considered. FIG. 4 is a partially enlarged view of the vicinity of time t1 in FIG. In a state where the phase of the output signal is locked to the feature point of the input signal set by the user (this is referred to as state A), the ADC 20 digitally converts the input signal Si to the clock indicated by CLK-A according to the frequency of the output signal So. AD (analog / digital) conversion to data. The cycle of the output signal So is a known value determined by the control voltage, and is assumed to be 20 ns in this example. At this time, at time t1, the input signal Si is converted into digital data at the 100th clock CLK-A, for example, counted from the time To. That is, in FIG. 4, the point indicated by 100A of the input signal Si is converted into digital data and stored in the 100th address of an arbitrary address set in the memory 22. Similarly, according to the clock CLK-A, the points 99A, 101A and 102A before and after the point 100A are converted into digital data and stored in the corresponding addresses of the memory 22. If the user does not set to shift the phase of the output signal So, this operation is repeated with the period determined by the time points To and Te as one cycle, and the address corresponding to each address set in the memory 22 is input to the corresponding address. Digital data having the same phase relationship of the signal Si is stored. The point “100A” of the input signal in FIG. 4 means that the data is converted into digital data according to the clock CLK-A at the 100th position of each address set. The same applies to the clock CLK-B described later.
[0018]
Here, if the user sets the phase shift amount ΔΦ through the operation panel 28 in order to shift the phase of the output signal So, the following occurs. FIG. 4 shows an example in which the phase of the output signal So is set to be delayed by ΔΦ (16 ns in this example). In this case, the ADC 20 should AD-convert the input signal Si into digital data according to the clock CLK-B delayed by a phase difference ΔΦ (16 ns in this example) with respect to the clock CLK-A. Therefore, for example, digital data (corresponding to the point 100B of the input signal Si) AD-converted according to the clock CLK-B and stored in the 100th address of an arbitrary address set in the memory 22 is AD-converted according to the clock CLK-A. Compared with digital data (corresponding to 100A) stored in the 100th address of the other address set of the memory 22, the digital signal obtained by AD conversion of the phase delayed by ΔΦ of the input signal Si・ It should be data.
[0019]
At this time, the calculated value (calculated value) of the digital data that should be obtained corresponding to the point 100B of the input signal Si can be calculated as follows. That is, referring to the example of FIG. 4, since the digital data at the points 100A and 101A of the input signal Si are already known, it is practically possible to use linear interpolation from these digital data and the known clock period. The calculated value of the digital data corresponding to the point 100B can be obtained with a satisfactory accuracy. That is, in this example, it is calculated that the point 100B is at a position of 16 (phase shift amount) for 20 (clock period) on the line connecting the point 100A and the point 101A. Similarly, calculated values of other digital data that should be obtained when AD conversion is performed according to CLK-B can be obtained. The control voltage that the CPU 24 supplies to the VCO 18 through the DAC 26 in order to change the phase of the output signal So in the direction in which the calculated value of digital data that should be obtained in calculation is actually obtained from the ADC 20 will be described with reference to FIG. As described above, control is performed to change temporarily.
[0020]
Even if the control voltage is controlled by calculation as described above, the actual measured value of the digital data actually obtained from the ADC 20 may be slightly different from the calculated value. Further, even after the phase of the output signal So is once shifted, it is necessary to maintain the phase difference. Therefore, the CPU 24 always compares the actual measured value of the digital data obtained by performing AD conversion with the ADC 20 in accordance with the output signal So whose phase is shifted by ΔΦ, and the calculated value of the previous digital data, and compares the digital data. The control voltage supplied to the VCO 18 through the DAC 26 is constantly controlled so that the difference between the actual measurement value and the calculated value of each data is minimized. However, in the time W during which the frequency variable control shown in FIG. 2 is performed, that is, in the transition state in which the phase is shifting, the measured value is not compared with the calculated value, and is performed after the phase shift is completed. . Note that the difference between the actually measured value and the calculated value may ideally be zero when the input signal waveform is completely the same in each cycle. However, normally, the input signal waveform is not completely the same in each period, and the approximate value obtained by linear interpolation is used as the calculated value, so that the difference between the plurality of actually measured values and the calculated value is minimized. Control of the control voltage is performed.
[0021]
As described above, the comparison between the measured value and the calculated value of the digital data may be performed for all the digital data except when the phase is in the transition state where the phase is shifting. However, you may selectively implement only about arbitrary digital data. For example, when one set of addresses is 150 addresses, only the 100th digital data of each set may be compared with the actually measured value and the calculated value.
[0022]
From the calculated values of the point 99B and the point 100B of the input signal Si, a calculated value of an arbitrary reference point is further calculated using linear interpolation, and the calculated value is compared with the actually measured value of the reference point. It may be determined whether the phase is appropriately shifted, and the control voltage may be controlled accordingly. Similarly to the above, for example, when one set of addresses is 150 addresses, from the measured values of the reference points calculated from the points 100A and 101A obtained by actual measurements and the calculated values of the points 99B and 100B. It is not necessary to compare all digital data by only comparing the calculated values of the reference points.
[0023]
The reference point is, for example, a point where the input signal crosses the reference level L set by the user. Further, when the input signal is, for example, a synchronization signal of a television signal, the measured value of the reference point may be obtained by actually measuring the upper and lower levels and calculating the intermediate value thereof. If the input signal is a sine wave, the upper and lower peak values may be measured over a plurality of periods, and the intermediate value may be calculated to obtain the measured value of the reference point.
[0024]
In order to calculate these actually measured values, it is convenient to use digital data obtained by actual measurement obtained from the ADC 20 according to the clock CLK-A according to the above-described example before shifting the phase. That is, as the actual measurement value and the calculation value used for the comparison, a value obtained by calculation from the actual measurement value of the plurality of digital data and the calculation value of the plurality of digital data may be used. However, in some cases, the actually measured value may be obtained by measuring by sampling the input signal Si by providing a separate new clock.
[0025]
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and corrections can be made without departing from the gist of the present invention. It will be apparent to those skilled in the art. For example, in the above description, linear interpolation is used to calculate the calculated value. However, when the calculation is easy depending on the type of the input signal, quadratic or higher order interpolation may be used.
[0026]
As described above, the phase shift oscillation circuit according to the present invention can output a signal obtained by arbitrarily shifting the phase once locked with respect to the input signal. Moreover, since the phase shift of the output signal is performed by controlling the control voltage of the VCO, the resolution (bit width) of the DAC that supplies the control voltage to the VCO without being limited by the width of one clock. It is possible to shift the phase by an arbitrary amount according to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an embodiment of a phase shift oscillation circuit according to the present invention.
FIG. 2 is a diagram illustrating a phase shift of an output signal performed in the present invention.
FIG. 3 is an overview diagram illustrating a positional relationship between an input signal and a phase shift.
4 is a partially enlarged view of the vicinity of a time point t1 in FIG.
FIG. 5 is a block diagram of an example of a general PLL oscillation circuit.
[Explanation of symbols]
18 Voltage controlled oscillation means 20 Analog / digital conversion means 22 Storage means 24, 26 Arithmetic control means 28 Setting means (operation panel)
30 Address counter CLK-A Clock CLK-B before phase shift Clock ΔΦ after phase shift Phase shift amount Si Input signal So Output signal

Claims (4)

Voltage-controlled oscillation means for receiving the control voltage and outputting an output signal; analog-digital conversion means for converting the periodically changing input signal into digital data according to the frequency of the output signal;
Storage means for storing the digital data;
Setting means for setting a phase shift amount indicating how much the phase of the output signal is shifted with respect to the phase of the input signal;
The digital-to-analog conversion means for calculating the calculated value of the digital data that should be obtained when the phase of the output signal is shifted by the phase shift amount using the digital data, and corresponding to the calculated value A phase shift oscillating circuit comprising arithmetic control means for controlling the control voltage in a direction in which an actual measurement value of the digital data from the digital data coincides with the calculated value. Voltage-controlled oscillation means for receiving the control voltage and outputting an output signal; analog-digital conversion means for converting the periodically changing input signal into digital data according to the frequency of the output signal;
Storage means for storing the digital data;
Setting means for setting a phase shift amount indicating how much the phase of the output signal is shifted with respect to the phase of the input signal;
Calculate the calculated value of the digital data that should be obtained when the phase of the output signal is shifted by the phase shift amount using the digital data, and use the calculated value to calculate an arbitrary value of the input signal Calculate the calculated value of the reference point, calculate the measured value of the reference point corresponding to the calculated value of the reference point using the measured value of the digital data from the analog-digital conversion means, A phase shift oscillation circuit comprising arithmetic control means for controlling the control voltage in a direction in which the calculated value and the corresponding actually measured value coincide with each other. 3. The phase shift oscillation circuit according to claim 1, wherein the arithmetic control unit calculates the calculated value only for arbitrary digital data from among the plurality of digital data. The operation control means shifts the phase of the output signal by changing the control voltage for a predetermined time to change the frequency of the output signal of the voltage controlled oscillation means. 4. The phase shift oscillation circuit according to any one of 3 above.

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