JP3766278B2 - Automatic placement and routing equipment - Google Patents

Description

【００４８】
ただし、Ｎｃ₁ 、Ｎｂ、Ｌｂは右の隣接ブロックの値、α、βは定数、ｌ（英字の小文字のエル）は概略配線のとき、実際に与えられる値である。
【００４９】
ここでＣｂ＜０なら配線可能であり、絶対値が大きいほど配線コストは低い。一方Ｃｂ＞０又はＣｂ＝０なら配線できないと判断する。
【００５０】
Ｂ．ブロック内の線分を引くコスト
あるブロック内で長さｌ（英字の小文字のエル）の線分を引くコストＣｉｎは下記の式により得られる。
【００５１】
【数２】

【００５２】
ただし、Ｎｂ、Ｌｂはこのブロックの値、γは定数である。
【００５３】
ここでＣｉｎ＜０なら配線可能であり、絶対値が大きいほど配線コストは低い。一方Ｃｉｎ＞０又はＣｉｎ＝０なら配線できないと判断する。
【００５４】
迷路法やラインサーチ法の中でこれらのコストを用いて、より配線コストの低い経路を決定する。
【００５５】
図６は、図２の配線混雑度算出ステップ（ＳＢ）において、８分割されたブロックｂ₀ 〜ｂ₇ のブロックｂ₁ 、ｂ₅ 、ｂ₃ に配置されたセルＡ、Ｂ、Ｃについて、セルＡ−Ｂ、セルＢ−Ｃ間に配線するとき、セルＡ−Ｂに点線で示す如く、最短距離で配線しようとしたとき、斜線領域で示す配線混雑度の高い領域がブロックｂ₁ 、ｂ₅ 間に存在するため、実線の如く、配線した例を示す。セルＢ−Ｃ間の実線も配線混雑度の高い領域が、斜線領域で示す如く、ブロックｂ₁ 、ｂ₂ 間に存在したことを考慮して実線の如く配線した例を示す。
【００５６】
このように配置の初期の段階から、なるべく正確な配線混雑度を見積り、迂回が避けられないネットを予測できる。
【００５７】
実際に、図３に示すフローにより、図１の自動配置配線手段１の動作状態を図２の配線混雑度算出ステップ（ＳＢ）について説明する。
【００５８】
ネットリストとしては、前記の如く、セルサイズ、ブロックサイズ、セルの接続情報、タイミング制約情報等が入力される。これにより、セルがブロックに高速配置され、このセルの接続情報であるネット（セルＡの端子Ｏｕｔ、セルＢの端子Ｉｎ）・・・の如く、接続関係が得られる。また配線経路Ｐとしてはこれを構成するセグメント（Ｓｅｇ）で示され、配線経路Ｐが複数のｍ本の線分で構成されているときは、
Ｐ＝｛Ｓｅｇ１、Ｓｅｇ２・・・Ｓｅｇｍ｝
の如く示される。
【００５９】
Ｓ１．まずネットリスト２よりネットリストが入力される。
【００６０】
Ｓ２．概略配置配線手段４では、これにより、例えばミニカット法によりブロックに割り当てられたセルを高速配置する。これにより前記セルの接続関係、配線経路Ｐ等が得られる。
【００６１】
Ｓ３．概略配置配線手段４は、ネットｉ＝０を選ぶ
Ｓ４．これによりネットｉ＝０を構成する配線経路の候補Ｐ₀ が選ばれ、Ｐ₀ を構成する。
【００６２】
Ｓ５．この配線経路Ｐ₀ を構成するセグメントＳｅｇ₀ が選ばれる。
【００６３】
Ｓ６．このセグメントＳｅｇ₀ の長さｌ（英字の小文字のエル）と、その通過ブロックｂが抽出される。
【００６４】
Ｓ７．この通過ブロックに対し、前記▲１▼のブロックの境界（左あるいは上）を通過できる線分本数Ｎｃ₁ を算出する。
【００６５】
Ｓ８．同じくこの通過ブロックに対し、前記▲２▼のブロックの境界（右あるいは下）を通過できる線分本数Ｎｃ₂ を算出する。
【００６６】
Ｓ９．次にこの通過ブロックに対し、前記▲３▼のブロック内に置ける長さＬ以上の線分数Ｎｂを算出する。
【００６７】
Ｓ１０．そして前記▲４▼のこの通過ブロック内に置ける長さＬ以上の前記各線分の平均長Ｌｂを算出する。
【００６８】
Ｓ１１．それから前記Ｎｃ₁ 、Ｎｃ₂ 、Ｎｂ、Ｌｂを用い、
右に隣接するブロックに水平で長さｌ（英字の小文字のエル）の線分を引くコストＣｂ₀ は
【００６９】
【数３】

【００７０】
で示され、
左に隣接するブロックに水平で長さｌ（英字の小文字のエル）の線分を引くコストＣｂ₁ は
【００７１】
【数４】

【００７２】
で示される。
【００７３】
Ｓ１２．そして前記Ｃｂ₀ 、Ｃｂ₁ がいずれも負であれば、配線可能であると判断する。そして次のＳ１３に移行する。しかもその絶対値が大きい程配線コストは低い。しかし前記Ｃｂ₀ 、Ｃｂ₁ の少なくとも一方が正または０であれば、その正または０のものに対しては配線できないと判断する。そして前記Ｓ４に戻り、他の配線経路の候補Ｐを選ぶことになる。
【００７４】
Ｓ１３．前記Ｓ１２において、Ｃｂ₀ 、Ｃｂ₁ がいずれも負であれば、両隣りのブロックに対し配線可能であると判断し、セグメントの番号を＋１して次のセグメントを抽出する。
【００７５】
Ｓ１４．このように各セグメントに対して同様の処理を行う。そして１セグメントに対する処理が終了したとき、全セグメント（セグメント数＝ｍ）に対して処理を行ったか否かを判断する。全セグメントに対して処理が終了すれば、そのネットに対する処理が終了したものと判断し、次のネットを抽出する。
【００７６】
Ｓ１５．このようにして配線可能と判断されると、これにもとづきネットの配線が行われる。そして配線情報としてブロックに入るセルと、ネットτがどのブロックを通過するのかを示す配置、配線情報が得られる。
【００７７】
Ｓ１６．このようにして全ネットに対する処理が終了したか否か判断し、処理すべきネットが残っていれば前記Ｓ３に戻る。このようにして全ネットに対する処理が終了すれば、図２に示す配線混雑度算出ステップ（Ｓ１３）が終了する。
【００７８】
迷路法やラインサーチ法の中で前記のコストを用いてより配線コストの低い経路を決定することができる。
【００７９】
（２）概略配線経路算出ステップについて
パーティショニング配置の各カットレベルで、セルの位置は割り当てられたブロックの中心にあると仮定して、前記の如く、前記（１）の配線混雑度算出ステップにより概略配線する。
【００８０】
そしてこの経路を次のカットレベルまで保存する。次のカットレベルでは、前回よりもブロックが細かくなっており、セルの位置が違うので、概略経路を配線し直す必要がある。このとき保存していた経路を用いて次の手順で配線する。
【００８１】
ａ．図８（Ａ）で示す、保存していた前回のカットレベルでの経路を、同（Ｂ）に示す如く、ドライバ（図８の例ではＡがドライバ）をルートとする配線木で見て、端子あるいはスタイナーポイント（Ｓ）間を結ぶ経路に分割する。
【００８２】
ｂ．前記ａで求めた各経路について、その経路が属していた前回のカットレベルでのブロックの領域内で経路を引き直し、図８（Ｃ）に示す如き配線を行う。
【００８３】
すなわち図８（Ａ）に対してカットレベルを＋１して各ブロックを２分割したとき、同（Ａ）のブロックｂ₁ は同（Ｃ）のブロックｂ₁₁、ｂ₁₂に分割され、同様にブロックｂ₂ はブロックｂ₂₁、ｂ₂₂に、ブロックｂ₅ はブロックｂ₅₁、ｂ₅₂に、ブロックｂ₇ はブロックｂ₇₁、ｂ₇₂に、ブロックｂ₈ はブロックｂ₈₁、ｂ₈₂に分割される。
【００８４】
このとき端子Ａがドライバなので、これをルートとして、図８（Ｂ）に示す如き配線木を得る。なお図８（Ｂ）でＳはスタイナーポイントである。そしてこの配線木で得られた各経路について、図８（Ｃ）に示す次のカットレベルのブロックに端子やスタイナーポイントの配置、配線経路等が引き直されるが、このとき前回のカットレベルのブロック内で、これらが行われる。
【００８５】
すなわち、図８（Ａ）に示す如く、前回のカットレベルでは端子Ａはブロックｂ₂ に位置し、端子Ｂはブロックｂ₈ に位置していたので、この関係は継承され、次のカットレベルでは端子Ａはブロックｂ₂₁、ｂ₂₂のいずれかに位置され、同様に端子Ｂはブロックｂ₈₁、ｂ₈₂のいずれかに位置されるものとなる。
【００８６】
同様に、図８（Ａ）に示すブロックｂ₁ 、ｂ₅ 、ｂ₇ を通る配線は、ブロックｂ₁₁、ｂ₁₂、ｂ₅₁、ｂ₅₂、ｂ₇₁、ｂ₇₂のいずれかを通過することになる。これらのブロック領域の継承や、最短距離の配線ということから、図８（Ｃ）の如く、端子Ａ、Ｂとその間の配線が引き直されることになる。
【００８７】
実際に動作するときは、図８（Ｂ）に示す配線木は出力されないので、図９（Ａ）→（Ｂ）に示す如く、出力される。すなわち、図９（Ａ）に示す如く、前回のカットレベルでは、部分経路Ａ〜Ｂ、Ａ〜Ｓ、Ｓ〜Ｃ、Ｓ〜Ｄが存在するが、次のカットレベルでは、この配線の接続関係を保つのみならず、ブロック関係も継承された新しい端子、配線の位置で、同（Ｂ）に示す如く、配線されることになる。
【００８８】
次に図７に示すフローにより、図１の自動配置配線手段１の動作状態を、図２の概略配線経路算出ステップ（ＳＣ）について説明する。
【００８９】
Ｓ２１．最初にネット抽出用のカウンタを初期化し、カウント値を「０」にする。
【００９０】
Ｓ２２．そしてこれにより、前記図２の配線混雑度算出ステップにもとづき得られた概略配置配線情報の最初のネットを選ぶ、これにより例えば図８（Ａ）に示す如き、概略配置配線図が得られ、これを保持する。
【００９１】
Ｓ２３．このようにして保持した前回のカットレベルの経路を、図８（Ｂ）に示す如く、そのネットのドライバ（この図の例では端子Ａ）をルートとする配線木として復元する。
【００９２】
Ｓ２４．この配線木の端子Ａ、Ｂ、Ｃ、ＤまたはスタイナーポイントＳを結ぶ部分経路を、図８（Ｂ）の点線で示す如く得る。
【００９３】
Ｓ２５．各部分経路について、その経路が属していたブロックの領域内で、現在のレベルでの端子と接続するように経路を配線し直す。そして次のネットを選ぶ。
【００９４】
Ｓ２６．そして選ばれたネットに対し前記Ｓ２３以下の処理が行われる。全ネットに対しこのような経路配線が行われたとき、このステップは終了する。
【００９５】
（３）パーティショニングの途中で配線混雑度を考慮した概略配線経路を次のカットレベルに継承するステップについて
前記（１）、（２）を用いて、パーティショニングの各カットレベルで、配線混雑度を考慮した概略配線経路を次のカットレベルに継承させ自動配置配線を行う。
【００９６】
図１１は、図２のパーティショニングの途中で配線混雑度を考慮した概略配線経路を次のカットレベルに継承した実施例である。すなわち図１１（Ａ）に示す如く、ブロックｂ₁ 、ｂ₂ 、ｂ₃ 、ｂ₄ 、ｂ₅ にセルＡ、Ｃ、Ｂ及び配線経路が位置するとき、図１１（Ｂ）に示す如く、カットレベルを上げて２分割したとき、ブロックｂ₅₂の配線混雑度が大きく、これを迂回することが必要と判断されると、セルＡはブロックｂ₁ に位置し、セルＣはブロックｂ₂ に位置し、セルＢはブロックｂ₃ に位置したこと、ブロックｂ₁ はブロックｂ₁₁、ｂ₁₂に、ブロックｂ₂ はブロックｂ₂₁、ｂ₂₂、ブロックｂ₃ はブロックｂ₃₁、ｂ₃₂に分割されたこと、及び配線経路がブロックｂ₁ −ｂ₃ 及びブロックｂ₃ −ｂ₄ −ｂ₅ −ｂ₂ に位置したこと、ブロックｂ₄ はブロックｂ₄₁、ｂ₄₂に、ブロックｂ₅ はブロックｂ₅₁、ｂ₅₂に分割されたこと等が継承され、またブロックｂ₅₂の配線混雑度が大きくこれを迂回することが必要なこと等が判断されて、図１１（Ａ）に示す概略配置配線が同（Ｂ）に示す状態となる。各セルの位置決めでも前記継承が行われる。
【００９７】
次に図１０に示すフローにより、図１の自動配置配線手段１の動作状態を、図２のパーティショニングの途中で配線混雑度を考慮した概略配線経路を次のカットレベルに継承するステップ（ＳＤ）について説明する。
【００９８】
Ｓ３１．例えば図１１（Ａ）に示す概略配置配線状態を保持しているとき、分割つまりカットレベルを１レベル進める。
【００９９】
Ｓ３２．各セル（又は端子）Ａ、Ｂ、Ｃをどのブロックに置くのか決める。これによりセルＡはブロックｂ₁₂に、セルＢはブロックｂ₃₂に、セルＣはブロックｂ₂₂に位置決めされる。
【０１００】
Ｓ３３．ネット毎に、保持していた前のレベルの配線経路をもとに、概略配線を行い得られた経路を保持する。例えば初めセルＡ−Ｂ間の配線経路はブロックｂ₁ −ｂ₃ であり、セルＢ−Ｃ間の経路はブロックｂ₃ −ｂ₄ −ｂ₅ −ｂ₂ であったことをもとに、ブロックｂ₁ がブロックｂ₁₁、ｂ₁₂に分割されたこと、ブロックｂ₂ がブロックｂ₂₁、ｂ₂₂に分割されたこと、ブロックｂ₃ ブロックｂ₃₁、ｂ₃₂に分割されたこと、ブロックｂ₄ がブロックｂ₄₁、ｂ₄₂に分割されたこと、ブロックｂ₅ がブロックｂ₅₁、ｂ₅₂に分割されたことが継承される。この継承により元のブロックｂ₁ の配線経路は分割後のブロックｂ₁₁、ｂ₁₂の一方または双方を通過することが必要であり、ブロックｂ₂ の配線経路はブロックｂ₂₁、ｂ₂₂の一方または双方を通過するこが必要であり、ブロックｂ₃ の配線経路はブロックｂ₃₁、ｂ₃₂の一方または双方を通過するこが必要である。他のブロックについても同様である。またブロックｂ₅₂においては配線混雑度が大きく、迂回が必要と判断される。この結果、図１１（Ａ）に対しては次のカットレベルで同（Ｂ）に示す概略配線経路が得られ、これが保持される。
【０１０１】
Ｓ３４．このとき、規定の分割回数は終了していなかったので、再び前記Ｓ３１に戻り、図１１（Ｂ）に示す概略配線経路に対し、カットレベルが＋１された同様の処理が行われ、図１１（Ｃ）に示す概略配線経路が得られる。なお、図１１（Ｃ）ではブロックｂ₃₂₁ に大きな配線混雑度が存在したので、これを迂回した状態となる。このような処理があらかじめ規定された分割回数行われたのち終了となる。
【０１０２】
（４）パーティショニングの途中で回路のタイミングを考慮した概略配線経路を次のカットレベルに継承するステップについて、
前記（１）、（２）、（３）を用いて、パーティショニングの各カットレベルで回路のタイミングを考慮した概略配線経路を次のカットレベルに継承させて自動配置配線を行う。
【０１０３】
図１３は、図２のパーティショニングの途中で回路のタイミングを考慮した概略配線経路を次のカットレベルに継承した実施例である。図１３（Ａ）はカットが８分割のときセル（端子）ＢからセルＣへの経路が長くなり、配線遅延が大きくなりタイミング制約に違反するのでこれを防止するために同（Ｂ）に示す如く、バッファＢＦが挿入される。
【０１０４】
このバッファＢＦの挿入経路は、８分割以降のカットレベルでも、バッファＢＦとの接続関係を保つように概略配線される。図１３（Ｃ）は３２分割されたときの概略配線経路を示している。
【０１０５】
次に図１２に示すフローにより、図１の自動配置配線手段１の動作状態を、図２のパーティショニングの途中で回路のタイミングを考慮した概略配線経路を次のカットレベルに継承するステップ（ＳＥ）について説明する。
【０１０６】
Ｓ４１．分割を１レベル進める。
【０１０７】
Ｓ４２．前のカットレベルで、ネットの長さによりタイミングクリティカルと認識されたネットの配線長が短くなるように、各セルを分割されたどのブロックに置くのか決める。
【０１０８】
Ｓ４３．ネット毎に保持していた前のレベルの配線経路をもとに、概略配線を行い、得られた経路を保持する。
【０１０９】
Ｓ４４．この得られた概略経路からタイミングのクリティカルなネットを認識し、タイミングのクリティカルなネットに対してはバッファを挿入する。
【０１１０】
Ｓ４５．このとき規定の分割回数が終了しているか否かを判断し、終了していなければ前記Ｓ４１に戻り、規定回数に達していれば終了する。
【０１１１】
（５）配置終了後、配置フェーズで得られた概略配置配線結果から詳細配線するステップについて
前記（１）、（２）、（３）、（４）を用いて得られた概略配置配線結果より詳細配線を行う。例えば図１５（Ａ）に示す如く、配置フェーズ終了時点で得られた概略配線に対し、例えば迷路法等の手法により詳細配線を行い、同（Ｂ）に示す如き、詳細配線経路を得るものである。
【０１１２】
次に図１４に示すフローにより、図１の自動配置配線手段１の動作状態を、図２の配置終了後、配置フェーズで得られた概略配線結果から詳細配線を行うステップ（ＳＦ）について説明する。
【０１１３】
Ｓ５１．前記（１）、（２）、（３）、（４）の手法によりセル（端子）を配置し、概略配線する。これにより、例えば図１５（Ａ）に示す如き概略配置配線経路が得られる。
【０１１４】
Ｓ５２．次にこの概略配置配線経路に対し、例えば迷路法により詳細配線を行い、図１５（Ｂ）に示す如き、詳細配線経路を得る。
【０１１５】
Ｓ５３．それから各ネットに対してタイミング解析を行う。
【０１１６】
Ｓ５４．タイミング解析の結果がタイミング制約を満たすものでなければ前記Ｓ５１、Ｓ５２に戻り概略配置配線あるいは詳細配線を再び行うことになる。そしてタイミング制約を満たすものであれば、本発明にかかる配置配線処理が終了する。
【０１１７】
このように本発明によれば、従来の方式でみられた配置フェーズで生成される配線パターンと、配線フェーズで生成される配線パターンが異なるために配置フェーズにおけるタイミング最適化が効率よく行われないという問題点が解決される。
【０１１８】
また配線経路を継承するために、最適化の方向が安定し、配置配線フローの収束性を高めることができる。
【０１１９】
本発明では、配置フェーズで行う概略配線において、仮配置を行うことにより混雑度の見積り精度を上げ、また配置初期段階の経路を継承することにより、実際の配線結果とより近いものになるようにする。また、配置の段階でクリティカルネットと認識した場合には、配置の工夫でクリティカルネットの配線長を短くするようにする。これらの処理により、従来方式で問題となっている、詳細配線後のタイミング解析から配線あるいは配置フェーズへの手戻りを減らすことができる。
【０１２０】
本発明の実施の態様を下記に付記する。
【０１２１】
（付記１）セルの配置にパーティショニングを用いる自動配置配線装置において、パーティショニング配置の各カットレベルでブロックに割り当てられたセルを高速な配置手法で仮配置する手段と、隣接ブロックとの境界を通過できる線分本数Ｎｃを算出する手段と、ブロック内に置くことのできる所定長さ以上の線分数Ｎｂを算出する手段と、前記所定長さ以上の線分数の平均長Ｌｂを算出する手段と、前記境界を通過できる線分本数Ｎｃと、所定長さ以上の線分数Ｎｂと、平均長Ｌｂにもとづき配線混雑度を算出する手段とを具備し、配線混雑度を見積り、概略配線を行うことを特徴とする。
【０１２２】
（付記２）セルの配置にパーティショニングを用いる自動配置配線装置において、パーティショニング配置の各レベルで、ネットの概略配線経路を保存する手段と、このネットの配線の接続関係を示す配線木を作成する手段と、この配線木の端子またはスタイナーポイントを結ぶ部分経路を得る手段と、各部分経路について、その経路が属していたブロックの領域内で現在のカットレべルでその端子と接続するように経路を配線し直す手段とを具備し、保存していた経路が通過したブロックの領域内で概略配線を行うことを特徴とする。
【０１２３】
（付記３）セルの配置にパーティショニングを用いる自動配置配線装置において、前の分割レベルで得られた経路を保持する手段と、分割レベルを＋１する手段と、各セルをどのブロックに置くのかを決める手段を具備し、ネット毎に、保持していた前のレベルの配線経路をもとにして概略配線を行い、配線混雑度と、保持していた経路が通過したブロックの領域内を通る経路を保持することを特徴とする。
【０１２４】
（付記４）セルの配置にパーティショニングを用いる自動配置配線装置において、前の分割レベルで得られた経路を保持する手段と、タイミングクリティカル・ネットを検出する手段と、分割レベルを＋１する手段と、前のレベルの配線結果からタイミングクリティカル・ネットを検出し、そのネットについて配線長を短くするように各セルをどのブロックに置くのか決めるとともに、タイミングクリティカル・ネットに対してはバッファを挿入する手段を具備し、ネット毎に、保持していた前のレベルの配線経路をもとに概略配線を行い、配線混雑度と、保持していた経路が通過したブロックの領域内を通る経路を保持することを特徴とする。
【０１２５】
（付記５）前記（付記３）において、概略配置配線を行いその配線結果を保持する手段と、詳細配線を行う手段を具備し、概略配置配線を行い、その配線結果を継承して詳細配線を行うことを特徴とする。
【０１２６】
（付記６）前記（付記３）、（付記４）により概略配置配線を行いその結果を保持する手段と、詳細配線を行う手段を具備し、この概略配置配線を継承して詳細配線を行うことを特徴とする。
【０１２７】
【発明の効果】
本発明により、下記の効果を奏することができる。
【０１２８】
（１）隣接ブロックとの境界を通過できる線分本数Ｎｃと、ブロック内に置くことのできる所定長さ以上の線分数Ｎｂと、この所定長さ以上の線分数の平均長Ｌｂにもとづき配線混雑度を求めてこれにもとづき概略配線を行うので、概略配線を精度よく行うことができる。
【０１２９】
（２）ネットの配線の接続関係を示す配線木を使用し、その接続関係を継承して部分経路を得るので、接続関係を正確に示すとともに、その端子がドライバであるのかを正確に認識できるので、タイミング制約の対処が正しくできる。
【０１３０】
（３）ブロックの分割レベルを＋１したときパーティショニングの途中で前のレベルの配線経路をもとに、配線混雑度を考慮して概略配線を行うことができるので、配線混雑度の大きい領域を避けて概略配線経路を定めることができるので、配線手戻りを避けることができる。
【０１３１】
（４）前のレベルの配線結果からタイミングクリティカル・ネットを検出し、このネットについては配線長を短くするようにセルの位置を決めたり、バッファの挿入を行うことができるので、配線手戻りを避けることができる。
【０１３２】
（５）配線混雑度や前回の経路の属していたブロックの領域内に現在のレベルでの端子接続をもとにして概略配線し、詳細配線するので、配線手戻りを避けて、短時間で自動配置配線可能なものを提供することができる。
【図面の簡単な説明】
【図１】本発明の概略構成図である。
【図２】本発明を適用した自動配置配線装置の動作説明図である。
【図３】本発明の配線混雑度算出状態説明図である。
【図４】ブロックの境界を通過できる線分の本数説明図である。
【図５】長さＬ以上の線分が置かれる領域説明図である。
【図６】配線混雑度を使用した配線状態説明図である。
【図７】本発明の概略配線経路配線手順説明図である。
【図８】概略配線経路手順の具体的説明図である。
【図９】概略配線経路配線手順を使用した配線状態説明図である。
【図１０】本発明の概略配線経路継承手順説明図である。
【図１１】配線混雑度を考慮した概略配線経路継承作成状態説明図である。
【図１２】本発明のタイミングを考慮した概略配線経路継承手順説明図である。
【図１３】タイミング考慮概略配線経路継承作成状態説明図である。
【図１４】詳細配線手順説明図である。
【図１５】詳細配線作成状態説明図である。
【図１６】従来の自動配置配線方式説明図である。
【図１７】迂回発生状態説明図である。
【符号の説明】
１ 自動配置配線手段
２ ネットリスト
３ 配置配線出力保持部
４ 概略配置配線手段
５ 詳細配置配線手段
６ 切換手段[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI automatic placement and routing apparatus, and more particularly, to an apparatus capable of keeping timing constraints with a short TAT (Turn Around Time) so that rework does not occur many times.
[0002]
[Prior art]
Recently, when an LSI chip, that is, a cell is positioned on a substrate, the automatic placement and routing apparatus is used for automatic positioning and wiring. By the way, in recent years, due to a remarkable improvement in the degree of circuit integration, it is difficult to keep the timing constraint with the conventional method, and there is a problem that TAT becomes long because rework occurs many times.
[0003]
In the conventional general automatic placement and routing method, as shown in FIG. 16, the cells are arranged on the substrate for rough wiring and detailed wiring, and then the timing analysis, that is, the wiring is too long and the signal is transmitted within a predetermined time. If the timing is too long, placement and wiring were performed again.
[0004]
In other words, in the conventional method, there are a placement phase in which the cell positions are finely divided and a wiring (schematic wiring that determines the approximate connection route, the number of connection lines that can pass between adjacent blocks, and detailed wiring that determines the three-dimensional wiring state) phase. Wiring is done after separation and placement. Then, after the wiring is completed, the timing is analyzed by a known timing analysis tool, and when the timing constraint that the signal is not transmitted within the specified time is violated, that is, when the timing No in FIG. Rework occurs.
[0005]
As recently, the degree of circuit integration has improved, and the influence of circuit delay on circuit timing has become dominant. Therefore, in the case shown in FIG. 16, it is essential to optimize the timing from the initial stage of placement and routing.
[0006]
The timing optimization in the placement phase is that the terminal of the net belongs to the specified net or a net that is determined to be timing critical, that is, the signal delay time exceeds the specified time from the approximate wiring length during placement. A common method is to place cells close to each other or perform processing such as gate sizing or buffer insertion.
[0007]
Also, in the rough / detailed routing phase, techniques such as creating a topology that minimizes the delay for timing critical nets that violate timing constraints, that is, changing the connection relationship or inserting a buffer are used. Yes.
[0008]
[Problems to be solved by the invention]
By the way, as shown in FIG. 16, in the case where timing driven placement and routing is performed by the conventional automatic placement and routing method, that is, when the direction of placement and routing is determined in consideration of timing, in the placement phase, an accurate wiring congestion degree is obtained. Therefore, a route different from the route obtained in the wiring phase may be output.
[0009]
For example, as shown in FIG.₁-T₂In the case of wiring between them, a non-routable area R that cannot be wired due to restrictions such as RAM in the block.₁, R₂, R_ThreeWhen there is a net that cannot be avoided in the routing phase, as shown by the dotted line in the schematic routing in the placement phase, the terminal T₁-T₂Since the shortest path LB is drawn between them, the shortest path LB is not recognized as a critical net, and timing optimization is not performed.
[0010]
However, the route in the wiring phase is a route LA indicated by a solid line in FIG. If this route LA violates the timing, means such as buffer insertion are required, but buffer insertion becomes a difficult problem due to the restriction that the placement is complete and other wirings exist, and the placement is difficult. A return may occur.
[0011]
However, if the above-described net is recognized as a timing critical net in the placement phase and a buffer is inserted, there is a possibility that rework in the placement phase can be reduced from the wiring phase.
[0012]
Accordingly, an object of the present invention is to provide an automatic placement and routing apparatus for improving the above problems.
[0013]
[Means for Solving the Problems]
A principle diagram of the present invention is shown in FIG. In FIG. 1, 1 is an automatic placement and routing unit, 2 is a net list, 3 is a placement and routing output holding unit, 4 is a schematic placement and routing unit, 5 is a detailed placement and routing unit, and 6 is a switching unit.
[0014]
  The object of the present invention is as follows (1) to(4)Can be achieved.
[0015]
(1) In an automatic placement and routing apparatus that uses partitioning for cell placement, the cells assigned to the blocks at each cut level of partitioning placement are temporarily placed by means of a high-speed placement method and the boundary between adjacent blocks. Means for calculating the number of line segments Nc, means for calculating the number of line segments Nb greater than or equal to a predetermined length that can be placed in the block, means for calculating the average length Lb of the number of line segments greater than or equal to the predetermined length, A line segment number Nc that can pass through the boundary, a line segment number Nb that is equal to or longer than a predetermined length, and a means for calculating a wiring congestion degree based on the average length Lb are provided, and the wiring congestion degree is estimated and rough wiring is performed. Features.
[0016]
  (2) In an automatic placement and routing apparatus that uses partitioning for cell placement, a means for preserving the net wiring route at each cut level of the partitioning placement and a wiring tree indicating the connection relation of the net wiring are created. Means for obtaining a partial wiring path connecting terminals or Steiner points of this wiring tree, and for each partial wiring path,Wiring pathMeans to reroute the path to connect to its terminal at the current cut level within the area of the block to whichMeans for determining in which block each cell is placed, and upon receiving an instruction to change the cut level, means for holding the wiring path obtained at the current cut level as the wiring path of the previous cut level, When changing to the next cut level based on the contents of the change, rough wiring is performed based on the previous level wiring route that has been held, the wiring congestion degree, and the block area that the held route has passed And means for inheriting the general wiring path to the next cut level so as to hold the path passing through the inside.
[0017]
  (3) In an automatic placement and routing apparatus that uses partitioning for cell placement,
  At each cut level of the partitioning arrangement, a means for storing the schematic wiring path of the net, a means for creating a wiring tree indicating the connection relation of the wiring of the net, and a partial path connecting the terminals or Steiner points of the wiring tree are provided. Means for obtaining, for each partial wiring path, means for re-wiring the wiring path so as to connect to the terminal at the current cut level within the area of the block to which the wiring path belonged, means for detecting the timing critical net When the instruction to change the cut level is received, the means for holding the wiring route obtained at the current cut level as the previous cut level, the next cut level is changed based on the change contents, and the previous The timing critical net is detected from the result of routing at the cut level and the wiring length is shortened for that net. To determine which block each cell is placed in, and to insert a buffer for the timing critical net, and to inherit the rough wiring path considering the circuit timing during the partitioning to the next cut level, It is comprised from these.
[0018]
  (4)In the above (2), characterized in that it comprises means for carrying out schematic arrangement and holding the result of wiring and means for carrying out detailed wiring, performing schematic arrangement and wiring, and performing detailed wiring by inheriting the wiring result. To do.
[0020]
As a result, the following effects can be obtained.
[0021]
(1) Congestion of wiring based on the number Nc of line segments that can pass through the boundary with an adjacent block, the number of line segments Nb that is greater than or equal to a predetermined length that can be placed in the block, and the average length Lb of the number of line segments that are greater than or equal to this predetermined length Since the degree is determined and the rough wiring is performed based on this, the rough wiring can be performed with high accuracy.
[0022]
(2) Since a partial route is obtained by using a wiring tree indicating the connection relation of the net wiring and inheriting the connection relation, it is possible to accurately indicate the connection relation and accurately recognize whether the terminal is a driver. Therefore, timing constraints can be dealt with correctly.
[0023]
(3) When the division level of the block is incremented by 1, rough wiring can be performed in consideration of the wiring congestion degree based on the wiring path of the previous level in the middle of the partitioning. By avoiding this, it is possible to determine a schematic wiring route, so that wiring rework can be avoided.
[0024]
(4) The timing critical net is detected from the previous level wiring result, and the cell position and buffer insertion can be performed for this net so as to shorten the wiring length. Can be avoided.
[0025]
(5) Wiring is performed roughly in the block area to which the previous route belonged based on the current level terminal connection, and detailed wiring is performed. What can be automatically placed and routed can be provided.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIG. 1 and based on FIGS. 1 is a schematic configuration diagram of the present invention, FIG. 2 is an operation explanatory diagram of an automatic placement and routing apparatus to which the present invention is applied, FIG. 3 is an explanatory diagram of a wiring congestion degree calculation state of the present invention, and FIG. 4 can pass through a block boundary. FIG. 5 is an explanatory diagram of a region where a line segment having a length of L or more is placed, FIG. 6 is an explanatory diagram of a wiring state using the wiring congestion degree, and FIG. 7 is a schematic wiring route wiring procedure of the present invention. FIG. 8 is a specific explanatory diagram of the schematic wiring route procedure of the present invention, FIG. 9 is an explanatory diagram of the wiring state using the schematic wiring route wiring procedure, and FIG. 10 is an explanatory diagram of the schematic wiring route inheritance procedure of the present invention, FIG. 11 is an explanatory diagram of a schematic wiring route inheritance creation state in consideration of the degree of wiring congestion, FIG. 12 is an explanatory diagram of a schematic wiring route inheritance procedure in consideration of the timing of the present invention, and FIG. 14 is an explanatory diagram of the detailed wiring procedure of the present invention, and FIG. It is a line created state illustration.
[0027]
In FIG. 1, 1 is an automatic placement and routing unit, 2 is a net list, 3 is a placement and routing output holding unit, 4 is a schematic placement and routing unit, 5 is a detailed placement and routing unit, and 6 is a switching unit.
[0028]
The automatic placement and routing means 1 temporarily arranges cells assigned to a block according to the cell size, block size, cell connection state, timing constraint information, etc. input from the netlist 2, The connection path between the two is roughly arranged, a buffer is inserted, and detailed wiring is performed from the result of the roughly arranged wiring. The automatic placement and routing unit 1 includes a schematic placement and routing unit 4, a detailed placement and routing unit 5, a switching unit 6 and the like, and is configured by a processor.
[0029]
The netlist 2 is netlist information such as substrate size, physical information for each of a plurality of cells (vertical / horizontal size), connection information of each cell, physical constraint information of an arrangement position of a power supply or a RAM, timing constraint information, etc. Is input to the automatic placement and routing means 1.
[0030]
The placement and routing output holding unit 3 holds detailed wiring information or schematic placement and routing information output from the automatic placement and routing means 1.
[0031]
The rough placement and routing unit 4 calculates the wiring congestion level based on the data input from the net list 2, calculates the rough wiring route, and inherits the rough wiring route considering the wiring congestion level to the next cut level. In addition, a schematic wiring path considering circuit timing is inherited to the next cut level.
[0032]
The detailed placement and routing means 5 performs detailed placement and routing based on the schematic placement and routing path.
[0033]
The switching means 6 selectively switches whether the output of the general placement and routing means 4 is output to the detailed placement and routing means 5 or to the placement and routing output holding unit 3.
[0034]
The operation of the automatic placement and routing apparatus of the present invention shown in FIG. 1 will be described in detail with reference to FIG.
[0035]
As shown in FIG. 2, the automatic placement and routing apparatus of the present invention is configured so that the net list input step (SA), the wiring congestion degree calculating step (SB), the rough wiring route calculating step (SC), and the wiring congestion degree during the partitioning. A step (SD) of inheriting the considered schematic wiring path to the next cut level (SD), a step of inheriting the schematic wiring path considering the circuit timing during the partitioning to the next cut level (SE), and the placement after the placement An operation such as a step (SF) of performing detailed wiring from the rough wiring result obtained in the phase is performed.
[0036]
(1) About the wiring congestion degree calculation step
A net list is input from the net list holding unit 2. The rough placement means 4 uses a well-known partitioning technique for the placement of cells, divides the placement area into 2, 4, 8,..., And places the cells in each block divided at each division phase, that is, at the cut level. In order to determine the detailed position of the cell, the cell is temporarily arranged.
[0037]
As a temporary placement method, for example, a mini-cut method is used in which partitioning placement is performed such that placement is possible within the range permitted by the timing, but the optimization is relaxed and placement is performed at high speed.
[0038]
When the temporary placement of cells is determined by this high-speed placement method, the wiring congestion degree of each block is calculated for each wiring layer. The wiring congestion degree is represented by a set of the following four values.
[0039]
▲ 1 ▼ Nc₁: Number of line segments that can pass through the block boundary (left or top)
(2) Nc₂: Number of line segments that can pass through the block boundary (right or bottom)
(3) Nb: Number of line segments longer than length L that can be placed in the block
(4) Lb: Average length of a line segment of length L or more that can be placed in the block
However, the direction of the line segments that can be placed on each layer is either horizontal or vertical.
[0040]
As shown in FIG. 4, the target block for which the degree of wiring congestion is calculated is B₀And the adjacent block is B₁, B₂When the area D is viewed from the boundary of the block, the number of line segments that can be placed in the area is the number Nc of line segments that can pass through the boundary of the blocks (1) and (2).₁, Nc₂And
[0041]
That is, block B₀And B₁At the boundary of cell C₁~ C_Five, C₆~ C_TenNc is calculated from the size of the passable area obtained by these arrangement relations and the width of the line segment that can pass through.₁= 4. Similarly Nc₂= 6. In this way, block B₀And B₁In between₁~ L_FourIt is possible to place a wire segment of the block B₀And B₂In between_Five~ L_TenIt can be seen that it is possible to place the wiring line segments. Further, if there is a non-wiring area such as a power source in the block, the passable area is determined by excluding this area.
[0042]
In addition, as shown in FIG.₁~ C₁₈Is placed in this block B, the line segment l of length L or more₁~ L₁₂Is determined, and the number of the line segments that can be placed thereon is counted to obtain Nb of (3). In the example of FIG. 5, Nb = 12.
[0043]
At this time, line segment l₁~ L₁₂By examining the respective lengths of these and calculating the average thereof, Lb of (4) can be obtained.
[0044]
Using the above four values, rough wiring (mainly between blocks) is performed in consideration of wiring congestion. The rough wiring is performed using a known wiring method such as a maze method or a line search method so that a detour route can be searched when the wiring is congested.
[0045]
At this time, the Nc₁, Nc₂, Nb, and Lb are used to calculate the next cost.
[0046]
A. Cost of drawing line segments between blocks
The cost of drawing a line segment of length l (lowercase letter L) from one block to the adjacent block on the top and bottom or left and right, for example, horizontally to the right adjacent block of length l (letter of lowercase letter L) The cost Cb for drawing a line segment is obtained by the following equation.
[0047]
[Expression 1]

[0048]
However, Nc₁, Nb, and Lb are values of the adjacent block on the right, α and β are constants, and l (a letter L in English letters) is a value that is actually given for rough wiring.
[0049]
If Cb <0, wiring is possible, and the larger the absolute value, the lower the wiring cost. On the other hand, if Cb> 0 or Cb = 0, it is determined that wiring is impossible.
[0050]
B. The cost of drawing a line segment in a block
A cost Cin for drawing a line segment having a length l (a lowercase letter L) in a certain block is obtained by the following equation.
[0051]
[Expression 2]

[0052]
However, Nb and Lb are values of this block, and γ is a constant.
[0053]
If Cin <0, wiring is possible, and the larger the absolute value, the lower the wiring cost. On the other hand, if Cin> 0 or Cin = 0, it is determined that wiring is impossible.
[0054]
Using these costs in the maze method and the line search method, a route with a lower wiring cost is determined.
[0055]
FIG. 6 shows the block b divided into eight in the wiring congestion degree calculation step (SB) of FIG.₀~ B₇Block b₁, B_Five, B_ThreeWhen the cells A, B, and C arranged in the cell A-B and the cell B-C are wired between the cells A-B and B-C, as shown by the dotted line, the cells A-B are shown by hatched areas when trying to wire at the shortest distance. Area with high wiring congestion is block b₁, B_FiveAn example of wiring is shown as a solid line because it exists in between. As shown by the hatched area, the solid line between the cells B and C has a high wiring congestion area.₁, B₂An example of wiring as shown by a solid line in consideration of the existence between them is shown.
[0056]
In this way, it is possible to estimate the degree of wiring congestion as accurate as possible from the initial stage of placement and predict a net that cannot be avoided.
[0057]
Actually, the operation state of the automatic placement and routing means 1 of FIG. 1 will be described with reference to the flow shown in FIG. 3 in the wiring congestion degree calculation step (SB) of FIG.
[0058]
As described above, the cell size, block size, cell connection information, timing constraint information, and the like are input as the net list. As a result, the cells are arranged at high speed in the block, and a connection relationship is obtained like a net (terminal Out of cell A, terminal In of cell B)... The wiring path P is indicated by a segment (Seg) constituting the wiring path P. When the wiring path P is configured by a plurality of m line segments,
P = {Seg1, Seg2,... Segm}
It is shown as follows.
[0059]
S1. First, a net list is input from net list 2.
[0060]
S2. In this way, the rough placement and routing unit 4 places the cells assigned to the blocks at a high speed by, for example, the mini-cut method. Thereby, the connection relation of the cells, the wiring path P, and the like are obtained.
[0061]
S3. The rough placement and routing unit 4 selects the net i = 0.
S4. As a result, the candidate P of the wiring path constituting the net i = 0₀Is selected and P₀Configure.
[0062]
S5. This wiring path P₀Segment Seg that composes₀Is selected.
[0063]
S6. This segment Seg₀And the passage block b is extracted.
[0064]
S7. The number Nc of line segments that can pass through the boundary (left or top) of the block (1) with respect to this passing block₁Is calculated.
[0065]
S8. Similarly, for this passing block, the number Nc of line segments that can pass through the block boundary (right or bottom) of (2) above.₂Is calculated.
[0066]
S9. Next, for this passing block, a line segment number Nb having a length L or more that can be placed in the block (3) is calculated.
[0067]
S10. Then, the average length Lb of each line segment that is not less than the length L that can be placed in this passing block of (4) is calculated.
[0068]
S11. Then said Nc₁, Nc₂, Nb, Lb,
Cost Cb for drawing a line segment of length l (English letter lowercase el) horizontally on the right adjacent block₀Is
[0069]
[Equation 3]

[0070]
Indicated by
Cost Cb for drawing a horizontal line segment of length l (English letter lower case el) to the block on the left₁Is
[0071]
[Expression 4]

[0072]
Indicated by
[0073]
S12. And Cb₀, Cb₁If both are negative, it is determined that wiring is possible. Then, the process proceeds to next S13. Moreover, the larger the absolute value, the lower the wiring cost. But the Cb₀, Cb₁If at least one of these is positive or 0, it is determined that wiring is not possible for that positive or 0. Then, returning to S4, another wiring route candidate P is selected.
[0074]
S13. In S12, Cb₀, Cb₁If both are negative, it is determined that wiring is possible for both adjacent blocks, and the segment number is incremented by 1 to extract the next segment.
[0075]
S14. In this way, the same processing is performed for each segment. When processing for one segment is completed, it is determined whether or not processing has been performed for all segments (number of segments = m). If the processing is completed for all the segments, it is determined that the processing for the net has been completed, and the next net is extracted.
[0076]
S15. When it is determined that wiring is possible in this way, net wiring is performed based on this. Then, as the wiring information, the arrangement and wiring information indicating the cells entering the block and the block through which the net τ passes are obtained.
[0077]
S16. In this way, it is determined whether or not the processing for all nets has been completed. If there are any nets to be processed, the process returns to S3. When the processing for all nets is completed in this way, the wiring congestion degree calculating step (S13) shown in FIG. 2 is completed.
[0078]
In the maze method or the line search method, a route having a lower wiring cost can be determined by using the cost.
[0079]
(2) About rough wiring route calculation step
Assuming that the cell position is at the center of the assigned block at each cut level of the partitioning arrangement, the wiring is roughly performed by the wiring congestion degree calculating step (1) as described above.
[0080]
This route is then saved to the next cut level. At the next cut level, the block is finer than the previous one, and the position of the cell is different. Therefore, it is necessary to reroute the rough route. Wiring is performed in the following procedure using the route saved at this time.
[0081]
a. As shown in FIG. 8B, the route at the previous cut level stored in FIG. 8A is viewed with a wiring tree rooted at the driver (A in the example of FIG. 8). Divide into routes connecting terminals or Steiner points (S).
[0082]
b. For each route obtained in a, the route is redrawn within the block area at the previous cut level to which the route belonged, and wiring as shown in FIG. 8C is performed.
[0083]
That is, when each block is divided into two by adding +1 to the cut level with respect to FIG. 8A, the block b of FIG.₁Is the block b of (C)₁₁, B₁₂And block b as well₂Is block b_{twenty one}, B_{twenty two}And block b_FiveIs block b₅₁, B₅₂And block b₇Is block b₇₁, B₇₂And block b₈Is block b₈₁, B₈₂It is divided into.
[0084]
At this time, since the terminal A is a driver, a wiring tree as shown in FIG. In FIG. 8B, S is a Steiner point. Then, for each path obtained by this wiring tree, the arrangement of terminals and Steiner points, the wiring path, etc. are redrawn to the next cut level block shown in FIG. 8C. These are done within.
[0085]
That is, as shown in FIG. 8A, the terminal A is in the block b at the previous cut level.₂And terminal B is in block b₈This relationship is inherited because the terminal A is in the block b at the next cut level._{twenty one}, B_{twenty two}Similarly, the terminal B is connected to the block b.₈₁, B₈₂It will be located in either.
[0086]
Similarly, the block b shown in FIG.₁, B_Five, B₇The wiring that passes through the block b₁₁, B₁₂, B₅₁, B₅₂, B₇₁, B₇₂Will pass either. Since these block areas are inherited and the wiring is the shortest distance, the terminals A and B and the wiring between them are redrawn as shown in FIG.
[0087]
When actually operating, since the wiring tree shown in FIG. 8B is not output, it is output as shown in FIGS. 9A to 9B. That is, as shown in FIG. 9A, partial paths A to B, A to S, S to C, and S to D exist at the previous cut level, but this wiring connection relation at the next cut level. As shown in FIG. 5B, wiring is performed at the position of the new terminal and wiring inheriting the block relationship.
[0088]
Next, the operation state of the automatic placement and routing unit 1 shown in FIG. 1 will be described with reference to the flow shown in FIG. 7 in the schematic wiring path calculation step (SC) shown in FIG.
[0089]
S21. First, a net extraction counter is initialized and the count value is set to “0”.
[0090]
S22. Then, the first net of the schematic layout and wiring information obtained based on the wiring congestion degree calculation step of FIG. 2 is selected, thereby obtaining a schematic layout and wiring diagram as shown in FIG. Hold.
[0091]
S23. As shown in FIG. 8B, the previous cut level path held in this way is restored as a wiring tree whose root is the driver of the net (terminal A in this example).
[0092]
S24. A partial path connecting the terminals A, B, C, D or Steiner point S of the wiring tree is obtained as shown by the dotted line in FIG.
[0093]
S25. For each partial path, reroute the path to connect to the terminal at the current level within the area of the block to which the path belonged. Then select the next net.
[0094]
S26. Then, the processing from S23 onward is performed on the selected net. When such route wiring is performed for all nets, this step ends.
[0095]
(3) About the step of inheriting the rough wiring route considering the degree of wiring congestion during the partitioning to the next cut level
Using the above (1) and (2), at each cut level of partitioning, the automatic wiring is performed by inheriting the rough wiring route considering the wiring congestion degree to the next cut level.
[0096]
FIG. 11 shows an embodiment in which the schematic wiring path considering the wiring congestion degree is inherited to the next cut level during the partitioning of FIG. That is, as shown in FIG.₁, B₂, B_Three, B_Four, B_FiveWhen the cells A, C, B and the wiring path are located in the block b, when the cut level is increased and divided into two as shown in FIG.₅₂If it is determined that it is necessary to bypass this, the cell A is in block b.₁Cell C is in block b₂Cell B is in block b_ThreeLocated in block b₁Is block b₁₁, B₁₂And block b₂Is block b_{twenty one}, B_{twenty two}, Block b_ThreeIs block b₃₁, B₃₂And the wiring route is block b.₁-B_ThreeAnd block b_Three-B_Four-B_Five-B₂Located in block b_FourIs block b₄₁, B₄₂And block b_FiveIs block b₅₁, B₅₂Is inherited, and block b₅₂It is determined that the degree of wiring congestion is large and it is necessary to bypass this, and the schematic layout wiring shown in FIG. 11A is in the state shown in FIG. The inheritance is also performed in positioning of each cell.
[0097]
Next, according to the flow shown in FIG. 10, the operation state of the automatic placement and routing unit 1 in FIG. ).
[0098]
S31. For example, when the schematic arrangement and wiring state shown in FIG. 11A is maintained, the division, that is, the cut level is advanced by one level.
[0099]
S32. Decide on which block each cell (or terminal) A, B, C is to be placed. This causes cell A to block b₁₂Cell B is block b₃₂Cell C is block b_{twenty two}Is positioned.
[0100]
S33. For each net, a route obtained by performing rough wiring is held based on the previous level wiring route held. For example, the wiring path between the cells A and B is initially a block b.₁-B_ThreeAnd the path between cells B-C is block b_Three-B_Four-B_Five-B₂Based on what was, block b₁Is block b₁₁, B₁₂Divided into blocks b₂Is block b_{twenty one}, B_{twenty two}Divided into blocks b_ThreeBlock b₃₁, B₃₂Divided into blocks b_FourIs block b₄₁, B₄₂Divided into blocks b_FiveIs block b₅₁, B₅₂It is inherited that it was divided. By this inheritance, the original block b₁The wiring path of the block b after the division₁₁, B₁₂Pass through one or both of the blocks b₂The wiring route is block b_{twenty one}, B_{twenty two}Must pass through one or both of the blocks b_ThreeThe wiring route is block b₃₁, B₃₂Of one or both of them. The same applies to the other blocks. Block b₅₂In, the degree of wiring congestion is large and it is determined that detouring is necessary. As a result, the schematic wiring path shown in FIG. 11B is obtained at the next cut level with respect to FIG.
[0101]
S34. At this time, since the prescribed number of divisions has not ended, the process returns to S31 again, and the same processing in which the cut level is incremented by 1 is performed on the schematic wiring path shown in FIG. 11B. The schematic wiring path shown in C) is obtained. In FIG. 11C, block b₃₂₁Since there is a large degree of wiring congestion, the state is bypassed. After such a process is performed a predetermined number of divisions, the process ends.
[0102]
(4) Regarding the step of inheriting the schematic wiring path considering the circuit timing during the partitioning to the next cut level,
Using the above (1), (2), and (3), automatic placement and routing is performed by inheriting a schematic wiring path in consideration of circuit timing at each cut level of partitioning to the next cut level.
[0103]
FIG. 13 shows an embodiment in which the schematic wiring path considering the circuit timing is inherited to the next cut level during the partitioning of FIG. FIG. 13 (A) shows the path from the cell (terminal) B to the cell C when the cut is divided into eight, and the wiring delay becomes large and the timing constraint is violated. Thus, the buffer BF is inserted.
[0104]
The insertion path of the buffer BF is roughly wired so as to maintain the connection relationship with the buffer BF even at cut levels of 8 divisions or later. FIG. 13C shows a schematic wiring path when divided into 32 parts.
[0105]
Next, according to the flow shown in FIG. 12, the operation state of the automatic placement and routing means 1 in FIG. 1 is transferred to the next cut level (SE) in which the schematic wiring path taking the circuit timing into consideration during the partitioning in FIG. ).
[0106]
S41. Advance the division one level.
[0107]
S42. In the previous cut level, it is determined in which block each cell is placed so that the wiring length of the net recognized as timing critical is shortened by the length of the net.
[0108]
S43. Schematic wiring is performed based on the previous level wiring route held for each net, and the obtained route is held.
[0109]
S44. A timing critical net is recognized from the obtained rough path, and a buffer is inserted into the timing critical net.
[0110]
S45. At this time, it is determined whether or not the prescribed number of divisions has been completed. If not, the process returns to S41, and if the prescribed number of divisions has been reached, the process is terminated.
[0111]
(5) About the step of performing detailed wiring from the rough placement and routing result obtained in the placement phase after the placement is completed
Detailed wiring is performed based on the result of the schematic placement and wiring obtained by using (1), (2), (3), and (4). For example, as shown in FIG. 15A, detailed wiring is performed on the schematic wiring obtained at the end of the placement phase by a method such as a labyrinth method to obtain a detailed wiring path as shown in FIG. is there.
[0112]
Next, referring to the flow shown in FIG. 14, the operation state of the automatic placement and routing means 1 in FIG. 1 will be described with reference to the step (SF) of performing detailed routing from the schematic routing result obtained in the placement phase after the placement in FIG. .
[0113]
S51. Cells (terminals) are arranged by the methods (1), (2), (3), and (4), and are roughly wired. Thereby, for example, a schematic placement and routing path as shown in FIG. 15A is obtained.
[0114]
S52. Next, detailed wiring is performed on the schematic layout wiring path by, for example, a maze method, and a detailed wiring path is obtained as shown in FIG.
[0115]
S53. Then perform timing analysis for each net.
[0116]
S54. If the result of the timing analysis does not satisfy the timing constraint, the process returns to S51 and S52 to perform the general placement wiring or the detailed wiring again. If the timing constraint is satisfied, the placement and routing process according to the present invention ends.
[0117]
As described above, according to the present invention, since the wiring pattern generated in the placement phase found in the conventional method is different from the wiring pattern generated in the wiring phase, timing optimization in the placement phase is not efficiently performed. This solves the problem.
[0118]
In addition, since the wiring path is inherited, the optimization direction is stabilized, and the convergence of the placement and routing flow can be improved.
[0119]
In the present invention, in the rough wiring performed in the placement phase, the estimation accuracy of the degree of congestion is improved by performing temporary placement, and the route in the initial stage of placement is inherited so as to be closer to the actual wiring result. To do. Also, when a critical net is recognized at the stage of placement, the wiring length of the critical net is shortened by means of placement. These processes can reduce rework from the timing analysis after detailed wiring to the wiring or placement phase, which is a problem in the conventional method.
[0120]
Embodiments of the present invention will be described below.
[0121]
(Supplementary note 1) In an automatic placement and routing apparatus that uses partitioning for cell placement, a means for temporarily placing cells assigned to blocks at each cut level of partitioning placement by a high-speed placement method and a boundary between adjacent blocks Means for calculating the number of line segments Nc that can be passed; means for calculating the number of line segments Nb greater than or equal to a predetermined length that can be placed in the block; and means for calculating an average length Lb of the number of line segments greater than or equal to the predetermined length And a means for calculating the wiring congestion degree based on the number Nc of line segments that can pass through the boundary, the number Nb of line segments of a predetermined length or more, and the average length Lb, and estimating the wiring congestion degree and performing rough wiring It is characterized by.
[0122]
(Supplementary note 2) In an automatic placement and routing apparatus that uses partitioning for cell placement, a means for storing the net wiring route at each level of the partitioning placement and a wiring tree indicating the connection relation of the net wiring are created. Means for obtaining a partial path connecting terminals or Steiner points of the wiring tree, and connecting each terminal path to the terminal at the current cut level within the block area to which the path belongs. Means for rerouting the route, and performing rough wiring in the area of the block through which the stored route has passed.
[0123]
(Supplementary Note 3) In an automatic placement and routing apparatus that uses partitioning for cell placement, means for holding a path obtained at the previous division level, means for incrementing the division level, and in which block each cell is placed A route is provided for each net based on the previous level wiring route that has been held, and the route that passes through the block area through which the route that has been held passes. It is characterized by holding.
[0124]
(Supplementary Note 4) In an automatic placement and routing apparatus using partitioning for cell placement, means for holding a path obtained at the previous division level, means for detecting a timing critical net, and means for incrementing the division level +1 Detecting the timing critical net from the previous level routing result, determining which block each cell should be placed to shorten the wiring length for that net, and inserting a buffer for the timing critical net For each net, rough wiring is performed based on the previous level wiring route held, and the route passing through the area of the block through which the route that has been held passes is retained. It is characterized by that.
[0125]
(Appendix 5) In the (Appendix 3), there is provided means for performing schematic layout and holding the wiring result and means for performing detailed wiring, performing schematic layout and performing detailed wiring by inheriting the wiring result. It is characterized by performing.
[0126]
(Appendix 6) Provided with means for carrying out schematic wiring according to the above (Appendix 3) and (Appendix 4) and holding the result, and means for performing detailed wiring, and carrying out detailed wiring by inheriting this schematic layout and wiring It is characterized by.
[0127]
【The invention's effect】
According to the present invention, the following effects can be obtained.
[0128]
(1) Congestion of wiring based on the number Nc of line segments that can pass through the boundary with an adjacent block, the number of line segments Nb that is greater than or equal to a predetermined length that can be placed in the block, and the average length Lb of the number of line segments that are greater than or equal to this predetermined length Since the degree is determined and the rough wiring is performed based on this, the rough wiring can be performed with high accuracy.
[0129]
(2) Since a partial route is obtained by using a wiring tree indicating the connection relation of the net wiring and inheriting the connection relation, it is possible to accurately indicate the connection relation and accurately recognize whether the terminal is a driver. Therefore, timing constraints can be dealt with correctly.
[0130]
(3) When the division level of the block is incremented by 1, rough wiring can be performed in consideration of the wiring congestion degree based on the wiring path of the previous level in the middle of the partitioning. By avoiding this, it is possible to determine a schematic wiring route, so that wiring rework can be avoided.
[0131]
(4) The timing critical net is detected from the previous level wiring result, and the cell position and buffer insertion can be performed for this net so as to shorten the wiring length. Can be avoided.
[0132]
(5) Wiring is performed roughly in the block area to which the previous route belonged based on the current level terminal connection, and detailed wiring is performed. What can be automatically placed and routed can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of the present invention.
FIG. 2 is an operation explanatory diagram of an automatic placement and routing apparatus to which the present invention is applied.
FIG. 3 is an explanatory diagram of a wiring congestion degree calculation state according to the present invention.
FIG. 4 is an explanatory diagram of the number of line segments that can pass through a block boundary.
FIG. 5 is an explanatory diagram of a region where a line segment having a length L or more is placed.
FIG. 6 is an explanatory diagram of a wiring state using a wiring congestion degree.
FIG. 7 is an explanatory diagram of a schematic wiring route wiring procedure of the present invention.
FIG. 8 is a specific explanatory diagram of a schematic wiring route procedure;
FIG. 9 is an explanatory diagram of a wiring state using a schematic wiring route wiring procedure;
FIG. 10 is an explanatory diagram of a schematic wiring route inheritance procedure according to the present invention.
FIG. 11 is an explanatory diagram of a schematic wiring route inheritance creation state in consideration of the degree of wiring congestion.
FIG. 12 is an explanatory diagram of a schematic wiring path inheritance procedure considering the timing of the present invention.
FIG. 13 is an explanatory diagram of a timing-considering schematic wiring path inheritance creation state.
FIG. 14 is an explanatory diagram of a detailed wiring procedure.
FIG. 15 is an explanatory diagram of a detailed wiring creation state.
FIG. 16 is an explanatory diagram of a conventional automatic placement and routing method.
FIG. 17 is an explanatory diagram of a detour occurrence state.
[Explanation of symbols]
1 Automatic placement and routing means
2 Netlist
3 Place and route output holding part
4 Outline placement and routing means
5 Detailed placement and routing means
6 Switching means

Claims (4)

In an automatic placement and routing apparatus that uses partitioning for cell placement, means for temporarily placing cells assigned to blocks at each cut level of partitioning placement by a high-speed placement method;
Means for calculating the number Nc of line segments that can pass through a boundary with an adjacent block;
Means for calculating a line segment Nb of a predetermined length or longer that can be placed in the block;
Means for calculating an average length Lb of the number of line segments greater than or equal to the predetermined length;
Means for calculating the wiring congestion degree based on the number Nc of line segments that can pass through the boundary, the number Nb of line segments of a predetermined length or more, and the average length Lb;
An automatic placement and routing apparatus characterized by estimating wiring congestion and performing rough wiring. In automatic placement and routing equipment that uses partitioning for cell placement,
Means for saving the net routing path of the net at each cut level of the partitioning arrangement;
Means for creating a wiring tree showing the connection relation of the net wiring;
Means for obtaining a partial wiring path connecting terminals or Steiner points of this wiring tree;
For each partial wiring path, means for rerouting the path to connect to its terminal at the current cut level within the area of the block to which the wiring path belonged,
Means for determining in which block each cell is placed,
When receiving an instruction to change the cut level,
Means for retaining the wiring path obtained at the current cut level as the wiring path of the previous cut level;
When changing to the next cut level based on the contents of the change, rough wiring is performed based on the wiring route of the previous level that has been retained, and the degree of wiring congestion and the block that the retained route has passed Means for inheriting the schematic wiring path to the next cut level so as to maintain the path through the area;
An automatic placement and routing apparatus characterized by comprising: In automatic placement and routing equipment that uses partitioning for cell placement,
Means for saving the net routing path of the net at each cut level of the partitioning arrangement;
Means for creating a wiring tree showing the connection relation of the net wiring;
Means for obtaining a partial path connecting terminals or Steiner points of this wiring tree;
For each partial wiring path, means for re-wiring the wiring path so as to connect to the terminal at the current cut level within the block area to which the wiring path belonged,
Means for detecting a timing critical net,
When receiving an instruction to change the cut level,
Means for retaining the wiring path obtained at the current cut level as the previous cut level;
Change to the next cut level based on the contents of the change, detect the timing critical net from the wiring result of the previous cut level, decide which block to place each cell so as to shorten the wiring length for that net , A means to insert a buffer for the timing critical net, and to inherit the rough wiring path considering the circuit timing during the partitioning to the next cut level,
An automatic placement and routing apparatus characterized by comprising: In claim 2,
Means for roughly placing and routing and holding the routing results;
Comprising means for performing detailed wiring;
An automatic placement and routing apparatus that performs schematic placement and routing and inherits the result of the routing and performs detailed routing.

Images